Commit | Line | Data |
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71bcada8 | 1 | /* |
c3eea194 | 2 | * Copyright Altera Corporation (C) 2014-2016. All rights reserved. |
71bcada8 TT |
3 | * Copyright 2011-2012 Calxeda, Inc. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | * | |
17 | * Adapted from the highbank_mc_edac driver. | |
18 | */ | |
19 | ||
c3eea194 | 20 | #include <asm/cacheflush.h> |
71bcada8 TT |
21 | #include <linux/ctype.h> |
22 | #include <linux/edac.h> | |
c3eea194 | 23 | #include <linux/genalloc.h> |
71bcada8 | 24 | #include <linux/interrupt.h> |
13ab8448 | 25 | #include <linux/irqchip/chained_irq.h> |
71bcada8 TT |
26 | #include <linux/kernel.h> |
27 | #include <linux/mfd/syscon.h> | |
588cb03e | 28 | #include <linux/of_address.h> |
13ab8448 | 29 | #include <linux/of_irq.h> |
71bcada8 TT |
30 | #include <linux/of_platform.h> |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/regmap.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/uaccess.h> | |
35 | ||
143f4a5a | 36 | #include "altera_edac.h" |
71bcada8 TT |
37 | #include "edac_core.h" |
38 | #include "edac_module.h" | |
39 | ||
40 | #define EDAC_MOD_STR "altera_edac" | |
41 | #define EDAC_VERSION "1" | |
c3eea194 | 42 | #define EDAC_DEVICE "Altera" |
71bcada8 | 43 | |
143f4a5a TT |
44 | static const struct altr_sdram_prv_data c5_data = { |
45 | .ecc_ctrl_offset = CV_CTLCFG_OFST, | |
46 | .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, | |
47 | .ecc_stat_offset = CV_DRAMSTS_OFST, | |
48 | .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, | |
49 | .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, | |
50 | .ecc_saddr_offset = CV_ERRADDR_OFST, | |
73bcc942 | 51 | .ecc_daddr_offset = CV_ERRADDR_OFST, |
143f4a5a TT |
52 | .ecc_cecnt_offset = CV_SBECOUNT_OFST, |
53 | .ecc_uecnt_offset = CV_DBECOUNT_OFST, | |
54 | .ecc_irq_en_offset = CV_DRAMINTR_OFST, | |
55 | .ecc_irq_en_mask = CV_DRAMINTR_INTREN, | |
56 | .ecc_irq_clr_offset = CV_DRAMINTR_OFST, | |
57 | .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), | |
58 | .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, | |
59 | .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, | |
143f4a5a TT |
60 | .ce_ue_trgr_offset = CV_CTLCFG_OFST, |
61 | .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, | |
62 | .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, | |
71bcada8 TT |
63 | }; |
64 | ||
73bcc942 TT |
65 | static const struct altr_sdram_prv_data a10_data = { |
66 | .ecc_ctrl_offset = A10_ECCCTRL1_OFST, | |
67 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
68 | .ecc_stat_offset = A10_INTSTAT_OFST, | |
69 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
70 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
71 | .ecc_saddr_offset = A10_SERRADDR_OFST, | |
72 | .ecc_daddr_offset = A10_DERRADDR_OFST, | |
73 | .ecc_irq_en_offset = A10_ERRINTEN_OFST, | |
74 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
75 | .ecc_irq_clr_offset = A10_INTSTAT_OFST, | |
76 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
77 | .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, | |
78 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
73bcc942 TT |
79 | .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, |
80 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
81 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
73bcc942 TT |
82 | }; |
83 | ||
c3eea194 TT |
84 | /*********************** EDAC Memory Controller Functions ****************/ |
85 | ||
86 | /* The SDRAM controller uses the EDAC Memory Controller framework. */ | |
87 | ||
71bcada8 TT |
88 | static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) |
89 | { | |
90 | struct mem_ctl_info *mci = dev_id; | |
91 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 92 | const struct altr_sdram_prv_data *priv = drvdata->data; |
73bcc942 | 93 | u32 status, err_count = 1, err_addr; |
71bcada8 | 94 | |
143f4a5a | 95 | regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); |
71bcada8 | 96 | |
143f4a5a | 97 | if (status & priv->ecc_stat_ue_mask) { |
73bcc942 TT |
98 | regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, |
99 | &err_addr); | |
100 | if (priv->ecc_uecnt_offset) | |
101 | regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, | |
102 | &err_count); | |
71bcada8 TT |
103 | panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", |
104 | err_count, err_addr); | |
105 | } | |
143f4a5a | 106 | if (status & priv->ecc_stat_ce_mask) { |
73bcc942 TT |
107 | regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, |
108 | &err_addr); | |
109 | if (priv->ecc_uecnt_offset) | |
110 | regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, | |
111 | &err_count); | |
71bcada8 TT |
112 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, |
113 | err_addr >> PAGE_SHIFT, | |
114 | err_addr & ~PAGE_MASK, 0, | |
115 | 0, 0, -1, mci->ctl_name, ""); | |
73bcc942 TT |
116 | /* Clear IRQ to resume */ |
117 | regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, | |
118 | priv->ecc_irq_clr_mask); | |
71bcada8 | 119 | |
73bcc942 TT |
120 | return IRQ_HANDLED; |
121 | } | |
122 | return IRQ_NONE; | |
71bcada8 TT |
123 | } |
124 | ||
71bcada8 TT |
125 | static ssize_t altr_sdr_mc_err_inject_write(struct file *file, |
126 | const char __user *data, | |
127 | size_t count, loff_t *ppos) | |
128 | { | |
129 | struct mem_ctl_info *mci = file->private_data; | |
130 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 131 | const struct altr_sdram_prv_data *priv = drvdata->data; |
71bcada8 TT |
132 | u32 *ptemp; |
133 | dma_addr_t dma_handle; | |
134 | u32 reg, read_reg; | |
135 | ||
136 | ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); | |
137 | if (!ptemp) { | |
138 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
139 | edac_printk(KERN_ERR, EDAC_MC, | |
140 | "Inject: Buffer Allocation error\n"); | |
141 | return -ENOMEM; | |
142 | } | |
143 | ||
143f4a5a TT |
144 | regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
145 | &read_reg); | |
146 | read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); | |
71bcada8 TT |
147 | |
148 | /* Error are injected by writing a word while the SBE or DBE | |
149 | * bit in the CTLCFG register is set. Reading the word will | |
150 | * trigger the SBE or DBE error and the corresponding IRQ. | |
151 | */ | |
152 | if (count == 3) { | |
153 | edac_printk(KERN_ALERT, EDAC_MC, | |
154 | "Inject Double bit error\n"); | |
143f4a5a TT |
155 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
156 | (read_reg | priv->ue_set_mask)); | |
71bcada8 TT |
157 | } else { |
158 | edac_printk(KERN_ALERT, EDAC_MC, | |
159 | "Inject Single bit error\n"); | |
143f4a5a TT |
160 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
161 | (read_reg | priv->ce_set_mask)); | |
71bcada8 TT |
162 | } |
163 | ||
164 | ptemp[0] = 0x5A5A5A5A; | |
165 | ptemp[1] = 0xA5A5A5A5; | |
166 | ||
167 | /* Clear the error injection bits */ | |
143f4a5a | 168 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); |
71bcada8 TT |
169 | /* Ensure it has been written out */ |
170 | wmb(); | |
171 | ||
172 | /* | |
173 | * To trigger the error, we need to read the data back | |
174 | * (the data was written with errors above). | |
175 | * The ACCESS_ONCE macros and printk are used to prevent the | |
176 | * the compiler optimizing these reads out. | |
177 | */ | |
178 | reg = ACCESS_ONCE(ptemp[0]); | |
179 | read_reg = ACCESS_ONCE(ptemp[1]); | |
180 | /* Force Read */ | |
181 | rmb(); | |
182 | ||
183 | edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", | |
184 | reg, read_reg); | |
185 | ||
186 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
187 | ||
188 | return count; | |
189 | } | |
190 | ||
191 | static const struct file_operations altr_sdr_mc_debug_inject_fops = { | |
192 | .open = simple_open, | |
193 | .write = altr_sdr_mc_err_inject_write, | |
194 | .llseek = generic_file_llseek, | |
195 | }; | |
196 | ||
197 | static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) | |
198 | { | |
bba3b31e BP |
199 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) |
200 | return; | |
201 | ||
202 | if (!mci->debugfs) | |
203 | return; | |
204 | ||
205 | edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci, | |
206 | &altr_sdr_mc_debug_inject_fops); | |
71bcada8 | 207 | } |
71bcada8 | 208 | |
f9ae487e TT |
209 | /* Get total memory size from Open Firmware DTB */ |
210 | static unsigned long get_total_mem(void) | |
71bcada8 | 211 | { |
f9ae487e TT |
212 | struct device_node *np = NULL; |
213 | const unsigned int *reg, *reg_end; | |
214 | int len, sw, aw; | |
215 | unsigned long start, size, total_mem = 0; | |
216 | ||
217 | for_each_node_by_type(np, "memory") { | |
218 | aw = of_n_addr_cells(np); | |
219 | sw = of_n_size_cells(np); | |
220 | reg = (const unsigned int *)of_get_property(np, "reg", &len); | |
221 | reg_end = reg + (len / sizeof(u32)); | |
222 | ||
223 | total_mem = 0; | |
224 | do { | |
225 | start = of_read_number(reg, aw); | |
226 | reg += aw; | |
227 | size = of_read_number(reg, sw); | |
228 | reg += sw; | |
229 | total_mem += size; | |
230 | } while (reg < reg_end); | |
231 | } | |
232 | edac_dbg(0, "total_mem 0x%lx\n", total_mem); | |
233 | return total_mem; | |
71bcada8 TT |
234 | } |
235 | ||
143f4a5a | 236 | static const struct of_device_id altr_sdram_ctrl_of_match[] = { |
2c911f6c AB |
237 | { .compatible = "altr,sdram-edac", .data = &c5_data}, |
238 | { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, | |
143f4a5a TT |
239 | {}, |
240 | }; | |
241 | MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); | |
242 | ||
73bcc942 TT |
243 | static int a10_init(struct regmap *mc_vbase) |
244 | { | |
245 | if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, | |
246 | A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { | |
247 | edac_printk(KERN_ERR, EDAC_MC, | |
248 | "Error setting SB IRQ mode\n"); | |
249 | return -ENODEV; | |
250 | } | |
251 | ||
252 | if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { | |
253 | edac_printk(KERN_ERR, EDAC_MC, | |
254 | "Error setting trigger count\n"); | |
255 | return -ENODEV; | |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static int a10_unmask_irq(struct platform_device *pdev, u32 mask) | |
262 | { | |
263 | void __iomem *sm_base; | |
264 | int ret = 0; | |
265 | ||
266 | if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), | |
267 | dev_name(&pdev->dev))) { | |
268 | edac_printk(KERN_ERR, EDAC_MC, | |
269 | "Unable to request mem region\n"); | |
270 | return -EBUSY; | |
271 | } | |
272 | ||
273 | sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
274 | if (!sm_base) { | |
275 | edac_printk(KERN_ERR, EDAC_MC, | |
276 | "Unable to ioremap device\n"); | |
277 | ||
278 | ret = -ENOMEM; | |
279 | goto release; | |
280 | } | |
281 | ||
282 | iowrite32(mask, sm_base); | |
283 | ||
284 | iounmap(sm_base); | |
285 | ||
286 | release: | |
287 | release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
288 | ||
289 | return ret; | |
290 | } | |
291 | ||
71bcada8 TT |
292 | static int altr_sdram_probe(struct platform_device *pdev) |
293 | { | |
143f4a5a | 294 | const struct of_device_id *id; |
71bcada8 TT |
295 | struct edac_mc_layer layers[2]; |
296 | struct mem_ctl_info *mci; | |
297 | struct altr_sdram_mc_data *drvdata; | |
143f4a5a | 298 | const struct altr_sdram_prv_data *priv; |
71bcada8 TT |
299 | struct regmap *mc_vbase; |
300 | struct dimm_info *dimm; | |
143f4a5a | 301 | u32 read_reg; |
73bcc942 TT |
302 | int irq, irq2, res = 0; |
303 | unsigned long mem_size, irqflags = 0; | |
143f4a5a TT |
304 | |
305 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
306 | if (!id) | |
307 | return -ENODEV; | |
71bcada8 | 308 | |
71bcada8 TT |
309 | /* Grab the register range from the sdr controller in device tree */ |
310 | mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
311 | "altr,sdr-syscon"); | |
312 | if (IS_ERR(mc_vbase)) { | |
313 | edac_printk(KERN_ERR, EDAC_MC, | |
314 | "regmap for altr,sdr-syscon lookup failed.\n"); | |
315 | return -ENODEV; | |
316 | } | |
317 | ||
143f4a5a TT |
318 | /* Check specific dependencies for the module */ |
319 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
320 | pdev->dev.of_node)->data; | |
321 | ||
322 | /* Validate the SDRAM controller has ECC enabled */ | |
323 | if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || | |
324 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
71bcada8 TT |
325 | edac_printk(KERN_ERR, EDAC_MC, |
326 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
327 | return -ENODEV; | |
328 | } | |
329 | ||
330 | /* Grab memory size from device tree. */ | |
f9ae487e | 331 | mem_size = get_total_mem(); |
71bcada8 | 332 | if (!mem_size) { |
f9ae487e | 333 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); |
71bcada8 TT |
334 | return -ENODEV; |
335 | } | |
336 | ||
143f4a5a TT |
337 | /* Ensure the SDRAM Interrupt is disabled */ |
338 | if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, | |
339 | priv->ecc_irq_en_mask, 0)) { | |
340 | edac_printk(KERN_ERR, EDAC_MC, | |
341 | "Error disabling SDRAM ECC IRQ\n"); | |
342 | return -ENODEV; | |
343 | } | |
344 | ||
345 | /* Toggle to clear the SDRAM Error count */ | |
346 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
347 | priv->ecc_cnt_rst_mask, | |
348 | priv->ecc_cnt_rst_mask)) { | |
349 | edac_printk(KERN_ERR, EDAC_MC, | |
350 | "Error clearing SDRAM ECC count\n"); | |
351 | return -ENODEV; | |
352 | } | |
353 | ||
354 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
355 | priv->ecc_cnt_rst_mask, 0)) { | |
71bcada8 | 356 | edac_printk(KERN_ERR, EDAC_MC, |
143f4a5a | 357 | "Error clearing SDRAM ECC count\n"); |
71bcada8 TT |
358 | return -ENODEV; |
359 | } | |
360 | ||
361 | irq = platform_get_irq(pdev, 0); | |
362 | if (irq < 0) { | |
363 | edac_printk(KERN_ERR, EDAC_MC, | |
364 | "No irq %d in DT\n", irq); | |
365 | return -ENODEV; | |
366 | } | |
367 | ||
73bcc942 TT |
368 | /* Arria10 has a 2nd IRQ */ |
369 | irq2 = platform_get_irq(pdev, 1); | |
370 | ||
71bcada8 TT |
371 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
372 | layers[0].size = 1; | |
373 | layers[0].is_virt_csrow = true; | |
374 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
375 | layers[1].size = 1; | |
376 | layers[1].is_virt_csrow = false; | |
377 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
378 | sizeof(struct altr_sdram_mc_data)); | |
379 | if (!mci) | |
380 | return -ENOMEM; | |
381 | ||
382 | mci->pdev = &pdev->dev; | |
383 | drvdata = mci->pvt_info; | |
384 | drvdata->mc_vbase = mc_vbase; | |
143f4a5a | 385 | drvdata->data = priv; |
71bcada8 TT |
386 | platform_set_drvdata(pdev, mci); |
387 | ||
388 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
143f4a5a TT |
389 | edac_printk(KERN_ERR, EDAC_MC, |
390 | "Unable to get managed device resource\n"); | |
71bcada8 TT |
391 | res = -ENOMEM; |
392 | goto free; | |
393 | } | |
394 | ||
395 | mci->mtype_cap = MEM_FLAG_DDR3; | |
396 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
397 | mci->edac_cap = EDAC_FLAG_SECDED; | |
398 | mci->mod_name = EDAC_MOD_STR; | |
399 | mci->mod_ver = EDAC_VERSION; | |
400 | mci->ctl_name = dev_name(&pdev->dev); | |
401 | mci->scrub_mode = SCRUB_SW_SRC; | |
402 | mci->dev_name = dev_name(&pdev->dev); | |
403 | ||
404 | dimm = *mci->dimms; | |
405 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
406 | dimm->grain = 8; | |
407 | dimm->dtype = DEV_X8; | |
408 | dimm->mtype = MEM_DDR3; | |
409 | dimm->edac_mode = EDAC_SECDED; | |
410 | ||
411 | res = edac_mc_add_mc(mci); | |
412 | if (res < 0) | |
413 | goto err; | |
414 | ||
73bcc942 TT |
415 | /* Only the Arria10 has separate IRQs */ |
416 | if (irq2 > 0) { | |
417 | /* Arria10 specific initialization */ | |
418 | res = a10_init(mc_vbase); | |
419 | if (res < 0) | |
420 | goto err2; | |
421 | ||
422 | res = devm_request_irq(&pdev->dev, irq2, | |
423 | altr_sdram_mc_err_handler, | |
424 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
425 | if (res < 0) { | |
426 | edac_mc_printk(mci, KERN_ERR, | |
427 | "Unable to request irq %d\n", irq2); | |
428 | res = -ENODEV; | |
429 | goto err2; | |
430 | } | |
431 | ||
432 | res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); | |
433 | if (res < 0) | |
434 | goto err2; | |
435 | ||
436 | irqflags = IRQF_SHARED; | |
437 | } | |
438 | ||
71bcada8 | 439 | res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, |
73bcc942 | 440 | irqflags, dev_name(&pdev->dev), mci); |
71bcada8 TT |
441 | if (res < 0) { |
442 | edac_mc_printk(mci, KERN_ERR, | |
443 | "Unable to request irq %d\n", irq); | |
444 | res = -ENODEV; | |
445 | goto err2; | |
446 | } | |
447 | ||
143f4a5a TT |
448 | /* Infrastructure ready - enable the IRQ */ |
449 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, | |
450 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
71bcada8 TT |
451 | edac_mc_printk(mci, KERN_ERR, |
452 | "Error enabling SDRAM ECC IRQ\n"); | |
453 | res = -ENODEV; | |
454 | goto err2; | |
455 | } | |
456 | ||
457 | altr_sdr_mc_create_debugfs_nodes(mci); | |
458 | ||
459 | devres_close_group(&pdev->dev, NULL); | |
460 | ||
461 | return 0; | |
462 | ||
463 | err2: | |
464 | edac_mc_del_mc(&pdev->dev); | |
465 | err: | |
466 | devres_release_group(&pdev->dev, NULL); | |
467 | free: | |
468 | edac_mc_free(mci); | |
469 | edac_printk(KERN_ERR, EDAC_MC, | |
470 | "EDAC Probe Failed; Error %d\n", res); | |
471 | ||
472 | return res; | |
473 | } | |
474 | ||
475 | static int altr_sdram_remove(struct platform_device *pdev) | |
476 | { | |
477 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
478 | ||
479 | edac_mc_del_mc(&pdev->dev); | |
480 | edac_mc_free(mci); | |
481 | platform_set_drvdata(pdev, NULL); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
6f2b6422 AT |
486 | /* |
487 | * If you want to suspend, need to disable EDAC by removing it | |
488 | * from the device tree or defconfig. | |
489 | */ | |
490 | #ifdef CONFIG_PM | |
491 | static int altr_sdram_prepare(struct device *dev) | |
492 | { | |
493 | pr_err("Suspend not allowed when EDAC is enabled.\n"); | |
494 | ||
495 | return -EPERM; | |
496 | } | |
497 | ||
498 | static const struct dev_pm_ops altr_sdram_pm_ops = { | |
499 | .prepare = altr_sdram_prepare, | |
500 | }; | |
501 | #endif | |
502 | ||
71bcada8 TT |
503 | static struct platform_driver altr_sdram_edac_driver = { |
504 | .probe = altr_sdram_probe, | |
505 | .remove = altr_sdram_remove, | |
506 | .driver = { | |
507 | .name = "altr_sdram_edac", | |
6f2b6422 AT |
508 | #ifdef CONFIG_PM |
509 | .pm = &altr_sdram_pm_ops, | |
510 | #endif | |
71bcada8 TT |
511 | .of_match_table = altr_sdram_ctrl_of_match, |
512 | }, | |
513 | }; | |
514 | ||
515 | module_platform_driver(altr_sdram_edac_driver); | |
516 | ||
c3eea194 TT |
517 | /************************* EDAC Parent Probe *************************/ |
518 | ||
519 | static const struct of_device_id altr_edac_device_of_match[]; | |
520 | ||
521 | static const struct of_device_id altr_edac_of_match[] = { | |
522 | { .compatible = "altr,socfpga-ecc-manager" }, | |
523 | {}, | |
524 | }; | |
525 | MODULE_DEVICE_TABLE(of, altr_edac_of_match); | |
526 | ||
527 | static int altr_edac_probe(struct platform_device *pdev) | |
528 | { | |
529 | of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, | |
530 | NULL, &pdev->dev); | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static struct platform_driver altr_edac_driver = { | |
535 | .probe = altr_edac_probe, | |
536 | .driver = { | |
537 | .name = "socfpga_ecc_manager", | |
538 | .of_match_table = altr_edac_of_match, | |
539 | }, | |
540 | }; | |
541 | module_platform_driver(altr_edac_driver); | |
542 | ||
543 | /************************* EDAC Device Functions *************************/ | |
544 | ||
545 | /* | |
546 | * EDAC Device Functions (shared between various IPs). | |
547 | * The discrete memories use the EDAC Device framework. The probe | |
548 | * and error handling functions are very similar between memories | |
549 | * so they are shared. The memory allocation and freeing for EDAC | |
550 | * trigger testing are different for each memory. | |
551 | */ | |
552 | ||
553 | const struct edac_device_prv_data ocramecc_data; | |
554 | const struct edac_device_prv_data l2ecc_data; | |
c7b4be8d | 555 | const struct edac_device_prv_data a10_ocramecc_data; |
588cb03e | 556 | const struct edac_device_prv_data a10_l2ecc_data; |
c3eea194 | 557 | |
c3eea194 TT |
558 | static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) |
559 | { | |
560 | irqreturn_t ret_value = IRQ_NONE; | |
561 | struct edac_device_ctl_info *dci = dev_id; | |
562 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
563 | const struct edac_device_prv_data *priv = drvdata->data; | |
564 | ||
565 | if (irq == drvdata->sb_irq) { | |
566 | if (priv->ce_clear_mask) | |
567 | writel(priv->ce_clear_mask, drvdata->base); | |
568 | edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); | |
569 | ret_value = IRQ_HANDLED; | |
570 | } else if (irq == drvdata->db_irq) { | |
571 | if (priv->ue_clear_mask) | |
572 | writel(priv->ue_clear_mask, drvdata->base); | |
573 | edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); | |
574 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
575 | ret_value = IRQ_HANDLED; | |
576 | } else { | |
577 | WARN_ON(1); | |
578 | } | |
579 | ||
580 | return ret_value; | |
581 | } | |
582 | ||
583 | static ssize_t altr_edac_device_trig(struct file *file, | |
584 | const char __user *user_buf, | |
585 | size_t count, loff_t *ppos) | |
586 | ||
587 | { | |
588 | u32 *ptemp, i, error_mask; | |
589 | int result = 0; | |
590 | u8 trig_type; | |
591 | unsigned long flags; | |
592 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
593 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
594 | const struct edac_device_prv_data *priv = drvdata->data; | |
595 | void *generic_ptr = edac_dci->dev; | |
596 | ||
597 | if (!user_buf || get_user(trig_type, user_buf)) | |
598 | return -EFAULT; | |
599 | ||
600 | if (!priv->alloc_mem) | |
601 | return -ENOMEM; | |
602 | ||
603 | /* | |
604 | * Note that generic_ptr is initialized to the device * but in | |
605 | * some alloc_functions, this is overridden and returns data. | |
606 | */ | |
607 | ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); | |
608 | if (!ptemp) { | |
609 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
610 | "Inject: Buffer Allocation error\n"); | |
611 | return -ENOMEM; | |
612 | } | |
613 | ||
614 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
615 | error_mask = priv->ue_set_mask; | |
616 | else | |
617 | error_mask = priv->ce_set_mask; | |
618 | ||
619 | edac_printk(KERN_ALERT, EDAC_DEVICE, | |
620 | "Trigger Error Mask (0x%X)\n", error_mask); | |
621 | ||
622 | local_irq_save(flags); | |
623 | /* write ECC corrupted data out. */ | |
624 | for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { | |
625 | /* Read data so we're in the correct state */ | |
626 | rmb(); | |
627 | if (ACCESS_ONCE(ptemp[i])) | |
628 | result = -1; | |
629 | /* Toggle Error bit (it is latched), leave ECC enabled */ | |
811fce4f TT |
630 | writel(error_mask, (drvdata->base + priv->set_err_ofst)); |
631 | writel(priv->ecc_enable_mask, (drvdata->base + | |
632 | priv->set_err_ofst)); | |
c3eea194 TT |
633 | ptemp[i] = i; |
634 | } | |
635 | /* Ensure it has been written out */ | |
636 | wmb(); | |
637 | local_irq_restore(flags); | |
638 | ||
639 | if (result) | |
640 | edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); | |
641 | ||
642 | /* Read out written data. ECC error caused here */ | |
643 | for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) | |
644 | if (ACCESS_ONCE(ptemp[i]) != i) | |
645 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
646 | "Read doesn't match written data\n"); | |
647 | ||
648 | if (priv->free_mem) | |
649 | priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); | |
650 | ||
651 | return count; | |
652 | } | |
653 | ||
654 | static const struct file_operations altr_edac_device_inject_fops = { | |
655 | .open = simple_open, | |
656 | .write = altr_edac_device_trig, | |
657 | .llseek = generic_file_llseek, | |
658 | }; | |
659 | ||
c7b4be8d TT |
660 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
661 | const char __user *user_buf, | |
662 | size_t count, loff_t *ppos); | |
663 | ||
664 | static const struct file_operations altr_edac_a10_device_inject_fops = { | |
665 | .open = simple_open, | |
666 | .write = altr_edac_a10_device_trig, | |
667 | .llseek = generic_file_llseek, | |
668 | }; | |
669 | ||
c3eea194 TT |
670 | static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, |
671 | const struct edac_device_prv_data *priv) | |
672 | { | |
673 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
674 | ||
675 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
676 | return; | |
677 | ||
678 | drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); | |
679 | if (!drvdata->debugfs_dir) | |
680 | return; | |
681 | ||
682 | if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR, | |
683 | drvdata->debugfs_dir, edac_dci, | |
e17ced2c | 684 | priv->inject_fops)) |
c3eea194 TT |
685 | debugfs_remove_recursive(drvdata->debugfs_dir); |
686 | } | |
687 | ||
688 | static const struct of_device_id altr_edac_device_of_match[] = { | |
689 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
2c911f6c AB |
690 | { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, |
691 | { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, | |
c3eea194 TT |
692 | #endif |
693 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
2c911f6c AB |
694 | { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, |
695 | { .compatible = "altr,socfpga-a10-ocram-ecc", .data = &a10_ocramecc_data }, | |
c3eea194 TT |
696 | #endif |
697 | {}, | |
698 | }; | |
699 | MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); | |
700 | ||
701 | /* | |
702 | * altr_edac_device_probe() | |
703 | * This is a generic EDAC device driver that will support | |
704 | * various Altera memory devices such as the L2 cache ECC and | |
705 | * OCRAM ECC as well as the memories for other peripherals. | |
706 | * Module specific initialization is done by passing the | |
707 | * function index in the device tree. | |
708 | */ | |
709 | static int altr_edac_device_probe(struct platform_device *pdev) | |
710 | { | |
711 | struct edac_device_ctl_info *dci; | |
712 | struct altr_edac_device_dev *drvdata; | |
713 | struct resource *r; | |
714 | int res = 0; | |
715 | struct device_node *np = pdev->dev.of_node; | |
716 | char *ecc_name = (char *)np->name; | |
717 | static int dev_instance; | |
718 | ||
719 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
720 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
721 | "Unable to open devm\n"); | |
722 | return -ENOMEM; | |
723 | } | |
724 | ||
725 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
726 | if (!r) { | |
727 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
728 | "Unable to get mem resource\n"); | |
729 | res = -ENODEV; | |
730 | goto fail; | |
731 | } | |
732 | ||
733 | if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), | |
734 | dev_name(&pdev->dev))) { | |
735 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
736 | "%s:Error requesting mem region\n", ecc_name); | |
737 | res = -EBUSY; | |
738 | goto fail; | |
739 | } | |
740 | ||
741 | dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, | |
742 | 1, ecc_name, 1, 0, NULL, 0, | |
743 | dev_instance++); | |
744 | ||
745 | if (!dci) { | |
746 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
747 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
748 | res = -ENOMEM; | |
749 | goto fail; | |
750 | } | |
751 | ||
752 | drvdata = dci->pvt_info; | |
753 | dci->dev = &pdev->dev; | |
754 | platform_set_drvdata(pdev, dci); | |
755 | drvdata->edac_dev_name = ecc_name; | |
756 | ||
757 | drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); | |
758 | if (!drvdata->base) | |
759 | goto fail1; | |
760 | ||
761 | /* Get driver specific data for this EDAC device */ | |
762 | drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; | |
763 | ||
764 | /* Check specific dependencies for the module */ | |
765 | if (drvdata->data->setup) { | |
328ca7ae | 766 | res = drvdata->data->setup(drvdata); |
c3eea194 TT |
767 | if (res) |
768 | goto fail1; | |
769 | } | |
770 | ||
771 | drvdata->sb_irq = platform_get_irq(pdev, 0); | |
772 | res = devm_request_irq(&pdev->dev, drvdata->sb_irq, | |
773 | altr_edac_device_handler, | |
774 | 0, dev_name(&pdev->dev), dci); | |
775 | if (res) | |
776 | goto fail1; | |
777 | ||
778 | drvdata->db_irq = platform_get_irq(pdev, 1); | |
779 | res = devm_request_irq(&pdev->dev, drvdata->db_irq, | |
780 | altr_edac_device_handler, | |
781 | 0, dev_name(&pdev->dev), dci); | |
782 | if (res) | |
783 | goto fail1; | |
784 | ||
785 | dci->mod_name = "Altera ECC Manager"; | |
786 | dci->dev_name = drvdata->edac_dev_name; | |
787 | ||
788 | res = edac_device_add_device(dci); | |
789 | if (res) | |
790 | goto fail1; | |
791 | ||
792 | altr_create_edacdev_dbgfs(dci, drvdata->data); | |
793 | ||
794 | devres_close_group(&pdev->dev, NULL); | |
795 | ||
796 | return 0; | |
797 | ||
798 | fail1: | |
799 | edac_device_free_ctl_info(dci); | |
800 | fail: | |
801 | devres_release_group(&pdev->dev, NULL); | |
802 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
803 | "%s:Error setting up EDAC device: %d\n", ecc_name, res); | |
804 | ||
805 | return res; | |
806 | } | |
807 | ||
808 | static int altr_edac_device_remove(struct platform_device *pdev) | |
809 | { | |
810 | struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); | |
811 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
812 | ||
813 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
814 | edac_device_del_device(&pdev->dev); | |
815 | edac_device_free_ctl_info(dci); | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
820 | static struct platform_driver altr_edac_device_driver = { | |
821 | .probe = altr_edac_device_probe, | |
822 | .remove = altr_edac_device_remove, | |
823 | .driver = { | |
824 | .name = "altr_edac_device", | |
825 | .of_match_table = altr_edac_device_of_match, | |
826 | }, | |
827 | }; | |
828 | module_platform_driver(altr_edac_device_driver); | |
829 | ||
830 | /*********************** OCRAM EDAC Device Functions *********************/ | |
831 | ||
832 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1aa6eb5c AB |
833 | /* |
834 | * Test for memory's ECC dependencies upon entry because platform specific | |
835 | * startup should have initialized the memory and enabled the ECC. | |
836 | * Can't turn on ECC here because accessing un-initialized memory will | |
837 | * cause CE/UE errors possibly causing an ABORT. | |
838 | */ | |
839 | static int altr_check_ecc_deps(struct altr_edac_device_dev *device) | |
840 | { | |
841 | void __iomem *base = device->base; | |
842 | const struct edac_device_prv_data *prv = device->data; | |
843 | ||
844 | if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) | |
845 | return 0; | |
846 | ||
847 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
848 | "%s: No ECC present or ECC disabled.\n", | |
849 | device->edac_dev_name); | |
850 | return -ENODEV; | |
851 | } | |
c3eea194 TT |
852 | |
853 | static void *ocram_alloc_mem(size_t size, void **other) | |
854 | { | |
855 | struct device_node *np; | |
856 | struct gen_pool *gp; | |
857 | void *sram_addr; | |
858 | ||
859 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); | |
860 | if (!np) | |
861 | return NULL; | |
862 | ||
863 | gp = of_gen_pool_get(np, "iram", 0); | |
864 | of_node_put(np); | |
865 | if (!gp) | |
866 | return NULL; | |
867 | ||
868 | sram_addr = (void *)gen_pool_alloc(gp, size); | |
869 | if (!sram_addr) | |
870 | return NULL; | |
871 | ||
872 | memset(sram_addr, 0, size); | |
873 | /* Ensure data is written out */ | |
874 | wmb(); | |
875 | ||
876 | /* Remember this handle for freeing later */ | |
877 | *other = gp; | |
878 | ||
879 | return sram_addr; | |
880 | } | |
881 | ||
882 | static void ocram_free_mem(void *p, size_t size, void *other) | |
883 | { | |
884 | gen_pool_free((struct gen_pool *)other, (u32)p, size); | |
885 | } | |
886 | ||
13ab8448 | 887 | static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id) |
1aa6eb5c | 888 | { |
13ab8448 | 889 | struct altr_edac_device_dev *dci = dev_id; |
1aa6eb5c AB |
890 | void __iomem *base = dci->base; |
891 | ||
13ab8448 | 892 | if (irq == dci->sb_irq) { |
1aa6eb5c AB |
893 | writel(ALTR_A10_ECC_SERRPENA, |
894 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
895 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
13ab8448 TT |
896 | |
897 | return IRQ_HANDLED; | |
898 | } else if (irq == dci->db_irq) { | |
1aa6eb5c AB |
899 | writel(ALTR_A10_ECC_DERRPENA, |
900 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
901 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
902 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
13ab8448 TT |
903 | |
904 | return IRQ_HANDLED; | |
1aa6eb5c | 905 | } |
13ab8448 TT |
906 | |
907 | WARN_ON(1); | |
908 | ||
909 | return IRQ_NONE; | |
1aa6eb5c AB |
910 | } |
911 | ||
c3eea194 | 912 | const struct edac_device_prv_data ocramecc_data = { |
aa1f06dc | 913 | .setup = altr_check_ecc_deps, |
c3eea194 TT |
914 | .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), |
915 | .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), | |
916 | .dbgfs_name = "altr_ocram_trigger", | |
917 | .alloc_mem = ocram_alloc_mem, | |
918 | .free_mem = ocram_free_mem, | |
919 | .ecc_enable_mask = ALTR_OCR_ECC_EN, | |
943ad917 | 920 | .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 TT |
921 | .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), |
922 | .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), | |
811fce4f | 923 | .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 | 924 | .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, |
e17ced2c | 925 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
926 | }; |
927 | ||
c7b4be8d TT |
928 | const struct edac_device_prv_data a10_ocramecc_data = { |
929 | .setup = altr_check_ecc_deps, | |
930 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, | |
931 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
932 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, | |
933 | .dbgfs_name = "altr_ocram_trigger", | |
934 | .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, | |
935 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
936 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
937 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
938 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
939 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
940 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
941 | }; | |
942 | ||
c3eea194 TT |
943 | #endif /* CONFIG_EDAC_ALTERA_OCRAM */ |
944 | ||
945 | /********************* L2 Cache EDAC Device Functions ********************/ | |
946 | ||
947 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
948 | ||
949 | static void *l2_alloc_mem(size_t size, void **other) | |
950 | { | |
951 | struct device *dev = *other; | |
952 | void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); | |
953 | ||
954 | if (!ptemp) | |
955 | return NULL; | |
956 | ||
957 | /* Make sure everything is written out */ | |
958 | wmb(); | |
959 | ||
960 | /* | |
961 | * Clean all cache levels up to LoC (includes L2) | |
962 | * This ensures the corrupted data is written into | |
963 | * L2 cache for readback test (which causes ECC error). | |
964 | */ | |
965 | flush_cache_all(); | |
966 | ||
967 | return ptemp; | |
968 | } | |
969 | ||
970 | static void l2_free_mem(void *p, size_t size, void *other) | |
971 | { | |
972 | struct device *dev = other; | |
973 | ||
974 | if (dev && p) | |
975 | devm_kfree(dev, p); | |
976 | } | |
977 | ||
978 | /* | |
979 | * altr_l2_check_deps() | |
980 | * Test for L2 cache ECC dependencies upon entry because | |
981 | * platform specific startup should have initialized the L2 | |
982 | * memory and enabled the ECC. | |
983 | * Bail if ECC is not enabled. | |
984 | * Note that L2 Cache Enable is forced at build time. | |
985 | */ | |
328ca7ae | 986 | static int altr_l2_check_deps(struct altr_edac_device_dev *device) |
c3eea194 | 987 | { |
328ca7ae | 988 | void __iomem *base = device->base; |
27439a1a TT |
989 | const struct edac_device_prv_data *prv = device->data; |
990 | ||
991 | if ((readl(base) & prv->ecc_enable_mask) == | |
992 | prv->ecc_enable_mask) | |
c3eea194 TT |
993 | return 0; |
994 | ||
995 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
996 | "L2: No ECC present, or ECC disabled\n"); | |
997 | return -ENODEV; | |
998 | } | |
999 | ||
13ab8448 | 1000 | static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) |
588cb03e | 1001 | { |
13ab8448 TT |
1002 | struct altr_edac_device_dev *dci = dev_id; |
1003 | ||
1004 | if (irq == dci->sb_irq) { | |
588cb03e TT |
1005 | regmap_write(dci->edac->ecc_mgr_map, |
1006 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1007 | A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); | |
1008 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
13ab8448 TT |
1009 | |
1010 | return IRQ_HANDLED; | |
1011 | } else if (irq == dci->db_irq) { | |
588cb03e TT |
1012 | regmap_write(dci->edac->ecc_mgr_map, |
1013 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1014 | A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); | |
1015 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1016 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
13ab8448 TT |
1017 | |
1018 | return IRQ_HANDLED; | |
588cb03e | 1019 | } |
13ab8448 TT |
1020 | |
1021 | WARN_ON(1); | |
1022 | ||
1023 | return IRQ_NONE; | |
588cb03e TT |
1024 | } |
1025 | ||
c3eea194 TT |
1026 | const struct edac_device_prv_data l2ecc_data = { |
1027 | .setup = altr_l2_check_deps, | |
1028 | .ce_clear_mask = 0, | |
1029 | .ue_clear_mask = 0, | |
1030 | .dbgfs_name = "altr_l2_trigger", | |
1031 | .alloc_mem = l2_alloc_mem, | |
1032 | .free_mem = l2_free_mem, | |
1033 | .ecc_enable_mask = ALTR_L2_ECC_EN, | |
1034 | .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), | |
1035 | .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), | |
811fce4f | 1036 | .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, |
c3eea194 | 1037 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, |
e17ced2c | 1038 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1039 | }; |
1040 | ||
588cb03e TT |
1041 | const struct edac_device_prv_data a10_l2ecc_data = { |
1042 | .setup = altr_l2_check_deps, | |
1043 | .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, | |
1044 | .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, | |
1045 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, | |
1046 | .dbgfs_name = "altr_l2_trigger", | |
1047 | .alloc_mem = l2_alloc_mem, | |
1048 | .free_mem = l2_free_mem, | |
1049 | .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, | |
1050 | .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, | |
1051 | .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, | |
1052 | .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, | |
1053 | .ecc_irq_handler = altr_edac_a10_l2_irq, | |
1054 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, | |
e17ced2c | 1055 | .inject_fops = &altr_edac_device_inject_fops, |
588cb03e TT |
1056 | }; |
1057 | ||
c3eea194 TT |
1058 | #endif /* CONFIG_EDAC_ALTERA_L2C */ |
1059 | ||
588cb03e TT |
1060 | /********************* Arria10 EDAC Device Functions *************************/ |
1061 | ||
1062 | /* | |
1063 | * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 | |
1064 | * because 2 IRQs are shared among the all ECC peripherals. The ECC | |
1065 | * manager manages the IRQs and the children. | |
1066 | * Based on xgene_edac.c peripheral code. | |
1067 | */ | |
1068 | ||
c7b4be8d TT |
1069 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
1070 | const char __user *user_buf, | |
1071 | size_t count, loff_t *ppos) | |
1072 | { | |
1073 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
1074 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
1075 | const struct edac_device_prv_data *priv = drvdata->data; | |
1076 | void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); | |
1077 | unsigned long flags; | |
1078 | u8 trig_type; | |
1079 | ||
1080 | if (!user_buf || get_user(trig_type, user_buf)) | |
1081 | return -EFAULT; | |
1082 | ||
1083 | local_irq_save(flags); | |
1084 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
1085 | writel(priv->ue_set_mask, set_addr); | |
1086 | else | |
1087 | writel(priv->ce_set_mask, set_addr); | |
1088 | /* Ensure the interrupt test bits are set */ | |
1089 | wmb(); | |
1090 | local_irq_restore(flags); | |
1091 | ||
1092 | return count; | |
1093 | } | |
1094 | ||
13ab8448 | 1095 | static void altr_edac_a10_irq_handler(struct irq_desc *desc) |
588cb03e | 1096 | { |
13ab8448 TT |
1097 | int dberr, bit, sm_offset, irq_status; |
1098 | struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); | |
1099 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1100 | int irq = irq_desc_get_irq(desc); | |
1101 | ||
1102 | dberr = (irq == edac->db_irq) ? 1 : 0; | |
1103 | sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : | |
1104 | A10_SYSMGR_ECC_INTSTAT_SERR_OFST; | |
1105 | ||
1106 | chained_irq_enter(chip, desc); | |
588cb03e TT |
1107 | |
1108 | regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); | |
1109 | ||
13ab8448 TT |
1110 | for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { |
1111 | irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); | |
1112 | if (irq) | |
1113 | generic_handle_irq(irq); | |
588cb03e TT |
1114 | } |
1115 | ||
13ab8448 | 1116 | chained_irq_exit(chip, desc); |
588cb03e TT |
1117 | } |
1118 | ||
1119 | static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, | |
1120 | struct device_node *np) | |
1121 | { | |
1122 | struct edac_device_ctl_info *dci; | |
1123 | struct altr_edac_device_dev *altdev; | |
1124 | char *ecc_name = (char *)np->name; | |
1125 | struct resource res; | |
1126 | int edac_idx; | |
1127 | int rc = 0; | |
1128 | const struct edac_device_prv_data *prv; | |
1129 | /* Get matching node and check for valid result */ | |
1130 | const struct of_device_id *pdev_id = | |
1131 | of_match_node(altr_edac_device_of_match, np); | |
1132 | if (IS_ERR_OR_NULL(pdev_id)) | |
1133 | return -ENODEV; | |
1134 | ||
1135 | /* Get driver specific data for this EDAC device */ | |
1136 | prv = pdev_id->data; | |
1137 | if (IS_ERR_OR_NULL(prv)) | |
1138 | return -ENODEV; | |
1139 | ||
1140 | if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) | |
1141 | return -ENOMEM; | |
1142 | ||
1143 | rc = of_address_to_resource(np, 0, &res); | |
1144 | if (rc < 0) { | |
1145 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1146 | "%s: no resource address\n", ecc_name); | |
1147 | goto err_release_group; | |
1148 | } | |
1149 | ||
1150 | edac_idx = edac_device_alloc_index(); | |
1151 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, | |
1152 | 1, ecc_name, 1, 0, NULL, 0, | |
1153 | edac_idx); | |
1154 | ||
1155 | if (!dci) { | |
1156 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1157 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
1158 | rc = -ENOMEM; | |
1159 | goto err_release_group; | |
1160 | } | |
1161 | ||
1162 | altdev = dci->pvt_info; | |
1163 | dci->dev = edac->dev; | |
1164 | altdev->edac_dev_name = ecc_name; | |
1165 | altdev->edac_idx = edac_idx; | |
1166 | altdev->edac = edac; | |
1167 | altdev->edac_dev = dci; | |
1168 | altdev->data = prv; | |
1169 | altdev->ddev = *edac->dev; | |
1170 | dci->dev = &altdev->ddev; | |
1171 | dci->ctl_name = "Altera ECC Manager"; | |
1172 | dci->mod_name = ecc_name; | |
1173 | dci->dev_name = ecc_name; | |
1174 | ||
1175 | altdev->base = devm_ioremap_resource(edac->dev, &res); | |
1176 | if (IS_ERR(altdev->base)) { | |
1177 | rc = PTR_ERR(altdev->base); | |
1178 | goto err_release_group1; | |
1179 | } | |
1180 | ||
1181 | /* Check specific dependencies for the module */ | |
1182 | if (altdev->data->setup) { | |
1183 | rc = altdev->data->setup(altdev); | |
1184 | if (rc) | |
1185 | goto err_release_group1; | |
1186 | } | |
1187 | ||
13ab8448 TT |
1188 | altdev->sb_irq = irq_of_parse_and_map(np, 0); |
1189 | if (!altdev->sb_irq) { | |
1190 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); | |
1191 | rc = -ENODEV; | |
1192 | goto err_release_group1; | |
1193 | } | |
1194 | rc = devm_request_irq(edac->dev, altdev->sb_irq, | |
1195 | prv->ecc_irq_handler, | |
1196 | IRQF_SHARED, ecc_name, altdev); | |
1197 | if (rc) { | |
1198 | edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); | |
1199 | goto err_release_group1; | |
1200 | } | |
1201 | ||
1202 | altdev->db_irq = irq_of_parse_and_map(np, 1); | |
1203 | if (!altdev->db_irq) { | |
1204 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); | |
1205 | rc = -ENODEV; | |
1206 | goto err_release_group1; | |
1207 | } | |
1208 | rc = devm_request_irq(edac->dev, altdev->db_irq, | |
1209 | prv->ecc_irq_handler, | |
1210 | IRQF_SHARED, ecc_name, altdev); | |
1211 | if (rc) { | |
1212 | edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); | |
1213 | goto err_release_group1; | |
1214 | } | |
1215 | ||
588cb03e TT |
1216 | rc = edac_device_add_device(dci); |
1217 | if (rc) { | |
1218 | dev_err(edac->dev, "edac_device_add_device failed\n"); | |
1219 | rc = -ENOMEM; | |
1220 | goto err_release_group1; | |
1221 | } | |
1222 | ||
1223 | altr_create_edacdev_dbgfs(dci, prv); | |
1224 | ||
1225 | list_add(&altdev->next, &edac->a10_ecc_devices); | |
1226 | ||
1227 | devres_remove_group(edac->dev, altr_edac_a10_device_add); | |
1228 | ||
1229 | return 0; | |
1230 | ||
1231 | err_release_group1: | |
1232 | edac_device_free_ctl_info(dci); | |
1233 | err_release_group: | |
588cb03e TT |
1234 | devres_release_group(edac->dev, NULL); |
1235 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1236 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1237 | ||
1238 | return rc; | |
1239 | } | |
1240 | ||
13ab8448 TT |
1241 | static void a10_eccmgr_irq_mask(struct irq_data *d) |
1242 | { | |
1243 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
1244 | ||
1245 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, | |
1246 | BIT(d->hwirq)); | |
1247 | } | |
1248 | ||
1249 | static void a10_eccmgr_irq_unmask(struct irq_data *d) | |
1250 | { | |
1251 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
1252 | ||
1253 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, | |
1254 | BIT(d->hwirq)); | |
1255 | } | |
1256 | ||
1257 | static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
1258 | irq_hw_number_t hwirq) | |
1259 | { | |
1260 | struct altr_arria10_edac *edac = d->host_data; | |
1261 | ||
1262 | irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); | |
1263 | irq_set_chip_data(irq, edac); | |
1264 | irq_set_noprobe(irq); | |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | struct irq_domain_ops a10_eccmgr_ic_ops = { | |
1270 | .map = a10_eccmgr_irqdomain_map, | |
1271 | .xlate = irq_domain_xlate_twocell, | |
1272 | }; | |
1273 | ||
588cb03e TT |
1274 | static int altr_edac_a10_probe(struct platform_device *pdev) |
1275 | { | |
1276 | struct altr_arria10_edac *edac; | |
1277 | struct device_node *child; | |
588cb03e TT |
1278 | |
1279 | edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); | |
1280 | if (!edac) | |
1281 | return -ENOMEM; | |
1282 | ||
1283 | edac->dev = &pdev->dev; | |
1284 | platform_set_drvdata(pdev, edac); | |
1285 | INIT_LIST_HEAD(&edac->a10_ecc_devices); | |
1286 | ||
1287 | edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
1288 | "altr,sysmgr-syscon"); | |
1289 | if (IS_ERR(edac->ecc_mgr_map)) { | |
1290 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1291 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
1292 | return PTR_ERR(edac->ecc_mgr_map); | |
1293 | } | |
1294 | ||
13ab8448 TT |
1295 | edac->irq_chip.name = pdev->dev.of_node->name; |
1296 | edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; | |
1297 | edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; | |
1298 | edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, | |
1299 | &a10_eccmgr_ic_ops, edac); | |
1300 | if (!edac->domain) { | |
1301 | dev_err(&pdev->dev, "Error adding IRQ domain\n"); | |
1302 | return -ENOMEM; | |
1303 | } | |
1304 | ||
588cb03e | 1305 | edac->sb_irq = platform_get_irq(pdev, 0); |
13ab8448 TT |
1306 | if (edac->sb_irq < 0) { |
1307 | dev_err(&pdev->dev, "No SBERR IRQ resource\n"); | |
1308 | return edac->sb_irq; | |
588cb03e TT |
1309 | } |
1310 | ||
13ab8448 TT |
1311 | irq_set_chained_handler_and_data(edac->sb_irq, |
1312 | altr_edac_a10_irq_handler, | |
1313 | edac); | |
1314 | ||
588cb03e | 1315 | edac->db_irq = platform_get_irq(pdev, 1); |
13ab8448 TT |
1316 | if (edac->db_irq < 0) { |
1317 | dev_err(&pdev->dev, "No DBERR IRQ resource\n"); | |
1318 | return edac->db_irq; | |
588cb03e | 1319 | } |
13ab8448 TT |
1320 | irq_set_chained_handler_and_data(edac->db_irq, |
1321 | altr_edac_a10_irq_handler, | |
1322 | edac); | |
588cb03e TT |
1323 | |
1324 | for_each_child_of_node(pdev->dev.of_node, child) { | |
1325 | if (!of_device_is_available(child)) | |
1326 | continue; | |
1327 | if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc")) | |
1328 | altr_edac_a10_device_add(edac, child); | |
c7b4be8d TT |
1329 | else if (of_device_is_compatible(child, |
1330 | "altr,socfpga-a10-ocram-ecc")) | |
1331 | altr_edac_a10_device_add(edac, child); | |
588cb03e TT |
1332 | } |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | static const struct of_device_id altr_edac_a10_of_match[] = { | |
1338 | { .compatible = "altr,socfpga-a10-ecc-manager" }, | |
1339 | {}, | |
1340 | }; | |
1341 | MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); | |
1342 | ||
1343 | static struct platform_driver altr_edac_a10_driver = { | |
1344 | .probe = altr_edac_a10_probe, | |
1345 | .driver = { | |
1346 | .name = "socfpga_a10_ecc_manager", | |
1347 | .of_match_table = altr_edac_a10_of_match, | |
1348 | }, | |
1349 | }; | |
1350 | module_platform_driver(altr_edac_a10_driver); | |
1351 | ||
71bcada8 TT |
1352 | MODULE_LICENSE("GPL v2"); |
1353 | MODULE_AUTHOR("Thor Thayer"); | |
c3eea194 | 1354 | MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); |