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3dab6bd5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
71bcada8 | 2 | /* |
3dab6bd5 | 3 | * Copyright (C) 2017-2018, Intel Corporation. All rights reserved |
c3eea194 | 4 | * Copyright Altera Corporation (C) 2014-2016. All rights reserved. |
71bcada8 | 5 | * Copyright 2011-2012 Calxeda, Inc. |
71bcada8 TT |
6 | */ |
7 | ||
c3eea194 | 8 | #include <asm/cacheflush.h> |
71bcada8 | 9 | #include <linux/ctype.h> |
1166fde9 | 10 | #include <linux/delay.h> |
71bcada8 | 11 | #include <linux/edac.h> |
fad9fab9 | 12 | #include <linux/firmware/intel/stratix10-smc.h> |
c3eea194 | 13 | #include <linux/genalloc.h> |
71bcada8 | 14 | #include <linux/interrupt.h> |
13ab8448 | 15 | #include <linux/irqchip/chained_irq.h> |
71bcada8 TT |
16 | #include <linux/kernel.h> |
17 | #include <linux/mfd/syscon.h> | |
e9918d7f | 18 | #include <linux/notifier.h> |
588cb03e | 19 | #include <linux/of_address.h> |
13ab8448 | 20 | #include <linux/of_irq.h> |
71bcada8 TT |
21 | #include <linux/of_platform.h> |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/regmap.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/uaccess.h> | |
26 | ||
143f4a5a | 27 | #include "altera_edac.h" |
71bcada8 TT |
28 | #include "edac_module.h" |
29 | ||
30 | #define EDAC_MOD_STR "altera_edac" | |
c3eea194 | 31 | #define EDAC_DEVICE "Altera" |
71bcada8 | 32 | |
580b5cf5 | 33 | #ifdef CONFIG_EDAC_ALTERA_SDRAM |
143f4a5a TT |
34 | static const struct altr_sdram_prv_data c5_data = { |
35 | .ecc_ctrl_offset = CV_CTLCFG_OFST, | |
36 | .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, | |
37 | .ecc_stat_offset = CV_DRAMSTS_OFST, | |
38 | .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, | |
39 | .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, | |
40 | .ecc_saddr_offset = CV_ERRADDR_OFST, | |
73bcc942 | 41 | .ecc_daddr_offset = CV_ERRADDR_OFST, |
143f4a5a TT |
42 | .ecc_cecnt_offset = CV_SBECOUNT_OFST, |
43 | .ecc_uecnt_offset = CV_DBECOUNT_OFST, | |
44 | .ecc_irq_en_offset = CV_DRAMINTR_OFST, | |
45 | .ecc_irq_en_mask = CV_DRAMINTR_INTREN, | |
46 | .ecc_irq_clr_offset = CV_DRAMINTR_OFST, | |
47 | .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), | |
48 | .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, | |
49 | .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, | |
143f4a5a TT |
50 | .ce_ue_trgr_offset = CV_CTLCFG_OFST, |
51 | .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, | |
52 | .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, | |
71bcada8 TT |
53 | }; |
54 | ||
73bcc942 TT |
55 | static const struct altr_sdram_prv_data a10_data = { |
56 | .ecc_ctrl_offset = A10_ECCCTRL1_OFST, | |
57 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
58 | .ecc_stat_offset = A10_INTSTAT_OFST, | |
59 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
60 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
61 | .ecc_saddr_offset = A10_SERRADDR_OFST, | |
62 | .ecc_daddr_offset = A10_DERRADDR_OFST, | |
63 | .ecc_irq_en_offset = A10_ERRINTEN_OFST, | |
64 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
65 | .ecc_irq_clr_offset = A10_INTSTAT_OFST, | |
66 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
67 | .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, | |
68 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
73bcc942 TT |
69 | .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, |
70 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
71 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
73bcc942 TT |
72 | }; |
73 | ||
c3eea194 TT |
74 | /*********************** EDAC Memory Controller Functions ****************/ |
75 | ||
76 | /* The SDRAM controller uses the EDAC Memory Controller framework. */ | |
77 | ||
71bcada8 TT |
78 | static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) |
79 | { | |
80 | struct mem_ctl_info *mci = dev_id; | |
81 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 82 | const struct altr_sdram_prv_data *priv = drvdata->data; |
73bcc942 | 83 | u32 status, err_count = 1, err_addr; |
71bcada8 | 84 | |
143f4a5a | 85 | regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); |
71bcada8 | 86 | |
143f4a5a | 87 | if (status & priv->ecc_stat_ue_mask) { |
73bcc942 TT |
88 | regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, |
89 | &err_addr); | |
90 | if (priv->ecc_uecnt_offset) | |
91 | regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, | |
92 | &err_count); | |
71bcada8 TT |
93 | panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", |
94 | err_count, err_addr); | |
95 | } | |
143f4a5a | 96 | if (status & priv->ecc_stat_ce_mask) { |
73bcc942 TT |
97 | regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, |
98 | &err_addr); | |
99 | if (priv->ecc_uecnt_offset) | |
100 | regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, | |
101 | &err_count); | |
71bcada8 TT |
102 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, |
103 | err_addr >> PAGE_SHIFT, | |
104 | err_addr & ~PAGE_MASK, 0, | |
105 | 0, 0, -1, mci->ctl_name, ""); | |
73bcc942 TT |
106 | /* Clear IRQ to resume */ |
107 | regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, | |
108 | priv->ecc_irq_clr_mask); | |
71bcada8 | 109 | |
73bcc942 TT |
110 | return IRQ_HANDLED; |
111 | } | |
112 | return IRQ_NONE; | |
71bcada8 TT |
113 | } |
114 | ||
71bcada8 TT |
115 | static ssize_t altr_sdr_mc_err_inject_write(struct file *file, |
116 | const char __user *data, | |
117 | size_t count, loff_t *ppos) | |
118 | { | |
119 | struct mem_ctl_info *mci = file->private_data; | |
120 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 121 | const struct altr_sdram_prv_data *priv = drvdata->data; |
71bcada8 TT |
122 | u32 *ptemp; |
123 | dma_addr_t dma_handle; | |
124 | u32 reg, read_reg; | |
125 | ||
126 | ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); | |
127 | if (!ptemp) { | |
128 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
129 | edac_printk(KERN_ERR, EDAC_MC, | |
130 | "Inject: Buffer Allocation error\n"); | |
131 | return -ENOMEM; | |
132 | } | |
133 | ||
143f4a5a TT |
134 | regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
135 | &read_reg); | |
136 | read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); | |
71bcada8 TT |
137 | |
138 | /* Error are injected by writing a word while the SBE or DBE | |
139 | * bit in the CTLCFG register is set. Reading the word will | |
140 | * trigger the SBE or DBE error and the corresponding IRQ. | |
141 | */ | |
142 | if (count == 3) { | |
143 | edac_printk(KERN_ALERT, EDAC_MC, | |
144 | "Inject Double bit error\n"); | |
90e493d7 | 145 | local_irq_disable(); |
143f4a5a TT |
146 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
147 | (read_reg | priv->ue_set_mask)); | |
90e493d7 | 148 | local_irq_enable(); |
71bcada8 TT |
149 | } else { |
150 | edac_printk(KERN_ALERT, EDAC_MC, | |
151 | "Inject Single bit error\n"); | |
90e493d7 | 152 | local_irq_disable(); |
143f4a5a TT |
153 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
154 | (read_reg | priv->ce_set_mask)); | |
90e493d7 | 155 | local_irq_enable(); |
71bcada8 TT |
156 | } |
157 | ||
158 | ptemp[0] = 0x5A5A5A5A; | |
159 | ptemp[1] = 0xA5A5A5A5; | |
160 | ||
161 | /* Clear the error injection bits */ | |
143f4a5a | 162 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); |
71bcada8 TT |
163 | /* Ensure it has been written out */ |
164 | wmb(); | |
165 | ||
166 | /* | |
167 | * To trigger the error, we need to read the data back | |
168 | * (the data was written with errors above). | |
332efa63 | 169 | * The READ_ONCE macros and printk are used to prevent the |
71bcada8 TT |
170 | * the compiler optimizing these reads out. |
171 | */ | |
332efa63 MR |
172 | reg = READ_ONCE(ptemp[0]); |
173 | read_reg = READ_ONCE(ptemp[1]); | |
71bcada8 TT |
174 | /* Force Read */ |
175 | rmb(); | |
176 | ||
177 | edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", | |
178 | reg, read_reg); | |
179 | ||
180 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
181 | ||
182 | return count; | |
183 | } | |
184 | ||
185 | static const struct file_operations altr_sdr_mc_debug_inject_fops = { | |
186 | .open = simple_open, | |
187 | .write = altr_sdr_mc_err_inject_write, | |
188 | .llseek = generic_file_llseek, | |
189 | }; | |
190 | ||
191 | static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) | |
192 | { | |
bba3b31e BP |
193 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) |
194 | return; | |
195 | ||
196 | if (!mci->debugfs) | |
197 | return; | |
198 | ||
b8978bad | 199 | edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, |
bba3b31e | 200 | &altr_sdr_mc_debug_inject_fops); |
71bcada8 | 201 | } |
71bcada8 | 202 | |
f9ae487e TT |
203 | /* Get total memory size from Open Firmware DTB */ |
204 | static unsigned long get_total_mem(void) | |
71bcada8 | 205 | { |
f9ae487e | 206 | struct device_node *np = NULL; |
ff0abed4 CP |
207 | struct resource res; |
208 | int ret; | |
209 | unsigned long total_mem = 0; | |
f9ae487e TT |
210 | |
211 | for_each_node_by_type(np, "memory") { | |
ff0abed4 CP |
212 | ret = of_address_to_resource(np, 0, &res); |
213 | if (ret) | |
214 | continue; | |
215 | ||
216 | total_mem += resource_size(&res); | |
f9ae487e TT |
217 | } |
218 | edac_dbg(0, "total_mem 0x%lx\n", total_mem); | |
219 | return total_mem; | |
71bcada8 TT |
220 | } |
221 | ||
143f4a5a | 222 | static const struct of_device_id altr_sdram_ctrl_of_match[] = { |
2c911f6c AB |
223 | { .compatible = "altr,sdram-edac", .data = &c5_data}, |
224 | { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, | |
08f08bfb | 225 | { .compatible = "altr,sdram-edac-s10", .data = &a10_data}, |
143f4a5a TT |
226 | {}, |
227 | }; | |
228 | MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); | |
229 | ||
73bcc942 TT |
230 | static int a10_init(struct regmap *mc_vbase) |
231 | { | |
232 | if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, | |
233 | A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { | |
234 | edac_printk(KERN_ERR, EDAC_MC, | |
235 | "Error setting SB IRQ mode\n"); | |
236 | return -ENODEV; | |
237 | } | |
238 | ||
239 | if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { | |
240 | edac_printk(KERN_ERR, EDAC_MC, | |
241 | "Error setting trigger count\n"); | |
242 | return -ENODEV; | |
243 | } | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | static int a10_unmask_irq(struct platform_device *pdev, u32 mask) | |
249 | { | |
250 | void __iomem *sm_base; | |
251 | int ret = 0; | |
252 | ||
253 | if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), | |
254 | dev_name(&pdev->dev))) { | |
255 | edac_printk(KERN_ERR, EDAC_MC, | |
256 | "Unable to request mem region\n"); | |
257 | return -EBUSY; | |
258 | } | |
259 | ||
260 | sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
261 | if (!sm_base) { | |
262 | edac_printk(KERN_ERR, EDAC_MC, | |
263 | "Unable to ioremap device\n"); | |
264 | ||
265 | ret = -ENOMEM; | |
266 | goto release; | |
267 | } | |
268 | ||
269 | iowrite32(mask, sm_base); | |
270 | ||
271 | iounmap(sm_base); | |
272 | ||
273 | release: | |
274 | release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
275 | ||
276 | return ret; | |
277 | } | |
278 | ||
08f08bfb | 279 | static int socfpga_is_a10(void); |
71bcada8 TT |
280 | static int altr_sdram_probe(struct platform_device *pdev) |
281 | { | |
143f4a5a | 282 | const struct of_device_id *id; |
71bcada8 TT |
283 | struct edac_mc_layer layers[2]; |
284 | struct mem_ctl_info *mci; | |
285 | struct altr_sdram_mc_data *drvdata; | |
143f4a5a | 286 | const struct altr_sdram_prv_data *priv; |
71bcada8 TT |
287 | struct regmap *mc_vbase; |
288 | struct dimm_info *dimm; | |
143f4a5a | 289 | u32 read_reg; |
73bcc942 TT |
290 | int irq, irq2, res = 0; |
291 | unsigned long mem_size, irqflags = 0; | |
143f4a5a TT |
292 | |
293 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
294 | if (!id) | |
295 | return -ENODEV; | |
71bcada8 | 296 | |
71bcada8 TT |
297 | /* Grab the register range from the sdr controller in device tree */ |
298 | mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
299 | "altr,sdr-syscon"); | |
300 | if (IS_ERR(mc_vbase)) { | |
301 | edac_printk(KERN_ERR, EDAC_MC, | |
302 | "regmap for altr,sdr-syscon lookup failed.\n"); | |
303 | return -ENODEV; | |
304 | } | |
305 | ||
143f4a5a TT |
306 | /* Check specific dependencies for the module */ |
307 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
308 | pdev->dev.of_node)->data; | |
309 | ||
310 | /* Validate the SDRAM controller has ECC enabled */ | |
311 | if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || | |
312 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
71bcada8 TT |
313 | edac_printk(KERN_ERR, EDAC_MC, |
314 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
315 | return -ENODEV; | |
316 | } | |
317 | ||
318 | /* Grab memory size from device tree. */ | |
f9ae487e | 319 | mem_size = get_total_mem(); |
71bcada8 | 320 | if (!mem_size) { |
f9ae487e | 321 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); |
71bcada8 TT |
322 | return -ENODEV; |
323 | } | |
324 | ||
143f4a5a TT |
325 | /* Ensure the SDRAM Interrupt is disabled */ |
326 | if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, | |
327 | priv->ecc_irq_en_mask, 0)) { | |
328 | edac_printk(KERN_ERR, EDAC_MC, | |
329 | "Error disabling SDRAM ECC IRQ\n"); | |
330 | return -ENODEV; | |
331 | } | |
332 | ||
333 | /* Toggle to clear the SDRAM Error count */ | |
334 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
335 | priv->ecc_cnt_rst_mask, | |
336 | priv->ecc_cnt_rst_mask)) { | |
337 | edac_printk(KERN_ERR, EDAC_MC, | |
338 | "Error clearing SDRAM ECC count\n"); | |
339 | return -ENODEV; | |
340 | } | |
341 | ||
342 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
343 | priv->ecc_cnt_rst_mask, 0)) { | |
71bcada8 | 344 | edac_printk(KERN_ERR, EDAC_MC, |
143f4a5a | 345 | "Error clearing SDRAM ECC count\n"); |
71bcada8 TT |
346 | return -ENODEV; |
347 | } | |
348 | ||
349 | irq = platform_get_irq(pdev, 0); | |
350 | if (irq < 0) { | |
351 | edac_printk(KERN_ERR, EDAC_MC, | |
352 | "No irq %d in DT\n", irq); | |
353 | return -ENODEV; | |
354 | } | |
355 | ||
73bcc942 TT |
356 | /* Arria10 has a 2nd IRQ */ |
357 | irq2 = platform_get_irq(pdev, 1); | |
358 | ||
71bcada8 TT |
359 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
360 | layers[0].size = 1; | |
361 | layers[0].is_virt_csrow = true; | |
362 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
363 | layers[1].size = 1; | |
364 | layers[1].is_virt_csrow = false; | |
365 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
366 | sizeof(struct altr_sdram_mc_data)); | |
367 | if (!mci) | |
368 | return -ENOMEM; | |
369 | ||
370 | mci->pdev = &pdev->dev; | |
371 | drvdata = mci->pvt_info; | |
372 | drvdata->mc_vbase = mc_vbase; | |
143f4a5a | 373 | drvdata->data = priv; |
71bcada8 TT |
374 | platform_set_drvdata(pdev, mci); |
375 | ||
376 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
143f4a5a TT |
377 | edac_printk(KERN_ERR, EDAC_MC, |
378 | "Unable to get managed device resource\n"); | |
71bcada8 TT |
379 | res = -ENOMEM; |
380 | goto free; | |
381 | } | |
382 | ||
383 | mci->mtype_cap = MEM_FLAG_DDR3; | |
384 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
385 | mci->edac_cap = EDAC_FLAG_SECDED; | |
386 | mci->mod_name = EDAC_MOD_STR; | |
71bcada8 TT |
387 | mci->ctl_name = dev_name(&pdev->dev); |
388 | mci->scrub_mode = SCRUB_SW_SRC; | |
389 | mci->dev_name = dev_name(&pdev->dev); | |
390 | ||
391 | dimm = *mci->dimms; | |
392 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
393 | dimm->grain = 8; | |
394 | dimm->dtype = DEV_X8; | |
395 | dimm->mtype = MEM_DDR3; | |
396 | dimm->edac_mode = EDAC_SECDED; | |
397 | ||
398 | res = edac_mc_add_mc(mci); | |
399 | if (res < 0) | |
400 | goto err; | |
401 | ||
73bcc942 | 402 | /* Only the Arria10 has separate IRQs */ |
08f08bfb | 403 | if (socfpga_is_a10()) { |
73bcc942 TT |
404 | /* Arria10 specific initialization */ |
405 | res = a10_init(mc_vbase); | |
406 | if (res < 0) | |
407 | goto err2; | |
408 | ||
409 | res = devm_request_irq(&pdev->dev, irq2, | |
410 | altr_sdram_mc_err_handler, | |
411 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
412 | if (res < 0) { | |
413 | edac_mc_printk(mci, KERN_ERR, | |
414 | "Unable to request irq %d\n", irq2); | |
415 | res = -ENODEV; | |
416 | goto err2; | |
417 | } | |
418 | ||
419 | res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); | |
420 | if (res < 0) | |
421 | goto err2; | |
422 | ||
423 | irqflags = IRQF_SHARED; | |
424 | } | |
425 | ||
71bcada8 | 426 | res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, |
73bcc942 | 427 | irqflags, dev_name(&pdev->dev), mci); |
71bcada8 TT |
428 | if (res < 0) { |
429 | edac_mc_printk(mci, KERN_ERR, | |
430 | "Unable to request irq %d\n", irq); | |
431 | res = -ENODEV; | |
432 | goto err2; | |
433 | } | |
434 | ||
143f4a5a TT |
435 | /* Infrastructure ready - enable the IRQ */ |
436 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, | |
437 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
71bcada8 TT |
438 | edac_mc_printk(mci, KERN_ERR, |
439 | "Error enabling SDRAM ECC IRQ\n"); | |
440 | res = -ENODEV; | |
441 | goto err2; | |
442 | } | |
443 | ||
444 | altr_sdr_mc_create_debugfs_nodes(mci); | |
445 | ||
446 | devres_close_group(&pdev->dev, NULL); | |
447 | ||
448 | return 0; | |
449 | ||
450 | err2: | |
451 | edac_mc_del_mc(&pdev->dev); | |
452 | err: | |
453 | devres_release_group(&pdev->dev, NULL); | |
454 | free: | |
455 | edac_mc_free(mci); | |
456 | edac_printk(KERN_ERR, EDAC_MC, | |
457 | "EDAC Probe Failed; Error %d\n", res); | |
458 | ||
459 | return res; | |
460 | } | |
461 | ||
462 | static int altr_sdram_remove(struct platform_device *pdev) | |
463 | { | |
464 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
465 | ||
466 | edac_mc_del_mc(&pdev->dev); | |
467 | edac_mc_free(mci); | |
468 | platform_set_drvdata(pdev, NULL); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
580b5cf5 TT |
473 | /* |
474 | * If you want to suspend, need to disable EDAC by removing it | |
475 | * from the device tree or defconfig. | |
476 | */ | |
477 | #ifdef CONFIG_PM | |
478 | static int altr_sdram_prepare(struct device *dev) | |
479 | { | |
480 | pr_err("Suspend not allowed when EDAC is enabled.\n"); | |
481 | ||
482 | return -EPERM; | |
483 | } | |
484 | ||
485 | static const struct dev_pm_ops altr_sdram_pm_ops = { | |
486 | .prepare = altr_sdram_prepare, | |
487 | }; | |
488 | #endif | |
489 | ||
490 | static struct platform_driver altr_sdram_edac_driver = { | |
491 | .probe = altr_sdram_probe, | |
492 | .remove = altr_sdram_remove, | |
493 | .driver = { | |
494 | .name = "altr_sdram_edac", | |
495 | #ifdef CONFIG_PM | |
496 | .pm = &altr_sdram_pm_ops, | |
497 | #endif | |
498 | .of_match_table = altr_sdram_ctrl_of_match, | |
499 | }, | |
500 | }; | |
501 | ||
502 | module_platform_driver(altr_sdram_edac_driver); | |
503 | ||
504 | #endif /* CONFIG_EDAC_ALTERA_SDRAM */ | |
505 | ||
3dab6bd5 TT |
506 | /**************** Stratix 10 EDAC Memory Controller Functions ************/ |
507 | ||
508 | /** | |
509 | * s10_protected_reg_write | |
510 | * Write to a protected SMC register. | |
511 | * @context: Not used. | |
512 | * @reg: Address of register | |
513 | * @value: Value to write | |
514 | * Return: INTEL_SIP_SMC_STATUS_OK (0) on success | |
515 | * INTEL_SIP_SMC_REG_ERROR on error | |
516 | * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported | |
517 | */ | |
518 | static int s10_protected_reg_write(void *context, unsigned int reg, | |
519 | unsigned int val) | |
520 | { | |
521 | struct arm_smccc_res result; | |
08f08bfb | 522 | unsigned long offset = (unsigned long)context; |
3dab6bd5 | 523 | |
08f08bfb | 524 | arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0, |
3dab6bd5 TT |
525 | 0, 0, 0, &result); |
526 | ||
527 | return (int)result.a0; | |
528 | } | |
529 | ||
530 | /** | |
531 | * s10_protected_reg_read | |
532 | * Read the status of a protected SMC register | |
533 | * @context: Not used. | |
534 | * @reg: Address of register | |
535 | * @value: Value read. | |
536 | * Return: INTEL_SIP_SMC_STATUS_OK (0) on success | |
537 | * INTEL_SIP_SMC_REG_ERROR on error | |
538 | * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported | |
539 | */ | |
540 | static int s10_protected_reg_read(void *context, unsigned int reg, | |
541 | unsigned int *val) | |
542 | { | |
543 | struct arm_smccc_res result; | |
08f08bfb | 544 | unsigned long offset = (unsigned long)context; |
3dab6bd5 | 545 | |
08f08bfb | 546 | arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0, |
3dab6bd5 TT |
547 | 0, 0, 0, &result); |
548 | ||
549 | *val = (unsigned int)result.a1; | |
550 | ||
551 | return (int)result.a0; | |
552 | } | |
553 | ||
3dab6bd5 TT |
554 | static const struct regmap_config s10_sdram_regmap_cfg = { |
555 | .name = "s10_ddr", | |
556 | .reg_bits = 32, | |
557 | .reg_stride = 4, | |
558 | .val_bits = 32, | |
08f08bfb | 559 | .max_register = 0xffd12228, |
3dab6bd5 TT |
560 | .reg_read = s10_protected_reg_read, |
561 | .reg_write = s10_protected_reg_write, | |
1c96a2f6 DF |
562 | .use_single_read = true, |
563 | .use_single_write = true, | |
3dab6bd5 TT |
564 | }; |
565 | ||
3dab6bd5 TT |
566 | /************** </Stratix10 EDAC Memory Controller Functions> ***********/ |
567 | ||
c3eea194 TT |
568 | /************************* EDAC Parent Probe *************************/ |
569 | ||
570 | static const struct of_device_id altr_edac_device_of_match[]; | |
571 | ||
572 | static const struct of_device_id altr_edac_of_match[] = { | |
573 | { .compatible = "altr,socfpga-ecc-manager" }, | |
574 | {}, | |
575 | }; | |
576 | MODULE_DEVICE_TABLE(of, altr_edac_of_match); | |
577 | ||
578 | static int altr_edac_probe(struct platform_device *pdev) | |
579 | { | |
580 | of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, | |
581 | NULL, &pdev->dev); | |
582 | return 0; | |
583 | } | |
584 | ||
585 | static struct platform_driver altr_edac_driver = { | |
586 | .probe = altr_edac_probe, | |
587 | .driver = { | |
588 | .name = "socfpga_ecc_manager", | |
589 | .of_match_table = altr_edac_of_match, | |
590 | }, | |
591 | }; | |
592 | module_platform_driver(altr_edac_driver); | |
593 | ||
594 | /************************* EDAC Device Functions *************************/ | |
595 | ||
596 | /* | |
597 | * EDAC Device Functions (shared between various IPs). | |
598 | * The discrete memories use the EDAC Device framework. The probe | |
599 | * and error handling functions are very similar between memories | |
600 | * so they are shared. The memory allocation and freeing for EDAC | |
601 | * trigger testing are different for each memory. | |
602 | */ | |
603 | ||
1cf70377 TT |
604 | static const struct edac_device_prv_data ocramecc_data; |
605 | static const struct edac_device_prv_data l2ecc_data; | |
606 | static const struct edac_device_prv_data a10_ocramecc_data; | |
607 | static const struct edac_device_prv_data a10_l2ecc_data; | |
c3eea194 | 608 | |
c3eea194 TT |
609 | static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) |
610 | { | |
611 | irqreturn_t ret_value = IRQ_NONE; | |
612 | struct edac_device_ctl_info *dci = dev_id; | |
613 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
614 | const struct edac_device_prv_data *priv = drvdata->data; | |
615 | ||
616 | if (irq == drvdata->sb_irq) { | |
617 | if (priv->ce_clear_mask) | |
618 | writel(priv->ce_clear_mask, drvdata->base); | |
619 | edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); | |
620 | ret_value = IRQ_HANDLED; | |
621 | } else if (irq == drvdata->db_irq) { | |
622 | if (priv->ue_clear_mask) | |
623 | writel(priv->ue_clear_mask, drvdata->base); | |
624 | edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); | |
625 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
626 | ret_value = IRQ_HANDLED; | |
627 | } else { | |
628 | WARN_ON(1); | |
629 | } | |
630 | ||
631 | return ret_value; | |
632 | } | |
633 | ||
634 | static ssize_t altr_edac_device_trig(struct file *file, | |
635 | const char __user *user_buf, | |
636 | size_t count, loff_t *ppos) | |
637 | ||
638 | { | |
639 | u32 *ptemp, i, error_mask; | |
640 | int result = 0; | |
641 | u8 trig_type; | |
642 | unsigned long flags; | |
643 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
644 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
645 | const struct edac_device_prv_data *priv = drvdata->data; | |
646 | void *generic_ptr = edac_dci->dev; | |
647 | ||
648 | if (!user_buf || get_user(trig_type, user_buf)) | |
649 | return -EFAULT; | |
650 | ||
651 | if (!priv->alloc_mem) | |
652 | return -ENOMEM; | |
653 | ||
654 | /* | |
655 | * Note that generic_ptr is initialized to the device * but in | |
656 | * some alloc_functions, this is overridden and returns data. | |
657 | */ | |
658 | ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); | |
659 | if (!ptemp) { | |
660 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
661 | "Inject: Buffer Allocation error\n"); | |
662 | return -ENOMEM; | |
663 | } | |
664 | ||
665 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
666 | error_mask = priv->ue_set_mask; | |
667 | else | |
668 | error_mask = priv->ce_set_mask; | |
669 | ||
670 | edac_printk(KERN_ALERT, EDAC_DEVICE, | |
671 | "Trigger Error Mask (0x%X)\n", error_mask); | |
672 | ||
673 | local_irq_save(flags); | |
674 | /* write ECC corrupted data out. */ | |
675 | for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { | |
676 | /* Read data so we're in the correct state */ | |
677 | rmb(); | |
332efa63 | 678 | if (READ_ONCE(ptemp[i])) |
c3eea194 TT |
679 | result = -1; |
680 | /* Toggle Error bit (it is latched), leave ECC enabled */ | |
811fce4f TT |
681 | writel(error_mask, (drvdata->base + priv->set_err_ofst)); |
682 | writel(priv->ecc_enable_mask, (drvdata->base + | |
683 | priv->set_err_ofst)); | |
c3eea194 TT |
684 | ptemp[i] = i; |
685 | } | |
686 | /* Ensure it has been written out */ | |
687 | wmb(); | |
688 | local_irq_restore(flags); | |
689 | ||
690 | if (result) | |
691 | edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); | |
692 | ||
693 | /* Read out written data. ECC error caused here */ | |
694 | for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) | |
332efa63 | 695 | if (READ_ONCE(ptemp[i]) != i) |
c3eea194 TT |
696 | edac_printk(KERN_ERR, EDAC_DEVICE, |
697 | "Read doesn't match written data\n"); | |
698 | ||
699 | if (priv->free_mem) | |
700 | priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); | |
701 | ||
702 | return count; | |
703 | } | |
704 | ||
705 | static const struct file_operations altr_edac_device_inject_fops = { | |
706 | .open = simple_open, | |
707 | .write = altr_edac_device_trig, | |
708 | .llseek = generic_file_llseek, | |
709 | }; | |
710 | ||
c7b4be8d TT |
711 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
712 | const char __user *user_buf, | |
713 | size_t count, loff_t *ppos); | |
714 | ||
715 | static const struct file_operations altr_edac_a10_device_inject_fops = { | |
716 | .open = simple_open, | |
717 | .write = altr_edac_a10_device_trig, | |
718 | .llseek = generic_file_llseek, | |
719 | }; | |
720 | ||
064acbd4 TT |
721 | static ssize_t altr_edac_a10_device_trig2(struct file *file, |
722 | const char __user *user_buf, | |
723 | size_t count, loff_t *ppos); | |
724 | ||
725 | static const struct file_operations altr_edac_a10_device_inject2_fops = { | |
726 | .open = simple_open, | |
727 | .write = altr_edac_a10_device_trig2, | |
728 | .llseek = generic_file_llseek, | |
729 | }; | |
730 | ||
c3eea194 TT |
731 | static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, |
732 | const struct edac_device_prv_data *priv) | |
733 | { | |
734 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
735 | ||
736 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
737 | return; | |
738 | ||
739 | drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); | |
740 | if (!drvdata->debugfs_dir) | |
741 | return; | |
742 | ||
f399f34b | 743 | if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, |
c3eea194 | 744 | drvdata->debugfs_dir, edac_dci, |
e17ced2c | 745 | priv->inject_fops)) |
c3eea194 TT |
746 | debugfs_remove_recursive(drvdata->debugfs_dir); |
747 | } | |
748 | ||
749 | static const struct of_device_id altr_edac_device_of_match[] = { | |
750 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
2c911f6c | 751 | { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, |
c3eea194 TT |
752 | #endif |
753 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
2c911f6c | 754 | { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, |
c3eea194 TT |
755 | #endif |
756 | {}, | |
757 | }; | |
758 | MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); | |
759 | ||
760 | /* | |
761 | * altr_edac_device_probe() | |
762 | * This is a generic EDAC device driver that will support | |
763 | * various Altera memory devices such as the L2 cache ECC and | |
764 | * OCRAM ECC as well as the memories for other peripherals. | |
765 | * Module specific initialization is done by passing the | |
766 | * function index in the device tree. | |
767 | */ | |
768 | static int altr_edac_device_probe(struct platform_device *pdev) | |
769 | { | |
770 | struct edac_device_ctl_info *dci; | |
771 | struct altr_edac_device_dev *drvdata; | |
772 | struct resource *r; | |
773 | int res = 0; | |
774 | struct device_node *np = pdev->dev.of_node; | |
775 | char *ecc_name = (char *)np->name; | |
776 | static int dev_instance; | |
777 | ||
778 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
779 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
780 | "Unable to open devm\n"); | |
781 | return -ENOMEM; | |
782 | } | |
783 | ||
784 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
785 | if (!r) { | |
786 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
787 | "Unable to get mem resource\n"); | |
788 | res = -ENODEV; | |
789 | goto fail; | |
790 | } | |
791 | ||
792 | if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), | |
793 | dev_name(&pdev->dev))) { | |
794 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
795 | "%s:Error requesting mem region\n", ecc_name); | |
796 | res = -EBUSY; | |
797 | goto fail; | |
798 | } | |
799 | ||
800 | dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, | |
801 | 1, ecc_name, 1, 0, NULL, 0, | |
802 | dev_instance++); | |
803 | ||
804 | if (!dci) { | |
805 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
806 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
807 | res = -ENOMEM; | |
808 | goto fail; | |
809 | } | |
810 | ||
811 | drvdata = dci->pvt_info; | |
812 | dci->dev = &pdev->dev; | |
813 | platform_set_drvdata(pdev, dci); | |
814 | drvdata->edac_dev_name = ecc_name; | |
815 | ||
816 | drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); | |
8b073d94 CJ |
817 | if (!drvdata->base) { |
818 | res = -ENOMEM; | |
c3eea194 | 819 | goto fail1; |
8b073d94 | 820 | } |
c3eea194 TT |
821 | |
822 | /* Get driver specific data for this EDAC device */ | |
823 | drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; | |
824 | ||
825 | /* Check specific dependencies for the module */ | |
826 | if (drvdata->data->setup) { | |
328ca7ae | 827 | res = drvdata->data->setup(drvdata); |
c3eea194 TT |
828 | if (res) |
829 | goto fail1; | |
830 | } | |
831 | ||
832 | drvdata->sb_irq = platform_get_irq(pdev, 0); | |
833 | res = devm_request_irq(&pdev->dev, drvdata->sb_irq, | |
834 | altr_edac_device_handler, | |
835 | 0, dev_name(&pdev->dev), dci); | |
836 | if (res) | |
837 | goto fail1; | |
838 | ||
839 | drvdata->db_irq = platform_get_irq(pdev, 1); | |
840 | res = devm_request_irq(&pdev->dev, drvdata->db_irq, | |
841 | altr_edac_device_handler, | |
842 | 0, dev_name(&pdev->dev), dci); | |
843 | if (res) | |
844 | goto fail1; | |
845 | ||
846 | dci->mod_name = "Altera ECC Manager"; | |
847 | dci->dev_name = drvdata->edac_dev_name; | |
848 | ||
849 | res = edac_device_add_device(dci); | |
850 | if (res) | |
851 | goto fail1; | |
852 | ||
853 | altr_create_edacdev_dbgfs(dci, drvdata->data); | |
854 | ||
855 | devres_close_group(&pdev->dev, NULL); | |
856 | ||
857 | return 0; | |
858 | ||
859 | fail1: | |
860 | edac_device_free_ctl_info(dci); | |
861 | fail: | |
862 | devres_release_group(&pdev->dev, NULL); | |
863 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
864 | "%s:Error setting up EDAC device: %d\n", ecc_name, res); | |
865 | ||
866 | return res; | |
867 | } | |
868 | ||
869 | static int altr_edac_device_remove(struct platform_device *pdev) | |
870 | { | |
871 | struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); | |
872 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
873 | ||
874 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
875 | edac_device_del_device(&pdev->dev); | |
876 | edac_device_free_ctl_info(dci); | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static struct platform_driver altr_edac_device_driver = { | |
882 | .probe = altr_edac_device_probe, | |
883 | .remove = altr_edac_device_remove, | |
884 | .driver = { | |
885 | .name = "altr_edac_device", | |
886 | .of_match_table = altr_edac_device_of_match, | |
887 | }, | |
888 | }; | |
889 | module_platform_driver(altr_edac_device_driver); | |
890 | ||
6b300fb9 | 891 | /******************* Arria10 Device ECC Shared Functions *****************/ |
c3eea194 | 892 | |
1aa6eb5c AB |
893 | /* |
894 | * Test for memory's ECC dependencies upon entry because platform specific | |
895 | * startup should have initialized the memory and enabled the ECC. | |
896 | * Can't turn on ECC here because accessing un-initialized memory will | |
897 | * cause CE/UE errors possibly causing an ABORT. | |
898 | */ | |
6b300fb9 TT |
899 | static int __maybe_unused |
900 | altr_check_ecc_deps(struct altr_edac_device_dev *device) | |
1aa6eb5c AB |
901 | { |
902 | void __iomem *base = device->base; | |
903 | const struct edac_device_prv_data *prv = device->data; | |
904 | ||
905 | if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) | |
906 | return 0; | |
907 | ||
908 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
909 | "%s: No ECC present or ECC disabled.\n", | |
910 | device->edac_dev_name); | |
911 | return -ENODEV; | |
912 | } | |
c3eea194 | 913 | |
6b300fb9 TT |
914 | static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) |
915 | { | |
916 | struct altr_edac_device_dev *dci = dev_id; | |
917 | void __iomem *base = dci->base; | |
918 | ||
919 | if (irq == dci->sb_irq) { | |
920 | writel(ALTR_A10_ECC_SERRPENA, | |
921 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
922 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
923 | ||
924 | return IRQ_HANDLED; | |
925 | } else if (irq == dci->db_irq) { | |
926 | writel(ALTR_A10_ECC_DERRPENA, | |
927 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
928 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
929 | if (dci->data->panic) | |
930 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
931 | ||
932 | return IRQ_HANDLED; | |
933 | } | |
934 | ||
935 | WARN_ON(1); | |
936 | ||
937 | return IRQ_NONE; | |
938 | } | |
939 | ||
1166fde9 TT |
940 | /******************* Arria10 Memory Buffer Functions *********************/ |
941 | ||
942 | static inline int a10_get_irq_mask(struct device_node *np) | |
943 | { | |
944 | int irq; | |
945 | const u32 *handle = of_get_property(np, "interrupts", NULL); | |
946 | ||
947 | if (!handle) | |
948 | return -ENODEV; | |
949 | irq = be32_to_cpup(handle); | |
950 | return irq; | |
951 | } | |
952 | ||
953 | static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) | |
954 | { | |
955 | u32 value = readl(ioaddr); | |
956 | ||
957 | value |= bit_mask; | |
958 | writel(value, ioaddr); | |
959 | } | |
960 | ||
961 | static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) | |
962 | { | |
963 | u32 value = readl(ioaddr); | |
964 | ||
965 | value &= ~bit_mask; | |
966 | writel(value, ioaddr); | |
967 | } | |
968 | ||
969 | static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) | |
970 | { | |
971 | u32 value = readl(ioaddr); | |
972 | ||
973 | return (value & bit_mask) ? 1 : 0; | |
974 | } | |
975 | ||
976 | /* | |
977 | * This function uses the memory initialization block in the Arria10 ECC | |
978 | * controller to initialize/clear the entire memory data and ECC data. | |
979 | */ | |
980 | static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) | |
981 | { | |
982 | int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; | |
983 | u32 init_mask, stat_mask, clear_mask; | |
984 | int ret = 0; | |
985 | ||
986 | if (port) { | |
987 | init_mask = ALTR_A10_ECC_INITB; | |
988 | stat_mask = ALTR_A10_ECC_INITCOMPLETEB; | |
989 | clear_mask = ALTR_A10_ECC_ERRPENB_MASK; | |
990 | } else { | |
991 | init_mask = ALTR_A10_ECC_INITA; | |
992 | stat_mask = ALTR_A10_ECC_INITCOMPLETEA; | |
993 | clear_mask = ALTR_A10_ECC_ERRPENA_MASK; | |
994 | } | |
995 | ||
996 | ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); | |
997 | while (limit--) { | |
998 | if (ecc_test_bits(stat_mask, | |
999 | (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) | |
1000 | break; | |
1001 | udelay(1); | |
1002 | } | |
1003 | if (limit < 0) | |
1004 | ret = -EBUSY; | |
1005 | ||
1006 | /* Clear any pending ECC interrupts */ | |
1007 | writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); | |
1008 | ||
1009 | return ret; | |
1010 | } | |
1011 | ||
064acbd4 TT |
1012 | static int socfpga_is_a10(void) |
1013 | { | |
1014 | return of_machine_is_compatible("altr,socfpga-arria10"); | |
1015 | } | |
1016 | ||
1017 | static int socfpga_is_s10(void) | |
1018 | { | |
1019 | return of_machine_is_compatible("altr,socfpga-stratix10"); | |
1020 | } | |
1021 | ||
1166fde9 TT |
1022 | static __init int __maybe_unused |
1023 | altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, | |
1024 | u32 ecc_ctrl_en_mask, bool dual_port) | |
1025 | { | |
1026 | int ret = 0; | |
1027 | void __iomem *ecc_block_base; | |
1028 | struct regmap *ecc_mgr_map; | |
1029 | char *ecc_name; | |
1030 | struct device_node *np_eccmgr; | |
1031 | ||
1032 | ecc_name = (char *)np->name; | |
1033 | ||
1034 | /* Get the ECC Manager - parent of the device EDACs */ | |
1035 | np_eccmgr = of_get_parent(np); | |
064acbd4 TT |
1036 | |
1037 | if (socfpga_is_a10()) { | |
1038 | ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr, | |
1039 | "altr,sysmgr-syscon"); | |
1040 | } else { | |
1041 | struct device_node *sysmgr_np; | |
1042 | struct resource res; | |
8537bf10 | 1043 | uintptr_t base; |
064acbd4 TT |
1044 | |
1045 | sysmgr_np = of_parse_phandle(np_eccmgr, | |
1046 | "altr,sysmgr-syscon", 0); | |
1047 | if (!sysmgr_np) { | |
1048 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1049 | "Unable to find altr,sysmgr-syscon\n"); | |
1050 | return -ENODEV; | |
1051 | } | |
1052 | ||
7f736599 HZ |
1053 | if (of_address_to_resource(sysmgr_np, 0, &res)) { |
1054 | of_node_put(sysmgr_np); | |
064acbd4 | 1055 | return -ENOMEM; |
7f736599 | 1056 | } |
064acbd4 TT |
1057 | |
1058 | /* Need physical address for SMCC call */ | |
8537bf10 | 1059 | base = res.start; |
064acbd4 | 1060 | |
8537bf10 | 1061 | ecc_mgr_map = regmap_init(NULL, NULL, (void *)base, |
064acbd4 | 1062 | &s10_sdram_regmap_cfg); |
7f736599 | 1063 | of_node_put(sysmgr_np); |
064acbd4 | 1064 | } |
1166fde9 TT |
1065 | of_node_put(np_eccmgr); |
1066 | if (IS_ERR(ecc_mgr_map)) { | |
1067 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1068 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
1069 | return -ENODEV; | |
1070 | } | |
1071 | ||
1072 | /* Map the ECC Block */ | |
1073 | ecc_block_base = of_iomap(np, 0); | |
1074 | if (!ecc_block_base) { | |
1075 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1076 | "Unable to map %s ECC block\n", ecc_name); | |
1077 | return -ENODEV; | |
1078 | } | |
1079 | ||
1080 | /* Disable ECC */ | |
1081 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); | |
1082 | writel(ALTR_A10_ECC_SERRINTEN, | |
1083 | (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); | |
1084 | ecc_clear_bits(ecc_ctrl_en_mask, | |
1085 | (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); | |
1086 | /* Ensure all writes complete */ | |
1087 | wmb(); | |
1088 | /* Use HW initialization block to initialize memory for ECC */ | |
1089 | ret = altr_init_memory_port(ecc_block_base, 0); | |
1090 | if (ret) { | |
1091 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1092 | "ECC: cannot init %s PORTA memory\n", ecc_name); | |
1093 | goto out; | |
1094 | } | |
1095 | ||
1096 | if (dual_port) { | |
1097 | ret = altr_init_memory_port(ecc_block_base, 1); | |
1098 | if (ret) { | |
1099 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1100 | "ECC: cannot init %s PORTB memory\n", | |
1101 | ecc_name); | |
1102 | goto out; | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | /* Interrupt mode set to every SBERR */ | |
1107 | regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, | |
1108 | ALTR_A10_ECC_INTMODE); | |
1109 | /* Enable ECC */ | |
1110 | ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + | |
1111 | ALTR_A10_ECC_CTRL_OFST)); | |
1112 | writel(ALTR_A10_ECC_SERRINTEN, | |
1113 | (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); | |
1114 | regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); | |
1115 | /* Ensure all writes complete */ | |
1116 | wmb(); | |
1117 | out: | |
1118 | iounmap(ecc_block_base); | |
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | static int validate_parent_available(struct device_node *np); | |
1123 | static const struct of_device_id altr_edac_a10_device_of_match[]; | |
1124 | static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) | |
1125 | { | |
1126 | int irq; | |
25b223dd TT |
1127 | struct device_node *child, *np; |
1128 | ||
064acbd4 | 1129 | if (!socfpga_is_a10() && !socfpga_is_s10()) |
25b223dd TT |
1130 | return -ENODEV; |
1131 | ||
1132 | np = of_find_compatible_node(NULL, NULL, | |
1133 | "altr,socfpga-a10-ecc-manager"); | |
1166fde9 TT |
1134 | if (!np) { |
1135 | edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); | |
1136 | return -ENODEV; | |
1137 | } | |
1138 | ||
1139 | for_each_child_of_node(np, child) { | |
1140 | const struct of_device_id *pdev_id; | |
1141 | const struct edac_device_prv_data *prv; | |
1142 | ||
1143 | if (!of_device_is_available(child)) | |
1144 | continue; | |
1145 | if (!of_device_is_compatible(child, compat)) | |
1146 | continue; | |
1147 | ||
1148 | if (validate_parent_available(child)) | |
1149 | continue; | |
1150 | ||
1151 | irq = a10_get_irq_mask(child); | |
1152 | if (irq < 0) | |
1153 | continue; | |
1154 | ||
1155 | /* Get matching node and check for valid result */ | |
1156 | pdev_id = of_match_node(altr_edac_a10_device_of_match, child); | |
1157 | if (IS_ERR_OR_NULL(pdev_id)) | |
1158 | continue; | |
1159 | ||
1160 | /* Validate private data pointer before dereferencing */ | |
1161 | prv = pdev_id->data; | |
1162 | if (!prv) | |
1163 | continue; | |
1164 | ||
1165 | altr_init_a10_ecc_block(child, BIT(irq), | |
1166 | prv->ecc_enable_mask, 0); | |
1167 | } | |
1168 | ||
1169 | of_node_put(np); | |
1170 | return 0; | |
1171 | } | |
1172 | ||
6b300fb9 TT |
1173 | /*********************** OCRAM EDAC Device Functions *********************/ |
1174 | ||
1175 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1176 | ||
c3eea194 TT |
1177 | static void *ocram_alloc_mem(size_t size, void **other) |
1178 | { | |
1179 | struct device_node *np; | |
1180 | struct gen_pool *gp; | |
1181 | void *sram_addr; | |
1182 | ||
1183 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); | |
1184 | if (!np) | |
1185 | return NULL; | |
1186 | ||
1187 | gp = of_gen_pool_get(np, "iram", 0); | |
1188 | of_node_put(np); | |
1189 | if (!gp) | |
1190 | return NULL; | |
1191 | ||
1192 | sram_addr = (void *)gen_pool_alloc(gp, size); | |
1193 | if (!sram_addr) | |
1194 | return NULL; | |
1195 | ||
1196 | memset(sram_addr, 0, size); | |
1197 | /* Ensure data is written out */ | |
1198 | wmb(); | |
1199 | ||
1200 | /* Remember this handle for freeing later */ | |
1201 | *other = gp; | |
1202 | ||
1203 | return sram_addr; | |
1204 | } | |
1205 | ||
1206 | static void ocram_free_mem(void *p, size_t size, void *other) | |
1207 | { | |
9ef20753 | 1208 | gen_pool_free((struct gen_pool *)other, (unsigned long)p, size); |
c3eea194 TT |
1209 | } |
1210 | ||
1cf70377 | 1211 | static const struct edac_device_prv_data ocramecc_data = { |
aa1f06dc | 1212 | .setup = altr_check_ecc_deps, |
c3eea194 TT |
1213 | .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), |
1214 | .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), | |
c3eea194 TT |
1215 | .alloc_mem = ocram_alloc_mem, |
1216 | .free_mem = ocram_free_mem, | |
1217 | .ecc_enable_mask = ALTR_OCR_ECC_EN, | |
943ad917 | 1218 | .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 TT |
1219 | .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), |
1220 | .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), | |
811fce4f | 1221 | .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 | 1222 | .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, |
e17ced2c | 1223 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1224 | }; |
1225 | ||
17e47dc6 TT |
1226 | static int __maybe_unused |
1227 | altr_check_ocram_deps_init(struct altr_edac_device_dev *device) | |
1228 | { | |
1229 | void __iomem *base = device->base; | |
1230 | int ret; | |
1231 | ||
1232 | ret = altr_check_ecc_deps(device); | |
1233 | if (ret) | |
1234 | return ret; | |
1235 | ||
1236 | /* Verify OCRAM has been initialized */ | |
1237 | if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, | |
1238 | (base + ALTR_A10_ECC_INITSTAT_OFST))) | |
1239 | return -ENODEV; | |
1240 | ||
1241 | /* Enable IRQ on Single Bit Error */ | |
1242 | writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); | |
1243 | /* Ensure all writes complete */ | |
1244 | wmb(); | |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
1cf70377 | 1249 | static const struct edac_device_prv_data a10_ocramecc_data = { |
17e47dc6 | 1250 | .setup = altr_check_ocram_deps_init, |
c7b4be8d TT |
1251 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1252 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
1253 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, | |
c7b4be8d TT |
1254 | .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, |
1255 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1256 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1257 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1258 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1259 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
17e47dc6 | 1260 | .inject_fops = &altr_edac_a10_device_inject2_fops, |
2b083d65 TT |
1261 | /* |
1262 | * OCRAM panic on uncorrectable error because sleep/resume | |
1263 | * functions and FPGA contents are stored in OCRAM. Prefer | |
1264 | * a kernel panic over executing/loading corrupted data. | |
1265 | */ | |
1266 | .panic = true, | |
c7b4be8d TT |
1267 | }; |
1268 | ||
c3eea194 TT |
1269 | #endif /* CONFIG_EDAC_ALTERA_OCRAM */ |
1270 | ||
1271 | /********************* L2 Cache EDAC Device Functions ********************/ | |
1272 | ||
1273 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1274 | ||
1275 | static void *l2_alloc_mem(size_t size, void **other) | |
1276 | { | |
1277 | struct device *dev = *other; | |
1278 | void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); | |
1279 | ||
1280 | if (!ptemp) | |
1281 | return NULL; | |
1282 | ||
1283 | /* Make sure everything is written out */ | |
1284 | wmb(); | |
1285 | ||
1286 | /* | |
1287 | * Clean all cache levels up to LoC (includes L2) | |
1288 | * This ensures the corrupted data is written into | |
1289 | * L2 cache for readback test (which causes ECC error). | |
1290 | */ | |
1291 | flush_cache_all(); | |
1292 | ||
1293 | return ptemp; | |
1294 | } | |
1295 | ||
1296 | static void l2_free_mem(void *p, size_t size, void *other) | |
1297 | { | |
1298 | struct device *dev = other; | |
1299 | ||
1300 | if (dev && p) | |
1301 | devm_kfree(dev, p); | |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * altr_l2_check_deps() | |
1306 | * Test for L2 cache ECC dependencies upon entry because | |
1307 | * platform specific startup should have initialized the L2 | |
1308 | * memory and enabled the ECC. | |
1309 | * Bail if ECC is not enabled. | |
1310 | * Note that L2 Cache Enable is forced at build time. | |
1311 | */ | |
328ca7ae | 1312 | static int altr_l2_check_deps(struct altr_edac_device_dev *device) |
c3eea194 | 1313 | { |
328ca7ae | 1314 | void __iomem *base = device->base; |
27439a1a TT |
1315 | const struct edac_device_prv_data *prv = device->data; |
1316 | ||
1317 | if ((readl(base) & prv->ecc_enable_mask) == | |
1318 | prv->ecc_enable_mask) | |
c3eea194 TT |
1319 | return 0; |
1320 | ||
1321 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1322 | "L2: No ECC present, or ECC disabled\n"); | |
1323 | return -ENODEV; | |
1324 | } | |
1325 | ||
13ab8448 | 1326 | static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) |
588cb03e | 1327 | { |
13ab8448 TT |
1328 | struct altr_edac_device_dev *dci = dev_id; |
1329 | ||
1330 | if (irq == dci->sb_irq) { | |
588cb03e TT |
1331 | regmap_write(dci->edac->ecc_mgr_map, |
1332 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1333 | A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); | |
1334 | edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
13ab8448 TT |
1335 | |
1336 | return IRQ_HANDLED; | |
1337 | } else if (irq == dci->db_irq) { | |
588cb03e TT |
1338 | regmap_write(dci->edac->ecc_mgr_map, |
1339 | A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, | |
1340 | A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); | |
1341 | edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); | |
1342 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
13ab8448 TT |
1343 | |
1344 | return IRQ_HANDLED; | |
588cb03e | 1345 | } |
13ab8448 TT |
1346 | |
1347 | WARN_ON(1); | |
1348 | ||
1349 | return IRQ_NONE; | |
588cb03e TT |
1350 | } |
1351 | ||
1cf70377 | 1352 | static const struct edac_device_prv_data l2ecc_data = { |
c3eea194 TT |
1353 | .setup = altr_l2_check_deps, |
1354 | .ce_clear_mask = 0, | |
1355 | .ue_clear_mask = 0, | |
c3eea194 TT |
1356 | .alloc_mem = l2_alloc_mem, |
1357 | .free_mem = l2_free_mem, | |
1358 | .ecc_enable_mask = ALTR_L2_ECC_EN, | |
1359 | .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), | |
1360 | .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), | |
811fce4f | 1361 | .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, |
c3eea194 | 1362 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, |
e17ced2c | 1363 | .inject_fops = &altr_edac_device_inject_fops, |
c3eea194 TT |
1364 | }; |
1365 | ||
1cf70377 | 1366 | static const struct edac_device_prv_data a10_l2ecc_data = { |
588cb03e TT |
1367 | .setup = altr_l2_check_deps, |
1368 | .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, | |
1369 | .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, | |
1370 | .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, | |
588cb03e TT |
1371 | .alloc_mem = l2_alloc_mem, |
1372 | .free_mem = l2_free_mem, | |
1373 | .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, | |
1374 | .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, | |
1375 | .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, | |
1376 | .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, | |
1377 | .ecc_irq_handler = altr_edac_a10_l2_irq, | |
1378 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, | |
e17ced2c | 1379 | .inject_fops = &altr_edac_device_inject_fops, |
588cb03e TT |
1380 | }; |
1381 | ||
c3eea194 TT |
1382 | #endif /* CONFIG_EDAC_ALTERA_L2C */ |
1383 | ||
ab8c1e0f TT |
1384 | /********************* Ethernet Device Functions ********************/ |
1385 | ||
1386 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1387 | ||
788586ef TT |
1388 | static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev) |
1389 | { | |
1390 | int ret; | |
1391 | ||
1392 | ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); | |
1393 | if (ret) | |
1394 | return ret; | |
1395 | ||
1396 | return altr_check_ecc_deps(dev); | |
1397 | } | |
1398 | ||
ab8c1e0f | 1399 | static const struct edac_device_prv_data a10_enetecc_data = { |
788586ef | 1400 | .setup = socfpga_init_ethernet_ecc, |
ab8c1e0f TT |
1401 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1402 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
ab8c1e0f TT |
1403 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1404 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1405 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1406 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1407 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1408 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
064acbd4 | 1409 | .inject_fops = &altr_edac_a10_device_inject2_fops, |
ab8c1e0f TT |
1410 | }; |
1411 | ||
ab8c1e0f TT |
1412 | #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ |
1413 | ||
c6882fb2 TT |
1414 | /********************** NAND Device Functions **********************/ |
1415 | ||
1416 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1417 | ||
788586ef TT |
1418 | static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device) |
1419 | { | |
1420 | int ret; | |
1421 | ||
1422 | ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); | |
1423 | if (ret) | |
1424 | return ret; | |
1425 | ||
1426 | return altr_check_ecc_deps(device); | |
1427 | } | |
1428 | ||
c6882fb2 | 1429 | static const struct edac_device_prv_data a10_nandecc_data = { |
788586ef | 1430 | .setup = socfpga_init_nand_ecc, |
c6882fb2 TT |
1431 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1432 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
c6882fb2 TT |
1433 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1434 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1435 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1436 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1437 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1438 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1439 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1440 | }; | |
1441 | ||
c6882fb2 TT |
1442 | #endif /* CONFIG_EDAC_ALTERA_NAND */ |
1443 | ||
e8263793 TT |
1444 | /********************** DMA Device Functions **********************/ |
1445 | ||
1446 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1447 | ||
788586ef TT |
1448 | static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device) |
1449 | { | |
1450 | int ret; | |
1451 | ||
1452 | ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); | |
1453 | if (ret) | |
1454 | return ret; | |
1455 | ||
1456 | return altr_check_ecc_deps(device); | |
1457 | } | |
1458 | ||
e8263793 | 1459 | static const struct edac_device_prv_data a10_dmaecc_data = { |
788586ef | 1460 | .setup = socfpga_init_dma_ecc, |
e8263793 TT |
1461 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1462 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
e8263793 TT |
1463 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1464 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1465 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1466 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1467 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1468 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1469 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1470 | }; | |
1471 | ||
e8263793 TT |
1472 | #endif /* CONFIG_EDAC_ALTERA_DMA */ |
1473 | ||
c609581d TT |
1474 | /********************** USB Device Functions **********************/ |
1475 | ||
1476 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1477 | ||
788586ef TT |
1478 | static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device) |
1479 | { | |
1480 | int ret; | |
1481 | ||
1482 | ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); | |
1483 | if (ret) | |
1484 | return ret; | |
1485 | ||
1486 | return altr_check_ecc_deps(device); | |
1487 | } | |
1488 | ||
c609581d | 1489 | static const struct edac_device_prv_data a10_usbecc_data = { |
788586ef | 1490 | .setup = socfpga_init_usb_ecc, |
c609581d TT |
1491 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1492 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
c609581d TT |
1493 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1494 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1495 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1496 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1497 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1498 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
064acbd4 | 1499 | .inject_fops = &altr_edac_a10_device_inject2_fops, |
c609581d TT |
1500 | }; |
1501 | ||
c609581d TT |
1502 | #endif /* CONFIG_EDAC_ALTERA_USB */ |
1503 | ||
485fe9e2 TT |
1504 | /********************** QSPI Device Functions **********************/ |
1505 | ||
1506 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1507 | ||
788586ef TT |
1508 | static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device) |
1509 | { | |
1510 | int ret; | |
1511 | ||
1512 | ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); | |
1513 | if (ret) | |
1514 | return ret; | |
1515 | ||
1516 | return altr_check_ecc_deps(device); | |
1517 | } | |
1518 | ||
485fe9e2 | 1519 | static const struct edac_device_prv_data a10_qspiecc_data = { |
788586ef | 1520 | .setup = socfpga_init_qspi_ecc, |
485fe9e2 TT |
1521 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1522 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
485fe9e2 TT |
1523 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1524 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1525 | .ce_set_mask = ALTR_A10_ECC_TSERRA, | |
1526 | .ue_set_mask = ALTR_A10_ECC_TDERRA, | |
1527 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1528 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1529 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1530 | }; | |
1531 | ||
485fe9e2 TT |
1532 | #endif /* CONFIG_EDAC_ALTERA_QSPI */ |
1533 | ||
91104984 TT |
1534 | /********************* SDMMC Device Functions **********************/ |
1535 | ||
1536 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1537 | ||
1538 | static const struct edac_device_prv_data a10_sdmmceccb_data; | |
1539 | static int altr_portb_setup(struct altr_edac_device_dev *device) | |
1540 | { | |
1541 | struct edac_device_ctl_info *dci; | |
1542 | struct altr_edac_device_dev *altdev; | |
1543 | char *ecc_name = "sdmmcb-ecc"; | |
1544 | int edac_idx, rc; | |
1545 | struct device_node *np; | |
1546 | const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; | |
1547 | ||
1548 | rc = altr_check_ecc_deps(device); | |
1549 | if (rc) | |
1550 | return rc; | |
1551 | ||
1552 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
1553 | if (!np) { | |
1554 | edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); | |
1555 | return -ENODEV; | |
1556 | } | |
1557 | ||
1558 | /* Create the PortB EDAC device */ | |
1559 | edac_idx = edac_device_alloc_index(); | |
1560 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, | |
1561 | ecc_name, 1, 0, NULL, 0, edac_idx); | |
1562 | if (!dci) { | |
1563 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1564 | "%s: Unable to allocate PortB EDAC device\n", | |
1565 | ecc_name); | |
1566 | return -ENOMEM; | |
1567 | } | |
1568 | ||
1569 | /* Initialize the PortB EDAC device structure from PortA structure */ | |
1570 | altdev = dci->pvt_info; | |
1571 | *altdev = *device; | |
1572 | ||
1573 | if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) | |
1574 | return -ENOMEM; | |
1575 | ||
1576 | /* Update PortB specific values */ | |
1577 | altdev->edac_dev_name = ecc_name; | |
1578 | altdev->edac_idx = edac_idx; | |
1579 | altdev->edac_dev = dci; | |
1580 | altdev->data = prv; | |
1581 | dci->dev = &altdev->ddev; | |
1582 | dci->ctl_name = "Altera ECC Manager"; | |
1583 | dci->mod_name = ecc_name; | |
1584 | dci->dev_name = ecc_name; | |
1585 | ||
a428b4d3 TT |
1586 | /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */ |
1587 | #ifdef CONFIG_ARCH_STRATIX10 | |
1588 | altdev->sb_irq = irq_of_parse_and_map(np, 1); | |
1589 | #else | |
91104984 | 1590 | altdev->sb_irq = irq_of_parse_and_map(np, 2); |
a428b4d3 | 1591 | #endif |
91104984 TT |
1592 | if (!altdev->sb_irq) { |
1593 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); | |
1594 | rc = -ENODEV; | |
1595 | goto err_release_group_1; | |
1596 | } | |
1597 | rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, | |
1598 | prv->ecc_irq_handler, | |
a29d64a4 TT |
1599 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, |
1600 | ecc_name, altdev); | |
91104984 TT |
1601 | if (rc) { |
1602 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); | |
1603 | goto err_release_group_1; | |
1604 | } | |
1605 | ||
a428b4d3 TT |
1606 | #ifdef CONFIG_ARCH_STRATIX10 |
1607 | /* Use IRQ to determine SError origin instead of assigning IRQ */ | |
1608 | rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq); | |
1609 | if (rc) { | |
1610 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1611 | "Error PortB DBIRQ alloc\n"); | |
1612 | goto err_release_group_1; | |
1613 | } | |
1614 | #else | |
91104984 TT |
1615 | altdev->db_irq = irq_of_parse_and_map(np, 3); |
1616 | if (!altdev->db_irq) { | |
1617 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); | |
1618 | rc = -ENODEV; | |
1619 | goto err_release_group_1; | |
1620 | } | |
1621 | rc = devm_request_irq(&altdev->ddev, altdev->db_irq, | |
1622 | prv->ecc_irq_handler, | |
a29d64a4 TT |
1623 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, |
1624 | ecc_name, altdev); | |
91104984 TT |
1625 | if (rc) { |
1626 | edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); | |
1627 | goto err_release_group_1; | |
1628 | } | |
a428b4d3 | 1629 | #endif |
91104984 TT |
1630 | |
1631 | rc = edac_device_add_device(dci); | |
1632 | if (rc) { | |
1633 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1634 | "edac_device_add_device portB failed\n"); | |
1635 | rc = -ENOMEM; | |
1636 | goto err_release_group_1; | |
1637 | } | |
1638 | altr_create_edacdev_dbgfs(dci, prv); | |
1639 | ||
1640 | list_add(&altdev->next, &altdev->edac->a10_ecc_devices); | |
1641 | ||
1642 | devres_remove_group(&altdev->ddev, altr_portb_setup); | |
1643 | ||
1644 | return 0; | |
1645 | ||
1646 | err_release_group_1: | |
1647 | edac_device_free_ctl_info(dci); | |
1648 | devres_release_group(&altdev->ddev, altr_portb_setup); | |
1649 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1650 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
1651 | return rc; | |
1652 | } | |
1653 | ||
788586ef TT |
1654 | static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device) |
1655 | { | |
1656 | int rc = -ENODEV; | |
1657 | struct device_node *child; | |
1658 | ||
1659 | child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); | |
1660 | if (!child) | |
1661 | return -ENODEV; | |
1662 | ||
1663 | if (!of_device_is_available(child)) | |
1664 | goto exit; | |
1665 | ||
1666 | if (validate_parent_available(child)) | |
1667 | goto exit; | |
1668 | ||
1669 | /* Init portB */ | |
1670 | rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, | |
1671 | a10_sdmmceccb_data.ecc_enable_mask, 1); | |
1672 | if (rc) | |
1673 | goto exit; | |
1674 | ||
1675 | /* Setup portB */ | |
1676 | return altr_portb_setup(device); | |
1677 | ||
1678 | exit: | |
1679 | of_node_put(child); | |
1680 | return rc; | |
1681 | } | |
1682 | ||
91104984 TT |
1683 | static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) |
1684 | { | |
1685 | struct altr_edac_device_dev *ad = dev_id; | |
1686 | void __iomem *base = ad->base; | |
1687 | const struct edac_device_prv_data *priv = ad->data; | |
1688 | ||
1689 | if (irq == ad->sb_irq) { | |
1690 | writel(priv->ce_clear_mask, | |
1691 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1692 | edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1693 | return IRQ_HANDLED; | |
1694 | } else if (irq == ad->db_irq) { | |
1695 | writel(priv->ue_clear_mask, | |
1696 | base + ALTR_A10_ECC_INTSTAT_OFST); | |
1697 | edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); | |
1698 | return IRQ_HANDLED; | |
1699 | } | |
1700 | ||
1701 | WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); | |
1702 | ||
1703 | return IRQ_NONE; | |
1704 | } | |
1705 | ||
1706 | static const struct edac_device_prv_data a10_sdmmcecca_data = { | |
788586ef | 1707 | .setup = socfpga_init_sdmmc_ecc, |
91104984 TT |
1708 | .ce_clear_mask = ALTR_A10_ECC_SERRPENA, |
1709 | .ue_clear_mask = ALTR_A10_ECC_DERRPENA, | |
91104984 TT |
1710 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1711 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1712 | .ce_set_mask = ALTR_A10_ECC_SERRPENA, | |
1713 | .ue_set_mask = ALTR_A10_ECC_DERRPENA, | |
1714 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1715 | .ecc_irq_handler = altr_edac_a10_ecc_irq, | |
1716 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1717 | }; | |
1718 | ||
1719 | static const struct edac_device_prv_data a10_sdmmceccb_data = { | |
788586ef | 1720 | .setup = socfpga_init_sdmmc_ecc, |
91104984 TT |
1721 | .ce_clear_mask = ALTR_A10_ECC_SERRPENB, |
1722 | .ue_clear_mask = ALTR_A10_ECC_DERRPENB, | |
91104984 TT |
1723 | .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, |
1724 | .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, | |
1725 | .ce_set_mask = ALTR_A10_ECC_TSERRB, | |
1726 | .ue_set_mask = ALTR_A10_ECC_TDERRB, | |
1727 | .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, | |
1728 | .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, | |
1729 | .inject_fops = &altr_edac_a10_device_inject_fops, | |
1730 | }; | |
1731 | ||
91104984 TT |
1732 | #endif /* CONFIG_EDAC_ALTERA_SDMMC */ |
1733 | ||
588cb03e | 1734 | /********************* Arria10 EDAC Device Functions *************************/ |
ab564cb5 TT |
1735 | static const struct of_device_id altr_edac_a10_device_of_match[] = { |
1736 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
1737 | { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, | |
1738 | #endif | |
1739 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
1740 | { .compatible = "altr,socfpga-a10-ocram-ecc", | |
1741 | .data = &a10_ocramecc_data }, | |
ab8c1e0f TT |
1742 | #endif |
1743 | #ifdef CONFIG_EDAC_ALTERA_ETHERNET | |
1744 | { .compatible = "altr,socfpga-eth-mac-ecc", | |
1745 | .data = &a10_enetecc_data }, | |
c6882fb2 TT |
1746 | #endif |
1747 | #ifdef CONFIG_EDAC_ALTERA_NAND | |
1748 | { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, | |
e8263793 TT |
1749 | #endif |
1750 | #ifdef CONFIG_EDAC_ALTERA_DMA | |
1751 | { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, | |
c609581d TT |
1752 | #endif |
1753 | #ifdef CONFIG_EDAC_ALTERA_USB | |
1754 | { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, | |
485fe9e2 TT |
1755 | #endif |
1756 | #ifdef CONFIG_EDAC_ALTERA_QSPI | |
1757 | { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, | |
91104984 TT |
1758 | #endif |
1759 | #ifdef CONFIG_EDAC_ALTERA_SDMMC | |
1760 | { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, | |
ab564cb5 TT |
1761 | #endif |
1762 | {}, | |
1763 | }; | |
1764 | MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); | |
588cb03e TT |
1765 | |
1766 | /* | |
1767 | * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 | |
1768 | * because 2 IRQs are shared among the all ECC peripherals. The ECC | |
1769 | * manager manages the IRQs and the children. | |
1770 | * Based on xgene_edac.c peripheral code. | |
1771 | */ | |
1772 | ||
c7b4be8d TT |
1773 | static ssize_t altr_edac_a10_device_trig(struct file *file, |
1774 | const char __user *user_buf, | |
1775 | size_t count, loff_t *ppos) | |
1776 | { | |
1777 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
1778 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
1779 | const struct edac_device_prv_data *priv = drvdata->data; | |
1780 | void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); | |
1781 | unsigned long flags; | |
1782 | u8 trig_type; | |
1783 | ||
1784 | if (!user_buf || get_user(trig_type, user_buf)) | |
1785 | return -EFAULT; | |
1786 | ||
1787 | local_irq_save(flags); | |
1788 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
1789 | writel(priv->ue_set_mask, set_addr); | |
1790 | else | |
1791 | writel(priv->ce_set_mask, set_addr); | |
064acbd4 TT |
1792 | |
1793 | /* Ensure the interrupt test bits are set */ | |
1794 | wmb(); | |
1795 | local_irq_restore(flags); | |
1796 | ||
1797 | return count; | |
1798 | } | |
1799 | ||
1800 | /* | |
1801 | * The Stratix10 EDAC Error Injection Functions differ from Arria10 | |
1802 | * slightly. A few Arria10 peripherals can use this injection function. | |
1803 | * Inject the error into the memory and then readback to trigger the IRQ. | |
1804 | */ | |
1805 | static ssize_t altr_edac_a10_device_trig2(struct file *file, | |
1806 | const char __user *user_buf, | |
1807 | size_t count, loff_t *ppos) | |
1808 | { | |
1809 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
1810 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
1811 | const struct edac_device_prv_data *priv = drvdata->data; | |
1812 | void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); | |
1813 | unsigned long flags; | |
1814 | u8 trig_type; | |
1815 | ||
1816 | if (!user_buf || get_user(trig_type, user_buf)) | |
1817 | return -EFAULT; | |
1818 | ||
1819 | local_irq_save(flags); | |
1820 | if (trig_type == ALTR_UE_TRIGGER_CHAR) { | |
1821 | writel(priv->ue_set_mask, set_addr); | |
1822 | } else { | |
436b0a58 | 1823 | /* Setup read/write of 4 bytes */ |
064acbd4 TT |
1824 | writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST); |
1825 | /* Setup Address to 0 */ | |
436b0a58 TT |
1826 | writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST); |
1827 | /* Setup accctrl to read & ecc & data override */ | |
1828 | writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); | |
064acbd4 TT |
1829 | /* Kick it. */ |
1830 | writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); | |
1831 | /* Setup write for single bit change */ | |
436b0a58 TT |
1832 | writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1, |
1833 | drvdata->base + ECC_BLK_WDATA0_OFST); | |
1834 | writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST), | |
1835 | drvdata->base + ECC_BLK_WDATA1_OFST); | |
1836 | writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST), | |
1837 | drvdata->base + ECC_BLK_WDATA2_OFST); | |
1838 | writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST), | |
1839 | drvdata->base + ECC_BLK_WDATA3_OFST); | |
1840 | ||
064acbd4 TT |
1841 | /* Copy Read ECC to Write ECC */ |
1842 | writel(readl(drvdata->base + ECC_BLK_RECC0_OFST), | |
1843 | drvdata->base + ECC_BLK_WECC0_OFST); | |
1844 | writel(readl(drvdata->base + ECC_BLK_RECC1_OFST), | |
1845 | drvdata->base + ECC_BLK_WECC1_OFST); | |
1846 | /* Setup accctrl to write & ecc override & data override */ | |
1847 | writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); | |
1848 | /* Kick it. */ | |
1849 | writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); | |
1850 | /* Setup accctrl to read & ecc overwrite & data overwrite */ | |
1851 | writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); | |
1852 | /* Kick it. */ | |
1853 | writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); | |
1854 | } | |
1855 | ||
c7b4be8d TT |
1856 | /* Ensure the interrupt test bits are set */ |
1857 | wmb(); | |
1858 | local_irq_restore(flags); | |
1859 | ||
1860 | return count; | |
1861 | } | |
1862 | ||
13ab8448 | 1863 | static void altr_edac_a10_irq_handler(struct irq_desc *desc) |
588cb03e | 1864 | { |
13ab8448 TT |
1865 | int dberr, bit, sm_offset, irq_status; |
1866 | struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); | |
1867 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1868 | int irq = irq_desc_get_irq(desc); | |
1869 | ||
1870 | dberr = (irq == edac->db_irq) ? 1 : 0; | |
1871 | sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : | |
1872 | A10_SYSMGR_ECC_INTSTAT_SERR_OFST; | |
1873 | ||
1874 | chained_irq_enter(chip, desc); | |
588cb03e TT |
1875 | |
1876 | regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); | |
1877 | ||
13ab8448 TT |
1878 | for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { |
1879 | irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); | |
1880 | if (irq) | |
1881 | generic_handle_irq(irq); | |
588cb03e TT |
1882 | } |
1883 | ||
13ab8448 | 1884 | chained_irq_exit(chip, desc); |
588cb03e TT |
1885 | } |
1886 | ||
44ec9b30 TT |
1887 | static int validate_parent_available(struct device_node *np) |
1888 | { | |
1889 | struct device_node *parent; | |
1890 | int ret = 0; | |
1891 | ||
1892 | /* Ensure parent device is enabled if parent node exists */ | |
1893 | parent = of_parse_phandle(np, "altr,ecc-parent", 0); | |
1894 | if (parent && !of_device_is_available(parent)) | |
1895 | ret = -ENODEV; | |
1896 | ||
1897 | of_node_put(parent); | |
1898 | return ret; | |
1899 | } | |
1900 | ||
588cb03e TT |
1901 | static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, |
1902 | struct device_node *np) | |
1903 | { | |
1904 | struct edac_device_ctl_info *dci; | |
1905 | struct altr_edac_device_dev *altdev; | |
1906 | char *ecc_name = (char *)np->name; | |
1907 | struct resource res; | |
1908 | int edac_idx; | |
1909 | int rc = 0; | |
1910 | const struct edac_device_prv_data *prv; | |
1911 | /* Get matching node and check for valid result */ | |
1912 | const struct of_device_id *pdev_id = | |
ab564cb5 | 1913 | of_match_node(altr_edac_a10_device_of_match, np); |
588cb03e TT |
1914 | if (IS_ERR_OR_NULL(pdev_id)) |
1915 | return -ENODEV; | |
1916 | ||
1917 | /* Get driver specific data for this EDAC device */ | |
1918 | prv = pdev_id->data; | |
1919 | if (IS_ERR_OR_NULL(prv)) | |
1920 | return -ENODEV; | |
1921 | ||
44ec9b30 TT |
1922 | if (validate_parent_available(np)) |
1923 | return -ENODEV; | |
1924 | ||
588cb03e TT |
1925 | if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) |
1926 | return -ENOMEM; | |
1927 | ||
1928 | rc = of_address_to_resource(np, 0, &res); | |
1929 | if (rc < 0) { | |
1930 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1931 | "%s: no resource address\n", ecc_name); | |
1932 | goto err_release_group; | |
1933 | } | |
1934 | ||
1935 | edac_idx = edac_device_alloc_index(); | |
1936 | dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, | |
1937 | 1, ecc_name, 1, 0, NULL, 0, | |
1938 | edac_idx); | |
1939 | ||
1940 | if (!dci) { | |
1941 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1942 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
1943 | rc = -ENOMEM; | |
1944 | goto err_release_group; | |
1945 | } | |
1946 | ||
1947 | altdev = dci->pvt_info; | |
1948 | dci->dev = edac->dev; | |
1949 | altdev->edac_dev_name = ecc_name; | |
1950 | altdev->edac_idx = edac_idx; | |
1951 | altdev->edac = edac; | |
1952 | altdev->edac_dev = dci; | |
1953 | altdev->data = prv; | |
1954 | altdev->ddev = *edac->dev; | |
1955 | dci->dev = &altdev->ddev; | |
1956 | dci->ctl_name = "Altera ECC Manager"; | |
1957 | dci->mod_name = ecc_name; | |
1958 | dci->dev_name = ecc_name; | |
1959 | ||
1960 | altdev->base = devm_ioremap_resource(edac->dev, &res); | |
1961 | if (IS_ERR(altdev->base)) { | |
1962 | rc = PTR_ERR(altdev->base); | |
1963 | goto err_release_group1; | |
1964 | } | |
1965 | ||
1966 | /* Check specific dependencies for the module */ | |
1967 | if (altdev->data->setup) { | |
1968 | rc = altdev->data->setup(altdev); | |
1969 | if (rc) | |
1970 | goto err_release_group1; | |
1971 | } | |
1972 | ||
13ab8448 TT |
1973 | altdev->sb_irq = irq_of_parse_and_map(np, 0); |
1974 | if (!altdev->sb_irq) { | |
1975 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); | |
1976 | rc = -ENODEV; | |
1977 | goto err_release_group1; | |
1978 | } | |
a29d64a4 TT |
1979 | rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, |
1980 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
1981 | ecc_name, altdev); | |
13ab8448 | 1982 | if (rc) { |
3763569f | 1983 | edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); |
13ab8448 TT |
1984 | goto err_release_group1; |
1985 | } | |
1986 | ||
1bd76ff4 TT |
1987 | #ifdef CONFIG_ARCH_STRATIX10 |
1988 | /* Use IRQ to determine SError origin instead of assigning IRQ */ | |
1989 | rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); | |
1990 | if (rc) { | |
1991 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
1992 | "Unable to parse DB IRQ index\n"); | |
1993 | goto err_release_group1; | |
1994 | } | |
1995 | #else | |
13ab8448 TT |
1996 | altdev->db_irq = irq_of_parse_and_map(np, 1); |
1997 | if (!altdev->db_irq) { | |
1998 | edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); | |
1999 | rc = -ENODEV; | |
2000 | goto err_release_group1; | |
2001 | } | |
a29d64a4 TT |
2002 | rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, |
2003 | IRQF_ONESHOT | IRQF_TRIGGER_HIGH, | |
2004 | ecc_name, altdev); | |
13ab8448 TT |
2005 | if (rc) { |
2006 | edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); | |
2007 | goto err_release_group1; | |
2008 | } | |
1bd76ff4 | 2009 | #endif |
13ab8448 | 2010 | |
588cb03e TT |
2011 | rc = edac_device_add_device(dci); |
2012 | if (rc) { | |
2013 | dev_err(edac->dev, "edac_device_add_device failed\n"); | |
2014 | rc = -ENOMEM; | |
2015 | goto err_release_group1; | |
2016 | } | |
2017 | ||
2018 | altr_create_edacdev_dbgfs(dci, prv); | |
2019 | ||
2020 | list_add(&altdev->next, &edac->a10_ecc_devices); | |
2021 | ||
2022 | devres_remove_group(edac->dev, altr_edac_a10_device_add); | |
2023 | ||
2024 | return 0; | |
2025 | ||
2026 | err_release_group1: | |
2027 | edac_device_free_ctl_info(dci); | |
2028 | err_release_group: | |
588cb03e TT |
2029 | devres_release_group(edac->dev, NULL); |
2030 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2031 | "%s:Error setting up EDAC device: %d\n", ecc_name, rc); | |
2032 | ||
2033 | return rc; | |
2034 | } | |
2035 | ||
13ab8448 TT |
2036 | static void a10_eccmgr_irq_mask(struct irq_data *d) |
2037 | { | |
2038 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
2039 | ||
2040 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, | |
2041 | BIT(d->hwirq)); | |
2042 | } | |
2043 | ||
2044 | static void a10_eccmgr_irq_unmask(struct irq_data *d) | |
2045 | { | |
2046 | struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); | |
2047 | ||
2048 | regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, | |
2049 | BIT(d->hwirq)); | |
2050 | } | |
2051 | ||
2052 | static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
2053 | irq_hw_number_t hwirq) | |
2054 | { | |
2055 | struct altr_arria10_edac *edac = d->host_data; | |
2056 | ||
2057 | irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); | |
2058 | irq_set_chip_data(irq, edac); | |
2059 | irq_set_noprobe(irq); | |
2060 | ||
2061 | return 0; | |
2062 | } | |
2063 | ||
18caec20 | 2064 | static const struct irq_domain_ops a10_eccmgr_ic_ops = { |
13ab8448 TT |
2065 | .map = a10_eccmgr_irqdomain_map, |
2066 | .xlate = irq_domain_xlate_twocell, | |
2067 | }; | |
2068 | ||
d5fc9125 TT |
2069 | /************** Stratix 10 EDAC Double Bit Error Handler ************/ |
2070 | #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m) | |
2071 | ||
1bd76ff4 TT |
2072 | #ifdef CONFIG_ARCH_STRATIX10 |
2073 | /* panic routine issues reboot on non-zero panic_timeout */ | |
2074 | extern int panic_timeout; | |
2075 | ||
d5fc9125 TT |
2076 | /* |
2077 | * The double bit error is handled through SError which is fatal. This is | |
2078 | * called as a panic notifier to printout ECC error info as part of the panic. | |
2079 | */ | |
2080 | static int s10_edac_dberr_handler(struct notifier_block *this, | |
2081 | unsigned long event, void *ptr) | |
2082 | { | |
2083 | struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier); | |
2084 | int err_addr, dberror; | |
2085 | ||
2086 | regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST, | |
2087 | &dberror); | |
2088 | regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror); | |
1bd76ff4 TT |
2089 | if (dberror & S10_DBE_IRQ_MASK) { |
2090 | struct list_head *position; | |
2091 | struct altr_edac_device_dev *ed; | |
2092 | struct arm_smccc_res result; | |
2093 | ||
2094 | /* Find the matching DBE in the list of devices */ | |
2095 | list_for_each(position, &edac->a10_ecc_devices) { | |
2096 | ed = list_entry(position, struct altr_edac_device_dev, | |
2097 | next); | |
2098 | if (!(BIT(ed->db_irq) & dberror)) | |
2099 | continue; | |
2100 | ||
2101 | writel(ALTR_A10_ECC_DERRPENA, | |
2102 | ed->base + ALTR_A10_ECC_INTSTAT_OFST); | |
2103 | err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST); | |
2104 | regmap_write(edac->ecc_mgr_map, | |
2105 | S10_SYSMGR_UE_ADDR_OFST, err_addr); | |
2106 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2107 | "EDAC: [Fatal DBE on %s @ 0x%08X]\n", | |
2108 | ed->edac_dev_name, err_addr); | |
2109 | break; | |
2110 | } | |
2111 | /* Notify the System through SMC. Reboot delay = 1 second */ | |
2112 | panic_timeout = 1; | |
2113 | arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0, | |
2114 | 0, 0, &result); | |
d5fc9125 TT |
2115 | } |
2116 | ||
2117 | return NOTIFY_DONE; | |
2118 | } | |
1bd76ff4 | 2119 | #endif |
d5fc9125 TT |
2120 | |
2121 | /****************** Arria 10 EDAC Probe Function *********************/ | |
588cb03e TT |
2122 | static int altr_edac_a10_probe(struct platform_device *pdev) |
2123 | { | |
2124 | struct altr_arria10_edac *edac; | |
2125 | struct device_node *child; | |
588cb03e TT |
2126 | |
2127 | edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); | |
2128 | if (!edac) | |
2129 | return -ENOMEM; | |
2130 | ||
2131 | edac->dev = &pdev->dev; | |
2132 | platform_set_drvdata(pdev, edac); | |
2133 | INIT_LIST_HEAD(&edac->a10_ecc_devices); | |
2134 | ||
d5fc9125 TT |
2135 | if (socfpga_is_a10()) { |
2136 | edac->ecc_mgr_map = | |
2137 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
588cb03e | 2138 | "altr,sysmgr-syscon"); |
d5fc9125 TT |
2139 | } else { |
2140 | struct device_node *sysmgr_np; | |
2141 | struct resource res; | |
8537bf10 | 2142 | uintptr_t base; |
d5fc9125 TT |
2143 | |
2144 | sysmgr_np = of_parse_phandle(pdev->dev.of_node, | |
2145 | "altr,sysmgr-syscon", 0); | |
2146 | if (!sysmgr_np) { | |
2147 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2148 | "Unable to find altr,sysmgr-syscon\n"); | |
2149 | return -ENODEV; | |
2150 | } | |
2151 | ||
2152 | if (of_address_to_resource(sysmgr_np, 0, &res)) | |
2153 | return -ENOMEM; | |
2154 | ||
2155 | /* Need physical address for SMCC call */ | |
8537bf10 | 2156 | base = res.start; |
d5fc9125 | 2157 | |
8537bf10 AB |
2158 | edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL, |
2159 | (void *)base, | |
d5fc9125 TT |
2160 | &s10_sdram_regmap_cfg); |
2161 | } | |
2162 | ||
588cb03e TT |
2163 | if (IS_ERR(edac->ecc_mgr_map)) { |
2164 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2165 | "Unable to get syscon altr,sysmgr-syscon\n"); | |
2166 | return PTR_ERR(edac->ecc_mgr_map); | |
2167 | } | |
2168 | ||
13ab8448 TT |
2169 | edac->irq_chip.name = pdev->dev.of_node->name; |
2170 | edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; | |
2171 | edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; | |
2172 | edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, | |
2173 | &a10_eccmgr_ic_ops, edac); | |
2174 | if (!edac->domain) { | |
2175 | dev_err(&pdev->dev, "Error adding IRQ domain\n"); | |
2176 | return -ENOMEM; | |
2177 | } | |
2178 | ||
588cb03e | 2179 | edac->sb_irq = platform_get_irq(pdev, 0); |
13ab8448 TT |
2180 | if (edac->sb_irq < 0) { |
2181 | dev_err(&pdev->dev, "No SBERR IRQ resource\n"); | |
2182 | return edac->sb_irq; | |
588cb03e TT |
2183 | } |
2184 | ||
13ab8448 TT |
2185 | irq_set_chained_handler_and_data(edac->sb_irq, |
2186 | altr_edac_a10_irq_handler, | |
2187 | edac); | |
2188 | ||
1bd76ff4 TT |
2189 | #ifdef CONFIG_ARCH_STRATIX10 |
2190 | { | |
d5fc9125 TT |
2191 | int dberror, err_addr; |
2192 | ||
2193 | edac->panic_notifier.notifier_call = s10_edac_dberr_handler; | |
2194 | atomic_notifier_chain_register(&panic_notifier_list, | |
2195 | &edac->panic_notifier); | |
2196 | ||
2197 | /* Printout a message if uncorrectable error previously. */ | |
2198 | regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, | |
2199 | &dberror); | |
2200 | if (dberror) { | |
2201 | regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST, | |
2202 | &err_addr); | |
2203 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
2204 | "Previous Boot UE detected[0x%X] @ 0x%X\n", | |
2205 | dberror, err_addr); | |
2206 | /* Reset the sticky registers */ | |
2207 | regmap_write(edac->ecc_mgr_map, | |
2208 | S10_SYSMGR_UE_VAL_OFST, 0); | |
2209 | regmap_write(edac->ecc_mgr_map, | |
2210 | S10_SYSMGR_UE_ADDR_OFST, 0); | |
2211 | } | |
588cb03e | 2212 | } |
1bd76ff4 TT |
2213 | #else |
2214 | edac->db_irq = platform_get_irq(pdev, 1); | |
2215 | if (edac->db_irq < 0) { | |
2216 | dev_err(&pdev->dev, "No DBERR IRQ resource\n"); | |
2217 | return edac->db_irq; | |
2218 | } | |
2219 | irq_set_chained_handler_and_data(edac->db_irq, | |
2220 | altr_edac_a10_irq_handler, edac); | |
2221 | #endif | |
588cb03e TT |
2222 | |
2223 | for_each_child_of_node(pdev->dev.of_node, child) { | |
2224 | if (!of_device_is_available(child)) | |
2225 | continue; | |
c6882fb2 TT |
2226 | |
2227 | if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || | |
2228 | of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || | |
2229 | of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || | |
e8263793 | 2230 | of_device_is_compatible(child, "altr,socfpga-nand-ecc") || |
c609581d | 2231 | of_device_is_compatible(child, "altr,socfpga-dma-ecc") || |
485fe9e2 | 2232 | of_device_is_compatible(child, "altr,socfpga-usb-ecc") || |
91104984 TT |
2233 | of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || |
2234 | of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) | |
c6882fb2 | 2235 | |
c7b4be8d | 2236 | altr_edac_a10_device_add(edac, child); |
c6882fb2 | 2237 | |
580b5cf5 | 2238 | #ifdef CONFIG_EDAC_ALTERA_SDRAM |
d5fc9125 TT |
2239 | else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) || |
2240 | (of_device_is_compatible(child, "altr,sdram-edac-s10"))) | |
ab564cb5 TT |
2241 | of_platform_populate(pdev->dev.of_node, |
2242 | altr_sdram_ctrl_of_match, | |
2243 | NULL, &pdev->dev); | |
580b5cf5 | 2244 | #endif |
588cb03e TT |
2245 | } |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | ||
2250 | static const struct of_device_id altr_edac_a10_of_match[] = { | |
2251 | { .compatible = "altr,socfpga-a10-ecc-manager" }, | |
d5fc9125 | 2252 | { .compatible = "altr,socfpga-s10-ecc-manager" }, |
588cb03e TT |
2253 | {}, |
2254 | }; | |
2255 | MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); | |
2256 | ||
2257 | static struct platform_driver altr_edac_a10_driver = { | |
2258 | .probe = altr_edac_a10_probe, | |
2259 | .driver = { | |
2260 | .name = "socfpga_a10_ecc_manager", | |
2261 | .of_match_table = altr_edac_a10_of_match, | |
2262 | }, | |
2263 | }; | |
2264 | module_platform_driver(altr_edac_a10_driver); | |
2265 | ||
71bcada8 TT |
2266 | MODULE_LICENSE("GPL v2"); |
2267 | MODULE_AUTHOR("Thor Thayer"); | |
c3eea194 | 2268 | MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); |