Commit | Line | Data |
---|---|---|
da9bb1d2 AC |
1 | # |
2 | # EDAC Kconfig | |
4577ca55 | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
da9bb1d2 | 4 | # Licensed and distributed under the GPL |
b01aec9b BP |
5 | |
6 | config EDAC_ATOMIC_SCRUB | |
7 | bool | |
da9bb1d2 | 8 | |
54451663 BP |
9 | config EDAC_SUPPORT |
10 | bool | |
11 | ||
751cb5e5 | 12 | menuconfig EDAC |
e3c4ff6d BP |
13 | tristate "EDAC (Error Detection And Correction) reporting" |
14 | depends on HAS_IOMEM && EDAC_SUPPORT && RAS | |
da9bb1d2 | 15 | help |
a06b85ff BP |
16 | EDAC is a subsystem along with hardware-specific drivers designed to |
17 | report hardware errors. These are low-level errors that are reported | |
18 | in the CPU or supporting chipset or other subsystems: | |
8cb2a398 DT |
19 | memory errors, cache errors, PCI errors, thermal throttling, etc.. |
20 | If unsure, select 'Y'. | |
da9bb1d2 | 21 | |
a06b85ff | 22 | The mailing list for the EDAC project is linux-edac@vger.kernel.org. |
57c432b5 | 23 | |
751cb5e5 | 24 | if EDAC |
da9bb1d2 | 25 | |
19974710 MCC |
26 | config EDAC_LEGACY_SYSFS |
27 | bool "EDAC legacy sysfs" | |
28 | default y | |
29 | help | |
30 | Enable the compatibility sysfs nodes. | |
31 | Use 'Y' if your edac utilities aren't ported to work with the newer | |
32 | structures. | |
33 | ||
da9bb1d2 AC |
34 | config EDAC_DEBUG |
35 | bool "Debugging" | |
1c5bf781 | 36 | select DEBUG_FS |
da9bb1d2 | 37 | help |
37929874 BP |
38 | This turns on debugging information for the entire EDAC subsystem. |
39 | You do so by inserting edac_module with "edac_debug_level=x." Valid | |
40 | levels are 0-4 (from low to high) and by default it is set to 2. | |
41 | Usually you should select 'N' here. | |
da9bb1d2 | 42 | |
9cdeb404 | 43 | config EDAC_DECODE_MCE |
0d18b2e3 | 44 | tristate "Decode MCEs in human-readable form (only on AMD for now)" |
168eb34d | 45 | depends on CPU_SUP_AMD && X86_MCE_AMD |
0d18b2e3 BP |
46 | default y |
47 | ---help--- | |
48 | Enable this option if you want to decode Machine Check Exceptions | |
25985edc | 49 | occurring on your machine in human-readable form. |
0d18b2e3 BP |
50 | |
51 | You should definitely say Y here in case you want to decode MCEs | |
52 | which occur really early upon boot, before the module infrastructure | |
53 | has been initialized. | |
54 | ||
77c5f5d2 MCC |
55 | config EDAC_GHES |
56 | bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" | |
e3c4ff6d | 57 | depends on ACPI_APEI_GHES && (EDAC=y) |
77c5f5d2 MCC |
58 | help |
59 | Not all machines support hardware-driven error report. Some of those | |
60 | provide a BIOS-driven error report mechanism via ACPI, using the | |
61 | APEI/GHES driver. By enabling this option, the error reports provided | |
62 | by GHES are sent to userspace via the EDAC API. | |
63 | ||
64 | When this option is enabled, it will disable the hardware-driven | |
65 | mechanisms, if a GHES BIOS is detected, entering into the | |
66 | "Firmware First" mode. | |
67 | ||
68 | It should be noticed that keeping both GHES and a hardware-driven | |
69 | error mechanism won't work well, as BIOS will race with OS, while | |
70 | reading the error registers. So, if you want to not use "Firmware | |
71 | first" GHES error mechanism, you should disable GHES either at | |
72 | compilation time or by passing "ghes.disable=1" Kernel parameter | |
73 | at boot time. | |
74 | ||
75 | In doubt, say 'Y'. | |
76 | ||
7d6034d3 | 77 | config EDAC_AMD64 |
f5b10c45 | 78 | tristate "AMD64 (Opteron, Athlon64)" |
e3c4ff6d | 79 | depends on AMD_NB && EDAC_DECODE_MCE |
7d6034d3 | 80 | help |
027dbd6f | 81 | Support for error detection and correction of DRAM ECC errors on |
f5b10c45 | 82 | the AMD64 families (>= K8) of memory controllers. |
7d6034d3 DT |
83 | |
84 | config EDAC_AMD64_ERROR_INJECTION | |
9cdeb404 | 85 | bool "Sysfs HW Error injection facilities" |
7d6034d3 DT |
86 | depends on EDAC_AMD64 |
87 | help | |
88 | Recent Opterons (Family 10h and later) provide for Memory Error | |
89 | Injection into the ECC detection circuits. The amd64_edac module | |
90 | allows the operator/user to inject Uncorrectable and Correctable | |
91 | errors into DRAM. | |
92 | ||
93 | When enabled, in each of the respective memory controller directories | |
94 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: | |
95 | ||
96 | - inject_section (0..3, 16-byte section of 64-byte cacheline), | |
97 | - inject_word (0..8, 16-bit word of 16-byte section), | |
98 | - inject_ecc_vector (hex ecc vector: select bits of inject word) | |
99 | ||
100 | In addition, there are two control files, inject_read and inject_write, | |
101 | which trigger the DRAM ECC Read and Write respectively. | |
da9bb1d2 AC |
102 | |
103 | config EDAC_AMD76X | |
104 | tristate "AMD 76x (760, 762, 768)" | |
e3c4ff6d | 105 | depends on PCI && X86_32 |
da9bb1d2 AC |
106 | help |
107 | Support for error detection and correction on the AMD 76x | |
108 | series of chipsets used with the Athlon processor. | |
109 | ||
110 | config EDAC_E7XXX | |
111 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" | |
e3c4ff6d | 112 | depends on PCI && X86_32 |
da9bb1d2 AC |
113 | help |
114 | Support for error detection and correction on the Intel | |
115 | E7205, E7500, E7501 and E7505 server chipsets. | |
116 | ||
117 | config EDAC_E752X | |
5135b797 | 118 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
e3c4ff6d | 119 | depends on PCI && X86 |
da9bb1d2 AC |
120 | help |
121 | Support for error detection and correction on the Intel | |
122 | E7520, E7525, E7320 server chipsets. | |
123 | ||
5a2c675c TS |
124 | config EDAC_I82443BXGX |
125 | tristate "Intel 82443BX/GX (440BX/GX)" | |
e3c4ff6d | 126 | depends on PCI && X86_32 |
28f96eea | 127 | depends on BROKEN |
5a2c675c TS |
128 | help |
129 | Support for error detection and correction on the Intel | |
130 | 82443BX/GX memory controllers (440BX/GX chipsets). | |
131 | ||
da9bb1d2 AC |
132 | config EDAC_I82875P |
133 | tristate "Intel 82875p (D82875P, E7210)" | |
e3c4ff6d | 134 | depends on PCI && X86_32 |
da9bb1d2 AC |
135 | help |
136 | Support for error detection and correction on the Intel | |
137 | DP82785P and E7210 server chipsets. | |
138 | ||
420390f0 RD |
139 | config EDAC_I82975X |
140 | tristate "Intel 82975x (D82975x)" | |
e3c4ff6d | 141 | depends on PCI && X86 |
420390f0 RD |
142 | help |
143 | Support for error detection and correction on the Intel | |
144 | DP82975x server chipsets. | |
145 | ||
535c6a53 JU |
146 | config EDAC_I3000 |
147 | tristate "Intel 3000/3010" | |
e3c4ff6d | 148 | depends on PCI && X86 |
535c6a53 JU |
149 | help |
150 | Support for error detection and correction on the Intel | |
151 | 3000 and 3010 server chipsets. | |
152 | ||
dd8ef1db JU |
153 | config EDAC_I3200 |
154 | tristate "Intel 3200" | |
e3c4ff6d | 155 | depends on PCI && X86 |
dd8ef1db JU |
156 | help |
157 | Support for error detection and correction on the Intel | |
158 | 3200 and 3210 server chipsets. | |
159 | ||
7ee40b89 JB |
160 | config EDAC_IE31200 |
161 | tristate "Intel e312xx" | |
e3c4ff6d | 162 | depends on PCI && X86 |
7ee40b89 JB |
163 | help |
164 | Support for error detection and correction on the Intel | |
165 | E3-1200 based DRAM controllers. | |
166 | ||
df8bc08c HM |
167 | config EDAC_X38 |
168 | tristate "Intel X38" | |
e3c4ff6d | 169 | depends on PCI && X86 |
df8bc08c HM |
170 | help |
171 | Support for error detection and correction on the Intel | |
172 | X38 server chipsets. | |
173 | ||
920c8df6 MCC |
174 | config EDAC_I5400 |
175 | tristate "Intel 5400 (Seaburg) chipsets" | |
e3c4ff6d | 176 | depends on PCI && X86 |
920c8df6 MCC |
177 | help |
178 | Support for error detection and correction the Intel | |
179 | i5400 MCH chipset (Seaburg). | |
180 | ||
a0c36a1f MCC |
181 | config EDAC_I7CORE |
182 | tristate "Intel i7 Core (Nehalem) processors" | |
e3c4ff6d | 183 | depends on PCI && X86 && X86_MCE_INTEL |
a0c36a1f MCC |
184 | help |
185 | Support for error detection and correction the Intel | |
696e409d MCC |
186 | i7 Core (Nehalem) Integrated Memory Controller that exists on |
187 | newer processors like i7 Core, i7 Core Extreme, Xeon 35xx | |
188 | and Xeon 55xx processors. | |
a0c36a1f | 189 | |
da9bb1d2 AC |
190 | config EDAC_I82860 |
191 | tristate "Intel 82860" | |
e3c4ff6d | 192 | depends on PCI && X86_32 |
da9bb1d2 AC |
193 | help |
194 | Support for error detection and correction on the Intel | |
195 | 82860 chipset. | |
196 | ||
197 | config EDAC_R82600 | |
198 | tristate "Radisys 82600 embedded chipset" | |
e3c4ff6d | 199 | depends on PCI && X86_32 |
da9bb1d2 AC |
200 | help |
201 | Support for error detection and correction on the Radisys | |
202 | 82600 embedded chipset. | |
203 | ||
eb60705a EW |
204 | config EDAC_I5000 |
205 | tristate "Intel Greencreek/Blackford chipset" | |
e3c4ff6d | 206 | depends on X86 && PCI |
eb60705a EW |
207 | help |
208 | Support for error detection and correction the Intel | |
209 | Greekcreek/Blackford chipsets. | |
210 | ||
8f421c59 AJ |
211 | config EDAC_I5100 |
212 | tristate "Intel San Clemente MCH" | |
e3c4ff6d | 213 | depends on X86 && PCI |
8f421c59 AJ |
214 | help |
215 | Support for error detection and correction the Intel | |
216 | San Clemente MCH. | |
217 | ||
fcaf780b MCC |
218 | config EDAC_I7300 |
219 | tristate "Intel Clarksboro MCH" | |
e3c4ff6d | 220 | depends on X86 && PCI |
fcaf780b MCC |
221 | help |
222 | Support for error detection and correction the Intel | |
223 | Clarksboro MCH (Intel 7300 chipset). | |
224 | ||
3d78c9af | 225 | config EDAC_SBRIDGE |
50d1bb93 | 226 | tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" |
e3c4ff6d | 227 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG |
3d78c9af MCC |
228 | help |
229 | Support for error detection and correction the Intel | |
50d1bb93 | 230 | Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. |
3d78c9af | 231 | |
4ec656bd TL |
232 | config EDAC_SKX |
233 | tristate "Intel Skylake server Integrated MC" | |
24c9d423 | 234 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI |
de245ae0 | 235 | depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y |
58ca9ac1 | 236 | select DMI |
24c9d423 | 237 | select ACPI_ADXL |
4ec656bd TL |
238 | help |
239 | Support for error detection and correction the Intel | |
58ca9ac1 TL |
240 | Skylake server Integrated Memory Controllers. If your |
241 | system has non-volatile DIMMs you should also manually | |
242 | select CONFIG_ACPI_NFIT. | |
4ec656bd | 243 | |
d4dc89d0 QZ |
244 | config EDAC_I10NM |
245 | tristate "Intel 10nm server Integrated MC" | |
d6a9f733 | 246 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI |
d4dc89d0 QZ |
247 | depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y |
248 | select DMI | |
d6a9f733 | 249 | select ACPI_ADXL |
d4dc89d0 QZ |
250 | help |
251 | Support for error detection and correction the Intel | |
252 | 10nm server Integrated Memory Controllers. If your | |
253 | system has non-volatile DIMMs you should also manually | |
254 | select CONFIG_ACPI_NFIT. | |
255 | ||
5c71ad17 TL |
256 | config EDAC_PND2 |
257 | tristate "Intel Pondicherry2" | |
e3c4ff6d | 258 | depends on PCI && X86_64 && X86_MCE_INTEL |
5c71ad17 TL |
259 | help |
260 | Support for error detection and correction on the Intel | |
261 | Pondicherry2 Integrated Memory Controller. This SoC IP is | |
262 | first used on the Apollo Lake platform and Denverton | |
263 | micro-server but may appear on others in the future. | |
264 | ||
a9a753d5 | 265 | config EDAC_MPC85XX |
2b8358a9 ME |
266 | bool "Freescale MPC83xx / MPC85xx" |
267 | depends on FSL_SOC && EDAC=y | |
a9a753d5 DJ |
268 | help |
269 | Support for error detection and correction on the Freescale | |
74210267 | 270 | MPC8349, MPC8560, MPC8540, MPC8548, T4240 |
a9a753d5 | 271 | |
eeb3d68b YS |
272 | config EDAC_LAYERSCAPE |
273 | tristate "Freescale Layerscape DDR" | |
28dd6726 | 274 | depends on ARCH_LAYERSCAPE || SOC_LS1021A |
eeb3d68b YS |
275 | help |
276 | Support for error detection and correction on Freescale memory | |
277 | controllers on Layerscape SoCs. | |
278 | ||
4f4aeeab DJ |
279 | config EDAC_MV64X60 |
280 | tristate "Marvell MV64x60" | |
e3c4ff6d | 281 | depends on MV64X60 |
4f4aeeab DJ |
282 | help |
283 | Support for error detection and correction on the Marvell | |
284 | MV64360 and MV64460 chipsets. | |
285 | ||
7d8536fb EM |
286 | config EDAC_PASEMI |
287 | tristate "PA Semi PWRficient" | |
e3c4ff6d | 288 | depends on PPC_PASEMI && PCI |
7d8536fb EM |
289 | help |
290 | Support for error detection and correction on PA Semi | |
291 | PWRficient. | |
292 | ||
48764e41 BH |
293 | config EDAC_CELL |
294 | tristate "Cell Broadband Engine memory controller" | |
e3c4ff6d | 295 | depends on PPC_CELL_COMMON |
48764e41 BH |
296 | help |
297 | Support for error detection and correction on the | |
298 | Cell Broadband Engine internal memory controller | |
299 | on platform without a hypervisor | |
7d8536fb | 300 | |
dba7a77c GE |
301 | config EDAC_PPC4XX |
302 | tristate "PPC4xx IBM DDR2 Memory Controller" | |
e3c4ff6d | 303 | depends on 4xx |
dba7a77c GE |
304 | help |
305 | This enables support for EDAC on the ECC memory used | |
306 | with the IBM DDR2 memory controller found in various | |
307 | PowerPC 4xx embedded processors such as the 405EX[r], | |
308 | 440SP, 440SPe, 460EX, 460GT and 460SX. | |
309 | ||
e8765584 HC |
310 | config EDAC_AMD8131 |
311 | tristate "AMD8131 HyperTransport PCI-X Tunnel" | |
e3c4ff6d | 312 | depends on PCI && PPC_MAPLE |
e8765584 HC |
313 | help |
314 | Support for error detection and correction on the | |
315 | AMD8131 HyperTransport PCI-X Tunnel chip. | |
715fe7af HC |
316 | Note, add more Kconfig dependency if it's adopted |
317 | on some machine other than Maple. | |
e8765584 | 318 | |
58b4ce6f HC |
319 | config EDAC_AMD8111 |
320 | tristate "AMD8111 HyperTransport I/O Hub" | |
e3c4ff6d | 321 | depends on PCI && PPC_MAPLE |
58b4ce6f HC |
322 | help |
323 | Support for error detection and correction on the | |
324 | AMD8111 HyperTransport I/O Hub chip. | |
715fe7af HC |
325 | Note, add more Kconfig dependency if it's adopted |
326 | on some machine other than Maple. | |
58b4ce6f | 327 | |
2a9036af HC |
328 | config EDAC_CPC925 |
329 | tristate "IBM CPC925 Memory Controller (PPC970FX)" | |
e3c4ff6d | 330 | depends on PPC64 |
2a9036af HC |
331 | help |
332 | Support for error detection and correction on the | |
333 | IBM CPC925 Bridge and Memory Controller, which is | |
334 | a companion chip to the PowerPC 970 family of | |
335 | processors. | |
336 | ||
a1b01edb RH |
337 | config EDAC_HIGHBANK_MC |
338 | tristate "Highbank Memory Controller" | |
e3c4ff6d | 339 | depends on ARCH_HIGHBANK |
a1b01edb RH |
340 | help |
341 | Support for error detection and correction on the | |
342 | Calxeda Highbank memory controller. | |
343 | ||
69154d06 RH |
344 | config EDAC_HIGHBANK_L2 |
345 | tristate "Highbank L2 Cache" | |
e3c4ff6d | 346 | depends on ARCH_HIGHBANK |
69154d06 RH |
347 | help |
348 | Support for error detection and correction on the | |
349 | Calxeda Highbank memory controller. | |
350 | ||
f65aad41 RB |
351 | config EDAC_OCTEON_PC |
352 | tristate "Cavium Octeon Primary Caches" | |
e3c4ff6d | 353 | depends on CPU_CAVIUM_OCTEON |
f65aad41 RB |
354 | help |
355 | Support for error detection and correction on the primary caches of | |
356 | the cnMIPS cores of Cavium Octeon family SOCs. | |
357 | ||
358 | config EDAC_OCTEON_L2C | |
359 | tristate "Cavium Octeon Secondary Caches (L2C)" | |
e3c4ff6d | 360 | depends on CAVIUM_OCTEON_SOC |
f65aad41 RB |
361 | help |
362 | Support for error detection and correction on the | |
363 | Cavium Octeon family of SOCs. | |
364 | ||
365 | config EDAC_OCTEON_LMC | |
366 | tristate "Cavium Octeon DRAM Memory Controller (LMC)" | |
e3c4ff6d | 367 | depends on CAVIUM_OCTEON_SOC |
f65aad41 RB |
368 | help |
369 | Support for error detection and correction on the | |
370 | Cavium Octeon family of SOCs. | |
371 | ||
372 | config EDAC_OCTEON_PCI | |
373 | tristate "Cavium Octeon PCI Controller" | |
e3c4ff6d | 374 | depends on PCI && CAVIUM_OCTEON_SOC |
f65aad41 RB |
375 | help |
376 | Support for error detection and correction on the | |
377 | Cavium Octeon family of SOCs. | |
378 | ||
41003396 ST |
379 | config EDAC_THUNDERX |
380 | tristate "Cavium ThunderX EDAC" | |
41003396 ST |
381 | depends on ARM64 |
382 | depends on PCI | |
383 | help | |
384 | Support for error detection and correction on the | |
385 | Cavium ThunderX memory controllers (LMC), Cache | |
386 | Coherent Processor Interconnect (CCPI) and L2 cache | |
387 | blocks (TAD, CBC, MCI). | |
388 | ||
c3eea194 TT |
389 | config EDAC_ALTERA |
390 | bool "Altera SOCFPGA ECC" | |
3dab6bd5 | 391 | depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10) |
71bcada8 TT |
392 | help |
393 | Support for error detection and correction on the | |
580b5cf5 TT |
394 | Altera SOCs. This is the global enable for the |
395 | various Altera peripherals. | |
396 | ||
397 | config EDAC_ALTERA_SDRAM | |
398 | bool "Altera SDRAM ECC" | |
399 | depends on EDAC_ALTERA=y | |
400 | help | |
401 | Support for error detection and correction on the | |
402 | Altera SDRAM Memory for Altera SoCs. Note that the | |
403 | preloader must initialize the SDRAM before loading | |
404 | the kernel. | |
c3eea194 TT |
405 | |
406 | config EDAC_ALTERA_L2C | |
407 | bool "Altera L2 Cache ECC" | |
3a8f21f1 | 408 | depends on EDAC_ALTERA=y && CACHE_L2X0 |
c3eea194 TT |
409 | help |
410 | Support for error detection and correction on the | |
411 | Altera L2 cache Memory for Altera SoCs. This option | |
3a8f21f1 | 412 | requires L2 cache. |
c3eea194 TT |
413 | |
414 | config EDAC_ALTERA_OCRAM | |
415 | bool "Altera On-Chip RAM ECC" | |
416 | depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR | |
417 | help | |
418 | Support for error detection and correction on the | |
419 | Altera On-Chip RAM Memory for Altera SoCs. | |
71bcada8 | 420 | |
ab8c1e0f TT |
421 | config EDAC_ALTERA_ETHERNET |
422 | bool "Altera Ethernet FIFO ECC" | |
423 | depends on EDAC_ALTERA=y | |
424 | help | |
425 | Support for error detection and correction on the | |
426 | Altera Ethernet FIFO Memory for Altera SoCs. | |
427 | ||
c6882fb2 TT |
428 | config EDAC_ALTERA_NAND |
429 | bool "Altera NAND FIFO ECC" | |
430 | depends on EDAC_ALTERA=y && MTD_NAND_DENALI | |
431 | help | |
432 | Support for error detection and correction on the | |
433 | Altera NAND FIFO Memory for Altera SoCs. | |
434 | ||
e8263793 TT |
435 | config EDAC_ALTERA_DMA |
436 | bool "Altera DMA FIFO ECC" | |
437 | depends on EDAC_ALTERA=y && PL330_DMA=y | |
438 | help | |
439 | Support for error detection and correction on the | |
440 | Altera DMA FIFO Memory for Altera SoCs. | |
441 | ||
c609581d TT |
442 | config EDAC_ALTERA_USB |
443 | bool "Altera USB FIFO ECC" | |
444 | depends on EDAC_ALTERA=y && USB_DWC2 | |
445 | help | |
446 | Support for error detection and correction on the | |
447 | Altera USB FIFO Memory for Altera SoCs. | |
448 | ||
485fe9e2 TT |
449 | config EDAC_ALTERA_QSPI |
450 | bool "Altera QSPI FIFO ECC" | |
451 | depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI | |
452 | help | |
453 | Support for error detection and correction on the | |
454 | Altera QSPI FIFO Memory for Altera SoCs. | |
455 | ||
91104984 TT |
456 | config EDAC_ALTERA_SDMMC |
457 | bool "Altera SDMMC FIFO ECC" | |
458 | depends on EDAC_ALTERA=y && MMC_DW | |
459 | help | |
460 | Support for error detection and correction on the | |
461 | Altera SDMMC FIFO Memory for Altera SoCs. | |
462 | ||
91abaeaa YS |
463 | config EDAC_SIFIVE |
464 | bool "Sifive platform EDAC driver" | |
9209fb51 | 465 | depends on EDAC=y && SIFIVE_L2 |
91abaeaa YS |
466 | help |
467 | Support for error detection and correction on the SiFive SoCs. | |
468 | ||
7f6998a4 JL |
469 | config EDAC_ARMADA_XP |
470 | bool "Marvell Armada XP DDR and L2 Cache ECC" | |
471 | depends on MACH_MVEBU_V7 | |
472 | help | |
473 | Support for error correction and detection on the Marvell Aramada XP | |
474 | DDR RAM and L2 cache controllers. | |
475 | ||
ae9b56e3 PCK |
476 | config EDAC_SYNOPSYS |
477 | tristate "Synopsys DDR Memory Controller" | |
b500b4a0 | 478 | depends on ARCH_ZYNQ || ARCH_ZYNQMP |
ae9b56e3 PCK |
479 | help |
480 | Support for error detection and correction on the Synopsys DDR | |
481 | memory controller. | |
482 | ||
0d442930 LH |
483 | config EDAC_XGENE |
484 | tristate "APM X-Gene SoC" | |
e3c4ff6d | 485 | depends on (ARM64 || COMPILE_TEST) |
0d442930 LH |
486 | help |
487 | Support for error detection and correction on the | |
488 | APM X-Gene family of SOCs. | |
489 | ||
86a18ee2 TK |
490 | config EDAC_TI |
491 | tristate "Texas Instruments DDR3 ECC Controller" | |
492 | depends on ARCH_KEYSTONE || SOC_DRA7XX | |
493 | help | |
a483e227 | 494 | Support for error detection and correction on the TI SoCs. |
86a18ee2 | 495 | |
27450653 CK |
496 | config EDAC_QCOM |
497 | tristate "QCOM EDAC Controller" | |
498 | depends on ARCH_QCOM && QCOM_LLCC | |
499 | help | |
500 | Support for error detection and correction on the | |
501 | Qualcomm Technologies, Inc. SoCs. | |
502 | ||
503 | This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). | |
504 | As of now, it supports error reporting for Last Level Cache Controller (LLCC) | |
505 | of Tag RAM and Data RAM. | |
506 | ||
507 | For debugging issues having to do with stability and overall system | |
508 | health, you should probably say 'Y' here. | |
509 | ||
9b7e6242 SS |
510 | config EDAC_ASPEED |
511 | tristate "Aspeed AST 2500 SoC" | |
512 | depends on MACH_ASPEED_G5 | |
513 | help | |
514 | Support for error detection and correction on the Aspeed AST 2500 SoC. | |
515 | ||
516 | First, ECC must be configured in the bootloader. Then, this driver | |
517 | will expose error counters via the EDAC kernel framework. | |
518 | ||
82413e56 SKR |
519 | config EDAC_BLUEFIELD |
520 | tristate "Mellanox BlueField Memory ECC" | |
521 | depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) | |
522 | help | |
523 | Support for error detection and correction on the | |
524 | Mellanox BlueField SoCs. | |
525 | ||
1088750d LW |
526 | config EDAC_DMC520 |
527 | tristate "ARM DMC-520 ECC" | |
528 | depends on ARM64 | |
529 | help | |
530 | Support for error detection and correction on the | |
531 | SoCs with ARM DMC-520 DRAM controller. | |
532 | ||
751cb5e5 | 533 | endif # EDAC |