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da9bb1d2 AC |
1 | # |
2 | # EDAC Kconfig | |
4577ca55 | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
da9bb1d2 AC |
4 | # Licensed and distributed under the GPL |
5 | # | |
da9bb1d2 | 6 | |
751cb5e5 | 7 | menuconfig EDAC |
e24aca67 | 8 | bool "EDAC (Error Detection And Correction) reporting" |
e25df120 | 9 | depends on HAS_IOMEM |
f65aad41 | 10 | depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT |
da9bb1d2 AC |
11 | help |
12 | EDAC is designed to report errors in the core system. | |
13 | These are low-level errors that are reported in the CPU or | |
8cb2a398 DT |
14 | supporting chipset or other subsystems: |
15 | memory errors, cache errors, PCI errors, thermal throttling, etc.. | |
16 | If unsure, select 'Y'. | |
da9bb1d2 | 17 | |
57c432b5 TS |
18 | If this code is reporting problems on your system, please |
19 | see the EDAC project web pages for more information at: | |
20 | ||
21 | <http://bluesmoke.sourceforge.net/> | |
22 | ||
23 | and: | |
24 | ||
25 | <http://buttersideup.com/edacwiki> | |
26 | ||
27 | There is also a mailing list for the EDAC project, which can | |
28 | be found via the sourceforge page. | |
29 | ||
f65aad41 RB |
30 | config EDAC_SUPPORT |
31 | bool | |
32 | ||
751cb5e5 | 33 | if EDAC |
da9bb1d2 AC |
34 | |
35 | comment "Reporting subsystems" | |
da9bb1d2 | 36 | |
19974710 MCC |
37 | config EDAC_LEGACY_SYSFS |
38 | bool "EDAC legacy sysfs" | |
39 | default y | |
40 | help | |
41 | Enable the compatibility sysfs nodes. | |
42 | Use 'Y' if your edac utilities aren't ported to work with the newer | |
43 | structures. | |
44 | ||
da9bb1d2 AC |
45 | config EDAC_DEBUG |
46 | bool "Debugging" | |
da9bb1d2 | 47 | help |
37929874 BP |
48 | This turns on debugging information for the entire EDAC subsystem. |
49 | You do so by inserting edac_module with "edac_debug_level=x." Valid | |
50 | levels are 0-4 (from low to high) and by default it is set to 2. | |
51 | Usually you should select 'N' here. | |
da9bb1d2 | 52 | |
9cdeb404 | 53 | config EDAC_DECODE_MCE |
0d18b2e3 | 54 | tristate "Decode MCEs in human-readable form (only on AMD for now)" |
168eb34d | 55 | depends on CPU_SUP_AMD && X86_MCE_AMD |
0d18b2e3 BP |
56 | default y |
57 | ---help--- | |
58 | Enable this option if you want to decode Machine Check Exceptions | |
25985edc | 59 | occurring on your machine in human-readable form. |
0d18b2e3 BP |
60 | |
61 | You should definitely say Y here in case you want to decode MCEs | |
62 | which occur really early upon boot, before the module infrastructure | |
63 | has been initialized. | |
64 | ||
9cdeb404 BP |
65 | config EDAC_MCE_INJ |
66 | tristate "Simple MCE injection interface over /sysfs" | |
67 | depends on EDAC_DECODE_MCE | |
68 | default n | |
69 | help | |
70 | This is a simple interface to inject MCEs over /sysfs and test | |
71 | the MCE decoding code in EDAC. | |
72 | ||
73 | This is currently AMD-only. | |
74 | ||
da9bb1d2 AC |
75 | config EDAC_MM_EDAC |
76 | tristate "Main Memory EDAC (Error Detection And Correction) reporting" | |
da9bb1d2 AC |
77 | help |
78 | Some systems are able to detect and correct errors in main | |
79 | memory. EDAC can report statistics on memory error | |
80 | detection and correction (EDAC - or commonly referred to ECC | |
81 | errors). EDAC will also try to decode where these errors | |
82 | occurred so that a particular failing memory module can be | |
83 | replaced. If unsure, select 'Y'. | |
84 | ||
7d6034d3 | 85 | config EDAC_AMD64 |
027dbd6f BP |
86 | tristate "AMD64 (Opteron, Athlon64) K8, F10h" |
87 | depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE | |
7d6034d3 | 88 | help |
027dbd6f BP |
89 | Support for error detection and correction of DRAM ECC errors on |
90 | the AMD64 families of memory controllers (K8 and F10h) | |
7d6034d3 DT |
91 | |
92 | config EDAC_AMD64_ERROR_INJECTION | |
9cdeb404 | 93 | bool "Sysfs HW Error injection facilities" |
7d6034d3 DT |
94 | depends on EDAC_AMD64 |
95 | help | |
96 | Recent Opterons (Family 10h and later) provide for Memory Error | |
97 | Injection into the ECC detection circuits. The amd64_edac module | |
98 | allows the operator/user to inject Uncorrectable and Correctable | |
99 | errors into DRAM. | |
100 | ||
101 | When enabled, in each of the respective memory controller directories | |
102 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: | |
103 | ||
104 | - inject_section (0..3, 16-byte section of 64-byte cacheline), | |
105 | - inject_word (0..8, 16-bit word of 16-byte section), | |
106 | - inject_ecc_vector (hex ecc vector: select bits of inject word) | |
107 | ||
108 | In addition, there are two control files, inject_read and inject_write, | |
109 | which trigger the DRAM ECC Read and Write respectively. | |
da9bb1d2 AC |
110 | |
111 | config EDAC_AMD76X | |
112 | tristate "AMD 76x (760, 762, 768)" | |
90cbc45b | 113 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
114 | help |
115 | Support for error detection and correction on the AMD 76x | |
116 | series of chipsets used with the Athlon processor. | |
117 | ||
118 | config EDAC_E7XXX | |
119 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" | |
39f1d8d3 | 120 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
121 | help |
122 | Support for error detection and correction on the Intel | |
123 | E7205, E7500, E7501 and E7505 server chipsets. | |
124 | ||
125 | config EDAC_E752X | |
5135b797 | 126 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
da960a6a | 127 | depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG |
da9bb1d2 AC |
128 | help |
129 | Support for error detection and correction on the Intel | |
130 | E7520, E7525, E7320 server chipsets. | |
131 | ||
5a2c675c TS |
132 | config EDAC_I82443BXGX |
133 | tristate "Intel 82443BX/GX (440BX/GX)" | |
134 | depends on EDAC_MM_EDAC && PCI && X86_32 | |
28f96eea | 135 | depends on BROKEN |
5a2c675c TS |
136 | help |
137 | Support for error detection and correction on the Intel | |
138 | 82443BX/GX memory controllers (440BX/GX chipsets). | |
139 | ||
da9bb1d2 AC |
140 | config EDAC_I82875P |
141 | tristate "Intel 82875p (D82875P, E7210)" | |
39f1d8d3 | 142 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
143 | help |
144 | Support for error detection and correction on the Intel | |
145 | DP82785P and E7210 server chipsets. | |
146 | ||
420390f0 RD |
147 | config EDAC_I82975X |
148 | tristate "Intel 82975x (D82975x)" | |
149 | depends on EDAC_MM_EDAC && PCI && X86 | |
150 | help | |
151 | Support for error detection and correction on the Intel | |
152 | DP82975x server chipsets. | |
153 | ||
535c6a53 JU |
154 | config EDAC_I3000 |
155 | tristate "Intel 3000/3010" | |
f5c0454c | 156 | depends on EDAC_MM_EDAC && PCI && X86 |
535c6a53 JU |
157 | help |
158 | Support for error detection and correction on the Intel | |
159 | 3000 and 3010 server chipsets. | |
160 | ||
dd8ef1db JU |
161 | config EDAC_I3200 |
162 | tristate "Intel 3200" | |
163 | depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL | |
164 | help | |
165 | Support for error detection and correction on the Intel | |
166 | 3200 and 3210 server chipsets. | |
167 | ||
df8bc08c HM |
168 | config EDAC_X38 |
169 | tristate "Intel X38" | |
170 | depends on EDAC_MM_EDAC && PCI && X86 | |
171 | help | |
172 | Support for error detection and correction on the Intel | |
173 | X38 server chipsets. | |
174 | ||
920c8df6 MCC |
175 | config EDAC_I5400 |
176 | tristate "Intel 5400 (Seaburg) chipsets" | |
177 | depends on EDAC_MM_EDAC && PCI && X86 | |
178 | help | |
179 | Support for error detection and correction the Intel | |
180 | i5400 MCH chipset (Seaburg). | |
181 | ||
a0c36a1f MCC |
182 | config EDAC_I7CORE |
183 | tristate "Intel i7 Core (Nehalem) processors" | |
168eb34d | 184 | depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL |
a0c36a1f MCC |
185 | help |
186 | Support for error detection and correction the Intel | |
696e409d MCC |
187 | i7 Core (Nehalem) Integrated Memory Controller that exists on |
188 | newer processors like i7 Core, i7 Core Extreme, Xeon 35xx | |
189 | and Xeon 55xx processors. | |
a0c36a1f | 190 | |
da9bb1d2 AC |
191 | config EDAC_I82860 |
192 | tristate "Intel 82860" | |
39f1d8d3 | 193 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
194 | help |
195 | Support for error detection and correction on the Intel | |
196 | 82860 chipset. | |
197 | ||
198 | config EDAC_R82600 | |
199 | tristate "Radisys 82600 embedded chipset" | |
39f1d8d3 | 200 | depends on EDAC_MM_EDAC && PCI && X86_32 |
da9bb1d2 AC |
201 | help |
202 | Support for error detection and correction on the Radisys | |
203 | 82600 embedded chipset. | |
204 | ||
eb60705a EW |
205 | config EDAC_I5000 |
206 | tristate "Intel Greencreek/Blackford chipset" | |
207 | depends on EDAC_MM_EDAC && X86 && PCI | |
208 | help | |
209 | Support for error detection and correction the Intel | |
210 | Greekcreek/Blackford chipsets. | |
211 | ||
8f421c59 AJ |
212 | config EDAC_I5100 |
213 | tristate "Intel San Clemente MCH" | |
214 | depends on EDAC_MM_EDAC && X86 && PCI | |
215 | help | |
216 | Support for error detection and correction the Intel | |
217 | San Clemente MCH. | |
218 | ||
fcaf780b MCC |
219 | config EDAC_I7300 |
220 | tristate "Intel Clarksboro MCH" | |
221 | depends on EDAC_MM_EDAC && X86 && PCI | |
222 | help | |
223 | Support for error detection and correction the Intel | |
224 | Clarksboro MCH (Intel 7300 chipset). | |
225 | ||
3d78c9af MCC |
226 | config EDAC_SBRIDGE |
227 | tristate "Intel Sandy-Bridge Integrated MC" | |
22a5c27b HW |
228 | depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL |
229 | depends on PCI_MMCONFIG && EXPERIMENTAL | |
3d78c9af MCC |
230 | help |
231 | Support for error detection and correction the Intel | |
232 | Sandy Bridge Integrated Memory Controller. | |
233 | ||
a9a753d5 | 234 | config EDAC_MPC85XX |
b4846251 | 235 | tristate "Freescale MPC83xx / MPC85xx" |
1cd8521e | 236 | depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx) |
a9a753d5 DJ |
237 | help |
238 | Support for error detection and correction on the Freescale | |
b4846251 | 239 | MPC8349, MPC8560, MPC8540, MPC8548 |
a9a753d5 | 240 | |
4f4aeeab DJ |
241 | config EDAC_MV64X60 |
242 | tristate "Marvell MV64x60" | |
243 | depends on EDAC_MM_EDAC && MV64X60 | |
244 | help | |
245 | Support for error detection and correction on the Marvell | |
246 | MV64360 and MV64460 chipsets. | |
247 | ||
7d8536fb EM |
248 | config EDAC_PASEMI |
249 | tristate "PA Semi PWRficient" | |
250 | depends on EDAC_MM_EDAC && PCI | |
ddcc3050 | 251 | depends on PPC_PASEMI |
7d8536fb EM |
252 | help |
253 | Support for error detection and correction on PA Semi | |
254 | PWRficient. | |
255 | ||
48764e41 BH |
256 | config EDAC_CELL |
257 | tristate "Cell Broadband Engine memory controller" | |
def434c2 | 258 | depends on EDAC_MM_EDAC && PPC_CELL_COMMON |
48764e41 BH |
259 | help |
260 | Support for error detection and correction on the | |
261 | Cell Broadband Engine internal memory controller | |
262 | on platform without a hypervisor | |
7d8536fb | 263 | |
dba7a77c GE |
264 | config EDAC_PPC4XX |
265 | tristate "PPC4xx IBM DDR2 Memory Controller" | |
266 | depends on EDAC_MM_EDAC && 4xx | |
267 | help | |
268 | This enables support for EDAC on the ECC memory used | |
269 | with the IBM DDR2 memory controller found in various | |
270 | PowerPC 4xx embedded processors such as the 405EX[r], | |
271 | 440SP, 440SPe, 460EX, 460GT and 460SX. | |
272 | ||
e8765584 HC |
273 | config EDAC_AMD8131 |
274 | tristate "AMD8131 HyperTransport PCI-X Tunnel" | |
715fe7af | 275 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
e8765584 HC |
276 | help |
277 | Support for error detection and correction on the | |
278 | AMD8131 HyperTransport PCI-X Tunnel chip. | |
715fe7af HC |
279 | Note, add more Kconfig dependency if it's adopted |
280 | on some machine other than Maple. | |
e8765584 | 281 | |
58b4ce6f HC |
282 | config EDAC_AMD8111 |
283 | tristate "AMD8111 HyperTransport I/O Hub" | |
715fe7af | 284 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
58b4ce6f HC |
285 | help |
286 | Support for error detection and correction on the | |
287 | AMD8111 HyperTransport I/O Hub chip. | |
715fe7af HC |
288 | Note, add more Kconfig dependency if it's adopted |
289 | on some machine other than Maple. | |
58b4ce6f | 290 | |
2a9036af HC |
291 | config EDAC_CPC925 |
292 | tristate "IBM CPC925 Memory Controller (PPC970FX)" | |
293 | depends on EDAC_MM_EDAC && PPC64 | |
294 | help | |
295 | Support for error detection and correction on the | |
296 | IBM CPC925 Bridge and Memory Controller, which is | |
297 | a companion chip to the PowerPC 970 family of | |
298 | processors. | |
299 | ||
5c770755 CM |
300 | config EDAC_TILE |
301 | tristate "Tilera Memory Controller" | |
302 | depends on EDAC_MM_EDAC && TILE | |
303 | default y | |
304 | help | |
305 | Support for error detection and correction on the | |
306 | Tilera memory controller. | |
307 | ||
a1b01edb RH |
308 | config EDAC_HIGHBANK_MC |
309 | tristate "Highbank Memory Controller" | |
310 | depends on EDAC_MM_EDAC && ARCH_HIGHBANK | |
311 | help | |
312 | Support for error detection and correction on the | |
313 | Calxeda Highbank memory controller. | |
314 | ||
69154d06 RH |
315 | config EDAC_HIGHBANK_L2 |
316 | tristate "Highbank L2 Cache" | |
317 | depends on EDAC_MM_EDAC && ARCH_HIGHBANK | |
318 | help | |
319 | Support for error detection and correction on the | |
320 | Calxeda Highbank memory controller. | |
321 | ||
f65aad41 RB |
322 | config EDAC_OCTEON_PC |
323 | tristate "Cavium Octeon Primary Caches" | |
324 | depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON | |
325 | help | |
326 | Support for error detection and correction on the primary caches of | |
327 | the cnMIPS cores of Cavium Octeon family SOCs. | |
328 | ||
329 | config EDAC_OCTEON_L2C | |
330 | tristate "Cavium Octeon Secondary Caches (L2C)" | |
331 | depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON | |
332 | help | |
333 | Support for error detection and correction on the | |
334 | Cavium Octeon family of SOCs. | |
335 | ||
336 | config EDAC_OCTEON_LMC | |
337 | tristate "Cavium Octeon DRAM Memory Controller (LMC)" | |
338 | depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON | |
339 | help | |
340 | Support for error detection and correction on the | |
341 | Cavium Octeon family of SOCs. | |
342 | ||
343 | config EDAC_OCTEON_PCI | |
344 | tristate "Cavium Octeon PCI Controller" | |
345 | depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON | |
346 | help | |
347 | Support for error detection and correction on the | |
348 | Cavium Octeon family of SOCs. | |
349 | ||
751cb5e5 | 350 | endif # EDAC |