drm/vgem: off by one in vgem_gem_fault()
[linux-2.6-block.git] / drivers / dma-buf / dma-fence.c
CommitLineData
e941759c
ML
1/*
2 * Fence mechanism for dma-buf and to allow for asynchronous dma access
3 *
4 * Copyright (C) 2012 Canonical Ltd
5 * Copyright (C) 2012 Texas Instruments
6 *
7 * Authors:
8 * Rob Clark <robdclark@gmail.com>
9 * Maarten Lankhorst <maarten.lankhorst@canonical.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 */
20
21#include <linux/slab.h>
22#include <linux/export.h>
23#include <linux/atomic.h>
f54d1867 24#include <linux/dma-fence.h>
174cd4b1 25#include <linux/sched/signal.h>
e941759c
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26
27#define CREATE_TRACE_POINTS
f54d1867 28#include <trace/events/dma_fence.h>
e941759c 29
f54d1867 30EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
8c96c678 31EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
e941759c 32
e9f3b796 33/*
e941759c
ML
34 * fence context counter: each execution context should have its own
35 * fence context, this allows checking if fences belong to the same
36 * context or not. One device can have multiple separate contexts,
37 * and they're used if some engine can run independently of another.
38 */
f54d1867 39static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(0);
e941759c
ML
40
41/**
f54d1867 42 * dma_fence_context_alloc - allocate an array of fence contexts
e941759c
ML
43 * @num: [in] amount of contexts to allocate
44 *
45 * This function will return the first index of the number of fences allocated.
46 * The fence context is used for setting fence->context to a unique number.
47 */
f54d1867 48u64 dma_fence_context_alloc(unsigned num)
e941759c 49{
6ce31263 50 WARN_ON(!num);
f54d1867 51 return atomic64_add_return(num, &dma_fence_context_counter) - num;
e941759c 52}
f54d1867 53EXPORT_SYMBOL(dma_fence_context_alloc);
e941759c
ML
54
55/**
f54d1867 56 * dma_fence_signal_locked - signal completion of a fence
e941759c
ML
57 * @fence: the fence to signal
58 *
59 * Signal completion for software callbacks on a fence, this will unblock
f54d1867
CW
60 * dma_fence_wait() calls and run all the callbacks added with
61 * dma_fence_add_callback(). Can be called multiple times, but since a fence
e941759c
ML
62 * can only go from unsignaled to signaled state, it will only be effective
63 * the first time.
64 *
f54d1867 65 * Unlike dma_fence_signal, this function must be called with fence->lock held.
e941759c 66 */
f54d1867 67int dma_fence_signal_locked(struct dma_fence *fence)
e941759c 68{
f54d1867 69 struct dma_fence_cb *cur, *tmp;
e941759c
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70 int ret = 0;
71
78010cd9
RC
72 lockdep_assert_held(fence->lock);
73
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74 if (WARN_ON(!fence))
75 return -EINVAL;
76
f54d1867 77 if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
e941759c
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78 ret = -EINVAL;
79
80 /*
f54d1867 81 * we might have raced with the unlocked dma_fence_signal,
e941759c
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82 * still run through all callbacks
83 */
76250f2b
CW
84 } else {
85 fence->timestamp = ktime_get();
86 set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
f54d1867 87 trace_dma_fence_signaled(fence);
76250f2b 88 }
e941759c
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89
90 list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
91 list_del_init(&cur->node);
92 cur->func(fence, cur);
93 }
94 return ret;
95}
f54d1867 96EXPORT_SYMBOL(dma_fence_signal_locked);
e941759c
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97
98/**
f54d1867 99 * dma_fence_signal - signal completion of a fence
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100 * @fence: the fence to signal
101 *
102 * Signal completion for software callbacks on a fence, this will unblock
f54d1867
CW
103 * dma_fence_wait() calls and run all the callbacks added with
104 * dma_fence_add_callback(). Can be called multiple times, but since a fence
e941759c
ML
105 * can only go from unsignaled to signaled state, it will only be effective
106 * the first time.
107 */
f54d1867 108int dma_fence_signal(struct dma_fence *fence)
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ML
109{
110 unsigned long flags;
111
112 if (!fence)
113 return -EINVAL;
114
f54d1867 115 if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
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116 return -EINVAL;
117
76250f2b
CW
118 fence->timestamp = ktime_get();
119 set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
f54d1867 120 trace_dma_fence_signaled(fence);
e941759c 121
f54d1867
CW
122 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) {
123 struct dma_fence_cb *cur, *tmp;
e941759c
ML
124
125 spin_lock_irqsave(fence->lock, flags);
126 list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
127 list_del_init(&cur->node);
128 cur->func(fence, cur);
129 }
130 spin_unlock_irqrestore(fence->lock, flags);
131 }
132 return 0;
133}
f54d1867 134EXPORT_SYMBOL(dma_fence_signal);
e941759c
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135
136/**
f54d1867 137 * dma_fence_wait_timeout - sleep until the fence gets signaled
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138 * or until timeout elapses
139 * @fence: [in] the fence to wait on
140 * @intr: [in] if true, do an interruptible wait
141 * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
142 *
143 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
144 * remaining timeout in jiffies on success. Other error values may be
145 * returned on custom implementations.
146 *
147 * Performs a synchronous wait on this fence. It is assumed the caller
148 * directly or indirectly (buf-mgr between reservation and committing)
149 * holds a reference to the fence, otherwise the fence might be
150 * freed before return, resulting in undefined behavior.
151 */
152signed long
f54d1867 153dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout)
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ML
154{
155 signed long ret;
156
157 if (WARN_ON(timeout < 0))
158 return -EINVAL;
159
f54d1867 160 trace_dma_fence_wait_start(fence);
418cc6ca
DV
161 if (fence->ops->wait)
162 ret = fence->ops->wait(fence, intr, timeout);
163 else
164 ret = dma_fence_default_wait(fence, intr, timeout);
f54d1867 165 trace_dma_fence_wait_end(fence);
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166 return ret;
167}
f54d1867 168EXPORT_SYMBOL(dma_fence_wait_timeout);
e941759c 169
f54d1867 170void dma_fence_release(struct kref *kref)
e941759c 171{
f54d1867
CW
172 struct dma_fence *fence =
173 container_of(kref, struct dma_fence, refcount);
e941759c 174
f54d1867 175 trace_dma_fence_destroy(fence);
e941759c 176
4518cd28 177 /* Failed to signal before release, could be a refcounting issue */
6ce31263 178 WARN_ON(!list_empty(&fence->cb_list));
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179
180 if (fence->ops->release)
181 fence->ops->release(fence);
182 else
f54d1867 183 dma_fence_free(fence);
e941759c 184}
f54d1867 185EXPORT_SYMBOL(dma_fence_release);
e941759c 186
f54d1867 187void dma_fence_free(struct dma_fence *fence)
e941759c 188{
3c3b177a 189 kfree_rcu(fence, rcu);
e941759c 190}
f54d1867 191EXPORT_SYMBOL(dma_fence_free);
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192
193/**
f54d1867 194 * dma_fence_enable_sw_signaling - enable signaling on fence
e941759c
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195 * @fence: [in] the fence to enable
196 *
197 * this will request for sw signaling to be enabled, to make the fence
198 * complete as soon as possible
199 */
f54d1867 200void dma_fence_enable_sw_signaling(struct dma_fence *fence)
e941759c
ML
201{
202 unsigned long flags;
203
f54d1867
CW
204 if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
205 &fence->flags) &&
c701317a
DV
206 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) &&
207 fence->ops->enable_signaling) {
f54d1867 208 trace_dma_fence_enable_signal(fence);
e941759c
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209
210 spin_lock_irqsave(fence->lock, flags);
211
212 if (!fence->ops->enable_signaling(fence))
f54d1867 213 dma_fence_signal_locked(fence);
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214
215 spin_unlock_irqrestore(fence->lock, flags);
216 }
217}
f54d1867 218EXPORT_SYMBOL(dma_fence_enable_sw_signaling);
e941759c
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219
220/**
f54d1867 221 * dma_fence_add_callback - add a callback to be called when the fence
e941759c
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222 * is signaled
223 * @fence: [in] the fence to wait on
224 * @cb: [in] the callback to register
225 * @func: [in] the function to call
226 *
f54d1867 227 * cb will be initialized by dma_fence_add_callback, no initialization
e941759c
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228 * by the caller is required. Any number of callbacks can be registered
229 * to a fence, but a callback can only be registered to one fence at a time.
230 *
231 * Note that the callback can be called from an atomic context. If
232 * fence is already signaled, this function will return -ENOENT (and
233 * *not* call the callback)
234 *
235 * Add a software callback to the fence. Same restrictions apply to
f54d1867 236 * refcount as it does to dma_fence_wait, however the caller doesn't need to
e941759c
ML
237 * keep a refcount to fence afterwards: when software access is enabled,
238 * the creator of the fence is required to keep the fence alive until
f54d1867 239 * after it signals with dma_fence_signal. The callback itself can be called
e941759c
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240 * from irq context.
241 *
f642de16
GP
242 * Returns 0 in case of success, -ENOENT if the fence is already signaled
243 * and -EINVAL in case of error.
e941759c 244 */
f54d1867
CW
245int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb,
246 dma_fence_func_t func)
e941759c
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247{
248 unsigned long flags;
249 int ret = 0;
250 bool was_set;
251
252 if (WARN_ON(!fence || !func))
253 return -EINVAL;
254
f54d1867 255 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
e941759c
ML
256 INIT_LIST_HEAD(&cb->node);
257 return -ENOENT;
258 }
259
260 spin_lock_irqsave(fence->lock, flags);
261
f54d1867
CW
262 was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
263 &fence->flags);
e941759c 264
f54d1867 265 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
e941759c 266 ret = -ENOENT;
c701317a 267 else if (!was_set && fence->ops->enable_signaling) {
f54d1867 268 trace_dma_fence_enable_signal(fence);
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269
270 if (!fence->ops->enable_signaling(fence)) {
f54d1867 271 dma_fence_signal_locked(fence);
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272 ret = -ENOENT;
273 }
274 }
275
276 if (!ret) {
277 cb->func = func;
278 list_add_tail(&cb->node, &fence->cb_list);
279 } else
280 INIT_LIST_HEAD(&cb->node);
281 spin_unlock_irqrestore(fence->lock, flags);
282
283 return ret;
284}
f54d1867 285EXPORT_SYMBOL(dma_fence_add_callback);
e941759c 286
d6c99f4b
CW
287/**
288 * dma_fence_get_status - returns the status upon completion
289 * @fence: [in] the dma_fence to query
290 *
291 * This wraps dma_fence_get_status_locked() to return the error status
292 * condition on a signaled fence. See dma_fence_get_status_locked() for more
293 * details.
294 *
295 * Returns 0 if the fence has not yet been signaled, 1 if the fence has
296 * been signaled without an error condition, or a negative error code
297 * if the fence has been completed in err.
298 */
299int dma_fence_get_status(struct dma_fence *fence)
300{
301 unsigned long flags;
302 int status;
303
304 spin_lock_irqsave(fence->lock, flags);
305 status = dma_fence_get_status_locked(fence);
306 spin_unlock_irqrestore(fence->lock, flags);
307
308 return status;
309}
310EXPORT_SYMBOL(dma_fence_get_status);
311
e941759c 312/**
f54d1867 313 * dma_fence_remove_callback - remove a callback from the signaling list
e941759c
ML
314 * @fence: [in] the fence to wait on
315 * @cb: [in] the callback to remove
316 *
317 * Remove a previously queued callback from the fence. This function returns
f353d71f 318 * true if the callback is successfully removed, or false if the fence has
e941759c
ML
319 * already been signaled.
320 *
321 * *WARNING*:
322 * Cancelling a callback should only be done if you really know what you're
323 * doing, since deadlocks and race conditions could occur all too easily. For
324 * this reason, it should only ever be done on hardware lockup recovery,
325 * with a reference held to the fence.
326 */
327bool
f54d1867 328dma_fence_remove_callback(struct dma_fence *fence, struct dma_fence_cb *cb)
e941759c
ML
329{
330 unsigned long flags;
331 bool ret;
332
333 spin_lock_irqsave(fence->lock, flags);
334
335 ret = !list_empty(&cb->node);
336 if (ret)
337 list_del_init(&cb->node);
338
339 spin_unlock_irqrestore(fence->lock, flags);
340
341 return ret;
342}
f54d1867 343EXPORT_SYMBOL(dma_fence_remove_callback);
e941759c
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344
345struct default_wait_cb {
f54d1867 346 struct dma_fence_cb base;
e941759c
ML
347 struct task_struct *task;
348};
349
350static void
f54d1867 351dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
e941759c
ML
352{
353 struct default_wait_cb *wait =
354 container_of(cb, struct default_wait_cb, base);
355
356 wake_up_state(wait->task, TASK_NORMAL);
357}
358
359/**
f54d1867 360 * dma_fence_default_wait - default sleep until the fence gets signaled
e941759c
ML
361 * or until timeout elapses
362 * @fence: [in] the fence to wait on
363 * @intr: [in] if true, do an interruptible wait
364 * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
365 *
366 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
bcc004b6
AD
367 * remaining timeout in jiffies on success. If timeout is zero the value one is
368 * returned if the fence is already signaled for consistency with other
369 * functions taking a jiffies timeout.
e941759c
ML
370 */
371signed long
f54d1867 372dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
e941759c
ML
373{
374 struct default_wait_cb cb;
375 unsigned long flags;
bcc004b6 376 signed long ret = timeout ? timeout : 1;
e941759c
ML
377 bool was_set;
378
f54d1867 379 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
bcc004b6 380 return ret;
e941759c
ML
381
382 spin_lock_irqsave(fence->lock, flags);
383
384 if (intr && signal_pending(current)) {
385 ret = -ERESTARTSYS;
386 goto out;
387 }
388
f54d1867
CW
389 was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
390 &fence->flags);
e941759c 391
f54d1867 392 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
e941759c
ML
393 goto out;
394
c701317a 395 if (!was_set && fence->ops->enable_signaling) {
f54d1867 396 trace_dma_fence_enable_signal(fence);
e941759c
ML
397
398 if (!fence->ops->enable_signaling(fence)) {
f54d1867 399 dma_fence_signal_locked(fence);
e941759c
ML
400 goto out;
401 }
402 }
403
03c0c5f6
AR
404 if (!timeout) {
405 ret = 0;
406 goto out;
407 }
408
f54d1867 409 cb.base.func = dma_fence_default_wait_cb;
e941759c
ML
410 cb.task = current;
411 list_add(&cb.base.node, &fence->cb_list);
412
f54d1867 413 while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) {
e941759c
ML
414 if (intr)
415 __set_current_state(TASK_INTERRUPTIBLE);
416 else
417 __set_current_state(TASK_UNINTERRUPTIBLE);
418 spin_unlock_irqrestore(fence->lock, flags);
419
420 ret = schedule_timeout(ret);
421
422 spin_lock_irqsave(fence->lock, flags);
423 if (ret > 0 && intr && signal_pending(current))
424 ret = -ERESTARTSYS;
425 }
426
427 if (!list_empty(&cb.base.node))
428 list_del(&cb.base.node);
429 __set_current_state(TASK_RUNNING);
430
431out:
432 spin_unlock_irqrestore(fence->lock, flags);
433 return ret;
434}
f54d1867 435EXPORT_SYMBOL(dma_fence_default_wait);
e941759c 436
a519435a 437static bool
7392b4bb 438dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count,
439 uint32_t *idx)
a519435a
CK
440{
441 int i;
442
443 for (i = 0; i < count; ++i) {
f54d1867 444 struct dma_fence *fence = fences[i];
7392b4bb 445 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
446 if (idx)
447 *idx = i;
a519435a 448 return true;
7392b4bb 449 }
a519435a
CK
450 }
451 return false;
452}
453
454/**
f54d1867 455 * dma_fence_wait_any_timeout - sleep until any fence gets signaled
a519435a
CK
456 * or until timeout elapses
457 * @fences: [in] array of fences to wait on
458 * @count: [in] number of fences to wait on
459 * @intr: [in] if true, do an interruptible wait
460 * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
7392b4bb 461 * @idx: [out] the first signaled fence index, meaningful only on
462 * positive return
a519435a
CK
463 *
464 * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if
465 * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies
466 * on success.
467 *
468 * Synchronous waits for the first fence in the array to be signaled. The
469 * caller needs to hold a reference to all fences in the array, otherwise a
470 * fence might be freed before return, resulting in undefined behavior.
471 */
472signed long
f54d1867 473dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
7392b4bb 474 bool intr, signed long timeout, uint32_t *idx)
a519435a
CK
475{
476 struct default_wait_cb *cb;
477 signed long ret = timeout;
478 unsigned i;
479
480 if (WARN_ON(!fences || !count || timeout < 0))
481 return -EINVAL;
482
483 if (timeout == 0) {
484 for (i = 0; i < count; ++i)
7392b4bb 485 if (dma_fence_is_signaled(fences[i])) {
486 if (idx)
487 *idx = i;
a519435a 488 return 1;
7392b4bb 489 }
a519435a
CK
490
491 return 0;
492 }
493
494 cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL);
495 if (cb == NULL) {
496 ret = -ENOMEM;
497 goto err_free_cb;
498 }
499
500 for (i = 0; i < count; ++i) {
f54d1867 501 struct dma_fence *fence = fences[i];
a519435a 502
a519435a 503 cb[i].task = current;
f54d1867
CW
504 if (dma_fence_add_callback(fence, &cb[i].base,
505 dma_fence_default_wait_cb)) {
a519435a 506 /* This fence is already signaled */
7392b4bb 507 if (idx)
508 *idx = i;
a519435a
CK
509 goto fence_rm_cb;
510 }
511 }
512
513 while (ret > 0) {
514 if (intr)
515 set_current_state(TASK_INTERRUPTIBLE);
516 else
517 set_current_state(TASK_UNINTERRUPTIBLE);
518
7392b4bb 519 if (dma_fence_test_signaled_any(fences, count, idx))
a519435a
CK
520 break;
521
522 ret = schedule_timeout(ret);
523
524 if (ret > 0 && intr && signal_pending(current))
525 ret = -ERESTARTSYS;
526 }
527
528 __set_current_state(TASK_RUNNING);
529
530fence_rm_cb:
531 while (i-- > 0)
f54d1867 532 dma_fence_remove_callback(fences[i], &cb[i].base);
a519435a
CK
533
534err_free_cb:
535 kfree(cb);
536
537 return ret;
538}
f54d1867 539EXPORT_SYMBOL(dma_fence_wait_any_timeout);
a519435a 540
e941759c 541/**
f54d1867 542 * dma_fence_init - Initialize a custom fence.
e941759c 543 * @fence: [in] the fence to initialize
f54d1867 544 * @ops: [in] the dma_fence_ops for operations on this fence
e941759c
ML
545 * @lock: [in] the irqsafe spinlock to use for locking this fence
546 * @context: [in] the execution context this fence is run on
547 * @seqno: [in] a linear increasing sequence number for this context
548 *
549 * Initializes an allocated fence, the caller doesn't have to keep its
550 * refcount after committing with this fence, but it will need to hold a
f54d1867 551 * refcount again if dma_fence_ops.enable_signaling gets called. This can
e941759c
ML
552 * be used for other implementing other types of fence.
553 *
554 * context and seqno are used for easy comparison between fences, allowing
f54d1867 555 * to check which fence is later by simply using dma_fence_later.
e941759c
ML
556 */
557void
f54d1867
CW
558dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops,
559 spinlock_t *lock, u64 context, unsigned seqno)
e941759c
ML
560{
561 BUG_ON(!lock);
418cc6ca 562 BUG_ON(!ops || !ops->get_driver_name || !ops->get_timeline_name);
e941759c
ML
563
564 kref_init(&fence->refcount);
565 fence->ops = ops;
566 INIT_LIST_HEAD(&fence->cb_list);
567 fence->lock = lock;
568 fence->context = context;
569 fence->seqno = seqno;
570 fence->flags = 0UL;
a009e975 571 fence->error = 0;
e941759c 572
f54d1867 573 trace_dma_fence_init(fence);
e941759c 574}
f54d1867 575EXPORT_SYMBOL(dma_fence_init);