drm/mcde: dsi: Fix return value check in mcde_dsi_bind()
[linux-2.6-block.git] / drivers / dma-buf / dma-fence.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
e941759c
ML
2/*
3 * Fence mechanism for dma-buf and to allow for asynchronous dma access
4 *
5 * Copyright (C) 2012 Canonical Ltd
6 * Copyright (C) 2012 Texas Instruments
7 *
8 * Authors:
9 * Rob Clark <robdclark@gmail.com>
10 * Maarten Lankhorst <maarten.lankhorst@canonical.com>
e941759c
ML
11 */
12
13#include <linux/slab.h>
14#include <linux/export.h>
15#include <linux/atomic.h>
f54d1867 16#include <linux/dma-fence.h>
174cd4b1 17#include <linux/sched/signal.h>
e941759c
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18
19#define CREATE_TRACE_POINTS
f54d1867 20#include <trace/events/dma_fence.h>
e941759c 21
f54d1867 22EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
8c96c678 23EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
c36beba6 24EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
e941759c 25
078dec33
CK
26static DEFINE_SPINLOCK(dma_fence_stub_lock);
27static struct dma_fence dma_fence_stub;
28
e9f3b796 29/*
e941759c
ML
30 * fence context counter: each execution context should have its own
31 * fence context, this allows checking if fences belong to the same
32 * context or not. One device can have multiple separate contexts,
33 * and they're used if some engine can run independently of another.
34 */
078dec33 35static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(1);
e941759c 36
4dd3cdb2
DV
37/**
38 * DOC: DMA fences overview
39 *
40 * DMA fences, represented by &struct dma_fence, are the kernel internal
41 * synchronization primitive for DMA operations like GPU rendering, video
42 * encoding/decoding, or displaying buffers on a screen.
43 *
44 * A fence is initialized using dma_fence_init() and completed using
45 * dma_fence_signal(). Fences are associated with a context, allocated through
46 * dma_fence_context_alloc(), and all fences on the same context are
47 * fully ordered.
48 *
49 * Since the purposes of fences is to facilitate cross-device and
50 * cross-application synchronization, there's multiple ways to use one:
51 *
52 * - Individual fences can be exposed as a &sync_file, accessed as a file
53 * descriptor from userspace, created by calling sync_file_create(). This is
54 * called explicit fencing, since userspace passes around explicit
55 * synchronization points.
56 *
57 * - Some subsystems also have their own explicit fencing primitives, like
58 * &drm_syncobj. Compared to &sync_file, a &drm_syncobj allows the underlying
59 * fence to be updated.
60 *
61 * - Then there's also implicit fencing, where the synchronization points are
62 * implicitly passed around as part of shared &dma_buf instances. Such
52791eee 63 * implicit fences are stored in &struct dma_resv through the
4dd3cdb2
DV
64 * &dma_buf.resv pointer.
65 */
66
078dec33
CK
67static const char *dma_fence_stub_get_name(struct dma_fence *fence)
68{
69 return "stub";
70}
71
72static const struct dma_fence_ops dma_fence_stub_ops = {
73 .get_driver_name = dma_fence_stub_get_name,
74 .get_timeline_name = dma_fence_stub_get_name,
75};
76
77/**
78 * dma_fence_get_stub - return a signaled fence
79 *
80 * Return a stub fence which is already signaled.
81 */
82struct dma_fence *dma_fence_get_stub(void)
83{
84 spin_lock(&dma_fence_stub_lock);
85 if (!dma_fence_stub.ops) {
86 dma_fence_init(&dma_fence_stub,
87 &dma_fence_stub_ops,
88 &dma_fence_stub_lock,
89 0, 0);
90 dma_fence_signal_locked(&dma_fence_stub);
91 }
92 spin_unlock(&dma_fence_stub_lock);
93
94 return dma_fence_get(&dma_fence_stub);
95}
96EXPORT_SYMBOL(dma_fence_get_stub);
97
e941759c 98/**
f54d1867 99 * dma_fence_context_alloc - allocate an array of fence contexts
4dd3cdb2 100 * @num: amount of contexts to allocate
e941759c 101 *
4dd3cdb2
DV
102 * This function will return the first index of the number of fence contexts
103 * allocated. The fence context is used for setting &dma_fence.context to a
104 * unique number by passing the context to dma_fence_init().
e941759c 105 */
f54d1867 106u64 dma_fence_context_alloc(unsigned num)
e941759c 107{
6ce31263 108 WARN_ON(!num);
f54d1867 109 return atomic64_add_return(num, &dma_fence_context_counter) - num;
e941759c 110}
f54d1867 111EXPORT_SYMBOL(dma_fence_context_alloc);
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ML
112
113/**
f54d1867 114 * dma_fence_signal_locked - signal completion of a fence
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115 * @fence: the fence to signal
116 *
117 * Signal completion for software callbacks on a fence, this will unblock
f54d1867
CW
118 * dma_fence_wait() calls and run all the callbacks added with
119 * dma_fence_add_callback(). Can be called multiple times, but since a fence
4dd3cdb2
DV
120 * can only go from the unsignaled to the signaled state and not back, it will
121 * only be effective the first time.
122 *
123 * Unlike dma_fence_signal(), this function must be called with &dma_fence.lock
124 * held.
e941759c 125 *
4dd3cdb2
DV
126 * Returns 0 on success and a negative error value when @fence has been
127 * signalled already.
e941759c 128 */
f54d1867 129int dma_fence_signal_locked(struct dma_fence *fence)
e941759c 130{
f54d1867 131 struct dma_fence_cb *cur, *tmp;
f2cb60e9 132 struct list_head cb_list;
e941759c 133
78010cd9
RC
134 lockdep_assert_held(fence->lock);
135
0fc89b68
CW
136 if (unlikely(test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
137 &fence->flags)))
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138 return -EINVAL;
139
f2cb60e9
CW
140 /* Stash the cb_list before replacing it with the timestamp */
141 list_replace(&fence->cb_list, &cb_list);
142
0fc89b68
CW
143 fence->timestamp = ktime_get();
144 set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
145 trace_dma_fence_signaled(fence);
e941759c 146
f2cb60e9
CW
147 list_for_each_entry_safe(cur, tmp, &cb_list, node) {
148 INIT_LIST_HEAD(&cur->node);
149 cur->func(fence, cur);
e941759c 150 }
0fc89b68
CW
151
152 return 0;
e941759c 153}
f54d1867 154EXPORT_SYMBOL(dma_fence_signal_locked);
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155
156/**
f54d1867 157 * dma_fence_signal - signal completion of a fence
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158 * @fence: the fence to signal
159 *
160 * Signal completion for software callbacks on a fence, this will unblock
f54d1867
CW
161 * dma_fence_wait() calls and run all the callbacks added with
162 * dma_fence_add_callback(). Can be called multiple times, but since a fence
4dd3cdb2
DV
163 * can only go from the unsignaled to the signaled state and not back, it will
164 * only be effective the first time.
165 *
166 * Returns 0 on success and a negative error value when @fence has been
167 * signalled already.
e941759c 168 */
f54d1867 169int dma_fence_signal(struct dma_fence *fence)
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ML
170{
171 unsigned long flags;
0fc89b68 172 int ret;
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173
174 if (!fence)
175 return -EINVAL;
176
0fc89b68
CW
177 spin_lock_irqsave(fence->lock, flags);
178 ret = dma_fence_signal_locked(fence);
179 spin_unlock_irqrestore(fence->lock, flags);
e941759c 180
0fc89b68 181 return ret;
e941759c 182}
f54d1867 183EXPORT_SYMBOL(dma_fence_signal);
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184
185/**
f54d1867 186 * dma_fence_wait_timeout - sleep until the fence gets signaled
e941759c 187 * or until timeout elapses
4dd3cdb2
DV
188 * @fence: the fence to wait on
189 * @intr: if true, do an interruptible wait
190 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
e941759c
ML
191 *
192 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
193 * remaining timeout in jiffies on success. Other error values may be
194 * returned on custom implementations.
195 *
196 * Performs a synchronous wait on this fence. It is assumed the caller
197 * directly or indirectly (buf-mgr between reservation and committing)
198 * holds a reference to the fence, otherwise the fence might be
199 * freed before return, resulting in undefined behavior.
4dd3cdb2
DV
200 *
201 * See also dma_fence_wait() and dma_fence_wait_any_timeout().
e941759c
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202 */
203signed long
f54d1867 204dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout)
e941759c
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205{
206 signed long ret;
207
208 if (WARN_ON(timeout < 0))
209 return -EINVAL;
210
f54d1867 211 trace_dma_fence_wait_start(fence);
418cc6ca
DV
212 if (fence->ops->wait)
213 ret = fence->ops->wait(fence, intr, timeout);
214 else
215 ret = dma_fence_default_wait(fence, intr, timeout);
f54d1867 216 trace_dma_fence_wait_end(fence);
e941759c
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217 return ret;
218}
f54d1867 219EXPORT_SYMBOL(dma_fence_wait_timeout);
e941759c 220
4dd3cdb2
DV
221/**
222 * dma_fence_release - default relese function for fences
223 * @kref: &dma_fence.recfount
224 *
225 * This is the default release functions for &dma_fence. Drivers shouldn't call
226 * this directly, but instead call dma_fence_put().
227 */
f54d1867 228void dma_fence_release(struct kref *kref)
e941759c 229{
f54d1867
CW
230 struct dma_fence *fence =
231 container_of(kref, struct dma_fence, refcount);
e941759c 232
f54d1867 233 trace_dma_fence_destroy(fence);
e941759c 234
f2cb60e9
CW
235 if (WARN(!list_empty(&fence->cb_list) &&
236 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags),
427231bc
CW
237 "Fence %s:%s:%llx:%llx released with pending signals!\n",
238 fence->ops->get_driver_name(fence),
239 fence->ops->get_timeline_name(fence),
240 fence->context, fence->seqno)) {
241 unsigned long flags;
242
243 /*
244 * Failed to signal before release, likely a refcounting issue.
245 *
246 * This should never happen, but if it does make sure that we
247 * don't leave chains dangling. We set the error flag first
248 * so that the callbacks know this signal is due to an error.
249 */
250 spin_lock_irqsave(fence->lock, flags);
251 fence->error = -EDEADLK;
252 dma_fence_signal_locked(fence);
253 spin_unlock_irqrestore(fence->lock, flags);
254 }
e941759c
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255
256 if (fence->ops->release)
257 fence->ops->release(fence);
258 else
f54d1867 259 dma_fence_free(fence);
e941759c 260}
f54d1867 261EXPORT_SYMBOL(dma_fence_release);
e941759c 262
4dd3cdb2
DV
263/**
264 * dma_fence_free - default release function for &dma_fence.
265 * @fence: fence to release
266 *
267 * This is the default implementation for &dma_fence_ops.release. It calls
268 * kfree_rcu() on @fence.
269 */
f54d1867 270void dma_fence_free(struct dma_fence *fence)
e941759c 271{
3c3b177a 272 kfree_rcu(fence, rcu);
e941759c 273}
f54d1867 274EXPORT_SYMBOL(dma_fence_free);
e941759c 275
9c98f021
CW
276static bool __dma_fence_enable_signaling(struct dma_fence *fence)
277{
278 bool was_set;
279
280 lockdep_assert_held(fence->lock);
281
282 was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
283 &fence->flags);
284
285 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
286 return false;
287
288 if (!was_set && fence->ops->enable_signaling) {
289 trace_dma_fence_enable_signal(fence);
290
291 if (!fence->ops->enable_signaling(fence)) {
292 dma_fence_signal_locked(fence);
293 return false;
294 }
295 }
296
297 return true;
298}
299
e941759c 300/**
f54d1867 301 * dma_fence_enable_sw_signaling - enable signaling on fence
4dd3cdb2 302 * @fence: the fence to enable
e941759c 303 *
4dd3cdb2
DV
304 * This will request for sw signaling to be enabled, to make the fence
305 * complete as soon as possible. This calls &dma_fence_ops.enable_signaling
306 * internally.
e941759c 307 */
f54d1867 308void dma_fence_enable_sw_signaling(struct dma_fence *fence)
e941759c
ML
309{
310 unsigned long flags;
311
9c98f021
CW
312 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
313 return;
e941759c 314
9c98f021
CW
315 spin_lock_irqsave(fence->lock, flags);
316 __dma_fence_enable_signaling(fence);
317 spin_unlock_irqrestore(fence->lock, flags);
e941759c 318}
f54d1867 319EXPORT_SYMBOL(dma_fence_enable_sw_signaling);
e941759c
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320
321/**
f54d1867 322 * dma_fence_add_callback - add a callback to be called when the fence
e941759c 323 * is signaled
4dd3cdb2
DV
324 * @fence: the fence to wait on
325 * @cb: the callback to register
326 * @func: the function to call
e941759c 327 *
4dd3cdb2 328 * @cb will be initialized by dma_fence_add_callback(), no initialization
e941759c
ML
329 * by the caller is required. Any number of callbacks can be registered
330 * to a fence, but a callback can only be registered to one fence at a time.
331 *
332 * Note that the callback can be called from an atomic context. If
333 * fence is already signaled, this function will return -ENOENT (and
4dd3cdb2 334 * *not* call the callback).
e941759c
ML
335 *
336 * Add a software callback to the fence. Same restrictions apply to
4dd3cdb2
DV
337 * refcount as it does to dma_fence_wait(), however the caller doesn't need to
338 * keep a refcount to fence afterward dma_fence_add_callback() has returned:
339 * when software access is enabled, the creator of the fence is required to keep
340 * the fence alive until after it signals with dma_fence_signal(). The callback
341 * itself can be called from irq context.
e941759c 342 *
f642de16
GP
343 * Returns 0 in case of success, -ENOENT if the fence is already signaled
344 * and -EINVAL in case of error.
e941759c 345 */
f54d1867
CW
346int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb,
347 dma_fence_func_t func)
e941759c
ML
348{
349 unsigned long flags;
350 int ret = 0;
e941759c
ML
351
352 if (WARN_ON(!fence || !func))
353 return -EINVAL;
354
f54d1867 355 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
e941759c
ML
356 INIT_LIST_HEAD(&cb->node);
357 return -ENOENT;
358 }
359
360 spin_lock_irqsave(fence->lock, flags);
361
9c98f021 362 if (__dma_fence_enable_signaling(fence)) {
e941759c
ML
363 cb->func = func;
364 list_add_tail(&cb->node, &fence->cb_list);
9c98f021 365 } else {
e941759c 366 INIT_LIST_HEAD(&cb->node);
9c98f021
CW
367 ret = -ENOENT;
368 }
369
e941759c
ML
370 spin_unlock_irqrestore(fence->lock, flags);
371
372 return ret;
373}
f54d1867 374EXPORT_SYMBOL(dma_fence_add_callback);
e941759c 375
d6c99f4b
CW
376/**
377 * dma_fence_get_status - returns the status upon completion
4dd3cdb2 378 * @fence: the dma_fence to query
d6c99f4b
CW
379 *
380 * This wraps dma_fence_get_status_locked() to return the error status
381 * condition on a signaled fence. See dma_fence_get_status_locked() for more
382 * details.
383 *
384 * Returns 0 if the fence has not yet been signaled, 1 if the fence has
385 * been signaled without an error condition, or a negative error code
386 * if the fence has been completed in err.
387 */
388int dma_fence_get_status(struct dma_fence *fence)
389{
390 unsigned long flags;
391 int status;
392
393 spin_lock_irqsave(fence->lock, flags);
394 status = dma_fence_get_status_locked(fence);
395 spin_unlock_irqrestore(fence->lock, flags);
396
397 return status;
398}
399EXPORT_SYMBOL(dma_fence_get_status);
400
e941759c 401/**
f54d1867 402 * dma_fence_remove_callback - remove a callback from the signaling list
4dd3cdb2
DV
403 * @fence: the fence to wait on
404 * @cb: the callback to remove
e941759c
ML
405 *
406 * Remove a previously queued callback from the fence. This function returns
f353d71f 407 * true if the callback is successfully removed, or false if the fence has
e941759c
ML
408 * already been signaled.
409 *
410 * *WARNING*:
411 * Cancelling a callback should only be done if you really know what you're
412 * doing, since deadlocks and race conditions could occur all too easily. For
413 * this reason, it should only ever be done on hardware lockup recovery,
414 * with a reference held to the fence.
4dd3cdb2
DV
415 *
416 * Behaviour is undefined if @cb has not been added to @fence using
417 * dma_fence_add_callback() beforehand.
e941759c
ML
418 */
419bool
f54d1867 420dma_fence_remove_callback(struct dma_fence *fence, struct dma_fence_cb *cb)
e941759c
ML
421{
422 unsigned long flags;
423 bool ret;
424
425 spin_lock_irqsave(fence->lock, flags);
426
427 ret = !list_empty(&cb->node);
428 if (ret)
429 list_del_init(&cb->node);
430
431 spin_unlock_irqrestore(fence->lock, flags);
432
433 return ret;
434}
f54d1867 435EXPORT_SYMBOL(dma_fence_remove_callback);
e941759c
ML
436
437struct default_wait_cb {
f54d1867 438 struct dma_fence_cb base;
e941759c
ML
439 struct task_struct *task;
440};
441
442static void
f54d1867 443dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
e941759c
ML
444{
445 struct default_wait_cb *wait =
446 container_of(cb, struct default_wait_cb, base);
447
448 wake_up_state(wait->task, TASK_NORMAL);
449}
450
451/**
f54d1867 452 * dma_fence_default_wait - default sleep until the fence gets signaled
e941759c 453 * or until timeout elapses
4dd3cdb2
DV
454 * @fence: the fence to wait on
455 * @intr: if true, do an interruptible wait
456 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
e941759c
ML
457 *
458 * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or the
bcc004b6
AD
459 * remaining timeout in jiffies on success. If timeout is zero the value one is
460 * returned if the fence is already signaled for consistency with other
461 * functions taking a jiffies timeout.
e941759c
ML
462 */
463signed long
f54d1867 464dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
e941759c
ML
465{
466 struct default_wait_cb cb;
467 unsigned long flags;
bcc004b6 468 signed long ret = timeout ? timeout : 1;
e941759c 469
f54d1867 470 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
bcc004b6 471 return ret;
e941759c
ML
472
473 spin_lock_irqsave(fence->lock, flags);
474
475 if (intr && signal_pending(current)) {
476 ret = -ERESTARTSYS;
477 goto out;
478 }
479
9c98f021 480 if (!__dma_fence_enable_signaling(fence))
e941759c
ML
481 goto out;
482
03c0c5f6
AR
483 if (!timeout) {
484 ret = 0;
485 goto out;
486 }
487
f54d1867 488 cb.base.func = dma_fence_default_wait_cb;
e941759c
ML
489 cb.task = current;
490 list_add(&cb.base.node, &fence->cb_list);
491
f54d1867 492 while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) {
e941759c
ML
493 if (intr)
494 __set_current_state(TASK_INTERRUPTIBLE);
495 else
496 __set_current_state(TASK_UNINTERRUPTIBLE);
497 spin_unlock_irqrestore(fence->lock, flags);
498
499 ret = schedule_timeout(ret);
500
501 spin_lock_irqsave(fence->lock, flags);
502 if (ret > 0 && intr && signal_pending(current))
503 ret = -ERESTARTSYS;
504 }
505
506 if (!list_empty(&cb.base.node))
507 list_del(&cb.base.node);
508 __set_current_state(TASK_RUNNING);
509
510out:
511 spin_unlock_irqrestore(fence->lock, flags);
512 return ret;
513}
f54d1867 514EXPORT_SYMBOL(dma_fence_default_wait);
e941759c 515
a519435a 516static bool
7392b4bb 517dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count,
518 uint32_t *idx)
a519435a
CK
519{
520 int i;
521
522 for (i = 0; i < count; ++i) {
f54d1867 523 struct dma_fence *fence = fences[i];
7392b4bb 524 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
525 if (idx)
526 *idx = i;
a519435a 527 return true;
7392b4bb 528 }
a519435a
CK
529 }
530 return false;
531}
532
533/**
f54d1867 534 * dma_fence_wait_any_timeout - sleep until any fence gets signaled
a519435a 535 * or until timeout elapses
4dd3cdb2
DV
536 * @fences: array of fences to wait on
537 * @count: number of fences to wait on
538 * @intr: if true, do an interruptible wait
539 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
540 * @idx: used to store the first signaled fence index, meaningful only on
541 * positive return
a519435a
CK
542 *
543 * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if
544 * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies
545 * on success.
546 *
547 * Synchronous waits for the first fence in the array to be signaled. The
548 * caller needs to hold a reference to all fences in the array, otherwise a
549 * fence might be freed before return, resulting in undefined behavior.
4dd3cdb2
DV
550 *
551 * See also dma_fence_wait() and dma_fence_wait_timeout().
a519435a
CK
552 */
553signed long
f54d1867 554dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
7392b4bb 555 bool intr, signed long timeout, uint32_t *idx)
a519435a
CK
556{
557 struct default_wait_cb *cb;
558 signed long ret = timeout;
559 unsigned i;
560
561 if (WARN_ON(!fences || !count || timeout < 0))
562 return -EINVAL;
563
564 if (timeout == 0) {
565 for (i = 0; i < count; ++i)
7392b4bb 566 if (dma_fence_is_signaled(fences[i])) {
567 if (idx)
568 *idx = i;
a519435a 569 return 1;
7392b4bb 570 }
a519435a
CK
571
572 return 0;
573 }
574
575 cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL);
576 if (cb == NULL) {
577 ret = -ENOMEM;
578 goto err_free_cb;
579 }
580
581 for (i = 0; i < count; ++i) {
f54d1867 582 struct dma_fence *fence = fences[i];
a519435a 583
a519435a 584 cb[i].task = current;
f54d1867
CW
585 if (dma_fence_add_callback(fence, &cb[i].base,
586 dma_fence_default_wait_cb)) {
a519435a 587 /* This fence is already signaled */
7392b4bb 588 if (idx)
589 *idx = i;
a519435a
CK
590 goto fence_rm_cb;
591 }
592 }
593
594 while (ret > 0) {
595 if (intr)
596 set_current_state(TASK_INTERRUPTIBLE);
597 else
598 set_current_state(TASK_UNINTERRUPTIBLE);
599
7392b4bb 600 if (dma_fence_test_signaled_any(fences, count, idx))
a519435a
CK
601 break;
602
603 ret = schedule_timeout(ret);
604
605 if (ret > 0 && intr && signal_pending(current))
606 ret = -ERESTARTSYS;
607 }
608
609 __set_current_state(TASK_RUNNING);
610
611fence_rm_cb:
612 while (i-- > 0)
f54d1867 613 dma_fence_remove_callback(fences[i], &cb[i].base);
a519435a
CK
614
615err_free_cb:
616 kfree(cb);
617
618 return ret;
619}
f54d1867 620EXPORT_SYMBOL(dma_fence_wait_any_timeout);
a519435a 621
e941759c 622/**
f54d1867 623 * dma_fence_init - Initialize a custom fence.
4dd3cdb2
DV
624 * @fence: the fence to initialize
625 * @ops: the dma_fence_ops for operations on this fence
626 * @lock: the irqsafe spinlock to use for locking this fence
627 * @context: the execution context this fence is run on
628 * @seqno: a linear increasing sequence number for this context
e941759c
ML
629 *
630 * Initializes an allocated fence, the caller doesn't have to keep its
631 * refcount after committing with this fence, but it will need to hold a
4dd3cdb2 632 * refcount again if &dma_fence_ops.enable_signaling gets called.
e941759c
ML
633 *
634 * context and seqno are used for easy comparison between fences, allowing
4dd3cdb2 635 * to check which fence is later by simply using dma_fence_later().
e941759c
ML
636 */
637void
f54d1867 638dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops,
b312d8ca 639 spinlock_t *lock, u64 context, u64 seqno)
e941759c
ML
640{
641 BUG_ON(!lock);
418cc6ca 642 BUG_ON(!ops || !ops->get_driver_name || !ops->get_timeline_name);
e941759c
ML
643
644 kref_init(&fence->refcount);
645 fence->ops = ops;
646 INIT_LIST_HEAD(&fence->cb_list);
647 fence->lock = lock;
648 fence->context = context;
649 fence->seqno = seqno;
650 fence->flags = 0UL;
a009e975 651 fence->error = 0;
e941759c 652
f54d1867 653 trace_dma_fence_init(fence);
e941759c 654}
f54d1867 655EXPORT_SYMBOL(dma_fence_init);