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25dcb5dd PU |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com | |
4 | */ | |
5 | ||
6 | #ifndef K3_UDMA_H_ | |
7 | #define K3_UDMA_H_ | |
8 | ||
9 | #include <linux/soc/ti/ti_sci_protocol.h> | |
10 | ||
11 | /* Global registers */ | |
12 | #define UDMA_REV_REG 0x0 | |
13 | #define UDMA_PERF_CTL_REG 0x4 | |
14 | #define UDMA_EMU_CTL_REG 0x8 | |
15 | #define UDMA_PSIL_TO_REG 0x10 | |
16 | #define UDMA_UTC_CTL_REG 0x1c | |
17 | #define UDMA_CAP_REG(i) (0x20 + ((i) * 4)) | |
18 | #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 | |
19 | #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 | |
20 | ||
01779473 | 21 | /* BCHANRT/TCHANRT/RCHANRT registers */ |
bc7e5523 PU |
22 | #define UDMA_CHAN_RT_CTL_REG 0x0 |
23 | #define UDMA_CHAN_RT_SWTRIG_REG 0x8 | |
24 | #define UDMA_CHAN_RT_STDATA_REG 0x80 | |
25dcb5dd | 25 | |
bc7e5523 PU |
26 | #define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4)) |
27 | #define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \ | |
28 | UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */ | |
29 | #define UDMA_CHAN_RT_PEER_STATIC_TR_Z_REG \ | |
30 | UDMA_CHAN_RT_PEER_REG(1) /* PSI-L: 0x401 */ | |
31 | #define UDMA_CHAN_RT_PEER_BCNT_REG \ | |
32 | UDMA_CHAN_RT_PEER_REG(4) /* PSI-L: 0x404 */ | |
33 | #define UDMA_CHAN_RT_PEER_RT_EN_REG \ | |
34 | UDMA_CHAN_RT_PEER_REG(8) /* PSI-L: 0x408 */ | |
25dcb5dd | 35 | |
bc7e5523 PU |
36 | #define UDMA_CHAN_RT_PCNT_REG 0x400 |
37 | #define UDMA_CHAN_RT_BCNT_REG 0x408 | |
38 | #define UDMA_CHAN_RT_SBCNT_REG 0x410 | |
25dcb5dd | 39 | |
44385c41 PU |
40 | /* UDMA_CAP Registers */ |
41 | #define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff) | |
42 | #define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff) | |
43 | #define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) | |
44 | #define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff) | |
daf4ad04 PU |
45 | #define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff) |
46 | #define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff) | |
44385c41 | 47 | |
01779473 PU |
48 | #define BCDMA_CAP2_BCHAN_CNT(val) ((val) & 0x1ff) |
49 | #define BCDMA_CAP2_TCHAN_CNT(val) (((val) >> 9) & 0x1ff) | |
50 | #define BCDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) | |
88448980 PU |
51 | #define BCDMA_CAP3_HBCHAN_CNT(val) (((val) >> 14) & 0x1ff) |
52 | #define BCDMA_CAP3_UBCHAN_CNT(val) (((val) >> 23) & 0x1ff) | |
53 | #define BCDMA_CAP4_HRCHAN_CNT(val) ((val) & 0xff) | |
54 | #define BCDMA_CAP4_URCHAN_CNT(val) (((val) >> 8) & 0xff) | |
55 | #define BCDMA_CAP4_HTCHAN_CNT(val) (((val) >> 16) & 0xff) | |
56 | #define BCDMA_CAP4_UTCHAN_CNT(val) (((val) >> 24) & 0xff) | |
01779473 | 57 | |
d2abc982 PU |
58 | #define PKTDMA_CAP4_TFLOW_CNT(val) ((val) & 0x3fff) |
59 | ||
bc7e5523 | 60 | /* UDMA_CHAN_RT_CTL_REG */ |
25dcb5dd PU |
61 | #define UDMA_CHAN_RT_CTL_EN BIT(31) |
62 | #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) | |
63 | #define UDMA_CHAN_RT_CTL_PAUSE BIT(29) | |
64 | #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28) | |
65 | #define UDMA_CHAN_RT_CTL_ERROR BIT(0) | |
66 | ||
bc7e5523 | 67 | /* UDMA_CHAN_RT_PEER_RT_EN_REG */ |
25dcb5dd PU |
68 | #define UDMA_PEER_RT_EN_ENABLE BIT(31) |
69 | #define UDMA_PEER_RT_EN_TEARDOWN BIT(30) | |
70 | #define UDMA_PEER_RT_EN_PAUSE BIT(29) | |
71 | #define UDMA_PEER_RT_EN_FLUSH BIT(28) | |
72 | #define UDMA_PEER_RT_EN_IDLE BIT(1) | |
73 | ||
74 | /* | |
75 | * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG / | |
76 | * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG | |
77 | */ | |
78 | #define PDMA_STATIC_TR_X_MASK GENMASK(26, 24) | |
79 | #define PDMA_STATIC_TR_X_SHIFT (24) | |
80 | #define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0) | |
81 | #define PDMA_STATIC_TR_Y_SHIFT (0) | |
82 | ||
83 | #define PDMA_STATIC_TR_Y(x) \ | |
84 | (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK) | |
85 | #define PDMA_STATIC_TR_X(x) \ | |
86 | (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK) | |
87 | ||
88 | #define PDMA_STATIC_TR_XY_ACC32 BIT(30) | |
89 | #define PDMA_STATIC_TR_XY_BURST BIT(31) | |
90 | ||
91 | /* | |
92 | * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG / | |
93 | * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG | |
94 | */ | |
95 | #define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask)) | |
96 | ||
01779473 PU |
97 | /* Address Space Select */ |
98 | #define K3_ADDRESS_ASEL_SHIFT 48 | |
99 | ||
25dcb5dd PU |
100 | struct udma_dev; |
101 | struct udma_tchan; | |
102 | struct udma_rchan; | |
103 | struct udma_rflow; | |
104 | ||
105 | enum udma_rm_range { | |
01779473 PU |
106 | RM_RANGE_BCHAN = 0, |
107 | RM_RANGE_TCHAN, | |
25dcb5dd PU |
108 | RM_RANGE_RCHAN, |
109 | RM_RANGE_RFLOW, | |
d2abc982 | 110 | RM_RANGE_TFLOW, |
25dcb5dd PU |
111 | RM_RANGE_LAST, |
112 | }; | |
113 | ||
114 | struct udma_tisci_rm { | |
115 | const struct ti_sci_handle *tisci; | |
116 | const struct ti_sci_rm_udmap_ops *tisci_udmap_ops; | |
117 | u32 tisci_dev_id; | |
118 | ||
119 | /* tisci information for PSI-L thread pairing/unpairing */ | |
120 | const struct ti_sci_rm_psil_ops *tisci_psil_ops; | |
121 | u32 tisci_navss_dev_id; | |
122 | ||
123 | struct ti_sci_resource *rm_ranges[RM_RANGE_LAST]; | |
124 | }; | |
125 | ||
d7024191 GS |
126 | /* Direct access to UDMA low lever resources for the glue layer */ |
127 | int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); | |
128 | int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, | |
129 | u32 dst_thread); | |
130 | ||
131 | struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property); | |
426506a7 | 132 | struct device *xudma_get_device(struct udma_dev *ud); |
aa8a4c4e | 133 | struct k3_ringacc *xudma_get_ringacc(struct udma_dev *ud); |
d7024191 GS |
134 | void xudma_dev_put(struct udma_dev *ud); |
135 | u32 xudma_dev_get_psil_base(struct udma_dev *ud); | |
136 | struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud); | |
137 | ||
138 | int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt); | |
139 | int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt); | |
140 | ||
141 | struct udma_tchan *xudma_tchan_get(struct udma_dev *ud, int id); | |
142 | struct udma_rchan *xudma_rchan_get(struct udma_dev *ud, int id); | |
143 | struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id); | |
144 | ||
145 | void xudma_tchan_put(struct udma_dev *ud, struct udma_tchan *p); | |
146 | void xudma_rchan_put(struct udma_dev *ud, struct udma_rchan *p); | |
147 | void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p); | |
148 | ||
149 | int xudma_tchan_get_id(struct udma_tchan *p); | |
150 | int xudma_rchan_get_id(struct udma_rchan *p); | |
151 | int xudma_rflow_get_id(struct udma_rflow *p); | |
152 | ||
153 | u32 xudma_tchanrt_read(struct udma_tchan *tchan, int reg); | |
154 | void xudma_tchanrt_write(struct udma_tchan *tchan, int reg, u32 val); | |
155 | u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg); | |
156 | void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val); | |
157 | bool xudma_rflow_is_gp(struct udma_dev *ud, int id); | |
d2abc982 | 158 | int xudma_get_rflow_ring_offset(struct udma_dev *ud); |
d7024191 | 159 | |
5b65781d VR |
160 | int xudma_is_pktdma(struct udma_dev *ud); |
161 | ||
162 | int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id); | |
163 | int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id); | |
25dcb5dd | 164 | #endif /* K3_UDMA_H_ */ |