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dmaengine: tegra210-dma: free dma controller in remove()
[linux-2.6-block.git] / drivers / dma / tegra210-adma.c
CommitLineData
f46b1957
JH		 1/*
2 * ADMA driver for Nvidia's Tegra210 ADMA controller.
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/iopoll.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/of_dma.h>
24#include <linux/of_irq.h>
f46b1957
JH		 25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27
28#include "virt-dma.h"
29
30#define ADMA_CH_CMD 0x00
31#define ADMA_CH_STATUS 0x0c
32#define ADMA_CH_STATUS_XFER_EN BIT(0)
94dc8f4e 33#define ADMA_CH_STATUS_XFER_PAUSED BIT(1)
f46b1957
JH		 34
35#define ADMA_CH_INT_STATUS 0x10
36#define ADMA_CH_INT_STATUS_XFER_DONE BIT(0)
37
38#define ADMA_CH_INT_CLEAR 0x1c
39#define ADMA_CH_CTRL 0x24
f46b1957
JH		 40#define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
41#define ADMA_CH_CTRL_DIR_AHUB2MEM 2
42#define ADMA_CH_CTRL_DIR_MEM2AHUB 4
43#define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
44#define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
94dc8f4e 45#define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
f46b1957
JH		 46
47#define ADMA_CH_CONFIG 0x28
48#define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28)
49#define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24)
433de642
SP		 50#define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
51#define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
f46b1957
JH		 52#define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
53#define ADMA_CH_CONFIG_MAX_BUFS 8
54
55#define ADMA_CH_FIFO_CTRL 0x2c
56#define ADMA_CH_FIFO_CTRL_OVRFW_THRES(val) (((val) & 0xf) << 24)
57#define ADMA_CH_FIFO_CTRL_STARV_THRES(val) (((val) & 0xf) << 16)
ded1f3db
SP		 58#define ADMA_CH_FIFO_CTRL_TX_FIFO_SIZE_SHIFT 8
59#define ADMA_CH_FIFO_CTRL_RX_FIFO_SIZE_SHIFT 0
f46b1957
JH		 60
61#define ADMA_CH_LOWER_SRC_ADDR 0x34
62#define ADMA_CH_LOWER_TRG_ADDR 0x3c
63#define ADMA_CH_TC 0x44
64#define ADMA_CH_TC_COUNT_MASK 0x3ffffffc
65
66#define ADMA_CH_XFER_STATUS 0x54
67#define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff
68
ded1f3db
SP		 69#define ADMA_GLOBAL_CMD 0x00
70#define ADMA_GLOBAL_SOFT_RESET 0x04
f46b1957 71
94dc8f4e
SP		 72#define TEGRA_ADMA_BURST_COMPLETE_TIME 20
73
f46b1957 74#define ADMA_CH_FIFO_CTRL_DEFAULT (ADMA_CH_FIFO_CTRL_OVRFW_THRES(1) | \
ded1f3db
SP		 75 ADMA_CH_FIFO_CTRL_STARV_THRES(1))
76
77#define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
78
f46b1957
JH		 79struct tegra_adma;
80
81/*
82 * struct tegra_adma_chip_data - Tegra chip specific data
ded1f3db
SP		 83 * @global_reg_offset: Register offset of DMA global register.
84 * @global_int_clear: Register offset of DMA global interrupt clear.
85 * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
86 * @ch_req_rx_shift: Register offset for AHUB receive channel select.
87 * @ch_base_offset: Reister offset of DMA channel registers.
88 * @ch_req_mask: Mask for Tx or Rx channel select.
89 * @ch_req_max: Maximum number of Tx or Rx channels available.
90 * @ch_reg_size: Size of DMA channel register space.
f46b1957
JH		 91 * @nr_channels: Number of DMA channels available.
92 */
93struct tegra_adma_chip_data {
433de642 94 unsigned int (*adma_get_burst_config)(unsigned int burst_size);
ded1f3db
SP		 95 unsigned int global_reg_offset;
96 unsigned int global_int_clear;
97 unsigned int ch_req_tx_shift;
98 unsigned int ch_req_rx_shift;
99 unsigned int ch_base_offset;
100 unsigned int ch_req_mask;
101 unsigned int ch_req_max;
102 unsigned int ch_reg_size;
103 unsigned int nr_channels;
f46b1957
JH		 104};
105
106/*
107 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
108 */
109struct tegra_adma_chan_regs {
110 unsigned int ctrl;
111 unsigned int config;
112 unsigned int src_addr;
113 unsigned int trg_addr;
114 unsigned int fifo_ctrl;
115 unsigned int tc;
116};
117
118/*
119 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
120 */
121struct tegra_adma_desc {
122 struct virt_dma_desc vd;
123 struct tegra_adma_chan_regs ch_regs;
124 size_t buf_len;
125 size_t period_len;
126 size_t num_periods;
127};
128
129/*
130 * struct tegra_adma_chan - Tegra ADMA channel information
131 */
132struct tegra_adma_chan {
133 struct virt_dma_chan vc;
134 struct tegra_adma_desc *desc;
135 struct tegra_adma *tdma;
136 int irq;
137 void __iomem *chan_addr;
138
139 /* Slave channel configuration info */
140 struct dma_slave_config sconfig;
141 enum dma_transfer_direction sreq_dir;
142 unsigned int sreq_index;
143 bool sreq_reserved;
144
145 /* Transfer count and position info */
146 unsigned int tx_buf_count;
147 unsigned int tx_buf_pos;
148};
149
150/*
151 * struct tegra_adma - Tegra ADMA controller information
152 */
153struct tegra_adma {
154 struct dma_device dma_dev;
155 struct device *dev;
156 void __iomem *base_addr;
f6ed6491 157 struct clk *ahub_clk;
f46b1957
JH		 158 unsigned int nr_channels;
159 unsigned long rx_requests_reserved;
160 unsigned long tx_requests_reserved;
161
162 /* Used to store global command register state when suspending */
163 unsigned int global_cmd;
164
ded1f3db
SP		 165 const struct tegra_adma_chip_data *cdata;
166
f46b1957
JH		 167 /* Last member of the structure */
168 struct tegra_adma_chan channels[0];
169};
170
171static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
172{
ded1f3db 173 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
f46b1957
JH		 174}
175
176static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
177{
ded1f3db 178 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
f46b1957
JH		 179}
180
181static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
182{
183 writel(val, tdc->chan_addr + reg);
184}
185
186static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
187{
188 return readl(tdc->chan_addr + reg);
189}
190
191static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
192{
193 return container_of(dc, struct tegra_adma_chan, vc.chan);
194}
195
196static inline struct tegra_adma_desc *to_tegra_adma_desc(
197 struct dma_async_tx_descriptor *td)
198{
199 return container_of(td, struct tegra_adma_desc, vd.tx);
200}
201
202static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
203{
204 return tdc->tdma->dev;
205}
206
207static void tegra_adma_desc_free(struct virt_dma_desc *vd)
208{
209 kfree(container_of(vd, struct tegra_adma_desc, vd));
210}
211
212static int tegra_adma_slave_config(struct dma_chan *dc,
213 struct dma_slave_config *sconfig)
214{
215 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
216
217 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
218
219 return 0;
220}
221
222static int tegra_adma_init(struct tegra_adma *tdma)
223{
224 u32 status;
225 int ret;
226
227 /* Clear any interrupts */
ded1f3db 228 tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
f46b1957
JH		 229
230 /* Assert soft reset */
231 tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
232
233 /* Wait for reset to clear */
234 ret = readx_poll_timeout(readl,
ded1f3db
SP		 235 tdma->base_addr +
236 tdma->cdata->global_reg_offset +
237 ADMA_GLOBAL_SOFT_RESET,
f46b1957
JH		 238 status, status == 0, 20, 10000);
239 if (ret)
240 return ret;
241
242 /* Enable global ADMA registers */
243 tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
244
245 return 0;
246}
247
248static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
249 enum dma_transfer_direction direction)
250{
251 struct tegra_adma *tdma = tdc->tdma;
252 unsigned int sreq_index = tdc->sreq_index;
253
254 if (tdc->sreq_reserved)
255 return tdc->sreq_dir == direction ? 0 : -EINVAL;
256
ded1f3db
SP		 257 if (sreq_index > tdma->cdata->ch_req_max) {
258 dev_err(tdma->dev, "invalid DMA request\n");
259 return -EINVAL;
260 }
261
f46b1957
JH		 262 switch (direction) {
263 case DMA_MEM_TO_DEV:
f46b1957
JH		 264 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
265 dev_err(tdma->dev, "DMA request reserved\n");
266 return -EINVAL;
267 }
268 break;
269
270 case DMA_DEV_TO_MEM:
f46b1957
JH		 271 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
272 dev_err(tdma->dev, "DMA request reserved\n");
273 return -EINVAL;
274 }
275 break;
276
277 default:
278 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
279 dma_chan_name(&tdc->vc.chan));
280 return -EINVAL;
281 }
282
283 tdc->sreq_dir = direction;
284 tdc->sreq_reserved = true;
285
286 return 0;
287}
288
289static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
290{
291 struct tegra_adma *tdma = tdc->tdma;
292
293 if (!tdc->sreq_reserved)
294 return;
295
296 switch (tdc->sreq_dir) {
297 case DMA_MEM_TO_DEV:
298 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
299 break;
300
301 case DMA_DEV_TO_MEM:
302 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
303 break;
304
305 default:
306 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
307 dma_chan_name(&tdc->vc.chan));
308 return;
309 }
310
311 tdc->sreq_reserved = false;
312}
313
314static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
315{
316 u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
317
318 return status & ADMA_CH_INT_STATUS_XFER_DONE;
319}
320
321static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
322{
323 u32 status = tegra_adma_irq_status(tdc);
324
325 if (status)
326 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
327
328 return status;
329}
330
331static void tegra_adma_stop(struct tegra_adma_chan *tdc)
332{
333 unsigned int status;
334
335 /* Disable ADMA */
336 tdma_ch_write(tdc, ADMA_CH_CMD, 0);
337
338 /* Clear interrupt status */
339 tegra_adma_irq_clear(tdc);
340
341 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
342 status, !(status & ADMA_CH_STATUS_XFER_EN),
343 20, 10000)) {
344 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
345 return;
346 }
347
348 kfree(tdc->desc);
349 tdc->desc = NULL;
350}
351
352static void tegra_adma_start(struct tegra_adma_chan *tdc)
353{
354 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
355 struct tegra_adma_chan_regs *ch_regs;
356 struct tegra_adma_desc *desc;
357
358 if (!vd)
359 return;
360
361 list_del(&vd->node);
362
363 desc = to_tegra_adma_desc(&vd->tx);
364
365 if (!desc) {
366 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
367 return;
368 }
369
370 ch_regs = &desc->ch_regs;
371
372 tdc->tx_buf_pos = 0;
373 tdc->tx_buf_count = 0;
374 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
375 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
376 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
377 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
378 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
379 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
380
381 /* Start ADMA */
382 tdma_ch_write(tdc, ADMA_CH_CMD, 1);
383
384 tdc->desc = desc;
385}
386
387static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
388{
389 struct tegra_adma_desc *desc = tdc->desc;
390 unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
391 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
392 unsigned int periods_remaining;
393
394 /*
395 * Handle wrap around of buffer count register
396 */
397 if (pos < tdc->tx_buf_pos)
398 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
399 else
400 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
401
402 periods_remaining = tdc->tx_buf_count % desc->num_periods;
403 tdc->tx_buf_pos = pos;
404
405 return desc->buf_len - (periods_remaining * desc->period_len);
406}
407
408static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
409{
410 struct tegra_adma_chan *tdc = dev_id;
411 unsigned long status;
412 unsigned long flags;
413
414 spin_lock_irqsave(&tdc->vc.lock, flags);
415
416 status = tegra_adma_irq_clear(tdc);
417 if (status == 0 || !tdc->desc) {
418 spin_unlock_irqrestore(&tdc->vc.lock, flags);
419 return IRQ_NONE;
420 }
421
422 vchan_cyclic_callback(&tdc->desc->vd);
423
424 spin_unlock_irqrestore(&tdc->vc.lock, flags);
425
426 return IRQ_HANDLED;
427}
428
429static void tegra_adma_issue_pending(struct dma_chan *dc)
430{
431 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
432 unsigned long flags;
433
434 spin_lock_irqsave(&tdc->vc.lock, flags);
435
436 if (vchan_issue_pending(&tdc->vc)) {
437 if (!tdc->desc)
438 tegra_adma_start(tdc);
439 }
440
441 spin_unlock_irqrestore(&tdc->vc.lock, flags);
442}
443
94dc8f4e
SP		 444static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
445{
446 u32 csts;
447
448 csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
449 csts &= ADMA_CH_STATUS_XFER_PAUSED;
450
451 return csts ? true : false;
452}
453
454static int tegra_adma_pause(struct dma_chan *dc)
455{
456 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
457 struct tegra_adma_desc *desc = tdc->desc;
458 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
459 int dcnt = 10;
460
461 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
462 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
463 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
464
465 while (dcnt-- && !tegra_adma_is_paused(tdc))
466 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
467
468 if (dcnt < 0) {
469 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
470 return -EBUSY;
471 }
472
473 return 0;
474}
475
476static int tegra_adma_resume(struct dma_chan *dc)
477{
478 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
479 struct tegra_adma_desc *desc = tdc->desc;
480 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
481
482 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
483 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
484 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
485
486 return 0;
487}
488
f46b1957
JH		 489static int tegra_adma_terminate_all(struct dma_chan *dc)
490{
491 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
492 unsigned long flags;
493 LIST_HEAD(head);
494
495 spin_lock_irqsave(&tdc->vc.lock, flags);
496
497 if (tdc->desc)
498 tegra_adma_stop(tdc);
499
500 tegra_adma_request_free(tdc);
501 vchan_get_all_descriptors(&tdc->vc, &head);
502 spin_unlock_irqrestore(&tdc->vc.lock, flags);
503 vchan_dma_desc_free_list(&tdc->vc, &head);
504
505 return 0;
506}
507
508static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
509 dma_cookie_t cookie,
510 struct dma_tx_state *txstate)
511{
512 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
513 struct tegra_adma_desc *desc;
514 struct virt_dma_desc *vd;
515 enum dma_status ret;
516 unsigned long flags;
517 unsigned int residual;
518
519 ret = dma_cookie_status(dc, cookie, txstate);
520 if (ret == DMA_COMPLETE || !txstate)
521 return ret;
522
523 spin_lock_irqsave(&tdc->vc.lock, flags);
524
525 vd = vchan_find_desc(&tdc->vc, cookie);
526 if (vd) {
527 desc = to_tegra_adma_desc(&vd->tx);
528 residual = desc->ch_regs.tc;
529 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
530 residual = tegra_adma_get_residue(tdc);
531 } else {
532 residual = 0;
533 }
534
535 spin_unlock_irqrestore(&tdc->vc.lock, flags);
536
537 dma_set_residue(txstate, residual);
538
539 return ret;
540}
541
433de642
SP		 542static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
543{
544 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
545 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
546
547 return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
548}
549
550static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
551{
552 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
553 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
554
555 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
556}
557
f46b1957
JH		 558static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
559 struct tegra_adma_desc *desc,
560 dma_addr_t buf_addr,
561 enum dma_transfer_direction direction)
562{
563 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
ded1f3db 564 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
f46b1957
JH		 565 unsigned int burst_size, adma_dir;
566
567 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
568 return -EINVAL;
569
570 switch (direction) {
571 case DMA_MEM_TO_DEV:
572 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
433de642 573 burst_size = tdc->sconfig.dst_maxburst;
f46b1957 574 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
ded1f3db
SP		 575 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
576 cdata->ch_req_mask,
577 cdata->ch_req_tx_shift);
f46b1957
JH		 578 ch_regs->src_addr = buf_addr;
579 break;
580
581 case DMA_DEV_TO_MEM:
582 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
433de642 583 burst_size = tdc->sconfig.src_maxburst;
f46b1957 584 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
ded1f3db
SP		 585 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
586 cdata->ch_req_mask,
587 cdata->ch_req_rx_shift);
f46b1957
JH		 588 ch_regs->trg_addr = buf_addr;
589 break;
590
591 default:
592 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
593 return -EINVAL;
594 }
595
f46b1957
JH		 596 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
597 ADMA_CH_CTRL_MODE_CONTINUOUS |
598 ADMA_CH_CTRL_FLOWCTRL_EN;
433de642 599 ch_regs->config |= cdata->adma_get_burst_config(burst_size);
f46b1957
JH		 600 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
601 ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT;
602 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
603
604 return tegra_adma_request_alloc(tdc, direction);
605}
606
607static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
608 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
609 size_t period_len, enum dma_transfer_direction direction,
610 unsigned long flags)
611{
612 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
613 struct tegra_adma_desc *desc = NULL;
614
615 if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
616 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
617 return NULL;
618 }
619
620 if (buf_len % period_len) {
621 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
622 return NULL;
623 }
624
625 if (!IS_ALIGNED(buf_addr, 4)) {
626 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
627 return NULL;
628 }
629
630 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
631 if (!desc)
632 return NULL;
633
634 desc->buf_len = buf_len;
635 desc->period_len = period_len;
636 desc->num_periods = buf_len / period_len;
637
638 if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
639 kfree(desc);
640 return NULL;
641 }
642
643 return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
644}
645
646static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
647{
648 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
649 int ret;
650
651 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
652 if (ret) {
653 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
654 dma_chan_name(dc));
655 return ret;
656 }
657
658 ret = pm_runtime_get_sync(tdc2dev(tdc));
659 if (ret < 0) {
660 free_irq(tdc->irq, tdc);
661 return ret;
662 }
663
664 dma_cookie_init(&tdc->vc.chan);
665
666 return 0;
667}
668
669static void tegra_adma_free_chan_resources(struct dma_chan *dc)
670{
671 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
672
673 tegra_adma_terminate_all(dc);
674 vchan_free_chan_resources(&tdc->vc);
675 tasklet_kill(&tdc->vc.task);
676 free_irq(tdc->irq, tdc);
677 pm_runtime_put(tdc2dev(tdc));
678
679 tdc->sreq_index = 0;
680 tdc->sreq_dir = DMA_TRANS_NONE;
681}
682
683static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
684 struct of_dma *ofdma)
685{
686 struct tegra_adma *tdma = ofdma->of_dma_data;
687 struct tegra_adma_chan *tdc;
688 struct dma_chan *chan;
689 unsigned int sreq_index;
690
691 if (dma_spec->args_count != 1)
692 return NULL;
693
694 sreq_index = dma_spec->args[0];
695
696 if (sreq_index == 0) {
697 dev_err(tdma->dev, "DMA request must not be 0\n");
698 return NULL;
699 }
700
701 chan = dma_get_any_slave_channel(&tdma->dma_dev);
702 if (!chan)
703 return NULL;
704
705 tdc = to_tegra_adma_chan(chan);
706 tdc->sreq_index = sreq_index;
707
708 return chan;
709}
710
711static int tegra_adma_runtime_suspend(struct device *dev)
712{
713 struct tegra_adma *tdma = dev_get_drvdata(dev);
714
715 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
f6ed6491 716 clk_disable_unprepare(tdma->ahub_clk);
f46b1957 717
f6ed6491 718 return 0;
f46b1957
JH		 719}
720
721static int tegra_adma_runtime_resume(struct device *dev)
722{
723 struct tegra_adma *tdma = dev_get_drvdata(dev);
724 int ret;
725
f6ed6491
SP		 726 ret = clk_prepare_enable(tdma->ahub_clk);
727 if (ret) {
728 dev_err(dev, "ahub clk_enable failed: %d\n", ret);
f46b1957 729 return ret;
f6ed6491 730 }
f46b1957
JH		 731 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
732
733 return 0;
734}
735
736static const struct tegra_adma_chip_data tegra210_chip_data = {
433de642 737 .adma_get_burst_config = tegra210_adma_get_burst_config,
ded1f3db
SP		 738 .global_reg_offset = 0xc00,
739 .global_int_clear = 0x20,
740 .ch_req_tx_shift = 28,
741 .ch_req_rx_shift = 24,
742 .ch_base_offset = 0,
743 .ch_req_mask = 0xf,
744 .ch_req_max = 10,
745 .ch_reg_size = 0x80,
746 .nr_channels = 22,
f46b1957
JH		 747};
748
433de642
SP		 749static const struct tegra_adma_chip_data tegra186_chip_data = {
750 .adma_get_burst_config = tegra186_adma_get_burst_config,
751 .global_reg_offset = 0,
752 .global_int_clear = 0x402c,
753 .ch_req_tx_shift = 27,
754 .ch_req_rx_shift = 22,
755 .ch_base_offset = 0x10000,
756 .ch_req_mask = 0x1f,
757 .ch_req_max = 20,
758 .ch_reg_size = 0x100,
759 .nr_channels = 32,
760};
761
f46b1957
JH		 762static const struct of_device_id tegra_adma_of_match[] = {
763 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
433de642 764 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
f46b1957
JH		 765 { },
766};
767MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
768
769static int tegra_adma_probe(struct platform_device *pdev)
770{
771 const struct tegra_adma_chip_data *cdata;
772 struct tegra_adma *tdma;
773 struct resource *res;
f46b1957
JH		 774 int ret, i;
775
776 cdata = of_device_get_match_data(&pdev->dev);
777 if (!cdata) {
778 dev_err(&pdev->dev, "device match data not found\n");
779 return -ENODEV;
780 }
781
863326a6
GS		 782 tdma = devm_kzalloc(&pdev->dev,
783 struct_size(tdma, channels, cdata->nr_channels),
784 GFP_KERNEL);
f46b1957
JH		 785 if (!tdma)
786 return -ENOMEM;
787
788 tdma->dev = &pdev->dev;
ded1f3db 789 tdma->cdata = cdata;
f46b1957
JH		 790 tdma->nr_channels = cdata->nr_channels;
791 platform_set_drvdata(pdev, tdma);
792
793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
794 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
795 if (IS_ERR(tdma->base_addr))
796 return PTR_ERR(tdma->base_addr);
797
f6ed6491
SP		 798 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
799 if (IS_ERR(tdma->ahub_clk)) {
800 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
801 return PTR_ERR(tdma->ahub_clk);
802 }
f46b1957
JH		 803
804 pm_runtime_enable(&pdev->dev);
805
806 ret = pm_runtime_get_sync(&pdev->dev);
807 if (ret < 0)
808 goto rpm_disable;
809
810 ret = tegra_adma_init(tdma);
811 if (ret)
812 goto rpm_put;
813
814 INIT_LIST_HEAD(&tdma->dma_dev.channels);
815 for (i = 0; i < tdma->nr_channels; i++) {
816 struct tegra_adma_chan *tdc = &tdma->channels[i];
817
ded1f3db
SP		 818 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
819 + (cdata->ch_reg_size * i);
f46b1957
JH		 820
821 tdc->irq = of_irq_get(pdev->dev.of_node, i);
7f577067
SS		 822 if (tdc->irq <= 0) {
823 ret = tdc->irq ?: -ENXIO;
f46b1957
JH		 824 goto irq_dispose;
825 }
826
827 vchan_init(&tdc->vc, &tdma->dma_dev);
828 tdc->vc.desc_free = tegra_adma_desc_free;
829 tdc->tdma = tdma;
830 }
831
832 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
833 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
834 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
835
836 tdma->dma_dev.dev = &pdev->dev;
837 tdma->dma_dev.device_alloc_chan_resources =
838 tegra_adma_alloc_chan_resources;
839 tdma->dma_dev.device_free_chan_resources =
840 tegra_adma_free_chan_resources;
841 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
842 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
843 tdma->dma_dev.device_config = tegra_adma_slave_config;
844 tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
845 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
846 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
847 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
848 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
849 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
94dc8f4e
SP		 850 tdma->dma_dev.device_pause = tegra_adma_pause;
851 tdma->dma_dev.device_resume = tegra_adma_resume;
f46b1957
JH		 852
853 ret = dma_async_device_register(&tdma->dma_dev);
854 if (ret < 0) {
855 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
856 goto irq_dispose;
857 }
858
859 ret = of_dma_controller_register(pdev->dev.of_node,
860 tegra_dma_of_xlate, tdma);
861 if (ret < 0) {
862 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
863 goto dma_remove;
864 }
865
866 pm_runtime_put(&pdev->dev);
867
868 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
869 tdma->nr_channels);
870
871 return 0;
872
873dma_remove:
874 dma_async_device_unregister(&tdma->dma_dev);
875irq_dispose:
876 while (--i >= 0)
877 irq_dispose_mapping(tdma->channels[i].irq);
878rpm_put:
879 pm_runtime_put_sync(&pdev->dev);
880rpm_disable:
881 pm_runtime_disable(&pdev->dev);
f46b1957
JH		 882
883 return ret;
884}
885
886static int tegra_adma_remove(struct platform_device *pdev)
887{
888 struct tegra_adma *tdma = platform_get_drvdata(pdev);
889 int i;
890
f030e419 891 of_dma_controller_free(pdev->dev.of_node);
f46b1957
JH		 892 dma_async_device_unregister(&tdma->dma_dev);
893
894 for (i = 0; i < tdma->nr_channels; ++i)
895 irq_dispose_mapping(tdma->channels[i].irq);
896
897 pm_runtime_put_sync(&pdev->dev);
898 pm_runtime_disable(&pdev->dev);
f46b1957
JH		 899
900 return 0;
901}
902
f46b1957
JH		 903static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
904 SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
905 tegra_adma_runtime_resume, NULL)
74fca241
SP		 906 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
907 pm_runtime_force_resume)
f46b1957
JH		 908};
909
910static struct platform_driver tegra_admac_driver = {
911 .driver = {
912 .name = "tegra-adma",
913 .pm = &tegra_adma_dev_pm_ops,
914 .of_match_table = tegra_adma_of_match,
915 },
916 .probe = tegra_adma_probe,
917 .remove = tegra_adma_remove,
918};
919
920module_platform_driver(tegra_admac_driver);
921
922MODULE_ALIAS("platform:tegra210-adma");
923MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
924MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
925MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
926MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)