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Merge tag 'pci-v6.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-2.6-block.git] / drivers / dma / tegra210-adma.c
CommitLineData
9952f691 1// SPDX-License-Identifier: GPL-2.0-only
f46b1957
JH		 2/*
3 * ADMA driver for Nvidia's Tegra210 ADMA controller.
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
f46b1957
JH		 6 */
7
8#include <linux/clk.h>
9#include <linux/iopoll.h>
10#include <linux/module.h>
11#include <linux/of_device.h>
12#include <linux/of_dma.h>
13#include <linux/of_irq.h>
f46b1957
JH		 14#include <linux/pm_runtime.h>
15#include <linux/slab.h>
16
17#include "virt-dma.h"
18
19#define ADMA_CH_CMD 0x00
20#define ADMA_CH_STATUS 0x0c
21#define ADMA_CH_STATUS_XFER_EN BIT(0)
94dc8f4e 22#define ADMA_CH_STATUS_XFER_PAUSED BIT(1)
f46b1957
JH		 23
24#define ADMA_CH_INT_STATUS 0x10
25#define ADMA_CH_INT_STATUS_XFER_DONE BIT(0)
26
27#define ADMA_CH_INT_CLEAR 0x1c
28#define ADMA_CH_CTRL 0x24
f46b1957
JH		 29#define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
30#define ADMA_CH_CTRL_DIR_AHUB2MEM 2
31#define ADMA_CH_CTRL_DIR_MEM2AHUB 4
32#define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
33#define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
94dc8f4e 34#define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
f46b1957
JH		 35
36#define ADMA_CH_CONFIG 0x28
37#define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28)
38#define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24)
433de642
SP		 39#define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
40#define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
f46b1957
JH		 41#define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
42#define ADMA_CH_CONFIG_MAX_BUFS 8
9ec691f4 43#define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
f46b1957
JH		 44
45#define ADMA_CH_FIFO_CTRL 0x2c
32de4745
SP		 46#define ADMA_CH_TX_FIFO_SIZE_SHIFT 8
47#define ADMA_CH_RX_FIFO_SIZE_SHIFT 0
f46b1957
JH		 48
49#define ADMA_CH_LOWER_SRC_ADDR 0x34
50#define ADMA_CH_LOWER_TRG_ADDR 0x3c
51#define ADMA_CH_TC 0x44
52#define ADMA_CH_TC_COUNT_MASK 0x3ffffffc
53
54#define ADMA_CH_XFER_STATUS 0x54
55#define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff
56
ded1f3db
SP		 57#define ADMA_GLOBAL_CMD 0x00
58#define ADMA_GLOBAL_SOFT_RESET 0x04
f46b1957 59
94dc8f4e
SP		 60#define TEGRA_ADMA_BURST_COMPLETE_TIME 20
61
ded1f3db
SP		 62#define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
63
f46b1957
JH		 64struct tegra_adma;
65
66/*
67 * struct tegra_adma_chip_data - Tegra chip specific data
c7f9c67f 68 * @adma_get_burst_config: Function callback used to set DMA burst size.
ded1f3db
SP		 69 * @global_reg_offset: Register offset of DMA global register.
70 * @global_int_clear: Register offset of DMA global interrupt clear.
71 * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
72 * @ch_req_rx_shift: Register offset for AHUB receive channel select.
49225249 73 * @ch_base_offset: Register offset of DMA channel registers.
9ab59bf5 74 * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
ded1f3db
SP		 75 * @ch_req_mask: Mask for Tx or Rx channel select.
76 * @ch_req_max: Maximum number of Tx or Rx channels available.
77 * @ch_reg_size: Size of DMA channel register space.
f46b1957 78 * @nr_channels: Number of DMA channels available.
32de4745
SP		 79 * @ch_fifo_size_mask: Mask for FIFO size field.
80 * @sreq_index_offset: Slave channel index offset.
35696789 81 * @has_outstanding_reqs: If DMA channel can have outstanding requests.
f46b1957
JH		 82 */
83struct tegra_adma_chip_data {
433de642 84 unsigned int (*adma_get_burst_config)(unsigned int burst_size);
ded1f3db
SP		 85 unsigned int global_reg_offset;
86 unsigned int global_int_clear;
87 unsigned int ch_req_tx_shift;
88 unsigned int ch_req_rx_shift;
89 unsigned int ch_base_offset;
9ab59bf5 90 unsigned int ch_fifo_ctrl;
ded1f3db
SP		 91 unsigned int ch_req_mask;
92 unsigned int ch_req_max;
93 unsigned int ch_reg_size;
94 unsigned int nr_channels;
32de4745
SP		 95 unsigned int ch_fifo_size_mask;
96 unsigned int sreq_index_offset;
9ec691f4 97 bool has_outstanding_reqs;
f46b1957
JH		 98};
99
100/*
101 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
102 */
103struct tegra_adma_chan_regs {
104 unsigned int ctrl;
105 unsigned int config;
106 unsigned int src_addr;
107 unsigned int trg_addr;
108 unsigned int fifo_ctrl;
f33e7bb3 109 unsigned int cmd;
f46b1957
JH		 110 unsigned int tc;
111};
112
113/*
114 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
115 */
116struct tegra_adma_desc {
117 struct virt_dma_desc vd;
118 struct tegra_adma_chan_regs ch_regs;
119 size_t buf_len;
120 size_t period_len;
121 size_t num_periods;
122};
123
124/*
125 * struct tegra_adma_chan - Tegra ADMA channel information
126 */
127struct tegra_adma_chan {
128 struct virt_dma_chan vc;
129 struct tegra_adma_desc *desc;
130 struct tegra_adma *tdma;
131 int irq;
132 void __iomem *chan_addr;
133
134 /* Slave channel configuration info */
135 struct dma_slave_config sconfig;
136 enum dma_transfer_direction sreq_dir;
137 unsigned int sreq_index;
138 bool sreq_reserved;
f33e7bb3 139 struct tegra_adma_chan_regs ch_regs;
f46b1957
JH		 140
141 /* Transfer count and position info */
142 unsigned int tx_buf_count;
143 unsigned int tx_buf_pos;
144};
145
146/*
147 * struct tegra_adma - Tegra ADMA controller information
148 */
149struct tegra_adma {
150 struct dma_device dma_dev;
151 struct device *dev;
152 void __iomem *base_addr;
f6ed6491 153 struct clk *ahub_clk;
f46b1957
JH		 154 unsigned int nr_channels;
155 unsigned long rx_requests_reserved;
156 unsigned long tx_requests_reserved;
157
158 /* Used to store global command register state when suspending */
159 unsigned int global_cmd;
160
ded1f3db
SP		 161 const struct tegra_adma_chip_data *cdata;
162
f46b1957 163 /* Last member of the structure */
1ee44529 164 struct tegra_adma_chan channels[];
f46b1957
JH		 165};
166
167static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
168{
ded1f3db 169 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
f46b1957
JH		 170}
171
172static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
173{
ded1f3db 174 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
f46b1957
JH		 175}
176
177static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
178{
179 writel(val, tdc->chan_addr + reg);
180}
181
182static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
183{
184 return readl(tdc->chan_addr + reg);
185}
186
187static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
188{
189 return container_of(dc, struct tegra_adma_chan, vc.chan);
190}
191
192static inline struct tegra_adma_desc *to_tegra_adma_desc(
193 struct dma_async_tx_descriptor *td)
194{
195 return container_of(td, struct tegra_adma_desc, vd.tx);
196}
197
198static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
199{
200 return tdc->tdma->dev;
201}
202
203static void tegra_adma_desc_free(struct virt_dma_desc *vd)
204{
205 kfree(container_of(vd, struct tegra_adma_desc, vd));
206}
207
208static int tegra_adma_slave_config(struct dma_chan *dc,
209 struct dma_slave_config *sconfig)
210{
211 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
212
213 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
214
215 return 0;
216}
217
218static int tegra_adma_init(struct tegra_adma *tdma)
219{
220 u32 status;
221 int ret;
222
223 /* Clear any interrupts */
9c7e355c 224 tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1);
f46b1957
JH		 225
226 /* Assert soft reset */
227 tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
228
229 /* Wait for reset to clear */
230 ret = readx_poll_timeout(readl,
ded1f3db
SP		 231 tdma->base_addr +
232 tdma->cdata->global_reg_offset +
233 ADMA_GLOBAL_SOFT_RESET,
f46b1957
JH		 234 status, status == 0, 20, 10000);
235 if (ret)
236 return ret;
237
238 /* Enable global ADMA registers */
239 tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
240
241 return 0;
242}
243
244static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
245 enum dma_transfer_direction direction)
246{
247 struct tegra_adma *tdma = tdc->tdma;
248 unsigned int sreq_index = tdc->sreq_index;
249
250 if (tdc->sreq_reserved)
251 return tdc->sreq_dir == direction ? 0 : -EINVAL;
252
ded1f3db
SP		 253 if (sreq_index > tdma->cdata->ch_req_max) {
254 dev_err(tdma->dev, "invalid DMA request\n");
255 return -EINVAL;
256 }
257
f46b1957
JH		 258 switch (direction) {
259 case DMA_MEM_TO_DEV:
f46b1957
JH		 260 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
261 dev_err(tdma->dev, "DMA request reserved\n");
262 return -EINVAL;
263 }
264 break;
265
266 case DMA_DEV_TO_MEM:
f46b1957
JH		 267 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
268 dev_err(tdma->dev, "DMA request reserved\n");
269 return -EINVAL;
270 }
271 break;
272
273 default:
274 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
275 dma_chan_name(&tdc->vc.chan));
276 return -EINVAL;
277 }
278
279 tdc->sreq_dir = direction;
280 tdc->sreq_reserved = true;
281
282 return 0;
283}
284
285static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
286{
287 struct tegra_adma *tdma = tdc->tdma;
288
289 if (!tdc->sreq_reserved)
290 return;
291
292 switch (tdc->sreq_dir) {
293 case DMA_MEM_TO_DEV:
294 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
295 break;
296
297 case DMA_DEV_TO_MEM:
298 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
299 break;
300
301 default:
302 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
303 dma_chan_name(&tdc->vc.chan));
304 return;
305 }
306
307 tdc->sreq_reserved = false;
308}
309
310static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
311{
312 u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
313
314 return status & ADMA_CH_INT_STATUS_XFER_DONE;
315}
316
317static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
318{
319 u32 status = tegra_adma_irq_status(tdc);
320
321 if (status)
322 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
323
324 return status;
325}
326
327static void tegra_adma_stop(struct tegra_adma_chan *tdc)
328{
329 unsigned int status;
330
331 /* Disable ADMA */
332 tdma_ch_write(tdc, ADMA_CH_CMD, 0);
333
334 /* Clear interrupt status */
335 tegra_adma_irq_clear(tdc);
336
337 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
338 status, !(status & ADMA_CH_STATUS_XFER_EN),
339 20, 10000)) {
340 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
341 return;
342 }
343
344 kfree(tdc->desc);
345 tdc->desc = NULL;
346}
347
348static void tegra_adma_start(struct tegra_adma_chan *tdc)
349{
350 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
351 struct tegra_adma_chan_regs *ch_regs;
352 struct tegra_adma_desc *desc;
353
354 if (!vd)
355 return;
356
357 list_del(&vd->node);
358
359 desc = to_tegra_adma_desc(&vd->tx);
360
361 if (!desc) {
362 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
363 return;
364 }
365
366 ch_regs = &desc->ch_regs;
367
368 tdc->tx_buf_pos = 0;
369 tdc->tx_buf_count = 0;
370 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
371 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
372 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
373 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
374 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
375 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
376
377 /* Start ADMA */
378 tdma_ch_write(tdc, ADMA_CH_CMD, 1);
379
380 tdc->desc = desc;
381}
382
383static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
384{
385 struct tegra_adma_desc *desc = tdc->desc;
386 unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
387 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
388 unsigned int periods_remaining;
389
390 /*
391 * Handle wrap around of buffer count register
392 */
393 if (pos < tdc->tx_buf_pos)
394 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
395 else
396 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
397
398 periods_remaining = tdc->tx_buf_count % desc->num_periods;
399 tdc->tx_buf_pos = pos;
400
401 return desc->buf_len - (periods_remaining * desc->period_len);
402}
403
404static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
405{
406 struct tegra_adma_chan *tdc = dev_id;
407 unsigned long status;
f46b1957 408
654115e3 409 spin_lock(&tdc->vc.lock);
f46b1957
JH		 410
411 status = tegra_adma_irq_clear(tdc);
412 if (status == 0 || !tdc->desc) {
654115e3 413 spin_unlock(&tdc->vc.lock);
f46b1957
JH		 414 return IRQ_NONE;
415 }
416
417 vchan_cyclic_callback(&tdc->desc->vd);
418
654115e3 419 spin_unlock(&tdc->vc.lock);
f46b1957
JH		 420
421 return IRQ_HANDLED;
422}
423
424static void tegra_adma_issue_pending(struct dma_chan *dc)
425{
426 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
427 unsigned long flags;
428
429 spin_lock_irqsave(&tdc->vc.lock, flags);
430
431 if (vchan_issue_pending(&tdc->vc)) {
432 if (!tdc->desc)
433 tegra_adma_start(tdc);
434 }
435
436 spin_unlock_irqrestore(&tdc->vc.lock, flags);
437}
438
94dc8f4e
SP		 439static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
440{
441 u32 csts;
442
443 csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
444 csts &= ADMA_CH_STATUS_XFER_PAUSED;
445
446 return csts ? true : false;
447}
448
449static int tegra_adma_pause(struct dma_chan *dc)
450{
451 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
452 struct tegra_adma_desc *desc = tdc->desc;
453 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
454 int dcnt = 10;
455
456 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
457 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
458 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
459
460 while (dcnt-- && !tegra_adma_is_paused(tdc))
461 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
462
463 if (dcnt < 0) {
464 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
465 return -EBUSY;
466 }
467
468 return 0;
469}
470
471static int tegra_adma_resume(struct dma_chan *dc)
472{
473 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
474 struct tegra_adma_desc *desc = tdc->desc;
475 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
476
477 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
478 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
479 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
480
481 return 0;
482}
483
f46b1957
JH		 484static int tegra_adma_terminate_all(struct dma_chan *dc)
485{
486 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
487 unsigned long flags;
488 LIST_HEAD(head);
489
490 spin_lock_irqsave(&tdc->vc.lock, flags);
491
492 if (tdc->desc)
493 tegra_adma_stop(tdc);
494
495 tegra_adma_request_free(tdc);
496 vchan_get_all_descriptors(&tdc->vc, &head);
497 spin_unlock_irqrestore(&tdc->vc.lock, flags);
498 vchan_dma_desc_free_list(&tdc->vc, &head);
499
500 return 0;
501}
502
503static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
504 dma_cookie_t cookie,
505 struct dma_tx_state *txstate)
506{
507 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
508 struct tegra_adma_desc *desc;
509 struct virt_dma_desc *vd;
510 enum dma_status ret;
511 unsigned long flags;
512 unsigned int residual;
513
514 ret = dma_cookie_status(dc, cookie, txstate);
515 if (ret == DMA_COMPLETE || !txstate)
516 return ret;
517
518 spin_lock_irqsave(&tdc->vc.lock, flags);
519
520 vd = vchan_find_desc(&tdc->vc, cookie);
521 if (vd) {
522 desc = to_tegra_adma_desc(&vd->tx);
523 residual = desc->ch_regs.tc;
524 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
525 residual = tegra_adma_get_residue(tdc);
526 } else {
527 residual = 0;
528 }
529
530 spin_unlock_irqrestore(&tdc->vc.lock, flags);
531
532 dma_set_residue(txstate, residual);
533
534 return ret;
535}
536
433de642
SP		 537static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
538{
539 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
540 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
541
542 return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
543}
544
545static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
546{
547 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
548 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
549
550 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
551}
552
f46b1957
JH		 553static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
554 struct tegra_adma_desc *desc,
555 dma_addr_t buf_addr,
556 enum dma_transfer_direction direction)
557{
558 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
ded1f3db 559 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
32de4745 560 unsigned int burst_size, adma_dir, fifo_size_shift;
f46b1957
JH		 561
562 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
563 return -EINVAL;
564
565 switch (direction) {
566 case DMA_MEM_TO_DEV:
32de4745 567 fifo_size_shift = ADMA_CH_TX_FIFO_SIZE_SHIFT;
f46b1957 568 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
433de642 569 burst_size = tdc->sconfig.dst_maxburst;
f46b1957 570 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
ded1f3db
SP		 571 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
572 cdata->ch_req_mask,
573 cdata->ch_req_tx_shift);
f46b1957
JH		 574 ch_regs->src_addr = buf_addr;
575 break;
576
577 case DMA_DEV_TO_MEM:
32de4745 578 fifo_size_shift = ADMA_CH_RX_FIFO_SIZE_SHIFT;
f46b1957 579 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
433de642 580 burst_size = tdc->sconfig.src_maxburst;
f46b1957 581 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
ded1f3db
SP		 582 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
583 cdata->ch_req_mask,
584 cdata->ch_req_rx_shift);
f46b1957
JH		 585 ch_regs->trg_addr = buf_addr;
586 break;
587
588 default:
589 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
590 return -EINVAL;
591 }
592
f46b1957
JH		 593 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
594 ADMA_CH_CTRL_MODE_CONTINUOUS |
595 ADMA_CH_CTRL_FLOWCTRL_EN;
433de642 596 ch_regs->config |= cdata->adma_get_burst_config(burst_size);
f46b1957 597 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
9ec691f4
SP		 598 if (cdata->has_outstanding_reqs)
599 ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
32de4745
SP		 600
601 /*
602 * 'sreq_index' represents the current ADMAIF channel number and as per
603 * HW recommendation its FIFO size should match with the corresponding
604 * ADMA channel.
605 *
606 * ADMA FIFO size is set as per below (based on default ADMAIF channel
607 * FIFO sizes):
608 * fifo_size = 0x2 (sreq_index > sreq_index_offset)
609 * fifo_size = 0x3 (sreq_index <= sreq_index_offset)
610 *
611 */
612 if (tdc->sreq_index > cdata->sreq_index_offset)
613 ch_regs->fifo_ctrl =
614 ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask,
615 fifo_size_shift);
616 else
617 ch_regs->fifo_ctrl =
618 ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask,
619 fifo_size_shift);
620
f46b1957
JH		 621 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
622
623 return tegra_adma_request_alloc(tdc, direction);
624}
625
626static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
627 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
628 size_t period_len, enum dma_transfer_direction direction,
629 unsigned long flags)
630{
631 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
632 struct tegra_adma_desc *desc = NULL;
633
634 if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
635 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
636 return NULL;
637 }
638
639 if (buf_len % period_len) {
640 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
641 return NULL;
642 }
643
644 if (!IS_ALIGNED(buf_addr, 4)) {
645 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
646 return NULL;
647 }
648
649 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
650 if (!desc)
651 return NULL;
652
653 desc->buf_len = buf_len;
654 desc->period_len = period_len;
655 desc->num_periods = buf_len / period_len;
656
657 if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
658 kfree(desc);
659 return NULL;
660 }
661
662 return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
663}
664
665static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
666{
667 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
668 int ret;
669
670 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
671 if (ret) {
672 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
673 dma_chan_name(dc));
674 return ret;
675 }
676
059e969c 677 ret = pm_runtime_resume_and_get(tdc2dev(tdc));
f46b1957
JH		 678 if (ret < 0) {
679 free_irq(tdc->irq, tdc);
680 return ret;
681 }
682
683 dma_cookie_init(&tdc->vc.chan);
684
685 return 0;
686}
687
688static void tegra_adma_free_chan_resources(struct dma_chan *dc)
689{
690 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
691
692 tegra_adma_terminate_all(dc);
693 vchan_free_chan_resources(&tdc->vc);
694 tasklet_kill(&tdc->vc.task);
695 free_irq(tdc->irq, tdc);
696 pm_runtime_put(tdc2dev(tdc));
697
698 tdc->sreq_index = 0;
699 tdc->sreq_dir = DMA_TRANS_NONE;
700}
701
702static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
703 struct of_dma *ofdma)
704{
705 struct tegra_adma *tdma = ofdma->of_dma_data;
706 struct tegra_adma_chan *tdc;
707 struct dma_chan *chan;
708 unsigned int sreq_index;
709
710 if (dma_spec->args_count != 1)
711 return NULL;
712
713 sreq_index = dma_spec->args[0];
714
715 if (sreq_index == 0) {
716 dev_err(tdma->dev, "DMA request must not be 0\n");
717 return NULL;
718 }
719
720 chan = dma_get_any_slave_channel(&tdma->dma_dev);
721 if (!chan)
722 return NULL;
723
724 tdc = to_tegra_adma_chan(chan);
725 tdc->sreq_index = sreq_index;
726
727 return chan;
728}
729
d105ef81 730static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev)
f46b1957
JH		 731{
732 struct tegra_adma *tdma = dev_get_drvdata(dev);
f33e7bb3
SP		 733 struct tegra_adma_chan_regs *ch_reg;
734 struct tegra_adma_chan *tdc;
735 int i;
f46b1957
JH		 736
737 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
f33e7bb3
SP		 738 if (!tdma->global_cmd)
739 goto clk_disable;
740
741 for (i = 0; i < tdma->nr_channels; i++) {
742 tdc = &tdma->channels[i];
743 ch_reg = &tdc->ch_regs;
744 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
745 /* skip if channel is not active */
746 if (!ch_reg->cmd)
747 continue;
748 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
749 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
750 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
751 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
752 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
753 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
754 }
755
756clk_disable:
f6ed6491 757 clk_disable_unprepare(tdma->ahub_clk);
f46b1957 758
f6ed6491 759 return 0;
f46b1957
JH		 760}
761
d105ef81 762static int __maybe_unused tegra_adma_runtime_resume(struct device *dev)
f46b1957
JH		 763{
764 struct tegra_adma *tdma = dev_get_drvdata(dev);
f33e7bb3
SP		 765 struct tegra_adma_chan_regs *ch_reg;
766 struct tegra_adma_chan *tdc;
767 int ret, i;
f46b1957 768
f6ed6491
SP		 769 ret = clk_prepare_enable(tdma->ahub_clk);
770 if (ret) {
771 dev_err(dev, "ahub clk_enable failed: %d\n", ret);
f46b1957 772 return ret;
f6ed6491 773 }
f46b1957
JH		 774 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
775
f33e7bb3
SP		 776 if (!tdma->global_cmd)
777 return 0;
778
779 for (i = 0; i < tdma->nr_channels; i++) {
780 tdc = &tdma->channels[i];
781 ch_reg = &tdc->ch_regs;
782 /* skip if channel was not active earlier */
783 if (!ch_reg->cmd)
784 continue;
785 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
786 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
787 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
788 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
789 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
790 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
791 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
792 }
793
f46b1957
JH		 794 return 0;
795}
796
797static const struct tegra_adma_chip_data tegra210_chip_data = {
433de642 798 .adma_get_burst_config = tegra210_adma_get_burst_config,
ded1f3db
SP		 799 .global_reg_offset = 0xc00,
800 .global_int_clear = 0x20,
801 .ch_req_tx_shift = 28,
802 .ch_req_rx_shift = 24,
803 .ch_base_offset = 0,
804 .ch_req_mask = 0xf,
805 .ch_req_max = 10,
806 .ch_reg_size = 0x80,
807 .nr_channels = 22,
32de4745
SP		 808 .ch_fifo_size_mask = 0xf,
809 .sreq_index_offset = 2,
35696789 810 .has_outstanding_reqs = false,
f46b1957
JH		 811};
812
433de642
SP		 813static const struct tegra_adma_chip_data tegra186_chip_data = {
814 .adma_get_burst_config = tegra186_adma_get_burst_config,
815 .global_reg_offset = 0,
816 .global_int_clear = 0x402c,
817 .ch_req_tx_shift = 27,
818 .ch_req_rx_shift = 22,
819 .ch_base_offset = 0x10000,
820 .ch_req_mask = 0x1f,
821 .ch_req_max = 20,
822 .ch_reg_size = 0x100,
823 .nr_channels = 32,
32de4745
SP		 824 .ch_fifo_size_mask = 0x1f,
825 .sreq_index_offset = 4,
35696789 826 .has_outstanding_reqs = true,
433de642
SP		 827};
828
f46b1957
JH		 829static const struct of_device_id tegra_adma_of_match[] = {
830 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
433de642 831 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
f46b1957
JH		 832 { },
833};
834MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
835
836static int tegra_adma_probe(struct platform_device *pdev)
837{
838 const struct tegra_adma_chip_data *cdata;
839 struct tegra_adma *tdma;
840 struct resource *res;
f46b1957
JH		 841 int ret, i;
842
843 cdata = of_device_get_match_data(&pdev->dev);
844 if (!cdata) {
845 dev_err(&pdev->dev, "device match data not found\n");
846 return -ENODEV;
847 }
848
863326a6
GS		 849 tdma = devm_kzalloc(&pdev->dev,
850 struct_size(tdma, channels, cdata->nr_channels),
851 GFP_KERNEL);
f46b1957
JH		 852 if (!tdma)
853 return -ENOMEM;
854
855 tdma->dev = &pdev->dev;
ded1f3db 856 tdma->cdata = cdata;
f46b1957
JH		 857 tdma->nr_channels = cdata->nr_channels;
858 platform_set_drvdata(pdev, tdma);
859
860 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
861 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
862 if (IS_ERR(tdma->base_addr))
863 return PTR_ERR(tdma->base_addr);
864
f6ed6491
SP		 865 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
866 if (IS_ERR(tdma->ahub_clk)) {
867 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
868 return PTR_ERR(tdma->ahub_clk);
869 }
f46b1957 870
f46b1957
JH		 871 INIT_LIST_HEAD(&tdma->dma_dev.channels);
872 for (i = 0; i < tdma->nr_channels; i++) {
873 struct tegra_adma_chan *tdc = &tdma->channels[i];
874
ded1f3db
SP		 875 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
876 + (cdata->ch_reg_size * i);
f46b1957
JH		 877
878 tdc->irq = of_irq_get(pdev->dev.of_node, i);
7f577067
SS		 879 if (tdc->irq <= 0) {
880 ret = tdc->irq ?: -ENXIO;
f46b1957
JH		 881 goto irq_dispose;
882 }
883
884 vchan_init(&tdc->vc, &tdma->dma_dev);
885 tdc->vc.desc_free = tegra_adma_desc_free;
886 tdc->tdma = tdma;
887 }
888
b53611fb
JH		 889 pm_runtime_enable(&pdev->dev);
890
c5a51fc8 891 ret = pm_runtime_resume_and_get(&pdev->dev);
059e969c 892 if (ret < 0)
b53611fb
JH		 893 goto rpm_disable;
894
895 ret = tegra_adma_init(tdma);
896 if (ret)
897 goto rpm_put;
898
f46b1957
JH		 899 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
900 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
901 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
902
903 tdma->dma_dev.dev = &pdev->dev;
904 tdma->dma_dev.device_alloc_chan_resources =
905 tegra_adma_alloc_chan_resources;
906 tdma->dma_dev.device_free_chan_resources =
907 tegra_adma_free_chan_resources;
908 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
909 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
910 tdma->dma_dev.device_config = tegra_adma_slave_config;
911 tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
912 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
913 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
914 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
915 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
916 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
94dc8f4e
SP		 917 tdma->dma_dev.device_pause = tegra_adma_pause;
918 tdma->dma_dev.device_resume = tegra_adma_resume;
f46b1957
JH		 919
920 ret = dma_async_device_register(&tdma->dma_dev);
921 if (ret < 0) {
922 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
3a5fd0db 923 goto rpm_put;
f46b1957
JH		 924 }
925
926 ret = of_dma_controller_register(pdev->dev.of_node,
927 tegra_dma_of_xlate, tdma);
928 if (ret < 0) {
929 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
930 goto dma_remove;
931 }
932
933 pm_runtime_put(&pdev->dev);
934
935 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
936 tdma->nr_channels);
937
938 return 0;
939
940dma_remove:
941 dma_async_device_unregister(&tdma->dma_dev);
f46b1957
JH		 942rpm_put:
943 pm_runtime_put_sync(&pdev->dev);
944rpm_disable:
945 pm_runtime_disable(&pdev->dev);
b53611fb
JH		 946irq_dispose:
947 while (--i >= 0)
948 irq_dispose_mapping(tdma->channels[i].irq);
f46b1957
JH		 949
950 return ret;
951}
952
953static int tegra_adma_remove(struct platform_device *pdev)
954{
955 struct tegra_adma *tdma = platform_get_drvdata(pdev);
956 int i;
957
f030e419 958 of_dma_controller_free(pdev->dev.of_node);
f46b1957
JH		 959 dma_async_device_unregister(&tdma->dma_dev);
960
961 for (i = 0; i < tdma->nr_channels; ++i)
962 irq_dispose_mapping(tdma->channels[i].irq);
963
f46b1957 964 pm_runtime_disable(&pdev->dev);
f46b1957
JH		 965
966 return 0;
967}
968
f46b1957
JH		 969static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
970 SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
971 tegra_adma_runtime_resume, NULL)
74fca241
SP		 972 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
973 pm_runtime_force_resume)
f46b1957
JH		 974};
975
976static struct platform_driver tegra_admac_driver = {
977 .driver = {
978 .name = "tegra-adma",
979 .pm = &tegra_adma_dev_pm_ops,
980 .of_match_table = tegra_adma_of_match,
981 },
982 .probe = tegra_adma_probe,
983 .remove = tegra_adma_remove,
984};
985
986module_platform_driver(tegra_admac_driver);
987
988MODULE_ALIAS("platform:tegra210-adma");
989MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
990MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
991MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
992MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)