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9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f46b1957 JH |
2 | /* |
3 | * ADMA driver for Nvidia's Tegra210 ADMA controller. | |
4 | * | |
5 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | |
f46b1957 JH |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/iopoll.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of_device.h> | |
12 | #include <linux/of_dma.h> | |
13 | #include <linux/of_irq.h> | |
f46b1957 JH |
14 | #include <linux/pm_runtime.h> |
15 | #include <linux/slab.h> | |
16 | ||
17 | #include "virt-dma.h" | |
18 | ||
19 | #define ADMA_CH_CMD 0x00 | |
20 | #define ADMA_CH_STATUS 0x0c | |
21 | #define ADMA_CH_STATUS_XFER_EN BIT(0) | |
94dc8f4e | 22 | #define ADMA_CH_STATUS_XFER_PAUSED BIT(1) |
f46b1957 JH |
23 | |
24 | #define ADMA_CH_INT_STATUS 0x10 | |
25 | #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0) | |
26 | ||
27 | #define ADMA_CH_INT_CLEAR 0x1c | |
28 | #define ADMA_CH_CTRL 0x24 | |
f46b1957 JH |
29 | #define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12) |
30 | #define ADMA_CH_CTRL_DIR_AHUB2MEM 2 | |
31 | #define ADMA_CH_CTRL_DIR_MEM2AHUB 4 | |
32 | #define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8) | |
33 | #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1) | |
94dc8f4e | 34 | #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0 |
f46b1957 JH |
35 | |
36 | #define ADMA_CH_CONFIG 0x28 | |
37 | #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28) | |
38 | #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24) | |
433de642 SP |
39 | #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20 |
40 | #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16 | |
f46b1957 JH |
41 | #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf) |
42 | #define ADMA_CH_CONFIG_MAX_BUFS 8 | |
9ec691f4 | 43 | #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4) |
f46b1957 JH |
44 | |
45 | #define ADMA_CH_FIFO_CTRL 0x2c | |
9ab59bf5 JH |
46 | #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8) |
47 | #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf) | |
9ab59bf5 JH |
48 | #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8) |
49 | #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f) | |
f46b1957 JH |
50 | |
51 | #define ADMA_CH_LOWER_SRC_ADDR 0x34 | |
52 | #define ADMA_CH_LOWER_TRG_ADDR 0x3c | |
53 | #define ADMA_CH_TC 0x44 | |
54 | #define ADMA_CH_TC_COUNT_MASK 0x3ffffffc | |
55 | ||
56 | #define ADMA_CH_XFER_STATUS 0x54 | |
57 | #define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff | |
58 | ||
ded1f3db SP |
59 | #define ADMA_GLOBAL_CMD 0x00 |
60 | #define ADMA_GLOBAL_SOFT_RESET 0x04 | |
f46b1957 | 61 | |
94dc8f4e SP |
62 | #define TEGRA_ADMA_BURST_COMPLETE_TIME 20 |
63 | ||
a9afc9ea | 64 | #define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \ |
9ab59bf5 JH |
65 | TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3)) |
66 | ||
a9afc9ea | 67 | #define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \ |
9ab59bf5 | 68 | TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3)) |
ded1f3db SP |
69 | |
70 | #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift) | |
71 | ||
f46b1957 JH |
72 | struct tegra_adma; |
73 | ||
74 | /* | |
75 | * struct tegra_adma_chip_data - Tegra chip specific data | |
ded1f3db SP |
76 | * @global_reg_offset: Register offset of DMA global register. |
77 | * @global_int_clear: Register offset of DMA global interrupt clear. | |
78 | * @ch_req_tx_shift: Register offset for AHUB transmit channel select. | |
79 | * @ch_req_rx_shift: Register offset for AHUB receive channel select. | |
49225249 | 80 | * @ch_base_offset: Register offset of DMA channel registers. |
9ec691f4 | 81 | * @has_outstanding_reqs: If DMA channel can have outstanding requests. |
9ab59bf5 | 82 | * @ch_fifo_ctrl: Default value for channel FIFO CTRL register. |
ded1f3db SP |
83 | * @ch_req_mask: Mask for Tx or Rx channel select. |
84 | * @ch_req_max: Maximum number of Tx or Rx channels available. | |
85 | * @ch_reg_size: Size of DMA channel register space. | |
f46b1957 JH |
86 | * @nr_channels: Number of DMA channels available. |
87 | */ | |
88 | struct tegra_adma_chip_data { | |
433de642 | 89 | unsigned int (*adma_get_burst_config)(unsigned int burst_size); |
ded1f3db SP |
90 | unsigned int global_reg_offset; |
91 | unsigned int global_int_clear; | |
92 | unsigned int ch_req_tx_shift; | |
93 | unsigned int ch_req_rx_shift; | |
94 | unsigned int ch_base_offset; | |
9ab59bf5 | 95 | unsigned int ch_fifo_ctrl; |
ded1f3db SP |
96 | unsigned int ch_req_mask; |
97 | unsigned int ch_req_max; | |
98 | unsigned int ch_reg_size; | |
99 | unsigned int nr_channels; | |
9ec691f4 | 100 | bool has_outstanding_reqs; |
f46b1957 JH |
101 | }; |
102 | ||
103 | /* | |
104 | * struct tegra_adma_chan_regs - Tegra ADMA channel registers | |
105 | */ | |
106 | struct tegra_adma_chan_regs { | |
107 | unsigned int ctrl; | |
108 | unsigned int config; | |
109 | unsigned int src_addr; | |
110 | unsigned int trg_addr; | |
111 | unsigned int fifo_ctrl; | |
f33e7bb3 | 112 | unsigned int cmd; |
f46b1957 JH |
113 | unsigned int tc; |
114 | }; | |
115 | ||
116 | /* | |
117 | * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests. | |
118 | */ | |
119 | struct tegra_adma_desc { | |
120 | struct virt_dma_desc vd; | |
121 | struct tegra_adma_chan_regs ch_regs; | |
122 | size_t buf_len; | |
123 | size_t period_len; | |
124 | size_t num_periods; | |
125 | }; | |
126 | ||
127 | /* | |
128 | * struct tegra_adma_chan - Tegra ADMA channel information | |
129 | */ | |
130 | struct tegra_adma_chan { | |
131 | struct virt_dma_chan vc; | |
132 | struct tegra_adma_desc *desc; | |
133 | struct tegra_adma *tdma; | |
134 | int irq; | |
135 | void __iomem *chan_addr; | |
136 | ||
137 | /* Slave channel configuration info */ | |
138 | struct dma_slave_config sconfig; | |
139 | enum dma_transfer_direction sreq_dir; | |
140 | unsigned int sreq_index; | |
141 | bool sreq_reserved; | |
f33e7bb3 | 142 | struct tegra_adma_chan_regs ch_regs; |
f46b1957 JH |
143 | |
144 | /* Transfer count and position info */ | |
145 | unsigned int tx_buf_count; | |
146 | unsigned int tx_buf_pos; | |
147 | }; | |
148 | ||
149 | /* | |
150 | * struct tegra_adma - Tegra ADMA controller information | |
151 | */ | |
152 | struct tegra_adma { | |
153 | struct dma_device dma_dev; | |
154 | struct device *dev; | |
155 | void __iomem *base_addr; | |
f6ed6491 | 156 | struct clk *ahub_clk; |
f46b1957 JH |
157 | unsigned int nr_channels; |
158 | unsigned long rx_requests_reserved; | |
159 | unsigned long tx_requests_reserved; | |
160 | ||
161 | /* Used to store global command register state when suspending */ | |
162 | unsigned int global_cmd; | |
163 | ||
ded1f3db SP |
164 | const struct tegra_adma_chip_data *cdata; |
165 | ||
f46b1957 | 166 | /* Last member of the structure */ |
1ee44529 | 167 | struct tegra_adma_chan channels[]; |
f46b1957 JH |
168 | }; |
169 | ||
170 | static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val) | |
171 | { | |
ded1f3db | 172 | writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); |
f46b1957 JH |
173 | } |
174 | ||
175 | static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg) | |
176 | { | |
ded1f3db | 177 | return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); |
f46b1957 JH |
178 | } |
179 | ||
180 | static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) | |
181 | { | |
182 | writel(val, tdc->chan_addr + reg); | |
183 | } | |
184 | ||
185 | static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg) | |
186 | { | |
187 | return readl(tdc->chan_addr + reg); | |
188 | } | |
189 | ||
190 | static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc) | |
191 | { | |
192 | return container_of(dc, struct tegra_adma_chan, vc.chan); | |
193 | } | |
194 | ||
195 | static inline struct tegra_adma_desc *to_tegra_adma_desc( | |
196 | struct dma_async_tx_descriptor *td) | |
197 | { | |
198 | return container_of(td, struct tegra_adma_desc, vd.tx); | |
199 | } | |
200 | ||
201 | static inline struct device *tdc2dev(struct tegra_adma_chan *tdc) | |
202 | { | |
203 | return tdc->tdma->dev; | |
204 | } | |
205 | ||
206 | static void tegra_adma_desc_free(struct virt_dma_desc *vd) | |
207 | { | |
208 | kfree(container_of(vd, struct tegra_adma_desc, vd)); | |
209 | } | |
210 | ||
211 | static int tegra_adma_slave_config(struct dma_chan *dc, | |
212 | struct dma_slave_config *sconfig) | |
213 | { | |
214 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
215 | ||
216 | memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static int tegra_adma_init(struct tegra_adma *tdma) | |
222 | { | |
223 | u32 status; | |
224 | int ret; | |
225 | ||
226 | /* Clear any interrupts */ | |
ded1f3db | 227 | tdma_write(tdma, tdma->cdata->global_int_clear, 0x1); |
f46b1957 JH |
228 | |
229 | /* Assert soft reset */ | |
230 | tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); | |
231 | ||
232 | /* Wait for reset to clear */ | |
233 | ret = readx_poll_timeout(readl, | |
ded1f3db SP |
234 | tdma->base_addr + |
235 | tdma->cdata->global_reg_offset + | |
236 | ADMA_GLOBAL_SOFT_RESET, | |
f46b1957 JH |
237 | status, status == 0, 20, 10000); |
238 | if (ret) | |
239 | return ret; | |
240 | ||
241 | /* Enable global ADMA registers */ | |
242 | tdma_write(tdma, ADMA_GLOBAL_CMD, 1); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc, | |
248 | enum dma_transfer_direction direction) | |
249 | { | |
250 | struct tegra_adma *tdma = tdc->tdma; | |
251 | unsigned int sreq_index = tdc->sreq_index; | |
252 | ||
253 | if (tdc->sreq_reserved) | |
254 | return tdc->sreq_dir == direction ? 0 : -EINVAL; | |
255 | ||
ded1f3db SP |
256 | if (sreq_index > tdma->cdata->ch_req_max) { |
257 | dev_err(tdma->dev, "invalid DMA request\n"); | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
f46b1957 JH |
261 | switch (direction) { |
262 | case DMA_MEM_TO_DEV: | |
f46b1957 JH |
263 | if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { |
264 | dev_err(tdma->dev, "DMA request reserved\n"); | |
265 | return -EINVAL; | |
266 | } | |
267 | break; | |
268 | ||
269 | case DMA_DEV_TO_MEM: | |
f46b1957 JH |
270 | if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { |
271 | dev_err(tdma->dev, "DMA request reserved\n"); | |
272 | return -EINVAL; | |
273 | } | |
274 | break; | |
275 | ||
276 | default: | |
277 | dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", | |
278 | dma_chan_name(&tdc->vc.chan)); | |
279 | return -EINVAL; | |
280 | } | |
281 | ||
282 | tdc->sreq_dir = direction; | |
283 | tdc->sreq_reserved = true; | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static void tegra_adma_request_free(struct tegra_adma_chan *tdc) | |
289 | { | |
290 | struct tegra_adma *tdma = tdc->tdma; | |
291 | ||
292 | if (!tdc->sreq_reserved) | |
293 | return; | |
294 | ||
295 | switch (tdc->sreq_dir) { | |
296 | case DMA_MEM_TO_DEV: | |
297 | clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); | |
298 | break; | |
299 | ||
300 | case DMA_DEV_TO_MEM: | |
301 | clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); | |
302 | break; | |
303 | ||
304 | default: | |
305 | dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", | |
306 | dma_chan_name(&tdc->vc.chan)); | |
307 | return; | |
308 | } | |
309 | ||
310 | tdc->sreq_reserved = false; | |
311 | } | |
312 | ||
313 | static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc) | |
314 | { | |
315 | u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS); | |
316 | ||
317 | return status & ADMA_CH_INT_STATUS_XFER_DONE; | |
318 | } | |
319 | ||
320 | static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc) | |
321 | { | |
322 | u32 status = tegra_adma_irq_status(tdc); | |
323 | ||
324 | if (status) | |
325 | tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status); | |
326 | ||
327 | return status; | |
328 | } | |
329 | ||
330 | static void tegra_adma_stop(struct tegra_adma_chan *tdc) | |
331 | { | |
332 | unsigned int status; | |
333 | ||
334 | /* Disable ADMA */ | |
335 | tdma_ch_write(tdc, ADMA_CH_CMD, 0); | |
336 | ||
337 | /* Clear interrupt status */ | |
338 | tegra_adma_irq_clear(tdc); | |
339 | ||
340 | if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, | |
341 | status, !(status & ADMA_CH_STATUS_XFER_EN), | |
342 | 20, 10000)) { | |
343 | dev_err(tdc2dev(tdc), "unable to stop DMA channel\n"); | |
344 | return; | |
345 | } | |
346 | ||
347 | kfree(tdc->desc); | |
348 | tdc->desc = NULL; | |
349 | } | |
350 | ||
351 | static void tegra_adma_start(struct tegra_adma_chan *tdc) | |
352 | { | |
353 | struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); | |
354 | struct tegra_adma_chan_regs *ch_regs; | |
355 | struct tegra_adma_desc *desc; | |
356 | ||
357 | if (!vd) | |
358 | return; | |
359 | ||
360 | list_del(&vd->node); | |
361 | ||
362 | desc = to_tegra_adma_desc(&vd->tx); | |
363 | ||
364 | if (!desc) { | |
365 | dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n"); | |
366 | return; | |
367 | } | |
368 | ||
369 | ch_regs = &desc->ch_regs; | |
370 | ||
371 | tdc->tx_buf_pos = 0; | |
372 | tdc->tx_buf_count = 0; | |
373 | tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); | |
374 | tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); | |
375 | tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); | |
376 | tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); | |
377 | tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); | |
378 | tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); | |
379 | ||
380 | /* Start ADMA */ | |
381 | tdma_ch_write(tdc, ADMA_CH_CMD, 1); | |
382 | ||
383 | tdc->desc = desc; | |
384 | } | |
385 | ||
386 | static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc) | |
387 | { | |
388 | struct tegra_adma_desc *desc = tdc->desc; | |
389 | unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1; | |
390 | unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS); | |
391 | unsigned int periods_remaining; | |
392 | ||
393 | /* | |
394 | * Handle wrap around of buffer count register | |
395 | */ | |
396 | if (pos < tdc->tx_buf_pos) | |
397 | tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); | |
398 | else | |
399 | tdc->tx_buf_count += pos - tdc->tx_buf_pos; | |
400 | ||
401 | periods_remaining = tdc->tx_buf_count % desc->num_periods; | |
402 | tdc->tx_buf_pos = pos; | |
403 | ||
404 | return desc->buf_len - (periods_remaining * desc->period_len); | |
405 | } | |
406 | ||
407 | static irqreturn_t tegra_adma_isr(int irq, void *dev_id) | |
408 | { | |
409 | struct tegra_adma_chan *tdc = dev_id; | |
410 | unsigned long status; | |
f46b1957 | 411 | |
654115e3 | 412 | spin_lock(&tdc->vc.lock); |
f46b1957 JH |
413 | |
414 | status = tegra_adma_irq_clear(tdc); | |
415 | if (status == 0 || !tdc->desc) { | |
654115e3 | 416 | spin_unlock(&tdc->vc.lock); |
f46b1957 JH |
417 | return IRQ_NONE; |
418 | } | |
419 | ||
420 | vchan_cyclic_callback(&tdc->desc->vd); | |
421 | ||
654115e3 | 422 | spin_unlock(&tdc->vc.lock); |
f46b1957 JH |
423 | |
424 | return IRQ_HANDLED; | |
425 | } | |
426 | ||
427 | static void tegra_adma_issue_pending(struct dma_chan *dc) | |
428 | { | |
429 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
430 | unsigned long flags; | |
431 | ||
432 | spin_lock_irqsave(&tdc->vc.lock, flags); | |
433 | ||
434 | if (vchan_issue_pending(&tdc->vc)) { | |
435 | if (!tdc->desc) | |
436 | tegra_adma_start(tdc); | |
437 | } | |
438 | ||
439 | spin_unlock_irqrestore(&tdc->vc.lock, flags); | |
440 | } | |
441 | ||
94dc8f4e SP |
442 | static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc) |
443 | { | |
444 | u32 csts; | |
445 | ||
446 | csts = tdma_ch_read(tdc, ADMA_CH_STATUS); | |
447 | csts &= ADMA_CH_STATUS_XFER_PAUSED; | |
448 | ||
449 | return csts ? true : false; | |
450 | } | |
451 | ||
452 | static int tegra_adma_pause(struct dma_chan *dc) | |
453 | { | |
454 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
455 | struct tegra_adma_desc *desc = tdc->desc; | |
456 | struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; | |
457 | int dcnt = 10; | |
458 | ||
459 | ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); | |
460 | ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); | |
461 | tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); | |
462 | ||
463 | while (dcnt-- && !tegra_adma_is_paused(tdc)) | |
464 | udelay(TEGRA_ADMA_BURST_COMPLETE_TIME); | |
465 | ||
466 | if (dcnt < 0) { | |
467 | dev_err(tdc2dev(tdc), "unable to pause DMA channel\n"); | |
468 | return -EBUSY; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | static int tegra_adma_resume(struct dma_chan *dc) | |
475 | { | |
476 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
477 | struct tegra_adma_desc *desc = tdc->desc; | |
478 | struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; | |
479 | ||
480 | ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); | |
481 | ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); | |
482 | tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
f46b1957 JH |
487 | static int tegra_adma_terminate_all(struct dma_chan *dc) |
488 | { | |
489 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
490 | unsigned long flags; | |
491 | LIST_HEAD(head); | |
492 | ||
493 | spin_lock_irqsave(&tdc->vc.lock, flags); | |
494 | ||
495 | if (tdc->desc) | |
496 | tegra_adma_stop(tdc); | |
497 | ||
498 | tegra_adma_request_free(tdc); | |
499 | vchan_get_all_descriptors(&tdc->vc, &head); | |
500 | spin_unlock_irqrestore(&tdc->vc.lock, flags); | |
501 | vchan_dma_desc_free_list(&tdc->vc, &head); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static enum dma_status tegra_adma_tx_status(struct dma_chan *dc, | |
507 | dma_cookie_t cookie, | |
508 | struct dma_tx_state *txstate) | |
509 | { | |
510 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
511 | struct tegra_adma_desc *desc; | |
512 | struct virt_dma_desc *vd; | |
513 | enum dma_status ret; | |
514 | unsigned long flags; | |
515 | unsigned int residual; | |
516 | ||
517 | ret = dma_cookie_status(dc, cookie, txstate); | |
518 | if (ret == DMA_COMPLETE || !txstate) | |
519 | return ret; | |
520 | ||
521 | spin_lock_irqsave(&tdc->vc.lock, flags); | |
522 | ||
523 | vd = vchan_find_desc(&tdc->vc, cookie); | |
524 | if (vd) { | |
525 | desc = to_tegra_adma_desc(&vd->tx); | |
526 | residual = desc->ch_regs.tc; | |
527 | } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { | |
528 | residual = tegra_adma_get_residue(tdc); | |
529 | } else { | |
530 | residual = 0; | |
531 | } | |
532 | ||
533 | spin_unlock_irqrestore(&tdc->vc.lock, flags); | |
534 | ||
535 | dma_set_residue(txstate, residual); | |
536 | ||
537 | return ret; | |
538 | } | |
539 | ||
433de642 SP |
540 | static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size) |
541 | { | |
542 | if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE) | |
543 | burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE; | |
544 | ||
545 | return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; | |
546 | } | |
547 | ||
548 | static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size) | |
549 | { | |
550 | if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE) | |
551 | burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE; | |
552 | ||
553 | return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; | |
554 | } | |
555 | ||
f46b1957 JH |
556 | static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, |
557 | struct tegra_adma_desc *desc, | |
558 | dma_addr_t buf_addr, | |
559 | enum dma_transfer_direction direction) | |
560 | { | |
561 | struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; | |
ded1f3db | 562 | const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; |
f46b1957 JH |
563 | unsigned int burst_size, adma_dir; |
564 | ||
565 | if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) | |
566 | return -EINVAL; | |
567 | ||
568 | switch (direction) { | |
569 | case DMA_MEM_TO_DEV: | |
570 | adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB; | |
433de642 | 571 | burst_size = tdc->sconfig.dst_maxburst; |
f46b1957 | 572 | ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); |
ded1f3db SP |
573 | ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, |
574 | cdata->ch_req_mask, | |
575 | cdata->ch_req_tx_shift); | |
f46b1957 JH |
576 | ch_regs->src_addr = buf_addr; |
577 | break; | |
578 | ||
579 | case DMA_DEV_TO_MEM: | |
580 | adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM; | |
433de642 | 581 | burst_size = tdc->sconfig.src_maxburst; |
f46b1957 | 582 | ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); |
ded1f3db SP |
583 | ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, |
584 | cdata->ch_req_mask, | |
585 | cdata->ch_req_rx_shift); | |
f46b1957 JH |
586 | ch_regs->trg_addr = buf_addr; |
587 | break; | |
588 | ||
589 | default: | |
590 | dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); | |
591 | return -EINVAL; | |
592 | } | |
593 | ||
f46b1957 JH |
594 | ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) | |
595 | ADMA_CH_CTRL_MODE_CONTINUOUS | | |
596 | ADMA_CH_CTRL_FLOWCTRL_EN; | |
433de642 | 597 | ch_regs->config |= cdata->adma_get_burst_config(burst_size); |
f46b1957 | 598 | ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); |
9ec691f4 SP |
599 | if (cdata->has_outstanding_reqs) |
600 | ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8); | |
9ab59bf5 | 601 | ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl; |
f46b1957 JH |
602 | ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; |
603 | ||
604 | return tegra_adma_request_alloc(tdc, direction); | |
605 | } | |
606 | ||
607 | static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic( | |
608 | struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, | |
609 | size_t period_len, enum dma_transfer_direction direction, | |
610 | unsigned long flags) | |
611 | { | |
612 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
613 | struct tegra_adma_desc *desc = NULL; | |
614 | ||
615 | if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) { | |
616 | dev_err(tdc2dev(tdc), "invalid buffer/period len\n"); | |
617 | return NULL; | |
618 | } | |
619 | ||
620 | if (buf_len % period_len) { | |
621 | dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n"); | |
622 | return NULL; | |
623 | } | |
624 | ||
625 | if (!IS_ALIGNED(buf_addr, 4)) { | |
626 | dev_err(tdc2dev(tdc), "invalid buffer alignment\n"); | |
627 | return NULL; | |
628 | } | |
629 | ||
630 | desc = kzalloc(sizeof(*desc), GFP_NOWAIT); | |
631 | if (!desc) | |
632 | return NULL; | |
633 | ||
634 | desc->buf_len = buf_len; | |
635 | desc->period_len = period_len; | |
636 | desc->num_periods = buf_len / period_len; | |
637 | ||
638 | if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) { | |
639 | kfree(desc); | |
640 | return NULL; | |
641 | } | |
642 | ||
643 | return vchan_tx_prep(&tdc->vc, &desc->vd, flags); | |
644 | } | |
645 | ||
646 | static int tegra_adma_alloc_chan_resources(struct dma_chan *dc) | |
647 | { | |
648 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
649 | int ret; | |
650 | ||
651 | ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); | |
652 | if (ret) { | |
653 | dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n", | |
654 | dma_chan_name(dc)); | |
655 | return ret; | |
656 | } | |
657 | ||
658 | ret = pm_runtime_get_sync(tdc2dev(tdc)); | |
659 | if (ret < 0) { | |
5b78fac4 | 660 | pm_runtime_put_noidle(tdc2dev(tdc)); |
f46b1957 JH |
661 | free_irq(tdc->irq, tdc); |
662 | return ret; | |
663 | } | |
664 | ||
665 | dma_cookie_init(&tdc->vc.chan); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | static void tegra_adma_free_chan_resources(struct dma_chan *dc) | |
671 | { | |
672 | struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); | |
673 | ||
674 | tegra_adma_terminate_all(dc); | |
675 | vchan_free_chan_resources(&tdc->vc); | |
676 | tasklet_kill(&tdc->vc.task); | |
677 | free_irq(tdc->irq, tdc); | |
678 | pm_runtime_put(tdc2dev(tdc)); | |
679 | ||
680 | tdc->sreq_index = 0; | |
681 | tdc->sreq_dir = DMA_TRANS_NONE; | |
682 | } | |
683 | ||
684 | static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, | |
685 | struct of_dma *ofdma) | |
686 | { | |
687 | struct tegra_adma *tdma = ofdma->of_dma_data; | |
688 | struct tegra_adma_chan *tdc; | |
689 | struct dma_chan *chan; | |
690 | unsigned int sreq_index; | |
691 | ||
692 | if (dma_spec->args_count != 1) | |
693 | return NULL; | |
694 | ||
695 | sreq_index = dma_spec->args[0]; | |
696 | ||
697 | if (sreq_index == 0) { | |
698 | dev_err(tdma->dev, "DMA request must not be 0\n"); | |
699 | return NULL; | |
700 | } | |
701 | ||
702 | chan = dma_get_any_slave_channel(&tdma->dma_dev); | |
703 | if (!chan) | |
704 | return NULL; | |
705 | ||
706 | tdc = to_tegra_adma_chan(chan); | |
707 | tdc->sreq_index = sreq_index; | |
708 | ||
709 | return chan; | |
710 | } | |
711 | ||
d105ef81 | 712 | static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) |
f46b1957 JH |
713 | { |
714 | struct tegra_adma *tdma = dev_get_drvdata(dev); | |
f33e7bb3 SP |
715 | struct tegra_adma_chan_regs *ch_reg; |
716 | struct tegra_adma_chan *tdc; | |
717 | int i; | |
f46b1957 JH |
718 | |
719 | tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); | |
f33e7bb3 SP |
720 | if (!tdma->global_cmd) |
721 | goto clk_disable; | |
722 | ||
723 | for (i = 0; i < tdma->nr_channels; i++) { | |
724 | tdc = &tdma->channels[i]; | |
725 | ch_reg = &tdc->ch_regs; | |
726 | ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); | |
727 | /* skip if channel is not active */ | |
728 | if (!ch_reg->cmd) | |
729 | continue; | |
730 | ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC); | |
731 | ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); | |
732 | ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); | |
733 | ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); | |
734 | ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); | |
735 | ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); | |
736 | } | |
737 | ||
738 | clk_disable: | |
f6ed6491 | 739 | clk_disable_unprepare(tdma->ahub_clk); |
f46b1957 | 740 | |
f6ed6491 | 741 | return 0; |
f46b1957 JH |
742 | } |
743 | ||
d105ef81 | 744 | static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) |
f46b1957 JH |
745 | { |
746 | struct tegra_adma *tdma = dev_get_drvdata(dev); | |
f33e7bb3 SP |
747 | struct tegra_adma_chan_regs *ch_reg; |
748 | struct tegra_adma_chan *tdc; | |
749 | int ret, i; | |
f46b1957 | 750 | |
f6ed6491 SP |
751 | ret = clk_prepare_enable(tdma->ahub_clk); |
752 | if (ret) { | |
753 | dev_err(dev, "ahub clk_enable failed: %d\n", ret); | |
f46b1957 | 754 | return ret; |
f6ed6491 | 755 | } |
f46b1957 JH |
756 | tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); |
757 | ||
f33e7bb3 SP |
758 | if (!tdma->global_cmd) |
759 | return 0; | |
760 | ||
761 | for (i = 0; i < tdma->nr_channels; i++) { | |
762 | tdc = &tdma->channels[i]; | |
763 | ch_reg = &tdc->ch_regs; | |
764 | /* skip if channel was not active earlier */ | |
765 | if (!ch_reg->cmd) | |
766 | continue; | |
767 | tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); | |
768 | tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); | |
769 | tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); | |
770 | tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); | |
771 | tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); | |
772 | tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); | |
773 | tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); | |
774 | } | |
775 | ||
f46b1957 JH |
776 | return 0; |
777 | } | |
778 | ||
779 | static const struct tegra_adma_chip_data tegra210_chip_data = { | |
433de642 | 780 | .adma_get_burst_config = tegra210_adma_get_burst_config, |
ded1f3db SP |
781 | .global_reg_offset = 0xc00, |
782 | .global_int_clear = 0x20, | |
783 | .ch_req_tx_shift = 28, | |
784 | .ch_req_rx_shift = 24, | |
785 | .ch_base_offset = 0, | |
9ec691f4 | 786 | .has_outstanding_reqs = false, |
9ab59bf5 | 787 | .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT, |
ded1f3db SP |
788 | .ch_req_mask = 0xf, |
789 | .ch_req_max = 10, | |
790 | .ch_reg_size = 0x80, | |
791 | .nr_channels = 22, | |
f46b1957 JH |
792 | }; |
793 | ||
433de642 SP |
794 | static const struct tegra_adma_chip_data tegra186_chip_data = { |
795 | .adma_get_burst_config = tegra186_adma_get_burst_config, | |
796 | .global_reg_offset = 0, | |
797 | .global_int_clear = 0x402c, | |
798 | .ch_req_tx_shift = 27, | |
799 | .ch_req_rx_shift = 22, | |
800 | .ch_base_offset = 0x10000, | |
9ec691f4 | 801 | .has_outstanding_reqs = true, |
9ab59bf5 | 802 | .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT, |
433de642 SP |
803 | .ch_req_mask = 0x1f, |
804 | .ch_req_max = 20, | |
805 | .ch_reg_size = 0x100, | |
806 | .nr_channels = 32, | |
807 | }; | |
808 | ||
f46b1957 JH |
809 | static const struct of_device_id tegra_adma_of_match[] = { |
810 | { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data }, | |
433de642 | 811 | { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data }, |
f46b1957 JH |
812 | { }, |
813 | }; | |
814 | MODULE_DEVICE_TABLE(of, tegra_adma_of_match); | |
815 | ||
816 | static int tegra_adma_probe(struct platform_device *pdev) | |
817 | { | |
818 | const struct tegra_adma_chip_data *cdata; | |
819 | struct tegra_adma *tdma; | |
820 | struct resource *res; | |
f46b1957 JH |
821 | int ret, i; |
822 | ||
823 | cdata = of_device_get_match_data(&pdev->dev); | |
824 | if (!cdata) { | |
825 | dev_err(&pdev->dev, "device match data not found\n"); | |
826 | return -ENODEV; | |
827 | } | |
828 | ||
863326a6 GS |
829 | tdma = devm_kzalloc(&pdev->dev, |
830 | struct_size(tdma, channels, cdata->nr_channels), | |
831 | GFP_KERNEL); | |
f46b1957 JH |
832 | if (!tdma) |
833 | return -ENOMEM; | |
834 | ||
835 | tdma->dev = &pdev->dev; | |
ded1f3db | 836 | tdma->cdata = cdata; |
f46b1957 JH |
837 | tdma->nr_channels = cdata->nr_channels; |
838 | platform_set_drvdata(pdev, tdma); | |
839 | ||
840 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
841 | tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); | |
842 | if (IS_ERR(tdma->base_addr)) | |
843 | return PTR_ERR(tdma->base_addr); | |
844 | ||
f6ed6491 SP |
845 | tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); |
846 | if (IS_ERR(tdma->ahub_clk)) { | |
847 | dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); | |
848 | return PTR_ERR(tdma->ahub_clk); | |
849 | } | |
f46b1957 | 850 | |
f46b1957 JH |
851 | INIT_LIST_HEAD(&tdma->dma_dev.channels); |
852 | for (i = 0; i < tdma->nr_channels; i++) { | |
853 | struct tegra_adma_chan *tdc = &tdma->channels[i]; | |
854 | ||
ded1f3db SP |
855 | tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset |
856 | + (cdata->ch_reg_size * i); | |
f46b1957 JH |
857 | |
858 | tdc->irq = of_irq_get(pdev->dev.of_node, i); | |
7f577067 SS |
859 | if (tdc->irq <= 0) { |
860 | ret = tdc->irq ?: -ENXIO; | |
f46b1957 JH |
861 | goto irq_dispose; |
862 | } | |
863 | ||
864 | vchan_init(&tdc->vc, &tdma->dma_dev); | |
865 | tdc->vc.desc_free = tegra_adma_desc_free; | |
866 | tdc->tdma = tdma; | |
867 | } | |
868 | ||
b53611fb JH |
869 | pm_runtime_enable(&pdev->dev); |
870 | ||
871 | ret = pm_runtime_get_sync(&pdev->dev); | |
5b78fac4 DL |
872 | if (ret < 0) { |
873 | pm_runtime_put_noidle(&pdev->dev); | |
b53611fb | 874 | goto rpm_disable; |
5b78fac4 | 875 | } |
b53611fb JH |
876 | |
877 | ret = tegra_adma_init(tdma); | |
878 | if (ret) | |
879 | goto rpm_put; | |
880 | ||
f46b1957 JH |
881 | dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); |
882 | dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); | |
883 | dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); | |
884 | ||
885 | tdma->dma_dev.dev = &pdev->dev; | |
886 | tdma->dma_dev.device_alloc_chan_resources = | |
887 | tegra_adma_alloc_chan_resources; | |
888 | tdma->dma_dev.device_free_chan_resources = | |
889 | tegra_adma_free_chan_resources; | |
890 | tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; | |
891 | tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; | |
892 | tdma->dma_dev.device_config = tegra_adma_slave_config; | |
893 | tdma->dma_dev.device_tx_status = tegra_adma_tx_status; | |
894 | tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; | |
895 | tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
896 | tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
897 | tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
898 | tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; | |
94dc8f4e SP |
899 | tdma->dma_dev.device_pause = tegra_adma_pause; |
900 | tdma->dma_dev.device_resume = tegra_adma_resume; | |
f46b1957 JH |
901 | |
902 | ret = dma_async_device_register(&tdma->dma_dev); | |
903 | if (ret < 0) { | |
904 | dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); | |
3a5fd0db | 905 | goto rpm_put; |
f46b1957 JH |
906 | } |
907 | ||
908 | ret = of_dma_controller_register(pdev->dev.of_node, | |
909 | tegra_dma_of_xlate, tdma); | |
910 | if (ret < 0) { | |
911 | dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); | |
912 | goto dma_remove; | |
913 | } | |
914 | ||
915 | pm_runtime_put(&pdev->dev); | |
916 | ||
917 | dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", | |
918 | tdma->nr_channels); | |
919 | ||
920 | return 0; | |
921 | ||
922 | dma_remove: | |
923 | dma_async_device_unregister(&tdma->dma_dev); | |
f46b1957 JH |
924 | rpm_put: |
925 | pm_runtime_put_sync(&pdev->dev); | |
926 | rpm_disable: | |
927 | pm_runtime_disable(&pdev->dev); | |
b53611fb JH |
928 | irq_dispose: |
929 | while (--i >= 0) | |
930 | irq_dispose_mapping(tdma->channels[i].irq); | |
f46b1957 JH |
931 | |
932 | return ret; | |
933 | } | |
934 | ||
935 | static int tegra_adma_remove(struct platform_device *pdev) | |
936 | { | |
937 | struct tegra_adma *tdma = platform_get_drvdata(pdev); | |
938 | int i; | |
939 | ||
f030e419 | 940 | of_dma_controller_free(pdev->dev.of_node); |
f46b1957 JH |
941 | dma_async_device_unregister(&tdma->dma_dev); |
942 | ||
943 | for (i = 0; i < tdma->nr_channels; ++i) | |
944 | irq_dispose_mapping(tdma->channels[i].irq); | |
945 | ||
946 | pm_runtime_put_sync(&pdev->dev); | |
947 | pm_runtime_disable(&pdev->dev); | |
f46b1957 JH |
948 | |
949 | return 0; | |
950 | } | |
951 | ||
f46b1957 JH |
952 | static const struct dev_pm_ops tegra_adma_dev_pm_ops = { |
953 | SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend, | |
954 | tegra_adma_runtime_resume, NULL) | |
74fca241 SP |
955 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
956 | pm_runtime_force_resume) | |
f46b1957 JH |
957 | }; |
958 | ||
959 | static struct platform_driver tegra_admac_driver = { | |
960 | .driver = { | |
961 | .name = "tegra-adma", | |
962 | .pm = &tegra_adma_dev_pm_ops, | |
963 | .of_match_table = tegra_adma_of_match, | |
964 | }, | |
965 | .probe = tegra_adma_probe, | |
966 | .remove = tegra_adma_remove, | |
967 | }; | |
968 | ||
969 | module_platform_driver(tegra_admac_driver); | |
970 | ||
971 | MODULE_ALIAS("platform:tegra210-adma"); | |
972 | MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver"); | |
973 | MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>"); | |
974 | MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>"); | |
975 | MODULE_LICENSE("GPL v2"); |