[linux-block.git] / drivers / dma / ste_dma40_ll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 */

#include <linux/kernel.h>
#include <linux/dmaengine.h>

#include "ste_dma40.h"
#include "ste_dma40_ll.h"

static u8 d40_width_to_bits(enum dma_slave_buswidth width)
{
	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
		return STEDMA40_ESIZE_8_BIT;
	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
		return STEDMA40_ESIZE_16_BIT;
	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
		return STEDMA40_ESIZE_64_BIT;
	else
		return STEDMA40_ESIZE_32_BIT;
}

/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *lcsp1, u32 *lcsp3)
{
	u32 l3 = 0; /* dst */
	u32 l1 = 0; /* src */

	/* src is mem? -> increase address pos */
	if (cfg->dir ==  DMA_MEM_TO_DEV ||
	    cfg->dir ==  DMA_MEM_TO_MEM)
		l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);

	/* dst is mem? -> increase address pos */
	if (cfg->dir ==  DMA_DEV_TO_MEM ||
	    cfg->dir ==  DMA_MEM_TO_MEM)
		l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);

	/* src is hw? -> master port 1 */
	if (cfg->dir ==  DMA_DEV_TO_MEM ||
	    cfg->dir ==  DMA_DEV_TO_DEV)
		l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);

	/* dst is hw? -> master port 1 */
	if (cfg->dir ==  DMA_MEM_TO_DEV ||
	    cfg->dir ==  DMA_DEV_TO_DEV)
		l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);

	l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	l3 |= d40_width_to_bits(cfg->dst_info.data_width)
		<< D40_MEM_LCSP3_DCFG_ESIZE_POS;

	l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	l1 |= d40_width_to_bits(cfg->src_info.data_width)
		<< D40_MEM_LCSP1_SCFG_ESIZE_POS;

	*lcsp1 = l1;
	*lcsp3 = l3;

}

void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
{
	u32 src = 0;
	u32 dst = 0;

	if ((cfg->dir == DMA_DEV_TO_MEM) ||
	    (cfg->dir == DMA_DEV_TO_DEV)) {
		/* Set master port to 1 */
		src |= BIT(D40_SREG_CFG_MST_POS);
		src |= D40_TYPE_TO_EVENT(cfg->dev_type);

		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
			src |= BIT(D40_SREG_CFG_PHY_TM_POS);
		else
			src |= 3 << D40_SREG_CFG_PHY_TM_POS;
	}
	if ((cfg->dir == DMA_MEM_TO_DEV) ||
	    (cfg->dir == DMA_DEV_TO_DEV)) {
		/* Set master port to 1 */
		dst |= BIT(D40_SREG_CFG_MST_POS);
		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);

		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
			dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
		else
			dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
	}
	/* Interrupt on end of transfer for destination */
	dst |= BIT(D40_SREG_CFG_TIM_POS);

	/* Generate interrupt on error */
	src |= BIT(D40_SREG_CFG_EIM_POS);
	dst |= BIT(D40_SREG_CFG_EIM_POS);

	/* PSIZE */
	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
		src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
	}
	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
		dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
	}

	/* Element size */
	src |= d40_width_to_bits(cfg->src_info.data_width)
		<< D40_SREG_CFG_ESIZE_POS;
	dst |= d40_width_to_bits(cfg->dst_info.data_width)
		<< D40_SREG_CFG_ESIZE_POS;

	/* Set the priority bit to high for the physical channel */
	if (cfg->high_priority) {
		src |= BIT(D40_SREG_CFG_PRI_POS);
		dst |= BIT(D40_SREG_CFG_PRI_POS);
	}

	if (cfg->src_info.big_endian)
		src |= BIT(D40_SREG_CFG_LBE_POS);
	if (cfg->dst_info.big_endian)
		dst |= BIT(D40_SREG_CFG_LBE_POS);

	*src_cfg = src;
	*dst_cfg = dst;
}

static int d40_phy_fill_lli(struct d40_phy_lli *lli,
			    dma_addr_t data,
			    u32 data_size,
			    dma_addr_t next_lli,
			    u32 reg_cfg,
			    struct stedma40_half_channel_info *info,
			    unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;
	bool term_int = flags & LLI_TERM_INT;
	unsigned int data_width = info->data_width;
	int psize = info->psize;
	int num_elems;

	if (psize == STEDMA40_PSIZE_PHY_1)
		num_elems = 1;
	else
		num_elems = 2 << psize;

	/* Must be aligned */
	if (!IS_ALIGNED(data, data_width))
		return -EINVAL;

	/* Transfer size can't be smaller than (num_elms * elem_size) */
	if (data_size < num_elems * data_width)
		return -EINVAL;

	/* The number of elements. IE now many chunks */
	lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;

	/*
	 * Distance to next element sized entry.
	 * Usually the size of the element unless you want gaps.
	 */
	if (addr_inc)
		lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;

	/* Where the data is */
	lli->reg_ptr = data;
	lli->reg_cfg = reg_cfg;

	/* If this scatter list entry is the last one, no next link */
	if (next_lli == 0)
		lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
	else
		lli->reg_lnk = next_lli;

	/* Set/clear interrupt generation on this link item.*/
	if (term_int)
		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
	else
		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);

	/*
	 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
	 * Relink happens after transfer completion.
	 */

	return 0;
}

static int d40_seg_size(int size, int data_width1, int data_width2)
{
	u32 max_w = max(data_width1, data_width2);
	u32 min_w = min(data_width1, data_width2);
	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);

	if (seg_max > STEDMA40_MAX_SEG_SIZE)
		seg_max -= max_w;

	if (size <= seg_max)
		return size;

	if (size <= 2 * seg_max)
		return ALIGN(size / 2, max_w);

	return seg_max;
}

static struct d40_phy_lli *
d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
		   dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
		   struct stedma40_half_channel_info *info,
		   struct stedma40_half_channel_info *otherinfo,
		   unsigned long flags)
{
	bool lastlink = flags & LLI_LAST_LINK;
	bool addr_inc = flags & LLI_ADDR_INC;
	bool term_int = flags & LLI_TERM_INT;
	bool cyclic = flags & LLI_CYCLIC;
	int err;
	dma_addr_t next = lli_phys;
	int size_rest = size;
	int size_seg = 0;

	/*
	 * This piece may be split up based on d40_seg_size(); we only want the
	 * term int on the last part.
	 */
	if (term_int)
		flags &= ~LLI_TERM_INT;

	do {
		size_seg = d40_seg_size(size_rest, info->data_width,
					otherinfo->data_width);
		size_rest -= size_seg;

		if (size_rest == 0 && term_int)
			flags |= LLI_TERM_INT;

		if (size_rest == 0 && lastlink)
			next = cyclic ? first_phys : 0;
		else
			next = ALIGN(next + sizeof(struct d40_phy_lli),
				     D40_LLI_ALIGN);

		err = d40_phy_fill_lli(lli, addr, size_seg, next,
				       reg_cfg, info, flags);

		if (err)
			goto err;

		lli++;
		if (addr_inc)
			addr += size_seg;
	} while (size_rest);

	return lli;

err:
	return NULL;
}

int d40_phy_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t target,
		      struct d40_phy_lli *lli_sg,
		      dma_addr_t lli_phys,
		      u32 reg_cfg,
		      struct stedma40_half_channel_info *info,
		      struct stedma40_half_channel_info *otherinfo,
		      unsigned long flags)
{
	int total_size = 0;
	int i;
	struct scatterlist *current_sg = sg;
	struct d40_phy_lli *lli = lli_sg;
	dma_addr_t l_phys = lli_phys;

	if (!target)
		flags |= LLI_ADDR_INC;

	for_each_sg(sg, current_sg, sg_len, i) {
		dma_addr_t sg_addr = sg_dma_address(current_sg);
		unsigned int len = sg_dma_len(current_sg);
		dma_addr_t dst = target ?: sg_addr;

		total_size += sg_dma_len(current_sg);

		if (i == sg_len - 1)
			flags |= LLI_TERM_INT | LLI_LAST_LINK;

		l_phys = ALIGN(lli_phys + (lli - lli_sg) *
			       sizeof(struct d40_phy_lli), D40_LLI_ALIGN);

		lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
					 reg_cfg, info, otherinfo, flags);

		if (lli == NULL)
			return -EINVAL;
	}

	return total_size;
}


/* DMA logical lli operations */

static void d40_log_lli_link(struct d40_log_lli *lli_dst,
			     struct d40_log_lli *lli_src,
			     int next, unsigned int flags)
{
	bool interrupt = flags & LLI_TERM_INT;
	u32 slos = 0;
	u32 dlos = 0;

	if (next != -EINVAL) {
		slos = next * 2;
		dlos = next * 2 + 1;
	}

	if (interrupt) {
		lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
		lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
	}

	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(slos << D40_MEM_LCSP1_SLOS_POS);

	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(dlos << D40_MEM_LCSP1_SLOS_POS);
}

void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next, unsigned int flags)
{
	d40_log_lli_link(lli_dst, lli_src, next, flags);

	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
}

void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next, unsigned int flags)
{
	d40_log_lli_link(lli_dst, lli_src, next, flags);

	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
}

static void d40_log_fill_lli(struct d40_log_lli *lli,
			     dma_addr_t data, u32 data_size,
			     u32 reg_cfg,
			     u32 data_width,
			     unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;

	lli->lcsp13 = reg_cfg;

	/* The number of elements to transfer */
	lli->lcsp02 = ((data_size / data_width) <<
		       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;

	BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);

	/* 16 LSBs address of the current element */
	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
	/* 16 MSBs address of the current element */
	lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;

	if (addr_inc)
		lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;

}

static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
				       dma_addr_t addr,
				       int size,
				       u32 lcsp13, /* src or dst*/
				       u32 data_width1,
				       u32 data_width2,
				       unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;
	struct d40_log_lli *lli = lli_sg;
	int size_rest = size;
	int size_seg = 0;

	do {
		size_seg = d40_seg_size(size_rest, data_width1, data_width2);
		size_rest -= size_seg;

		d40_log_fill_lli(lli,
				 addr,
				 size_seg,
				 lcsp13, data_width1,
				 flags);
		if (addr_inc)
			addr += size_seg;
		lli++;
	} while (size_rest);

	return lli;
}

int d40_log_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t dev_addr,
		      struct d40_log_lli *lli_sg,
		      u32 lcsp13, /* src or dst*/
		      u32 data_width1, u32 data_width2)
{
	int total_size = 0;
	struct scatterlist *current_sg = sg;
	int i;
	struct d40_log_lli *lli = lli_sg;
	unsigned long flags = 0;

	if (!dev_addr)
		flags |= LLI_ADDR_INC;

	for_each_sg(sg, current_sg, sg_len, i) {
		dma_addr_t sg_addr = sg_dma_address(current_sg);
		unsigned int len = sg_dma_len(current_sg);
		dma_addr_t addr = dev_addr ?: sg_addr;

		total_size += sg_dma_len(current_sg);

		lli = d40_log_buf_to_lli(lli, addr, len,
					 lcsp13,
					 data_width1,
					 data_width2,
					 flags);
	}

	return total_size;
}
Commit	Line	Data
af873fce	1	// SPDX-License-Identifier: GPL-2.0-only
8d318a50	2	/*
767a9675	3	* Copyright (C) ST-Ericsson SA 2007-2010
d49278e3	4	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	5	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 LW	6	*/
	7
	8	#include <linux/kernel.h>
42ae6f16	9	#include <linux/dmaengine.h>
8d318a50	10
42ae6f16	11	#include "ste_dma40.h"
8d318a50 LW	12	#include "ste_dma40_ll.h"
8d318a50 LW	13
0161df13	14	static u8 d40_width_to_bits(enum dma_slave_buswidth width)
43f2e1a3 LJ	15	{
	16	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
	17	return STEDMA40_ESIZE_8_BIT;
	18	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
	19	return STEDMA40_ESIZE_16_BIT;
	20	else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
	21	return STEDMA40_ESIZE_64_BIT;
	22	else
	23	return STEDMA40_ESIZE_32_BIT;
	24	}
	25
8d318a50 LW	26	/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
	27	void d40_log_cfg(struct stedma40_chan_cfg *cfg,
	28	u32 lcsp1, u32 lcsp3)
	29	{
	30	u32 l3 = 0; /* dst */
	31	u32 l1 = 0; /* src */
	32
	33	/* src is mem? -> increase address pos */
2c2b62d5 LJ	34	if (cfg->dir == DMA_MEM_TO_DEV \|\|
2c2b62d5 LJ	35	cfg->dir == DMA_MEM_TO_MEM)
16db3411	36	l1 \|= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
8d318a50 LW	37
8d318a50 LW	38	/* dst is mem? -> increase address pos */
2c2b62d5 LJ	39	if (cfg->dir == DMA_DEV_TO_MEM \|\|
2c2b62d5 LJ	40	cfg->dir == DMA_MEM_TO_MEM)
16db3411	41	l3 \|= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
8d318a50 LW	42
8d318a50 LW	43	/* src is hw? -> master port 1 */
2c2b62d5 LJ	44	if (cfg->dir == DMA_DEV_TO_MEM \|\|
2c2b62d5 LJ	45	cfg->dir == DMA_DEV_TO_DEV)
16db3411	46	l1 \|= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
8d318a50 LW	47
8d318a50 LW	48	/* dst is hw? -> master port 1 */
2c2b62d5 LJ	49	if (cfg->dir == DMA_MEM_TO_DEV \|\|
2c2b62d5 LJ	50	cfg->dir == DMA_DEV_TO_DEV)
16db3411	51	l3 \|= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
8d318a50	52
16db3411	53	l3 \|= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
8d318a50	54	l3 \|= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
43f2e1a3 LJ	55	l3 \|= d40_width_to_bits(cfg->dst_info.data_width)
43f2e1a3 LJ	56	<< D40_MEM_LCSP3_DCFG_ESIZE_POS;
8d318a50	57
16db3411	58	l1 \|= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
8d318a50	59	l1 \|= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
43f2e1a3 LJ	60	l1 \|= d40_width_to_bits(cfg->src_info.data_width)
43f2e1a3 LJ	61	<< D40_MEM_LCSP1_SCFG_ESIZE_POS;
8d318a50 LW	62
	63	*lcsp1 = l1;
	64	*lcsp3 = l3;
	65
	66	}
	67
57e65ad7	68	void d40_phy_cfg(struct stedma40_chan_cfg cfg, u32 src_cfg, u32 *dst_cfg)
8d318a50 LW	69	{
	70	u32 src = 0;
	71	u32 dst = 0;
	72
2c2b62d5 LJ	73	if ((cfg->dir == DMA_DEV_TO_MEM) \|\|
2c2b62d5 LJ	74	(cfg->dir == DMA_DEV_TO_DEV)) {
57e65ad7	75	/* Set master port to 1 */
16db3411	76	src \|= BIT(D40_SREG_CFG_MST_POS);
57e65ad7 LJ	77	src \|= D40_TYPE_TO_EVENT(cfg->dev_type);
	78
	79	if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
16db3411	80	src \|= BIT(D40_SREG_CFG_PHY_TM_POS);
57e65ad7 LJ	81	else
	82	src \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	83	}
2c2b62d5 LJ	84	if ((cfg->dir == DMA_MEM_TO_DEV) \|\|
2c2b62d5 LJ	85	(cfg->dir == DMA_DEV_TO_DEV)) {
57e65ad7	86	/* Set master port to 1 */
16db3411	87	dst \|= BIT(D40_SREG_CFG_MST_POS);
57e65ad7 LJ	88	dst \|= D40_TYPE_TO_EVENT(cfg->dev_type);
	89
	90	if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
16db3411	91	dst \|= BIT(D40_SREG_CFG_PHY_TM_POS);
57e65ad7 LJ	92	else
	93	dst \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	94	}
	95	/* Interrupt on end of transfer for destination */
16db3411	96	dst \|= BIT(D40_SREG_CFG_TIM_POS);
57e65ad7 LJ	97
57e65ad7 LJ	98	/* Generate interrupt on error */
16db3411 LJ	99	src \|= BIT(D40_SREG_CFG_EIM_POS);
16db3411 LJ	100	dst \|= BIT(D40_SREG_CFG_EIM_POS);
57e65ad7 LJ	101
	102	/* PSIZE */
	103	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
16db3411	104	src \|= BIT(D40_SREG_CFG_PHY_PEN_POS);
57e65ad7 LJ	105	src \|= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
	106	}
	107	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
16db3411	108	dst \|= BIT(D40_SREG_CFG_PHY_PEN_POS);
57e65ad7 LJ	109	dst \|= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
	110	}
	111
	112	/* Element size */
43f2e1a3 LJ	113	src \|= d40_width_to_bits(cfg->src_info.data_width)
	114	<< D40_SREG_CFG_ESIZE_POS;
	115	dst \|= d40_width_to_bits(cfg->dst_info.data_width)
	116	<< D40_SREG_CFG_ESIZE_POS;
57e65ad7 LJ	117
	118	/* Set the priority bit to high for the physical channel */
	119	if (cfg->high_priority) {
16db3411 LJ	120	src \|= BIT(D40_SREG_CFG_PRI_POS);
16db3411 LJ	121	dst \|= BIT(D40_SREG_CFG_PRI_POS);
8d318a50 LW	122	}
8d318a50 LW	123
51f5d744	124	if (cfg->src_info.big_endian)
16db3411	125	src \|= BIT(D40_SREG_CFG_LBE_POS);
51f5d744	126	if (cfg->dst_info.big_endian)
16db3411	127	dst \|= BIT(D40_SREG_CFG_LBE_POS);
8d318a50 LW	128
	129	*src_cfg = src;
	130	*dst_cfg = dst;
	131	}
	132
d49278e3 PF	133	static int d40_phy_fill_lli(struct d40_phy_lli *lli,
	134	dma_addr_t data,
	135	u32 data_size,
d49278e3 PF	136	dma_addr_t next_lli,
d49278e3 PF	137	u32 reg_cfg,
7f933bed RV	138	struct stedma40_half_channel_info *info,
7f933bed RV	139	unsigned int flags)
8d318a50	140	{
7f933bed RV	141	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	142	bool term_int = flags & LLI_TERM_INT;
cc31b6f7 RV	143	unsigned int data_width = info->data_width;
cc31b6f7 RV	144	int psize = info->psize;
8d318a50 LW	145	int num_elems;
	146
	147	if (psize == STEDMA40_PSIZE_PHY_1)
	148	num_elems = 1;
	149	else
	150	num_elems = 2 << psize;
	151
8d318a50	152	/* Must be aligned */
43f2e1a3	153	if (!IS_ALIGNED(data, data_width))
8d318a50 LW	154	return -EINVAL;
	155
	156	/* Transfer size can't be smaller than (num_elms * elem_size) */
43f2e1a3	157	if (data_size < num_elems * data_width)
8d318a50 LW	158	return -EINVAL;
	159
	160	/* The number of elements. IE now many chunks */
43f2e1a3	161	lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
8d318a50 LW	162
	163	/*
	164	* Distance to next element sized entry.
	165	* Usually the size of the element unless you want gaps.
	166	*/
7f933bed	167	if (addr_inc)
43f2e1a3	168	lli->reg_elt \|= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
8d318a50 LW	169
	170	/* Where the data is */
	171	lli->reg_ptr = data;
	172	lli->reg_cfg = reg_cfg;
	173
	174	/* If this scatter list entry is the last one, no next link */
	175	if (next_lli == 0)
16db3411	176	lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
8d318a50 LW	177	else
	178	lli->reg_lnk = next_lli;
	179
	180	/* Set/clear interrupt generation on this link item.*/
	181	if (term_int)
16db3411	182	lli->reg_cfg \|= BIT(D40_SREG_CFG_TIM_POS);
8d318a50	183	else
16db3411	184	lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
8d318a50	185
8cc5af12 LJ	186	/*
	187	* Post link - D40_SREG_LNK_PHY_PRE_POS = 0
	188	* Relink happens after transfer completion.
	189	*/
8d318a50 LW	190
	191	return 0;
	192	}
	193
d49278e3 PF	194	static int d40_seg_size(int size, int data_width1, int data_width2)
	195	{
	196	u32 max_w = max(data_width1, data_width2);
	197	u32 min_w = min(data_width1, data_width2);
43f2e1a3	198	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
d49278e3 PF	199
d49278e3 PF	200	if (seg_max > STEDMA40_MAX_SEG_SIZE)
43f2e1a3	201	seg_max -= max_w;
d49278e3 PF	202
	203	if (size <= seg_max)
	204	return size;
	205
	206	if (size <= 2 * seg_max)
43f2e1a3	207	return ALIGN(size / 2, max_w);
d49278e3 PF	208
	209	return seg_max;
	210	}
	211
cc31b6f7 RV	212	static struct d40_phy_lli *
cc31b6f7 RV	213	d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
0c842b55	214	dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
7f933bed RV	215	struct stedma40_half_channel_info *info,
	216	struct stedma40_half_channel_info *otherinfo,
	217	unsigned long flags)
d49278e3	218	{
0c842b55	219	bool lastlink = flags & LLI_LAST_LINK;
7f933bed RV	220	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	221	bool term_int = flags & LLI_TERM_INT;
0c842b55	222	bool cyclic = flags & LLI_CYCLIC;
d49278e3 PF	223	int err;
	224	dma_addr_t next = lli_phys;
	225	int size_rest = size;
	226	int size_seg = 0;
	227
7f933bed RV	228	/*
	229	* This piece may be split up based on d40_seg_size(); we only want the
	230	* term int on the last part.
	231	*/
	232	if (term_int)
	233	flags &= ~LLI_TERM_INT;
	234
d49278e3	235	do {
cc31b6f7 RV	236	size_seg = d40_seg_size(size_rest, info->data_width,
cc31b6f7 RV	237	otherinfo->data_width);
d49278e3 PF	238	size_rest -= size_seg;
d49278e3 PF	239
0c842b55	240	if (size_rest == 0 && term_int)
7f933bed	241	flags \|= LLI_TERM_INT;
0c842b55 RV	242
	243	if (size_rest == 0 && lastlink)
	244	next = cyclic ? first_phys : 0;
	245	else
d49278e3 PF	246	next = ALIGN(next + sizeof(struct d40_phy_lli),
	247	D40_LLI_ALIGN);
	248
7f933bed RV	249	err = d40_phy_fill_lli(lli, addr, size_seg, next,
7f933bed RV	250	reg_cfg, info, flags);
d49278e3 PF	251
	252	if (err)
	253	goto err;
	254
	255	lli++;
7f933bed	256	if (addr_inc)
d49278e3 PF	257	addr += size_seg;
	258	} while (size_rest);
	259
	260	return lli;
	261
f26e03ad	262	err:
d49278e3 PF	263	return NULL;
	264	}
	265
8d318a50 LW	266	int d40_phy_sg_to_lli(struct scatterlist *sg,
	267	int sg_len,
	268	dma_addr_t target,
d49278e3	269	struct d40_phy_lli *lli_sg,
8d318a50 LW	270	dma_addr_t lli_phys,
8d318a50 LW	271	u32 reg_cfg,
cc31b6f7	272	struct stedma40_half_channel_info *info,
0c842b55 RV	273	struct stedma40_half_channel_info *otherinfo,
0c842b55 RV	274	unsigned long flags)
8d318a50 LW	275	{
	276	int total_size = 0;
	277	int i;
	278	struct scatterlist *current_sg = sg;
d49278e3 PF	279	struct d40_phy_lli *lli = lli_sg;
d49278e3 PF	280	dma_addr_t l_phys = lli_phys;
7f933bed RV	281
	282	if (!target)
	283	flags \|= LLI_ADDR_INC;
8d318a50 LW	284
8d318a50 LW	285	for_each_sg(sg, current_sg, sg_len, i) {
7f933bed RV	286	dma_addr_t sg_addr = sg_dma_address(current_sg);
	287	unsigned int len = sg_dma_len(current_sg);
	288	dma_addr_t dst = target ?: sg_addr;
8d318a50 LW	289
	290	total_size += sg_dma_len(current_sg);
	291
7f933bed	292	if (i == sg_len - 1)
0c842b55	293	flags \|= LLI_TERM_INT \| LLI_LAST_LINK;
8d318a50	294
d49278e3 PF	295	l_phys = ALIGN(lli_phys + (lli - lli_sg) *
	296	sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
	297
0c842b55	298	lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
7f933bed RV	299	reg_cfg, info, otherinfo, flags);
7f933bed RV	300
d49278e3 PF	301	if (lli == NULL)
d49278e3 PF	302	return -EINVAL;
8d318a50 LW	303	}
	304
	305	return total_size;
8d318a50 LW	306	}
	307
	308
8d318a50 LW	309	/* DMA logical lli operations */
8d318a50 LW	310
698e4732 JA	311	static void d40_log_lli_link(struct d40_log_lli *lli_dst,
698e4732 JA	312	struct d40_log_lli *lli_src,
0c842b55	313	int next, unsigned int flags)
698e4732	314	{
0c842b55	315	bool interrupt = flags & LLI_TERM_INT;
698e4732 JA	316	u32 slos = 0;
	317	u32 dlos = 0;
	318
	319	if (next != -EINVAL) {
	320	slos = next * 2;
	321	dlos = next * 2 + 1;
0c842b55 RV	322	}
	323
	324	if (interrupt) {
698e4732 JA	325	lli_dst->lcsp13 \|= D40_MEM_LCSP1_SCFG_TIM_MASK;
	326	lli_dst->lcsp13 \|= D40_MEM_LCSP3_DTCP_MASK;
	327	}
	328
	329	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	330	(slos << D40_MEM_LCSP1_SLOS_POS);
	331
	332	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	333	(dlos << D40_MEM_LCSP1_SLOS_POS);
	334	}
	335
	336	void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
	337	struct d40_log_lli *lli_dst,
	338	struct d40_log_lli *lli_src,
0c842b55	339	int next, unsigned int flags)
698e4732	340	{
0c842b55	341	d40_log_lli_link(lli_dst, lli_src, next, flags);
698e4732	342
8a5d2039 PF	343	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
	344	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
	345	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
	346	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
698e4732 JA	347	}
	348
	349	void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
	350	struct d40_log_lli *lli_dst,
	351	struct d40_log_lli *lli_src,
0c842b55	352	int next, unsigned int flags)
698e4732	353	{
0c842b55	354	d40_log_lli_link(lli_dst, lli_src, next, flags);
698e4732	355
8a5d2039 PF	356	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
	357	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
	358	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
	359	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
698e4732 JA	360	}
698e4732 JA	361
d49278e3 PF	362	static void d40_log_fill_lli(struct d40_log_lli *lli,
	363	dma_addr_t data, u32 data_size,
	364	u32 reg_cfg,
	365	u32 data_width,
7f933bed	366	unsigned int flags)
8d318a50	367	{
7f933bed RV	368	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	369
8d318a50 LW	370	lli->lcsp13 = reg_cfg;
	371
	372	/* The number of elements to transfer */
43f2e1a3	373	lli->lcsp02 = ((data_size / data_width) <<
8d318a50	374	D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
d49278e3	375
43f2e1a3	376	BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
d49278e3	377
8d318a50 LW	378	/* 16 LSBs address of the current element */
	379	lli->lcsp02 \|= data & D40_MEM_LCSP0_SPTR_MASK;
	380	/* 16 MSBs address of the current element */
	381	lli->lcsp13 \|= data & D40_MEM_LCSP1_SPTR_MASK;
	382
	383	if (addr_inc)
	384	lli->lcsp13 \|= D40_MEM_LCSP1_SCFG_INCR_MASK;
	385
8d318a50 LW	386	}
8d318a50 LW	387
1f7622ca	388	static struct d40_log_lli d40_log_buf_to_lli(struct d40_log_lli lli_sg,
d49278e3 PF	389	dma_addr_t addr,
	390	int size,
	391	u32 lcsp13, /* src or dst*/
	392	u32 data_width1,
	393	u32 data_width2,
7f933bed	394	unsigned int flags)
d49278e3	395	{
7f933bed	396	bool addr_inc = flags & LLI_ADDR_INC;
d49278e3 PF	397	struct d40_log_lli *lli = lli_sg;
	398	int size_rest = size;
	399	int size_seg = 0;
	400
	401	do {
	402	size_seg = d40_seg_size(size_rest, data_width1, data_width2);
	403	size_rest -= size_seg;
	404
	405	d40_log_fill_lli(lli,
	406	addr,
	407	size_seg,
	408	lcsp13, data_width1,
7f933bed	409	flags);
d49278e3 PF	410	if (addr_inc)
	411	addr += size_seg;
	412	lli++;
	413	} while (size_rest);
	414
	415	return lli;
	416	}
	417
698e4732	418	int d40_log_sg_to_lli(struct scatterlist *sg,
8d318a50	419	int sg_len,
5ed04b85	420	dma_addr_t dev_addr,
8d318a50 LW	421	struct d40_log_lli *lli_sg,
8d318a50 LW	422	u32 lcsp13, /* src or dst*/
d49278e3	423	u32 data_width1, u32 data_width2)
8d318a50 LW	424	{
	425	int total_size = 0;
	426	struct scatterlist *current_sg = sg;
	427	int i;
d49278e3	428	struct d40_log_lli *lli = lli_sg;
7f933bed RV	429	unsigned long flags = 0;
	430
	431	if (!dev_addr)
	432	flags \|= LLI_ADDR_INC;
8d318a50 LW	433
8d318a50 LW	434	for_each_sg(sg, current_sg, sg_len, i) {
5ed04b85 RV	435	dma_addr_t sg_addr = sg_dma_address(current_sg);
	436	unsigned int len = sg_dma_len(current_sg);
	437	dma_addr_t addr = dev_addr ?: sg_addr;
	438
8d318a50	439	total_size += sg_dma_len(current_sg);
5ed04b85 RV	440
5ed04b85 RV	441	lli = d40_log_buf_to_lli(lli, addr, len,
d49278e3	442	lcsp13,
5ed04b85 RV	443	data_width1,
5ed04b85 RV	444	data_width2,
7f933bed	445	flags);
8d318a50	446	}
5ed04b85	447
8d318a50 LW	448	return total_size;
8d318a50 LW	449	}