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dmaengine: sprd: Fix potential NULL dereference in sprd_dma_probe()
[linux-2.6-block.git] / drivers / dma / sprd-dma.c
CommitLineData
9b3b8171
BW		 1/*
2 * Copyright (C) 2017 Spreadtrum Communications Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <linux/clk.h>
8#include <linux/dma-mapping.h>
ab42ddb9 9#include <linux/dma/sprd-dma.h>
9b3b8171
BW		 10#include <linux/errno.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_dma.h>
18#include <linux/of_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21
22#include "virt-dma.h"
23
24#define SPRD_DMA_CHN_REG_OFFSET 0x1000
25#define SPRD_DMA_CHN_REG_LENGTH 0x40
26#define SPRD_DMA_MEMCPY_MIN_SIZE 64
27
28/* DMA global registers definition */
29#define SPRD_DMA_GLB_PAUSE 0x0
30#define SPRD_DMA_GLB_FRAG_WAIT 0x4
31#define SPRD_DMA_GLB_REQ_PEND0_EN 0x8
32#define SPRD_DMA_GLB_REQ_PEND1_EN 0xc
33#define SPRD_DMA_GLB_INT_RAW_STS 0x10
34#define SPRD_DMA_GLB_INT_MSK_STS 0x14
35#define SPRD_DMA_GLB_REQ_STS 0x18
36#define SPRD_DMA_GLB_CHN_EN_STS 0x1c
37#define SPRD_DMA_GLB_DEBUG_STS 0x20
38#define SPRD_DMA_GLB_ARB_SEL_STS 0x24
39#define SPRD_DMA_GLB_REQ_UID(uid) (0x4 * ((uid) - 1))
40#define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000
41
42/* DMA channel registers definition */
43#define SPRD_DMA_CHN_PAUSE 0x0
44#define SPRD_DMA_CHN_REQ 0x4
45#define SPRD_DMA_CHN_CFG 0x8
46#define SPRD_DMA_CHN_INTC 0xc
47#define SPRD_DMA_CHN_SRC_ADDR 0x10
48#define SPRD_DMA_CHN_DES_ADDR 0x14
49#define SPRD_DMA_CHN_FRG_LEN 0x18
50#define SPRD_DMA_CHN_BLK_LEN 0x1c
51#define SPRD_DMA_CHN_TRSC_LEN 0x20
52#define SPRD_DMA_CHN_TRSF_STEP 0x24
53#define SPRD_DMA_CHN_WARP_PTR 0x28
54#define SPRD_DMA_CHN_WARP_TO 0x2c
55#define SPRD_DMA_CHN_LLIST_PTR 0x30
56#define SPRD_DMA_CHN_FRAG_STEP 0x34
57#define SPRD_DMA_CHN_SRC_BLK_STEP 0x38
58#define SPRD_DMA_CHN_DES_BLK_STEP 0x3c
59
60/* SPRD_DMA_CHN_INTC register definition */
61#define SPRD_DMA_INT_MASK GENMASK(4, 0)
62#define SPRD_DMA_INT_CLR_OFFSET 24
63#define SPRD_DMA_FRAG_INT_EN BIT(0)
64#define SPRD_DMA_BLK_INT_EN BIT(1)
65#define SPRD_DMA_TRANS_INT_EN BIT(2)
66#define SPRD_DMA_LIST_INT_EN BIT(3)
67#define SPRD_DMA_CFG_ERR_INT_EN BIT(4)
68
69/* SPRD_DMA_CHN_CFG register definition */
70#define SPRD_DMA_CHN_EN BIT(0)
71#define SPRD_DMA_WAIT_BDONE_OFFSET 24
72#define SPRD_DMA_DONOT_WAIT_BDONE 1
73
74/* SPRD_DMA_CHN_REQ register definition */
75#define SPRD_DMA_REQ_EN BIT(0)
76
77/* SPRD_DMA_CHN_PAUSE register definition */
78#define SPRD_DMA_PAUSE_EN BIT(0)
79#define SPRD_DMA_PAUSE_STS BIT(2)
80#define SPRD_DMA_PAUSE_CNT 0x2000
81
82/* DMA_CHN_WARP_* register definition */
83#define SPRD_DMA_HIGH_ADDR_MASK GENMASK(31, 28)
84#define SPRD_DMA_LOW_ADDR_MASK GENMASK(31, 0)
85#define SPRD_DMA_HIGH_ADDR_OFFSET 4
86
87/* SPRD_DMA_CHN_INTC register definition */
88#define SPRD_DMA_FRAG_INT_STS BIT(16)
89#define SPRD_DMA_BLK_INT_STS BIT(17)
90#define SPRD_DMA_TRSC_INT_STS BIT(18)
91#define SPRD_DMA_LIST_INT_STS BIT(19)
92#define SPRD_DMA_CFGERR_INT_STS BIT(20)
93#define SPRD_DMA_CHN_INT_STS \
94 (SPRD_DMA_FRAG_INT_STS | SPRD_DMA_BLK_INT_STS | \
95 SPRD_DMA_TRSC_INT_STS | SPRD_DMA_LIST_INT_STS | \
96 SPRD_DMA_CFGERR_INT_STS)
97
98/* SPRD_DMA_CHN_FRG_LEN register definition */
99#define SPRD_DMA_SRC_DATAWIDTH_OFFSET 30
100#define SPRD_DMA_DES_DATAWIDTH_OFFSET 28
101#define SPRD_DMA_SWT_MODE_OFFSET 26
102#define SPRD_DMA_REQ_MODE_OFFSET 24
103#define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0)
104#define SPRD_DMA_FIX_SEL_OFFSET 21
105#define SPRD_DMA_FIX_EN_OFFSET 20
106#define SPRD_DMA_LLIST_END_OFFSET 19
107#define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0)
108
109/* SPRD_DMA_CHN_BLK_LEN register definition */
110#define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0)
111
112/* SPRD_DMA_CHN_TRSC_LEN register definition */
113#define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0)
114
115/* SPRD_DMA_CHN_TRSF_STEP register definition */
116#define SPRD_DMA_DEST_TRSF_STEP_OFFSET 16
117#define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0
118#define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)
119
6b1d255e
EL		 120/* define the DMA transfer step type */
121#define SPRD_DMA_NONE_STEP 0
122#define SPRD_DMA_BYTE_STEP 1
123#define SPRD_DMA_SHORT_STEP 2
124#define SPRD_DMA_WORD_STEP 4
125#define SPRD_DMA_DWORD_STEP 8
126
9b3b8171
BW		 127#define SPRD_DMA_SOFTWARE_UID 0
128
d7c33cf8
BW		 129/* dma data width values */
130enum sprd_dma_datawidth {
131 SPRD_DMA_DATAWIDTH_1_BYTE,
132 SPRD_DMA_DATAWIDTH_2_BYTES,
133 SPRD_DMA_DATAWIDTH_4_BYTES,
134 SPRD_DMA_DATAWIDTH_8_BYTES,
135};
136
9b3b8171
BW		 137/* dma channel hardware configuration */
138struct sprd_dma_chn_hw {
139 u32 pause;
140 u32 req;
141 u32 cfg;
142 u32 intc;
143 u32 src_addr;
144 u32 des_addr;
145 u32 frg_len;
146 u32 blk_len;
147 u32 trsc_len;
148 u32 trsf_step;
149 u32 wrap_ptr;
150 u32 wrap_to;
151 u32 llist_ptr;
152 u32 frg_step;
153 u32 src_blk_step;
154 u32 des_blk_step;
155};
156
157/* dma request description */
158struct sprd_dma_desc {
159 struct virt_dma_desc vd;
160 struct sprd_dma_chn_hw chn_hw;
161};
162
163/* dma channel description */
164struct sprd_dma_chn {
165 struct virt_dma_chan vc;
166 void __iomem *chn_base;
167 u32 chn_num;
168 u32 dev_id;
169 struct sprd_dma_desc *cur_desc;
170};
171
172/* SPRD dma device */
173struct sprd_dma_dev {
174 struct dma_device dma_dev;
175 void __iomem *glb_base;
176 struct clk *clk;
177 struct clk *ashb_clk;
178 int irq;
179 u32 total_chns;
180 struct sprd_dma_chn channels[0];
181};
182
183static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param);
184static struct of_dma_filter_info sprd_dma_info = {
185 .filter_fn = sprd_dma_filter_fn,
186};
187
188static inline struct sprd_dma_chn *to_sprd_dma_chan(struct dma_chan *c)
189{
190 return container_of(c, struct sprd_dma_chn, vc.chan);
191}
192
193static inline struct sprd_dma_dev *to_sprd_dma_dev(struct dma_chan *c)
194{
195 struct sprd_dma_chn *schan = to_sprd_dma_chan(c);
196
197 return container_of(schan, struct sprd_dma_dev, channels[c->chan_id]);
198}
199
200static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd)
201{
202 return container_of(vd, struct sprd_dma_desc, vd);
203}
204
205static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg,
206 u32 mask, u32 val)
207{
208 u32 orig = readl(schan->chn_base + reg);
209 u32 tmp;
210
211 tmp = (orig & ~mask) | val;
212 writel(tmp, schan->chn_base + reg);
213}
214
215static int sprd_dma_enable(struct sprd_dma_dev *sdev)
216{
217 int ret;
218
219 ret = clk_prepare_enable(sdev->clk);
220 if (ret)
221 return ret;
222
223 /*
224 * The ashb_clk is optional and only for AGCP DMA controller, so we
225 * need add one condition to check if the ashb_clk need enable.
226 */
227 if (!IS_ERR(sdev->ashb_clk))
228 ret = clk_prepare_enable(sdev->ashb_clk);
229
230 return ret;
231}
232
233static void sprd_dma_disable(struct sprd_dma_dev *sdev)
234{
235 clk_disable_unprepare(sdev->clk);
236
237 /*
238 * Need to check if we need disable the optional ashb_clk for AGCP DMA.
239 */
240 if (!IS_ERR(sdev->ashb_clk))
241 clk_disable_unprepare(sdev->ashb_clk);
242}
243
244static void sprd_dma_set_uid(struct sprd_dma_chn *schan)
245{
246 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
247 u32 dev_id = schan->dev_id;
248
249 if (dev_id != SPRD_DMA_SOFTWARE_UID) {
250 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
251 SPRD_DMA_GLB_REQ_UID(dev_id);
252
253 writel(schan->chn_num + 1, sdev->glb_base + uid_offset);
254 }
255}
256
257static void sprd_dma_unset_uid(struct sprd_dma_chn *schan)
258{
259 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
260 u32 dev_id = schan->dev_id;
261
262 if (dev_id != SPRD_DMA_SOFTWARE_UID) {
263 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
264 SPRD_DMA_GLB_REQ_UID(dev_id);
265
266 writel(0, sdev->glb_base + uid_offset);
267 }
268}
269
270static void sprd_dma_clear_int(struct sprd_dma_chn *schan)
271{
272 sprd_dma_chn_update(schan, SPRD_DMA_CHN_INTC,
273 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET,
274 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET);
275}
276
277static void sprd_dma_enable_chn(struct sprd_dma_chn *schan)
278{
279 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN,
280 SPRD_DMA_CHN_EN);
281}
282
283static void sprd_dma_disable_chn(struct sprd_dma_chn *schan)
284{
285 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN, 0);
286}
287
288static void sprd_dma_soft_request(struct sprd_dma_chn *schan)
289{
290 sprd_dma_chn_update(schan, SPRD_DMA_CHN_REQ, SPRD_DMA_REQ_EN,
291 SPRD_DMA_REQ_EN);
292}
293
294static void sprd_dma_pause_resume(struct sprd_dma_chn *schan, bool enable)
295{
296 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
297 u32 pause, timeout = SPRD_DMA_PAUSE_CNT;
298
299 if (enable) {
300 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
301 SPRD_DMA_PAUSE_EN, SPRD_DMA_PAUSE_EN);
302
303 do {
304 pause = readl(schan->chn_base + SPRD_DMA_CHN_PAUSE);
305 if (pause & SPRD_DMA_PAUSE_STS)
306 break;
307
308 cpu_relax();
309 } while (--timeout > 0);
310
311 if (!timeout)
312 dev_warn(sdev->dma_dev.dev,
313 "pause dma controller timeout\n");
314 } else {
315 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
316 SPRD_DMA_PAUSE_EN, 0);
317 }
318}
319
320static void sprd_dma_stop_and_disable(struct sprd_dma_chn *schan)
321{
322 u32 cfg = readl(schan->chn_base + SPRD_DMA_CHN_CFG);
323
324 if (!(cfg & SPRD_DMA_CHN_EN))
325 return;
326
327 sprd_dma_pause_resume(schan, true);
328 sprd_dma_disable_chn(schan);
329}
330
331static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan)
332{
333 unsigned long addr, addr_high;
334
335 addr = readl(schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
336 addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_TO) &
337 SPRD_DMA_HIGH_ADDR_MASK;
338
339 return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
340}
341
342static enum sprd_dma_int_type sprd_dma_get_int_type(struct sprd_dma_chn *schan)
343{
344 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
345 u32 intc_sts = readl(schan->chn_base + SPRD_DMA_CHN_INTC) &
346 SPRD_DMA_CHN_INT_STS;
347
348 switch (intc_sts) {
349 case SPRD_DMA_CFGERR_INT_STS:
350 return SPRD_DMA_CFGERR_INT;
351
352 case SPRD_DMA_LIST_INT_STS:
353 return SPRD_DMA_LIST_INT;
354
355 case SPRD_DMA_TRSC_INT_STS:
356 return SPRD_DMA_TRANS_INT;
357
358 case SPRD_DMA_BLK_INT_STS:
359 return SPRD_DMA_BLK_INT;
360
361 case SPRD_DMA_FRAG_INT_STS:
362 return SPRD_DMA_FRAG_INT;
363
364 default:
365 dev_warn(sdev->dma_dev.dev, "incorrect dma interrupt type\n");
366 return SPRD_DMA_NO_INT;
367 }
368}
369
370static enum sprd_dma_req_mode sprd_dma_get_req_type(struct sprd_dma_chn *schan)
371{
372 u32 frag_reg = readl(schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
373
374 return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK;
375}
376
377static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan,
378 struct sprd_dma_desc *sdesc)
379{
380 struct sprd_dma_chn_hw *cfg = &sdesc->chn_hw;
381
382 writel(cfg->pause, schan->chn_base + SPRD_DMA_CHN_PAUSE);
383 writel(cfg->cfg, schan->chn_base + SPRD_DMA_CHN_CFG);
384 writel(cfg->intc, schan->chn_base + SPRD_DMA_CHN_INTC);
385 writel(cfg->src_addr, schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
386 writel(cfg->des_addr, schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
387 writel(cfg->frg_len, schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
388 writel(cfg->blk_len, schan->chn_base + SPRD_DMA_CHN_BLK_LEN);
389 writel(cfg->trsc_len, schan->chn_base + SPRD_DMA_CHN_TRSC_LEN);
390 writel(cfg->trsf_step, schan->chn_base + SPRD_DMA_CHN_TRSF_STEP);
391 writel(cfg->wrap_ptr, schan->chn_base + SPRD_DMA_CHN_WARP_PTR);
392 writel(cfg->wrap_to, schan->chn_base + SPRD_DMA_CHN_WARP_TO);
393 writel(cfg->llist_ptr, schan->chn_base + SPRD_DMA_CHN_LLIST_PTR);
394 writel(cfg->frg_step, schan->chn_base + SPRD_DMA_CHN_FRAG_STEP);
395 writel(cfg->src_blk_step, schan->chn_base + SPRD_DMA_CHN_SRC_BLK_STEP);
396 writel(cfg->des_blk_step, schan->chn_base + SPRD_DMA_CHN_DES_BLK_STEP);
397 writel(cfg->req, schan->chn_base + SPRD_DMA_CHN_REQ);
398}
399
400static void sprd_dma_start(struct sprd_dma_chn *schan)
401{
402 struct virt_dma_desc *vd = vchan_next_desc(&schan->vc);
403
404 if (!vd)
405 return;
406
407 list_del(&vd->node);
408 schan->cur_desc = to_sprd_dma_desc(vd);
409
410 /*
411 * Copy the DMA configuration from DMA descriptor to this hardware
412 * channel.
413 */
414 sprd_dma_set_chn_config(schan, schan->cur_desc);
415 sprd_dma_set_uid(schan);
416 sprd_dma_enable_chn(schan);
417
418 if (schan->dev_id == SPRD_DMA_SOFTWARE_UID)
419 sprd_dma_soft_request(schan);
420}
421
422static void sprd_dma_stop(struct sprd_dma_chn *schan)
423{
424 sprd_dma_stop_and_disable(schan);
425 sprd_dma_unset_uid(schan);
426 sprd_dma_clear_int(schan);
427}
428
429static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc,
430 enum sprd_dma_int_type int_type,
431 enum sprd_dma_req_mode req_mode)
432{
433 if (int_type == SPRD_DMA_NO_INT)
434 return false;
435
436 if (int_type >= req_mode + 1)
437 return true;
438 else
439 return false;
440}
441
442static irqreturn_t dma_irq_handle(int irq, void *dev_id)
443{
444 struct sprd_dma_dev *sdev = (struct sprd_dma_dev *)dev_id;
445 u32 irq_status = readl(sdev->glb_base + SPRD_DMA_GLB_INT_MSK_STS);
446 struct sprd_dma_chn *schan;
447 struct sprd_dma_desc *sdesc;
448 enum sprd_dma_req_mode req_type;
449 enum sprd_dma_int_type int_type;
450 bool trans_done = false;
451 u32 i;
452
453 while (irq_status) {
454 i = __ffs(irq_status);
455 irq_status &= (irq_status - 1);
456 schan = &sdev->channels[i];
457
458 spin_lock(&schan->vc.lock);
459 int_type = sprd_dma_get_int_type(schan);
460 req_type = sprd_dma_get_req_type(schan);
461 sprd_dma_clear_int(schan);
462
463 sdesc = schan->cur_desc;
464
465 /* Check if the dma request descriptor is done. */
466 trans_done = sprd_dma_check_trans_done(sdesc, int_type,
467 req_type);
468 if (trans_done == true) {
469 vchan_cookie_complete(&sdesc->vd);
470 schan->cur_desc = NULL;
471 sprd_dma_start(schan);
472 }
473 spin_unlock(&schan->vc.lock);
474 }
475
476 return IRQ_HANDLED;
477}
478
479static int sprd_dma_alloc_chan_resources(struct dma_chan *chan)
480{
481 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
482 int ret;
483
484 ret = pm_runtime_get_sync(chan->device->dev);
485 if (ret < 0)
486 return ret;
487
488 schan->dev_id = SPRD_DMA_SOFTWARE_UID;
489 return 0;
490}
491
492static void sprd_dma_free_chan_resources(struct dma_chan *chan)
493{
494 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
495 unsigned long flags;
496
497 spin_lock_irqsave(&schan->vc.lock, flags);
498 sprd_dma_stop(schan);
499 spin_unlock_irqrestore(&schan->vc.lock, flags);
500
501 vchan_free_chan_resources(&schan->vc);
502 pm_runtime_put(chan->device->dev);
503}
504
505static enum dma_status sprd_dma_tx_status(struct dma_chan *chan,
506 dma_cookie_t cookie,
507 struct dma_tx_state *txstate)
508{
509 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
510 struct virt_dma_desc *vd;
511 unsigned long flags;
512 enum dma_status ret;
513 u32 pos;
514
515 ret = dma_cookie_status(chan, cookie, txstate);
516 if (ret == DMA_COMPLETE || !txstate)
517 return ret;
518
519 spin_lock_irqsave(&schan->vc.lock, flags);
520 vd = vchan_find_desc(&schan->vc, cookie);
521 if (vd) {
522 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
523 struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
524
525 if (hw->trsc_len > 0)
526 pos = hw->trsc_len;
527 else if (hw->blk_len > 0)
528 pos = hw->blk_len;
529 else if (hw->frg_len > 0)
530 pos = hw->frg_len;
531 else
532 pos = 0;
533 } else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
534 pos = sprd_dma_get_dst_addr(schan);
535 } else {
536 pos = 0;
537 }
538 spin_unlock_irqrestore(&schan->vc.lock, flags);
539
540 dma_set_residue(txstate, pos);
541 return ret;
542}
543
544static void sprd_dma_issue_pending(struct dma_chan *chan)
545{
546 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
547 unsigned long flags;
548
549 spin_lock_irqsave(&schan->vc.lock, flags);
550 if (vchan_issue_pending(&schan->vc) && !schan->cur_desc)
551 sprd_dma_start(schan);
552 spin_unlock_irqrestore(&schan->vc.lock, flags);
553}
554
555static int sprd_dma_config(struct dma_chan *chan, struct sprd_dma_desc *sdesc,
556 dma_addr_t dest, dma_addr_t src, size_t len)
557{
558 struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
559 struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
560 u32 datawidth, src_step, des_step, fragment_len;
561 u32 block_len, req_mode, irq_mode, transcation_len;
562 u32 fix_mode = 0, fix_en = 0;
563
564 if (IS_ALIGNED(len, 4)) {
d7c33cf8 565 datawidth = SPRD_DMA_DATAWIDTH_4_BYTES;
6b1d255e
EL		 566 src_step = SPRD_DMA_WORD_STEP;
567 des_step = SPRD_DMA_WORD_STEP;
9b3b8171 568 } else if (IS_ALIGNED(len, 2)) {
d7c33cf8 569 datawidth = SPRD_DMA_DATAWIDTH_2_BYTES;
6b1d255e
EL		 570 src_step = SPRD_DMA_SHORT_STEP;
571 des_step = SPRD_DMA_SHORT_STEP;
9b3b8171 572 } else {
d7c33cf8 573 datawidth = SPRD_DMA_DATAWIDTH_1_BYTE;
6b1d255e
EL		 574 src_step = SPRD_DMA_BYTE_STEP;
575 des_step = SPRD_DMA_BYTE_STEP;
9b3b8171
BW		 576 }
577
578 fragment_len = SPRD_DMA_MEMCPY_MIN_SIZE;
579 if (len <= SPRD_DMA_BLK_LEN_MASK) {
580 block_len = len;
581 transcation_len = 0;
582 req_mode = SPRD_DMA_BLK_REQ;
583 irq_mode = SPRD_DMA_BLK_INT;
584 } else {
585 block_len = SPRD_DMA_MEMCPY_MIN_SIZE;
586 transcation_len = len;
587 req_mode = SPRD_DMA_TRANS_REQ;
588 irq_mode = SPRD_DMA_TRANS_INT;
589 }
590
591 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
592 hw->wrap_ptr = (u32)((src >> SPRD_DMA_HIGH_ADDR_OFFSET) &
593 SPRD_DMA_HIGH_ADDR_MASK);
594 hw->wrap_to = (u32)((dest >> SPRD_DMA_HIGH_ADDR_OFFSET) &
595 SPRD_DMA_HIGH_ADDR_MASK);
596
597 hw->src_addr = (u32)(src & SPRD_DMA_LOW_ADDR_MASK);
598 hw->des_addr = (u32)(dest & SPRD_DMA_LOW_ADDR_MASK);
599
600 if ((src_step != 0 && des_step != 0) || (src_step | des_step) == 0) {
601 fix_en = 0;
602 } else {
603 fix_en = 1;
604 if (src_step)
605 fix_mode = 1;
606 else
607 fix_mode = 0;
608 }
609
610 hw->frg_len = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET |
611 datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET |
612 req_mode << SPRD_DMA_REQ_MODE_OFFSET |
613 fix_mode << SPRD_DMA_FIX_SEL_OFFSET |
614 fix_en << SPRD_DMA_FIX_EN_OFFSET |
615 (fragment_len & SPRD_DMA_FRG_LEN_MASK);
616 hw->blk_len = block_len & SPRD_DMA_BLK_LEN_MASK;
617
618 hw->intc = SPRD_DMA_CFG_ERR_INT_EN;
619
620 switch (irq_mode) {
621 case SPRD_DMA_NO_INT:
622 break;
623
624 case SPRD_DMA_FRAG_INT:
625 hw->intc |= SPRD_DMA_FRAG_INT_EN;
626 break;
627
628 case SPRD_DMA_BLK_INT:
629 hw->intc |= SPRD_DMA_BLK_INT_EN;
630 break;
631
632 case SPRD_DMA_BLK_FRAG_INT:
633 hw->intc |= SPRD_DMA_BLK_INT_EN | SPRD_DMA_FRAG_INT_EN;
634 break;
635
636 case SPRD_DMA_TRANS_INT:
637 hw->intc |= SPRD_DMA_TRANS_INT_EN;
638 break;
639
640 case SPRD_DMA_TRANS_FRAG_INT:
641 hw->intc |= SPRD_DMA_TRANS_INT_EN | SPRD_DMA_FRAG_INT_EN;
642 break;
643
644 case SPRD_DMA_TRANS_BLK_INT:
645 hw->intc |= SPRD_DMA_TRANS_INT_EN | SPRD_DMA_BLK_INT_EN;
646 break;
647
648 case SPRD_DMA_LIST_INT:
649 hw->intc |= SPRD_DMA_LIST_INT_EN;
650 break;
651
652 case SPRD_DMA_CFGERR_INT:
653 hw->intc |= SPRD_DMA_CFG_ERR_INT_EN;
654 break;
655
656 default:
657 dev_err(sdev->dma_dev.dev, "invalid irq mode\n");
658 return -EINVAL;
659 }
660
661 if (transcation_len == 0)
662 hw->trsc_len = block_len & SPRD_DMA_TRSC_LEN_MASK;
663 else
664 hw->trsc_len = transcation_len & SPRD_DMA_TRSC_LEN_MASK;
665
666 hw->trsf_step = (des_step & SPRD_DMA_TRSF_STEP_MASK) <<
667 SPRD_DMA_DEST_TRSF_STEP_OFFSET |
668 (src_step & SPRD_DMA_TRSF_STEP_MASK) <<
669 SPRD_DMA_SRC_TRSF_STEP_OFFSET;
670
671 hw->frg_step = 0;
672 hw->src_blk_step = 0;
673 hw->des_blk_step = 0;
674 hw->src_blk_step = 0;
675 return 0;
676}
677
1ab8da11 678static struct dma_async_tx_descriptor *
9b3b8171
BW		 679sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
680 size_t len, unsigned long flags)
681{
682 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
683 struct sprd_dma_desc *sdesc;
684 int ret;
685
686 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
687 if (!sdesc)
688 return NULL;
689
690 ret = sprd_dma_config(chan, sdesc, dest, src, len);
691 if (ret) {
692 kfree(sdesc);
693 return NULL;
694 }
695
696 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
697}
698
699static int sprd_dma_pause(struct dma_chan *chan)
700{
701 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
702 unsigned long flags;
703
704 spin_lock_irqsave(&schan->vc.lock, flags);
705 sprd_dma_pause_resume(schan, true);
706 spin_unlock_irqrestore(&schan->vc.lock, flags);
707
708 return 0;
709}
710
711static int sprd_dma_resume(struct dma_chan *chan)
712{
713 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
714 unsigned long flags;
715
716 spin_lock_irqsave(&schan->vc.lock, flags);
717 sprd_dma_pause_resume(schan, false);
718 spin_unlock_irqrestore(&schan->vc.lock, flags);
719
720 return 0;
721}
722
723static int sprd_dma_terminate_all(struct dma_chan *chan)
724{
725 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
726 unsigned long flags;
727 LIST_HEAD(head);
728
729 spin_lock_irqsave(&schan->vc.lock, flags);
730 sprd_dma_stop(schan);
731
732 vchan_get_all_descriptors(&schan->vc, &head);
733 spin_unlock_irqrestore(&schan->vc.lock, flags);
734
735 vchan_dma_desc_free_list(&schan->vc, &head);
736 return 0;
737}
738
739static void sprd_dma_free_desc(struct virt_dma_desc *vd)
740{
741 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
742
743 kfree(sdesc);
744}
745
746static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param)
747{
748 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
749 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
750 u32 req = *(u32 *)param;
751
752 if (req < sdev->total_chns)
753 return req == schan->chn_num + 1;
754 else
755 return false;
756}
757
758static int sprd_dma_probe(struct platform_device *pdev)
759{
760 struct device_node *np = pdev->dev.of_node;
761 struct sprd_dma_dev *sdev;
762 struct sprd_dma_chn *dma_chn;
763 struct resource *res;
764 u32 chn_count;
765 int ret, i;
766
767 ret = device_property_read_u32(&pdev->dev, "#dma-channels", &chn_count);
768 if (ret) {
769 dev_err(&pdev->dev, "get dma channels count failed\n");
770 return ret;
771 }
772
773 sdev = devm_kzalloc(&pdev->dev, sizeof(*sdev) +
774 sizeof(*dma_chn) * chn_count,
775 GFP_KERNEL);
776 if (!sdev)
777 return -ENOMEM;
778
779 sdev->clk = devm_clk_get(&pdev->dev, "enable");
780 if (IS_ERR(sdev->clk)) {
781 dev_err(&pdev->dev, "get enable clock failed\n");
782 return PTR_ERR(sdev->clk);
783 }
784
785 /* ashb clock is optional for AGCP DMA */
786 sdev->ashb_clk = devm_clk_get(&pdev->dev, "ashb_eb");
787 if (IS_ERR(sdev->ashb_clk))
788 dev_warn(&pdev->dev, "no optional ashb eb clock\n");
789
790 /*
791 * We have three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
792 * DMA controller, it can or do not request the irq, which will save
793 * system power without resuming system by DMA interrupts if AGCP DMA
794 * does not request the irq. Thus the DMA interrupts property should
795 * be optional.
796 */
797 sdev->irq = platform_get_irq(pdev, 0);
798 if (sdev->irq > 0) {
799 ret = devm_request_irq(&pdev->dev, sdev->irq, dma_irq_handle,
800 0, "sprd_dma", (void *)sdev);
801 if (ret < 0) {
802 dev_err(&pdev->dev, "request dma irq failed\n");
803 return ret;
804 }
805 } else {
806 dev_warn(&pdev->dev, "no interrupts for the dma controller\n");
807 }
808
809 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e891e41e
WY		 810 if (!res)
811 return -EINVAL;
9b3b8171
BW		 812 sdev->glb_base = devm_ioremap_nocache(&pdev->dev, res->start,
813 resource_size(res));
814 if (!sdev->glb_base)
815 return -ENOMEM;
816
817 dma_cap_set(DMA_MEMCPY, sdev->dma_dev.cap_mask);
818 sdev->total_chns = chn_count;
819 sdev->dma_dev.chancnt = chn_count;
820 INIT_LIST_HEAD(&sdev->dma_dev.channels);
821 INIT_LIST_HEAD(&sdev->dma_dev.global_node);
822 sdev->dma_dev.dev = &pdev->dev;
823 sdev->dma_dev.device_alloc_chan_resources = sprd_dma_alloc_chan_resources;
824 sdev->dma_dev.device_free_chan_resources = sprd_dma_free_chan_resources;
825 sdev->dma_dev.device_tx_status = sprd_dma_tx_status;
826 sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending;
827 sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy;
828 sdev->dma_dev.device_pause = sprd_dma_pause;
829 sdev->dma_dev.device_resume = sprd_dma_resume;
830 sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all;
831
832 for (i = 0; i < chn_count; i++) {
833 dma_chn = &sdev->channels[i];
834 dma_chn->chn_num = i;
835 dma_chn->cur_desc = NULL;
836 /* get each channel's registers base address. */
837 dma_chn->chn_base = sdev->glb_base + SPRD_DMA_CHN_REG_OFFSET +
838 SPRD_DMA_CHN_REG_LENGTH * i;
839
840 dma_chn->vc.desc_free = sprd_dma_free_desc;
841 vchan_init(&dma_chn->vc, &sdev->dma_dev);
842 }
843
844 platform_set_drvdata(pdev, sdev);
845 ret = sprd_dma_enable(sdev);
846 if (ret)
847 return ret;
848
849 pm_runtime_set_active(&pdev->dev);
850 pm_runtime_enable(&pdev->dev);
851
852 ret = pm_runtime_get_sync(&pdev->dev);
853 if (ret < 0)
854 goto err_rpm;
855
856 ret = dma_async_device_register(&sdev->dma_dev);
857 if (ret < 0) {
858 dev_err(&pdev->dev, "register dma device failed:%d\n", ret);
859 goto err_register;
860 }
861
862 sprd_dma_info.dma_cap = sdev->dma_dev.cap_mask;
863 ret = of_dma_controller_register(np, of_dma_simple_xlate,
864 &sprd_dma_info);
865 if (ret)
866 goto err_of_register;
867
868 pm_runtime_put(&pdev->dev);
869 return 0;
870
871err_of_register:
872 dma_async_device_unregister(&sdev->dma_dev);
873err_register:
874 pm_runtime_put_noidle(&pdev->dev);
875 pm_runtime_disable(&pdev->dev);
876err_rpm:
877 sprd_dma_disable(sdev);
878 return ret;
879}
880
881static int sprd_dma_remove(struct platform_device *pdev)
882{
883 struct sprd_dma_dev *sdev = platform_get_drvdata(pdev);
884 struct sprd_dma_chn *c, *cn;
885 int ret;
886
887 ret = pm_runtime_get_sync(&pdev->dev);
888 if (ret < 0)
889 return ret;
890
891 /* explicitly free the irq */
892 if (sdev->irq > 0)
893 devm_free_irq(&pdev->dev, sdev->irq, sdev);
894
895 list_for_each_entry_safe(c, cn, &sdev->dma_dev.channels,
896 vc.chan.device_node) {
897 list_del(&c->vc.chan.device_node);
898 tasklet_kill(&c->vc.task);
899 }
900
901 of_dma_controller_free(pdev->dev.of_node);
902 dma_async_device_unregister(&sdev->dma_dev);
903 sprd_dma_disable(sdev);
904
905 pm_runtime_put_noidle(&pdev->dev);
906 pm_runtime_disable(&pdev->dev);
907 return 0;
908}
909
910static const struct of_device_id sprd_dma_match[] = {
911 { .compatible = "sprd,sc9860-dma", },
912 {},
913};
914
915static int __maybe_unused sprd_dma_runtime_suspend(struct device *dev)
916{
917 struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
918
919 sprd_dma_disable(sdev);
920 return 0;
921}
922
923static int __maybe_unused sprd_dma_runtime_resume(struct device *dev)
924{
925 struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
926 int ret;
927
928 ret = sprd_dma_enable(sdev);
929 if (ret)
930 dev_err(sdev->dma_dev.dev, "enable dma failed\n");
931
932 return ret;
933}
934
935static const struct dev_pm_ops sprd_dma_pm_ops = {
936 SET_RUNTIME_PM_OPS(sprd_dma_runtime_suspend,
937 sprd_dma_runtime_resume,
938 NULL)
939};
940
941static struct platform_driver sprd_dma_driver = {
942 .probe = sprd_dma_probe,
943 .remove = sprd_dma_remove,
944 .driver = {
945 .name = "sprd-dma",
946 .of_match_table = sprd_dma_match,
947 .pm = &sprd_dma_pm_ops,
948 },
949};
950module_platform_driver(sprd_dma_driver);
951
952MODULE_LICENSE("GPL v2");
953MODULE_DESCRIPTION("DMA driver for Spreadtrum");
954MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
955MODULE_ALIAS("platform:sprd-dma");
Linux 6.x block layer and io_uring tree(s)