Commit | Line | Data |
---|---|---|
d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
6 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
7 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
8 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
9 | * | |
10 | * This is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
16 | * - MAX DMA size is 16MB. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
d8902adc NI |
23 | #include <linux/interrupt.h> |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/dma-mapping.h> | |
d8902adc | 27 | #include <linux/platform_device.h> |
20f2a3b5 | 28 | #include <linux/pm_runtime.h> |
b2623a61 | 29 | #include <linux/sh_dma.h> |
03aa18f5 PM |
30 | #include <linux/notifier.h> |
31 | #include <linux/kdebug.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/rculist.h> | |
d8902adc NI |
34 | #include "shdma.h" |
35 | ||
36 | /* DMA descriptor control */ | |
3542a113 GL |
37 | enum sh_dmae_desc_status { |
38 | DESC_IDLE, | |
39 | DESC_PREPARED, | |
40 | DESC_SUBMITTED, | |
41 | DESC_COMPLETED, /* completed, have to call callback */ | |
42 | DESC_WAITING, /* callback called, waiting for ack / re-submit */ | |
43 | }; | |
d8902adc NI |
44 | |
45 | #define NR_DESCS_PER_CHANNEL 32 | |
8b1935e6 GL |
46 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
47 | #define LOG2_DEFAULT_XFER_SIZE 2 | |
d8902adc | 48 | |
03aa18f5 PM |
49 | /* |
50 | * Used for write-side mutual exclusion for the global device list, | |
2dc66667 | 51 | * read-side synchronization by way of RCU, and per-controller data. |
03aa18f5 PM |
52 | */ |
53 | static DEFINE_SPINLOCK(sh_dmae_lock); | |
54 | static LIST_HEAD(sh_dmae_devices); | |
55 | ||
cfefe997 | 56 | /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */ |
02ca5083 | 57 | static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)]; |
cfefe997 | 58 | |
3542a113 GL |
59 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all); |
60 | ||
d8902adc NI |
61 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
62 | { | |
027811b9 | 63 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); |
d8902adc NI |
64 | } |
65 | ||
66 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
67 | { | |
027811b9 GL |
68 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); |
69 | } | |
70 | ||
71 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
72 | { | |
73 | return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32)); | |
74 | } | |
75 | ||
76 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
77 | { | |
78 | __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); | |
d8902adc NI |
79 | } |
80 | ||
d8902adc NI |
81 | /* |
82 | * Reset DMA controller | |
83 | * | |
84 | * SH7780 has two DMAOR register | |
85 | */ | |
027811b9 | 86 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 87 | { |
2dc66667 GL |
88 | unsigned short dmaor; |
89 | unsigned long flags; | |
90 | ||
91 | spin_lock_irqsave(&sh_dmae_lock, flags); | |
d8902adc | 92 | |
2dc66667 | 93 | dmaor = dmaor_read(shdev); |
027811b9 | 94 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
2dc66667 GL |
95 | |
96 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
d8902adc NI |
97 | } |
98 | ||
027811b9 | 99 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
100 | { |
101 | unsigned short dmaor; | |
2dc66667 | 102 | unsigned long flags; |
d8902adc | 103 | |
2dc66667 | 104 | spin_lock_irqsave(&sh_dmae_lock, flags); |
d8902adc | 105 | |
2dc66667 GL |
106 | dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); |
107 | ||
108 | dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init); | |
109 | ||
110 | dmaor = dmaor_read(shdev); | |
111 | ||
112 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
113 | ||
114 | if (dmaor & (DMAOR_AE | DMAOR_NMIF)) { | |
115 | dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n"); | |
116 | return -EIO; | |
d8902adc NI |
117 | } |
118 | return 0; | |
119 | } | |
120 | ||
fc461857 | 121 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc NI |
122 | { |
123 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
fc461857 GL |
124 | |
125 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
126 | return true; /* working */ | |
127 | ||
128 | return false; /* waiting */ | |
d8902adc NI |
129 | } |
130 | ||
8b1935e6 | 131 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
d8902adc | 132 | { |
c4e0dd78 | 133 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
8b1935e6 GL |
134 | struct sh_dmae_pdata *pdata = shdev->pdata; |
135 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | | |
136 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | |
137 | ||
138 | if (cnt >= pdata->ts_shift_num) | |
139 | cnt = 0; | |
623b4ac4 | 140 | |
8b1935e6 GL |
141 | return pdata->ts_shift[cnt]; |
142 | } | |
143 | ||
144 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | |
145 | { | |
c4e0dd78 | 146 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
8b1935e6 GL |
147 | struct sh_dmae_pdata *pdata = shdev->pdata; |
148 | int i; | |
149 | ||
150 | for (i = 0; i < pdata->ts_shift_num; i++) | |
151 | if (pdata->ts_shift[i] == l2size) | |
152 | break; | |
153 | ||
154 | if (i == pdata->ts_shift_num) | |
155 | i = 0; | |
156 | ||
157 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | |
158 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | |
d8902adc NI |
159 | } |
160 | ||
3542a113 | 161 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 162 | { |
3542a113 GL |
163 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
164 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 165 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
166 | } |
167 | ||
168 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
169 | { | |
170 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
171 | ||
86d61b33 | 172 | chcr |= CHCR_DE | CHCR_IE; |
cfefe997 | 173 | sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR); |
d8902adc NI |
174 | } |
175 | ||
176 | static void dmae_halt(struct sh_dmae_chan *sh_chan) | |
177 | { | |
178 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
179 | ||
180 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | |
181 | sh_dmae_writel(sh_chan, chcr, CHCR); | |
182 | } | |
183 | ||
cfefe997 GL |
184 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
185 | { | |
8b1935e6 GL |
186 | /* |
187 | * Default configuration for dual address memory-memory transfer. | |
188 | * 0x400 represents auto-request. | |
189 | */ | |
190 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | |
191 | LOG2_DEFAULT_XFER_SIZE); | |
192 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | |
cfefe997 GL |
193 | sh_dmae_writel(sh_chan, chcr, CHCR); |
194 | } | |
195 | ||
d8902adc NI |
196 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
197 | { | |
2dc66667 | 198 | /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ |
fc461857 GL |
199 | if (dmae_is_busy(sh_chan)) |
200 | return -EBUSY; | |
d8902adc | 201 | |
8b1935e6 | 202 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
d8902adc | 203 | sh_dmae_writel(sh_chan, val, CHCR); |
cfefe997 | 204 | |
d8902adc NI |
205 | return 0; |
206 | } | |
207 | ||
d8902adc NI |
208 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
209 | { | |
c4e0dd78 | 210 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
027811b9 | 211 | struct sh_dmae_pdata *pdata = shdev->pdata; |
5bac942d | 212 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id]; |
26fc02ab | 213 | u16 __iomem *addr = shdev->dmars; |
027811b9 | 214 | int shift = chan_pdata->dmars_bit; |
fc461857 GL |
215 | |
216 | if (dmae_is_busy(sh_chan)) | |
217 | return -EBUSY; | |
d8902adc | 218 | |
26fc02ab MD |
219 | /* in the case of a missing DMARS resource use first memory window */ |
220 | if (!addr) | |
221 | addr = (u16 __iomem *)shdev->chan_reg; | |
222 | addr += chan_pdata->dmars / sizeof(u16); | |
223 | ||
027811b9 GL |
224 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
225 | addr); | |
d8902adc NI |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx) | |
231 | { | |
3542a113 | 232 | struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c; |
d8902adc | 233 | struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan); |
3542a113 | 234 | dma_async_tx_callback callback = tx->callback; |
d8902adc NI |
235 | dma_cookie_t cookie; |
236 | ||
237 | spin_lock_bh(&sh_chan->desc_lock); | |
238 | ||
239 | cookie = sh_chan->common.cookie; | |
240 | cookie++; | |
241 | if (cookie < 0) | |
242 | cookie = 1; | |
243 | ||
3542a113 GL |
244 | sh_chan->common.cookie = cookie; |
245 | tx->cookie = cookie; | |
246 | ||
247 | /* Mark all chunks of this descriptor as submitted, move to the queue */ | |
248 | list_for_each_entry_safe(chunk, c, desc->node.prev, node) { | |
249 | /* | |
250 | * All chunks are on the global ld_free, so, we have to find | |
251 | * the end of the chain ourselves | |
252 | */ | |
253 | if (chunk != desc && (chunk->mark == DESC_IDLE || | |
254 | chunk->async_tx.cookie > 0 || | |
255 | chunk->async_tx.cookie == -EBUSY || | |
256 | &chunk->node == &sh_chan->ld_free)) | |
257 | break; | |
258 | chunk->mark = DESC_SUBMITTED; | |
259 | /* Callback goes to the last chunk */ | |
260 | chunk->async_tx.callback = NULL; | |
261 | chunk->cookie = cookie; | |
262 | list_move_tail(&chunk->node, &sh_chan->ld_queue); | |
263 | last = chunk; | |
264 | } | |
d8902adc | 265 | |
3542a113 GL |
266 | last->async_tx.callback = callback; |
267 | last->async_tx.callback_param = tx->callback_param; | |
268 | ||
269 | dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n", | |
270 | tx->cookie, &last->async_tx, sh_chan->id, | |
271 | desc->hw.sar, desc->hw.tcr, desc->hw.dar); | |
d8902adc NI |
272 | |
273 | spin_unlock_bh(&sh_chan->desc_lock); | |
274 | ||
275 | return cookie; | |
276 | } | |
277 | ||
3542a113 | 278 | /* Called with desc_lock held */ |
d8902adc NI |
279 | static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan) |
280 | { | |
3542a113 | 281 | struct sh_desc *desc; |
d8902adc | 282 | |
3542a113 GL |
283 | list_for_each_entry(desc, &sh_chan->ld_free, node) |
284 | if (desc->mark != DESC_PREPARED) { | |
285 | BUG_ON(desc->mark != DESC_IDLE); | |
d8902adc | 286 | list_del(&desc->node); |
3542a113 | 287 | return desc; |
d8902adc | 288 | } |
d8902adc | 289 | |
3542a113 | 290 | return NULL; |
d8902adc NI |
291 | } |
292 | ||
5bac942d | 293 | static const struct sh_dmae_slave_config *sh_dmae_find_slave( |
4bab9d42 | 294 | struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param) |
cfefe997 | 295 | { |
c4e0dd78 | 296 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
027811b9 | 297 | struct sh_dmae_pdata *pdata = shdev->pdata; |
cfefe997 GL |
298 | int i; |
299 | ||
02ca5083 | 300 | if (param->slave_id >= SH_DMA_SLAVE_NUMBER) |
cfefe997 GL |
301 | return NULL; |
302 | ||
027811b9 | 303 | for (i = 0; i < pdata->slave_num; i++) |
4bab9d42 | 304 | if (pdata->slave[i].slave_id == param->slave_id) |
027811b9 | 305 | return pdata->slave + i; |
cfefe997 GL |
306 | |
307 | return NULL; | |
308 | } | |
309 | ||
d8902adc NI |
310 | static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) |
311 | { | |
312 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
313 | struct sh_desc *desc; | |
cfefe997 | 314 | struct sh_dmae_slave *param = chan->private; |
83515bc7 | 315 | int ret; |
cfefe997 | 316 | |
20f2a3b5 GL |
317 | pm_runtime_get_sync(sh_chan->dev); |
318 | ||
cfefe997 GL |
319 | /* |
320 | * This relies on the guarantee from dmaengine that alloc_chan_resources | |
321 | * never runs concurrently with itself or free_chan_resources. | |
322 | */ | |
323 | if (param) { | |
5bac942d | 324 | const struct sh_dmae_slave_config *cfg; |
cfefe997 | 325 | |
4bab9d42 | 326 | cfg = sh_dmae_find_slave(sh_chan, param); |
83515bc7 GL |
327 | if (!cfg) { |
328 | ret = -EINVAL; | |
329 | goto efindslave; | |
330 | } | |
cfefe997 | 331 | |
83515bc7 GL |
332 | if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) { |
333 | ret = -EBUSY; | |
334 | goto etestused; | |
335 | } | |
cfefe997 GL |
336 | |
337 | param->config = cfg; | |
338 | ||
339 | dmae_set_dmars(sh_chan, cfg->mid_rid); | |
340 | dmae_set_chcr(sh_chan, cfg->chcr); | |
a1b2cc50 | 341 | } else { |
8b1935e6 | 342 | dmae_init(sh_chan); |
cfefe997 | 343 | } |
d8902adc NI |
344 | |
345 | spin_lock_bh(&sh_chan->desc_lock); | |
346 | while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
347 | spin_unlock_bh(&sh_chan->desc_lock); | |
348 | desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL); | |
349 | if (!desc) { | |
350 | spin_lock_bh(&sh_chan->desc_lock); | |
351 | break; | |
352 | } | |
353 | dma_async_tx_descriptor_init(&desc->async_tx, | |
354 | &sh_chan->common); | |
355 | desc->async_tx.tx_submit = sh_dmae_tx_submit; | |
3542a113 | 356 | desc->mark = DESC_IDLE; |
d8902adc NI |
357 | |
358 | spin_lock_bh(&sh_chan->desc_lock); | |
3542a113 | 359 | list_add(&desc->node, &sh_chan->ld_free); |
d8902adc NI |
360 | sh_chan->descs_allocated++; |
361 | } | |
362 | spin_unlock_bh(&sh_chan->desc_lock); | |
363 | ||
83515bc7 GL |
364 | if (!sh_chan->descs_allocated) { |
365 | ret = -ENOMEM; | |
366 | goto edescalloc; | |
367 | } | |
20f2a3b5 | 368 | |
d8902adc | 369 | return sh_chan->descs_allocated; |
83515bc7 GL |
370 | |
371 | edescalloc: | |
372 | if (param) | |
373 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
374 | etestused: | |
375 | efindslave: | |
376 | pm_runtime_put(sh_chan->dev); | |
377 | return ret; | |
d8902adc NI |
378 | } |
379 | ||
380 | /* | |
381 | * sh_dma_free_chan_resources - Free all resources of the channel. | |
382 | */ | |
383 | static void sh_dmae_free_chan_resources(struct dma_chan *chan) | |
384 | { | |
385 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
386 | struct sh_desc *desc, *_desc; | |
387 | LIST_HEAD(list); | |
20f2a3b5 | 388 | int descs = sh_chan->descs_allocated; |
d8902adc | 389 | |
2dc66667 GL |
390 | /* Protect against ISR */ |
391 | spin_lock_irq(&sh_chan->desc_lock); | |
cfefe997 | 392 | dmae_halt(sh_chan); |
2dc66667 GL |
393 | spin_unlock_irq(&sh_chan->desc_lock); |
394 | ||
395 | /* Now no new interrupts will occur */ | |
cfefe997 | 396 | |
3542a113 GL |
397 | /* Prepared and not submitted descriptors can still be on the queue */ |
398 | if (!list_empty(&sh_chan->ld_queue)) | |
399 | sh_dmae_chan_ld_cleanup(sh_chan, true); | |
400 | ||
cfefe997 GL |
401 | if (chan->private) { |
402 | /* The caller is holding dma_list_mutex */ | |
403 | struct sh_dmae_slave *param = chan->private; | |
404 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
2dc66667 | 405 | chan->private = NULL; |
cfefe997 GL |
406 | } |
407 | ||
d8902adc NI |
408 | spin_lock_bh(&sh_chan->desc_lock); |
409 | ||
410 | list_splice_init(&sh_chan->ld_free, &list); | |
411 | sh_chan->descs_allocated = 0; | |
412 | ||
413 | spin_unlock_bh(&sh_chan->desc_lock); | |
414 | ||
20f2a3b5 GL |
415 | if (descs > 0) |
416 | pm_runtime_put(sh_chan->dev); | |
417 | ||
d8902adc NI |
418 | list_for_each_entry_safe(desc, _desc, &list, node) |
419 | kfree(desc); | |
420 | } | |
421 | ||
cfefe997 | 422 | /** |
fc461857 GL |
423 | * sh_dmae_add_desc - get, set up and return one transfer descriptor |
424 | * @sh_chan: DMA channel | |
425 | * @flags: DMA transfer flags | |
426 | * @dest: destination DMA address, incremented when direction equals | |
427 | * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL | |
428 | * @src: source DMA address, incremented when direction equals | |
429 | * DMA_TO_DEVICE or DMA_BIDIRECTIONAL | |
430 | * @len: DMA transfer length | |
431 | * @first: if NULL, set to the current descriptor and cookie set to -EBUSY | |
432 | * @direction: needed for slave DMA to decide which address to keep constant, | |
433 | * equals DMA_BIDIRECTIONAL for MEMCPY | |
434 | * Returns 0 or an error | |
435 | * Locks: called with desc_lock held | |
436 | */ | |
437 | static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan, | |
438 | unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len, | |
439 | struct sh_desc **first, enum dma_data_direction direction) | |
d8902adc | 440 | { |
fc461857 | 441 | struct sh_desc *new; |
d8902adc NI |
442 | size_t copy_size; |
443 | ||
fc461857 | 444 | if (!*len) |
d8902adc NI |
445 | return NULL; |
446 | ||
fc461857 GL |
447 | /* Allocate the link descriptor from the free list */ |
448 | new = sh_dmae_get_desc(sh_chan); | |
449 | if (!new) { | |
450 | dev_err(sh_chan->dev, "No free link descriptor available\n"); | |
d8902adc | 451 | return NULL; |
fc461857 | 452 | } |
d8902adc | 453 | |
fc461857 GL |
454 | copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1); |
455 | ||
456 | new->hw.sar = *src; | |
457 | new->hw.dar = *dest; | |
458 | new->hw.tcr = copy_size; | |
459 | ||
460 | if (!*first) { | |
461 | /* First desc */ | |
462 | new->async_tx.cookie = -EBUSY; | |
463 | *first = new; | |
464 | } else { | |
465 | /* Other desc - invisible to the user */ | |
466 | new->async_tx.cookie = -EINVAL; | |
467 | } | |
468 | ||
cfefe997 GL |
469 | dev_dbg(sh_chan->dev, |
470 | "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n", | |
fc461857 | 471 | copy_size, *len, *src, *dest, &new->async_tx, |
cfefe997 | 472 | new->async_tx.cookie, sh_chan->xmit_shift); |
fc461857 GL |
473 | |
474 | new->mark = DESC_PREPARED; | |
475 | new->async_tx.flags = flags; | |
cfefe997 | 476 | new->direction = direction; |
fc461857 GL |
477 | |
478 | *len -= copy_size; | |
479 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE) | |
480 | *src += copy_size; | |
481 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE) | |
482 | *dest += copy_size; | |
483 | ||
484 | return new; | |
485 | } | |
486 | ||
487 | /* | |
488 | * sh_dmae_prep_sg - prepare transfer descriptors from an SG list | |
489 | * | |
490 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
491 | * converted to scatter-gather to guarantee consistent locking and a correct | |
492 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
493 | * logically, the SG list is RAM and the addr variable contains slave address, | |
494 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL | |
495 | * and the SG list contains only one element and points at the source buffer. | |
496 | */ | |
497 | static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan, | |
498 | struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, | |
499 | enum dma_data_direction direction, unsigned long flags) | |
500 | { | |
501 | struct scatterlist *sg; | |
502 | struct sh_desc *first = NULL, *new = NULL /* compiler... */; | |
503 | LIST_HEAD(tx_list); | |
504 | int chunks = 0; | |
505 | int i; | |
506 | ||
507 | if (!sg_len) | |
508 | return NULL; | |
509 | ||
510 | for_each_sg(sgl, sg, sg_len, i) | |
511 | chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) / | |
512 | (SH_DMA_TCR_MAX + 1); | |
d8902adc | 513 | |
3542a113 GL |
514 | /* Have to lock the whole loop to protect against concurrent release */ |
515 | spin_lock_bh(&sh_chan->desc_lock); | |
516 | ||
517 | /* | |
518 | * Chaining: | |
519 | * first descriptor is what user is dealing with in all API calls, its | |
520 | * cookie is at first set to -EBUSY, at tx-submit to a positive | |
521 | * number | |
522 | * if more than one chunk is needed further chunks have cookie = -EINVAL | |
523 | * the last chunk, if not equal to the first, has cookie = -ENOSPC | |
524 | * all chunks are linked onto the tx_list head with their .node heads | |
525 | * only during this function, then they are immediately spliced | |
526 | * back onto the free list in form of a chain | |
527 | */ | |
fc461857 GL |
528 | for_each_sg(sgl, sg, sg_len, i) { |
529 | dma_addr_t sg_addr = sg_dma_address(sg); | |
530 | size_t len = sg_dma_len(sg); | |
531 | ||
532 | if (!len) | |
533 | goto err_get_desc; | |
534 | ||
535 | do { | |
536 | dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n", | |
537 | i, sg, len, (unsigned long long)sg_addr); | |
538 | ||
539 | if (direction == DMA_FROM_DEVICE) | |
540 | new = sh_dmae_add_desc(sh_chan, flags, | |
541 | &sg_addr, addr, &len, &first, | |
542 | direction); | |
543 | else | |
544 | new = sh_dmae_add_desc(sh_chan, flags, | |
545 | addr, &sg_addr, &len, &first, | |
546 | direction); | |
547 | if (!new) | |
548 | goto err_get_desc; | |
549 | ||
550 | new->chunks = chunks--; | |
551 | list_add_tail(&new->node, &tx_list); | |
552 | } while (len); | |
553 | } | |
d8902adc | 554 | |
3542a113 GL |
555 | if (new != first) |
556 | new->async_tx.cookie = -ENOSPC; | |
d8902adc | 557 | |
3542a113 GL |
558 | /* Put them back on the free list, so, they don't get lost */ |
559 | list_splice_tail(&tx_list, &sh_chan->ld_free); | |
d8902adc | 560 | |
3542a113 | 561 | spin_unlock_bh(&sh_chan->desc_lock); |
d8902adc | 562 | |
3542a113 | 563 | return &first->async_tx; |
fc461857 GL |
564 | |
565 | err_get_desc: | |
566 | list_for_each_entry(new, &tx_list, node) | |
567 | new->mark = DESC_IDLE; | |
568 | list_splice(&tx_list, &sh_chan->ld_free); | |
569 | ||
570 | spin_unlock_bh(&sh_chan->desc_lock); | |
571 | ||
572 | return NULL; | |
573 | } | |
574 | ||
575 | static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy( | |
576 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, | |
577 | size_t len, unsigned long flags) | |
578 | { | |
579 | struct sh_dmae_chan *sh_chan; | |
580 | struct scatterlist sg; | |
581 | ||
582 | if (!chan || !len) | |
583 | return NULL; | |
584 | ||
585 | sh_chan = to_sh_chan(chan); | |
586 | ||
587 | sg_init_table(&sg, 1); | |
588 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len, | |
589 | offset_in_page(dma_src)); | |
590 | sg_dma_address(&sg) = dma_src; | |
591 | sg_dma_len(&sg) = len; | |
592 | ||
593 | return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL, | |
594 | flags); | |
d8902adc NI |
595 | } |
596 | ||
cfefe997 GL |
597 | static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg( |
598 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
599 | enum dma_data_direction direction, unsigned long flags) | |
600 | { | |
601 | struct sh_dmae_slave *param; | |
602 | struct sh_dmae_chan *sh_chan; | |
5bac942d | 603 | dma_addr_t slave_addr; |
cfefe997 GL |
604 | |
605 | if (!chan) | |
606 | return NULL; | |
607 | ||
608 | sh_chan = to_sh_chan(chan); | |
609 | param = chan->private; | |
610 | ||
611 | /* Someone calling slave DMA on a public channel? */ | |
612 | if (!param || !sg_len) { | |
613 | dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n", | |
614 | __func__, param, sg_len, param ? param->slave_id : -1); | |
615 | return NULL; | |
616 | } | |
617 | ||
9f9ff20d DC |
618 | slave_addr = param->config->addr; |
619 | ||
cfefe997 GL |
620 | /* |
621 | * if (param != NULL), this is a successfully requested slave channel, | |
622 | * therefore param->config != NULL too. | |
623 | */ | |
5bac942d | 624 | return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr, |
cfefe997 GL |
625 | direction, flags); |
626 | } | |
627 | ||
05827630 LW |
628 | static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
629 | unsigned long arg) | |
cfefe997 GL |
630 | { |
631 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
632 | ||
c3635c78 LW |
633 | /* Only supports DMA_TERMINATE_ALL */ |
634 | if (cmd != DMA_TERMINATE_ALL) | |
635 | return -ENXIO; | |
636 | ||
cfefe997 | 637 | if (!chan) |
c3635c78 | 638 | return -EINVAL; |
cfefe997 | 639 | |
2dc66667 | 640 | spin_lock_bh(&sh_chan->desc_lock); |
c014906a GL |
641 | dmae_halt(sh_chan); |
642 | ||
c014906a GL |
643 | if (!list_empty(&sh_chan->ld_queue)) { |
644 | /* Record partial transfer */ | |
645 | struct sh_desc *desc = list_entry(sh_chan->ld_queue.next, | |
646 | struct sh_desc, node); | |
647 | desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) << | |
648 | sh_chan->xmit_shift; | |
649 | ||
650 | } | |
651 | spin_unlock_bh(&sh_chan->desc_lock); | |
652 | ||
cfefe997 | 653 | sh_dmae_chan_ld_cleanup(sh_chan, true); |
c3635c78 LW |
654 | |
655 | return 0; | |
cfefe997 GL |
656 | } |
657 | ||
3542a113 | 658 | static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) |
d8902adc NI |
659 | { |
660 | struct sh_desc *desc, *_desc; | |
3542a113 GL |
661 | /* Is the "exposed" head of a chain acked? */ |
662 | bool head_acked = false; | |
663 | dma_cookie_t cookie = 0; | |
664 | dma_async_tx_callback callback = NULL; | |
665 | void *param = NULL; | |
d8902adc NI |
666 | |
667 | spin_lock_bh(&sh_chan->desc_lock); | |
668 | list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) { | |
3542a113 GL |
669 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
670 | ||
671 | BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie); | |
672 | BUG_ON(desc->mark != DESC_SUBMITTED && | |
673 | desc->mark != DESC_COMPLETED && | |
674 | desc->mark != DESC_WAITING); | |
675 | ||
676 | /* | |
677 | * queue is ordered, and we use this loop to (1) clean up all | |
678 | * completed descriptors, and to (2) update descriptor flags of | |
679 | * any chunks in a (partially) completed chain | |
680 | */ | |
681 | if (!all && desc->mark == DESC_SUBMITTED && | |
682 | desc->cookie != cookie) | |
d8902adc NI |
683 | break; |
684 | ||
3542a113 GL |
685 | if (tx->cookie > 0) |
686 | cookie = tx->cookie; | |
d8902adc | 687 | |
3542a113 | 688 | if (desc->mark == DESC_COMPLETED && desc->chunks == 1) { |
cfefe997 GL |
689 | if (sh_chan->completed_cookie != desc->cookie - 1) |
690 | dev_dbg(sh_chan->dev, | |
691 | "Completing cookie %d, expected %d\n", | |
692 | desc->cookie, | |
693 | sh_chan->completed_cookie + 1); | |
3542a113 GL |
694 | sh_chan->completed_cookie = desc->cookie; |
695 | } | |
d8902adc | 696 | |
3542a113 GL |
697 | /* Call callback on the last chunk */ |
698 | if (desc->mark == DESC_COMPLETED && tx->callback) { | |
699 | desc->mark = DESC_WAITING; | |
700 | callback = tx->callback; | |
701 | param = tx->callback_param; | |
702 | dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n", | |
703 | tx->cookie, tx, sh_chan->id); | |
704 | BUG_ON(desc->chunks != 1); | |
705 | break; | |
706 | } | |
d8902adc | 707 | |
3542a113 GL |
708 | if (tx->cookie > 0 || tx->cookie == -EBUSY) { |
709 | if (desc->mark == DESC_COMPLETED) { | |
710 | BUG_ON(tx->cookie < 0); | |
711 | desc->mark = DESC_WAITING; | |
712 | } | |
713 | head_acked = async_tx_test_ack(tx); | |
714 | } else { | |
715 | switch (desc->mark) { | |
716 | case DESC_COMPLETED: | |
717 | desc->mark = DESC_WAITING; | |
718 | /* Fall through */ | |
719 | case DESC_WAITING: | |
720 | if (head_acked) | |
721 | async_tx_ack(&desc->async_tx); | |
722 | } | |
723 | } | |
724 | ||
725 | dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n", | |
726 | tx, tx->cookie); | |
727 | ||
728 | if (((desc->mark == DESC_COMPLETED || | |
729 | desc->mark == DESC_WAITING) && | |
730 | async_tx_test_ack(&desc->async_tx)) || all) { | |
731 | /* Remove from ld_queue list */ | |
732 | desc->mark = DESC_IDLE; | |
733 | list_move(&desc->node, &sh_chan->ld_free); | |
d8902adc NI |
734 | } |
735 | } | |
2dc66667 GL |
736 | |
737 | if (all && !callback) | |
738 | /* | |
739 | * Terminating and the loop completed normally: forgive | |
740 | * uncompleted cookies | |
741 | */ | |
742 | sh_chan->completed_cookie = sh_chan->common.cookie; | |
743 | ||
d8902adc | 744 | spin_unlock_bh(&sh_chan->desc_lock); |
3542a113 GL |
745 | |
746 | if (callback) | |
747 | callback(param); | |
748 | ||
749 | return callback; | |
750 | } | |
751 | ||
752 | /* | |
753 | * sh_chan_ld_cleanup - Clean up link descriptors | |
754 | * | |
755 | * This function cleans up the ld_queue of DMA channel. | |
756 | */ | |
757 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) | |
758 | { | |
759 | while (__ld_cleanup(sh_chan, all)) | |
760 | ; | |
d8902adc NI |
761 | } |
762 | ||
763 | static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) | |
764 | { | |
47a4dc26 | 765 | struct sh_desc *desc; |
d8902adc | 766 | |
3542a113 | 767 | spin_lock_bh(&sh_chan->desc_lock); |
d8902adc | 768 | /* DMA work check */ |
3542a113 GL |
769 | if (dmae_is_busy(sh_chan)) { |
770 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc | 771 | return; |
3542a113 | 772 | } |
d8902adc | 773 | |
5a3a7658 | 774 | /* Find the first not transferred descriptor */ |
47a4dc26 GL |
775 | list_for_each_entry(desc, &sh_chan->ld_queue, node) |
776 | if (desc->mark == DESC_SUBMITTED) { | |
c014906a GL |
777 | dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n", |
778 | desc->async_tx.cookie, sh_chan->id, | |
779 | desc->hw.tcr, desc->hw.sar, desc->hw.dar); | |
3542a113 | 780 | /* Get the ld start address from ld_queue */ |
47a4dc26 | 781 | dmae_set_reg(sh_chan, &desc->hw); |
3542a113 GL |
782 | dmae_start(sh_chan); |
783 | break; | |
784 | } | |
785 | ||
786 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc NI |
787 | } |
788 | ||
789 | static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan) | |
790 | { | |
791 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
792 | sh_chan_xfer_ld_queue(sh_chan); | |
793 | } | |
794 | ||
07934481 | 795 | static enum dma_status sh_dmae_tx_status(struct dma_chan *chan, |
d8902adc | 796 | dma_cookie_t cookie, |
07934481 | 797 | struct dma_tx_state *txstate) |
d8902adc NI |
798 | { |
799 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
800 | dma_cookie_t last_used; | |
801 | dma_cookie_t last_complete; | |
47a4dc26 | 802 | enum dma_status status; |
d8902adc | 803 | |
3542a113 | 804 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc | 805 | |
2dc66667 | 806 | /* First read completed cookie to avoid a skew */ |
d8902adc | 807 | last_complete = sh_chan->completed_cookie; |
2dc66667 GL |
808 | rmb(); |
809 | last_used = chan->cookie; | |
3542a113 | 810 | BUG_ON(last_complete < 0); |
bca34692 | 811 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
d8902adc | 812 | |
47a4dc26 GL |
813 | spin_lock_bh(&sh_chan->desc_lock); |
814 | ||
815 | status = dma_async_is_complete(cookie, last_complete, last_used); | |
816 | ||
817 | /* | |
818 | * If we don't find cookie on the queue, it has been aborted and we have | |
819 | * to report error | |
820 | */ | |
821 | if (status != DMA_SUCCESS) { | |
822 | struct sh_desc *desc; | |
823 | status = DMA_ERROR; | |
824 | list_for_each_entry(desc, &sh_chan->ld_queue, node) | |
825 | if (desc->cookie == cookie) { | |
826 | status = DMA_IN_PROGRESS; | |
827 | break; | |
828 | } | |
829 | } | |
830 | ||
831 | spin_unlock_bh(&sh_chan->desc_lock); | |
832 | ||
833 | return status; | |
d8902adc NI |
834 | } |
835 | ||
836 | static irqreturn_t sh_dmae_interrupt(int irq, void *data) | |
837 | { | |
838 | irqreturn_t ret = IRQ_NONE; | |
2dc66667 GL |
839 | struct sh_dmae_chan *sh_chan = data; |
840 | u32 chcr; | |
841 | ||
842 | spin_lock(&sh_chan->desc_lock); | |
843 | ||
844 | chcr = sh_dmae_readl(sh_chan, CHCR); | |
d8902adc NI |
845 | |
846 | if (chcr & CHCR_TE) { | |
847 | /* DMA stop */ | |
848 | dmae_halt(sh_chan); | |
849 | ||
850 | ret = IRQ_HANDLED; | |
851 | tasklet_schedule(&sh_chan->tasklet); | |
852 | } | |
853 | ||
2dc66667 GL |
854 | spin_unlock(&sh_chan->desc_lock); |
855 | ||
d8902adc NI |
856 | return ret; |
857 | } | |
858 | ||
2dc66667 GL |
859 | /* Called from error IRQ or NMI */ |
860 | static bool sh_dmae_reset(struct sh_dmae_device *shdev) | |
d8902adc | 861 | { |
03aa18f5 | 862 | unsigned int handled = 0; |
47a4dc26 | 863 | int i; |
d8902adc | 864 | |
47a4dc26 | 865 | /* halt the dma controller */ |
027811b9 | 866 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
867 | |
868 | /* We cannot detect, which channel caused the error, have to reset all */ | |
8b1935e6 | 869 | for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) { |
47a4dc26 | 870 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
03aa18f5 | 871 | struct sh_desc *desc; |
2dc66667 | 872 | LIST_HEAD(dl); |
03aa18f5 PM |
873 | |
874 | if (!sh_chan) | |
875 | continue; | |
876 | ||
2dc66667 GL |
877 | spin_lock(&sh_chan->desc_lock); |
878 | ||
03aa18f5 PM |
879 | /* Stop the channel */ |
880 | dmae_halt(sh_chan); | |
881 | ||
2dc66667 GL |
882 | list_splice_init(&sh_chan->ld_queue, &dl); |
883 | ||
884 | spin_unlock(&sh_chan->desc_lock); | |
885 | ||
03aa18f5 | 886 | /* Complete all */ |
2dc66667 | 887 | list_for_each_entry(desc, &dl, node) { |
03aa18f5 PM |
888 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
889 | desc->mark = DESC_IDLE; | |
890 | if (tx->callback) | |
891 | tx->callback(tx->callback_param); | |
d8902adc | 892 | } |
03aa18f5 | 893 | |
2dc66667 GL |
894 | spin_lock(&sh_chan->desc_lock); |
895 | list_splice(&dl, &sh_chan->ld_free); | |
896 | spin_unlock(&sh_chan->desc_lock); | |
897 | ||
03aa18f5 | 898 | handled++; |
d8902adc | 899 | } |
03aa18f5 | 900 | |
027811b9 | 901 | sh_dmae_rst(shdev); |
47a4dc26 | 902 | |
03aa18f5 PM |
903 | return !!handled; |
904 | } | |
905 | ||
906 | static irqreturn_t sh_dmae_err(int irq, void *data) | |
907 | { | |
ff7690b4 YS |
908 | struct sh_dmae_device *shdev = data; |
909 | ||
2dc66667 | 910 | if (!(dmaor_read(shdev) & DMAOR_AE)) |
ff7690b4 | 911 | return IRQ_NONE; |
2dc66667 GL |
912 | |
913 | sh_dmae_reset(data); | |
914 | return IRQ_HANDLED; | |
d8902adc | 915 | } |
d8902adc NI |
916 | |
917 | static void dmae_do_tasklet(unsigned long data) | |
918 | { | |
919 | struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; | |
3542a113 | 920 | struct sh_desc *desc; |
d8902adc | 921 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 922 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 923 | |
3542a113 GL |
924 | spin_lock(&sh_chan->desc_lock); |
925 | list_for_each_entry(desc, &sh_chan->ld_queue, node) { | |
cfefe997 GL |
926 | if (desc->mark == DESC_SUBMITTED && |
927 | ((desc->direction == DMA_FROM_DEVICE && | |
928 | (desc->hw.dar + desc->hw.tcr) == dar_buf) || | |
929 | (desc->hw.sar + desc->hw.tcr) == sar_buf)) { | |
3542a113 GL |
930 | dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n", |
931 | desc->async_tx.cookie, &desc->async_tx, | |
932 | desc->hw.dar); | |
933 | desc->mark = DESC_COMPLETED; | |
d8902adc NI |
934 | break; |
935 | } | |
936 | } | |
3542a113 | 937 | spin_unlock(&sh_chan->desc_lock); |
d8902adc | 938 | |
d8902adc NI |
939 | /* Next desc */ |
940 | sh_chan_xfer_ld_queue(sh_chan); | |
3542a113 | 941 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc NI |
942 | } |
943 | ||
03aa18f5 PM |
944 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) |
945 | { | |
03aa18f5 PM |
946 | /* Fast path out if NMIF is not asserted for this controller */ |
947 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | |
948 | return false; | |
949 | ||
2dc66667 | 950 | return sh_dmae_reset(shdev); |
03aa18f5 PM |
951 | } |
952 | ||
953 | static int sh_dmae_nmi_handler(struct notifier_block *self, | |
954 | unsigned long cmd, void *data) | |
955 | { | |
956 | struct sh_dmae_device *shdev; | |
957 | int ret = NOTIFY_DONE; | |
958 | bool triggered; | |
959 | ||
960 | /* | |
961 | * Only concern ourselves with NMI events. | |
962 | * | |
963 | * Normally we would check the die chain value, but as this needs | |
964 | * to be architecture independent, check for NMI context instead. | |
965 | */ | |
966 | if (!in_nmi()) | |
967 | return NOTIFY_DONE; | |
968 | ||
969 | rcu_read_lock(); | |
970 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | |
971 | /* | |
972 | * Only stop if one of the controllers has NMIF asserted, | |
973 | * we do not want to interfere with regular address error | |
974 | * handling or NMI events that don't concern the DMACs. | |
975 | */ | |
976 | triggered = sh_dmae_nmi_notify(shdev); | |
977 | if (triggered == true) | |
978 | ret = NOTIFY_OK; | |
979 | } | |
980 | rcu_read_unlock(); | |
981 | ||
982 | return ret; | |
983 | } | |
984 | ||
985 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | |
986 | .notifier_call = sh_dmae_nmi_handler, | |
987 | ||
988 | /* Run before NMI debug handler and KGDB */ | |
989 | .priority = 1, | |
990 | }; | |
991 | ||
027811b9 GL |
992 | static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
993 | int irq, unsigned long flags) | |
d8902adc NI |
994 | { |
995 | int err; | |
5bac942d | 996 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
027811b9 | 997 | struct platform_device *pdev = to_platform_device(shdev->common.dev); |
d8902adc NI |
998 | struct sh_dmae_chan *new_sh_chan; |
999 | ||
1000 | /* alloc channel */ | |
1001 | new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); | |
1002 | if (!new_sh_chan) { | |
86d61b33 GL |
1003 | dev_err(shdev->common.dev, |
1004 | "No free memory for allocating dma channels!\n"); | |
d8902adc NI |
1005 | return -ENOMEM; |
1006 | } | |
1007 | ||
8b1935e6 GL |
1008 | /* copy struct dma_device */ |
1009 | new_sh_chan->common.device = &shdev->common; | |
1010 | ||
d8902adc NI |
1011 | new_sh_chan->dev = shdev->common.dev; |
1012 | new_sh_chan->id = id; | |
027811b9 GL |
1013 | new_sh_chan->irq = irq; |
1014 | new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); | |
d8902adc NI |
1015 | |
1016 | /* Init DMA tasklet */ | |
1017 | tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet, | |
1018 | (unsigned long)new_sh_chan); | |
1019 | ||
d8902adc NI |
1020 | spin_lock_init(&new_sh_chan->desc_lock); |
1021 | ||
1022 | /* Init descripter manage list */ | |
1023 | INIT_LIST_HEAD(&new_sh_chan->ld_queue); | |
1024 | INIT_LIST_HEAD(&new_sh_chan->ld_free); | |
1025 | ||
d8902adc NI |
1026 | /* Add the channel to DMA device channel list */ |
1027 | list_add_tail(&new_sh_chan->common.device_node, | |
1028 | &shdev->common.channels); | |
1029 | shdev->common.chancnt++; | |
1030 | ||
027811b9 GL |
1031 | if (pdev->id >= 0) |
1032 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
1033 | "sh-dmae%d.%d", pdev->id, new_sh_chan->id); | |
1034 | else | |
1035 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
1036 | "sh-dma%d", new_sh_chan->id); | |
d8902adc NI |
1037 | |
1038 | /* set up channel irq */ | |
027811b9 | 1039 | err = request_irq(irq, &sh_dmae_interrupt, flags, |
86d61b33 | 1040 | new_sh_chan->dev_id, new_sh_chan); |
d8902adc NI |
1041 | if (err) { |
1042 | dev_err(shdev->common.dev, "DMA channel %d request_irq error " | |
1043 | "with return %d\n", id, err); | |
1044 | goto err_no_irq; | |
1045 | } | |
1046 | ||
d8902adc NI |
1047 | shdev->chan[id] = new_sh_chan; |
1048 | return 0; | |
1049 | ||
1050 | err_no_irq: | |
1051 | /* remove from dmaengine device node */ | |
1052 | list_del(&new_sh_chan->common.device_node); | |
1053 | kfree(new_sh_chan); | |
1054 | return err; | |
1055 | } | |
1056 | ||
1057 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
1058 | { | |
1059 | int i; | |
1060 | ||
1061 | for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) { | |
1062 | if (shdev->chan[i]) { | |
027811b9 GL |
1063 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
1064 | ||
1065 | free_irq(sh_chan->irq, sh_chan); | |
d8902adc | 1066 | |
027811b9 GL |
1067 | list_del(&sh_chan->common.device_node); |
1068 | kfree(sh_chan); | |
d8902adc NI |
1069 | shdev->chan[i] = NULL; |
1070 | } | |
1071 | } | |
1072 | shdev->common.chancnt = 0; | |
1073 | } | |
1074 | ||
1075 | static int __init sh_dmae_probe(struct platform_device *pdev) | |
1076 | { | |
027811b9 GL |
1077 | struct sh_dmae_pdata *pdata = pdev->dev.platform_data; |
1078 | unsigned long irqflags = IRQF_DISABLED, | |
8b1935e6 GL |
1079 | chan_flag[SH_DMAC_MAX_CHANNELS] = {}; |
1080 | int errirq, chan_irq[SH_DMAC_MAX_CHANNELS]; | |
300e5f97 | 1081 | int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; |
d8902adc | 1082 | struct sh_dmae_device *shdev; |
027811b9 | 1083 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 1084 | |
56adf7e8 | 1085 | /* get platform data */ |
027811b9 | 1086 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
1087 | return -ENODEV; |
1088 | ||
027811b9 | 1089 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
26fc02ab | 1090 | /* DMARS area is optional */ |
027811b9 GL |
1091 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1092 | /* | |
1093 | * IRQ resources: | |
1094 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
1095 | * the error IRQ, in which case it is the only IRQ in this resource: | |
1096 | * start == end. If it is the only IRQ resource, all channels also | |
1097 | * use the same IRQ. | |
1098 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
1099 | * ranges (start != end) | |
1100 | * 3. iff all events (channels and, optionally, error) on this | |
1101 | * controller use the same IRQ, only one IRQ resource can be | |
1102 | * specified, otherwise there must be one IRQ per channel, even if | |
1103 | * some of them are equal | |
1104 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
1105 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
1106 | * requested with the IRQF_SHARED flag | |
1107 | */ | |
1108 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1109 | if (!chan || !errirq_res) | |
1110 | return -ENODEV; | |
1111 | ||
1112 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | |
1113 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | |
1114 | return -EBUSY; | |
1115 | } | |
1116 | ||
1117 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | |
1118 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | |
1119 | err = -EBUSY; | |
1120 | goto ermrdmars; | |
1121 | } | |
1122 | ||
1123 | err = -ENOMEM; | |
d8902adc NI |
1124 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); |
1125 | if (!shdev) { | |
027811b9 GL |
1126 | dev_err(&pdev->dev, "Not enough memory\n"); |
1127 | goto ealloc; | |
1128 | } | |
1129 | ||
1130 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); | |
1131 | if (!shdev->chan_reg) | |
1132 | goto emapchan; | |
1133 | if (dmars) { | |
1134 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | |
1135 | if (!shdev->dmars) | |
1136 | goto emapdmars; | |
d8902adc NI |
1137 | } |
1138 | ||
d8902adc | 1139 | /* platform data */ |
027811b9 | 1140 | shdev->pdata = pdata; |
d8902adc | 1141 | |
5c2de444 PM |
1142 | platform_set_drvdata(pdev, shdev); |
1143 | ||
20f2a3b5 GL |
1144 | pm_runtime_enable(&pdev->dev); |
1145 | pm_runtime_get_sync(&pdev->dev); | |
1146 | ||
31705e21 | 1147 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 1148 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); |
31705e21 | 1149 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 1150 | |
2dc66667 | 1151 | /* reset dma controller - only needed as a test */ |
027811b9 | 1152 | err = sh_dmae_rst(shdev); |
d8902adc NI |
1153 | if (err) |
1154 | goto rst_err; | |
1155 | ||
d8902adc NI |
1156 | INIT_LIST_HEAD(&shdev->common.channels); |
1157 | ||
1158 | dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask); | |
26fc02ab | 1159 | if (pdata->slave && pdata->slave_num) |
027811b9 | 1160 | dma_cap_set(DMA_SLAVE, shdev->common.cap_mask); |
cfefe997 | 1161 | |
d8902adc NI |
1162 | shdev->common.device_alloc_chan_resources |
1163 | = sh_dmae_alloc_chan_resources; | |
1164 | shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources; | |
1165 | shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy; | |
07934481 | 1166 | shdev->common.device_tx_status = sh_dmae_tx_status; |
d8902adc | 1167 | shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending; |
cfefe997 GL |
1168 | |
1169 | /* Compulsory for DMA_SLAVE fields */ | |
1170 | shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg; | |
c3635c78 | 1171 | shdev->common.device_control = sh_dmae_control; |
cfefe997 | 1172 | |
d8902adc | 1173 | shdev->common.dev = &pdev->dev; |
ddb4f0f0 | 1174 | /* Default transfer size of 32 bytes requires 32-byte alignment */ |
8b1935e6 | 1175 | shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; |
d8902adc | 1176 | |
927a7c9c | 1177 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 GL |
1178 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
1179 | ||
1180 | if (!chanirq_res) | |
1181 | chanirq_res = errirq_res; | |
1182 | else | |
1183 | irqres++; | |
1184 | ||
1185 | if (chanirq_res == errirq_res || | |
1186 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 1187 | irqflags = IRQF_SHARED; |
027811b9 GL |
1188 | |
1189 | errirq = errirq_res->start; | |
1190 | ||
1191 | err = request_irq(errirq, sh_dmae_err, irqflags, | |
1192 | "DMAC Address Error", shdev); | |
1193 | if (err) { | |
1194 | dev_err(&pdev->dev, | |
1195 | "DMA failed requesting irq #%d, error %d\n", | |
1196 | errirq, err); | |
1197 | goto eirq_err; | |
d8902adc NI |
1198 | } |
1199 | ||
027811b9 GL |
1200 | #else |
1201 | chanirq_res = errirq_res; | |
927a7c9c | 1202 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ |
027811b9 GL |
1203 | |
1204 | if (chanirq_res->start == chanirq_res->end && | |
1205 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
1206 | /* Special case - all multiplexed */ | |
1207 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
300e5f97 MD |
1208 | if (irq_cnt < SH_DMAC_MAX_CHANNELS) { |
1209 | chan_irq[irq_cnt] = chanirq_res->start; | |
1210 | chan_flag[irq_cnt] = IRQF_SHARED; | |
1211 | } else { | |
1212 | irq_cap = 1; | |
1213 | break; | |
1214 | } | |
d8902adc | 1215 | } |
027811b9 GL |
1216 | } else { |
1217 | do { | |
1218 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
1219 | if ((errirq_res->flags & IORESOURCE_BITS) == | |
1220 | IORESOURCE_IRQ_SHAREABLE) | |
1221 | chan_flag[irq_cnt] = IRQF_SHARED; | |
1222 | else | |
1223 | chan_flag[irq_cnt] = IRQF_DISABLED; | |
1224 | dev_dbg(&pdev->dev, | |
1225 | "Found IRQ %d for channel %d\n", | |
1226 | i, irq_cnt); | |
1227 | chan_irq[irq_cnt++] = i; | |
300e5f97 MD |
1228 | |
1229 | if (irq_cnt >= SH_DMAC_MAX_CHANNELS) | |
1230 | break; | |
1231 | } | |
1232 | ||
1233 | if (irq_cnt >= SH_DMAC_MAX_CHANNELS) { | |
1234 | irq_cap = 1; | |
1235 | break; | |
027811b9 GL |
1236 | } |
1237 | chanirq_res = platform_get_resource(pdev, | |
1238 | IORESOURCE_IRQ, ++irqres); | |
1239 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 1240 | } |
027811b9 | 1241 | |
d8902adc | 1242 | /* Create DMA Channel */ |
300e5f97 | 1243 | for (i = 0; i < irq_cnt; i++) { |
027811b9 | 1244 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); |
d8902adc NI |
1245 | if (err) |
1246 | goto chan_probe_err; | |
1247 | } | |
1248 | ||
300e5f97 MD |
1249 | if (irq_cap) |
1250 | dev_notice(&pdev->dev, "Attempting to register %d DMA " | |
1251 | "channels when a maximum of %d are supported.\n", | |
1252 | pdata->channel_num, SH_DMAC_MAX_CHANNELS); | |
1253 | ||
20f2a3b5 GL |
1254 | pm_runtime_put(&pdev->dev); |
1255 | ||
d8902adc NI |
1256 | dma_async_device_register(&shdev->common); |
1257 | ||
1258 | return err; | |
1259 | ||
1260 | chan_probe_err: | |
1261 | sh_dmae_chan_remove(shdev); | |
300e5f97 | 1262 | |
927a7c9c | 1263 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 | 1264 | free_irq(errirq, shdev); |
d8902adc | 1265 | eirq_err: |
027811b9 | 1266 | #endif |
d8902adc | 1267 | rst_err: |
31705e21 | 1268 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 1269 | list_del_rcu(&shdev->node); |
31705e21 | 1270 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 1271 | |
20f2a3b5 | 1272 | pm_runtime_put(&pdev->dev); |
467017b8 GL |
1273 | pm_runtime_disable(&pdev->dev); |
1274 | ||
027811b9 GL |
1275 | if (dmars) |
1276 | iounmap(shdev->dmars); | |
5c2de444 PM |
1277 | |
1278 | platform_set_drvdata(pdev, NULL); | |
027811b9 GL |
1279 | emapdmars: |
1280 | iounmap(shdev->chan_reg); | |
31705e21 | 1281 | synchronize_rcu(); |
027811b9 | 1282 | emapchan: |
d8902adc | 1283 | kfree(shdev); |
027811b9 GL |
1284 | ealloc: |
1285 | if (dmars) | |
1286 | release_mem_region(dmars->start, resource_size(dmars)); | |
1287 | ermrdmars: | |
1288 | release_mem_region(chan->start, resource_size(chan)); | |
d8902adc | 1289 | |
d8902adc NI |
1290 | return err; |
1291 | } | |
1292 | ||
1293 | static int __exit sh_dmae_remove(struct platform_device *pdev) | |
1294 | { | |
1295 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 GL |
1296 | struct resource *res; |
1297 | int errirq = platform_get_irq(pdev, 0); | |
d8902adc NI |
1298 | |
1299 | dma_async_device_unregister(&shdev->common); | |
1300 | ||
027811b9 GL |
1301 | if (errirq > 0) |
1302 | free_irq(errirq, shdev); | |
d8902adc | 1303 | |
31705e21 | 1304 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 1305 | list_del_rcu(&shdev->node); |
31705e21 | 1306 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 1307 | |
d8902adc NI |
1308 | /* channel data remove */ |
1309 | sh_dmae_chan_remove(shdev); | |
1310 | ||
20f2a3b5 GL |
1311 | pm_runtime_disable(&pdev->dev); |
1312 | ||
027811b9 GL |
1313 | if (shdev->dmars) |
1314 | iounmap(shdev->dmars); | |
1315 | iounmap(shdev->chan_reg); | |
1316 | ||
5c2de444 PM |
1317 | platform_set_drvdata(pdev, NULL); |
1318 | ||
31705e21 | 1319 | synchronize_rcu(); |
d8902adc NI |
1320 | kfree(shdev); |
1321 | ||
027811b9 GL |
1322 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1323 | if (res) | |
1324 | release_mem_region(res->start, resource_size(res)); | |
1325 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1326 | if (res) | |
1327 | release_mem_region(res->start, resource_size(res)); | |
1328 | ||
d8902adc NI |
1329 | return 0; |
1330 | } | |
1331 | ||
1332 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
1333 | { | |
1334 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 | 1335 | sh_dmae_ctl_stop(shdev); |
d8902adc NI |
1336 | } |
1337 | ||
467017b8 GL |
1338 | static int sh_dmae_runtime_suspend(struct device *dev) |
1339 | { | |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int sh_dmae_runtime_resume(struct device *dev) | |
1344 | { | |
1345 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
1346 | ||
1347 | return sh_dmae_rst(shdev); | |
1348 | } | |
1349 | ||
1350 | #ifdef CONFIG_PM | |
1351 | static int sh_dmae_suspend(struct device *dev) | |
1352 | { | |
1353 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
1354 | int i; | |
1355 | ||
1356 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
1357 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
1358 | if (sh_chan->descs_allocated) | |
1359 | sh_chan->pm_error = pm_runtime_put_sync(dev); | |
1360 | } | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | static int sh_dmae_resume(struct device *dev) | |
1366 | { | |
1367 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
1368 | int i; | |
1369 | ||
1370 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
1371 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
1372 | struct sh_dmae_slave *param = sh_chan->common.private; | |
1373 | ||
1374 | if (!sh_chan->descs_allocated) | |
1375 | continue; | |
1376 | ||
1377 | if (!sh_chan->pm_error) | |
1378 | pm_runtime_get_sync(dev); | |
1379 | ||
1380 | if (param) { | |
1381 | const struct sh_dmae_slave_config *cfg = param->config; | |
1382 | dmae_set_dmars(sh_chan, cfg->mid_rid); | |
1383 | dmae_set_chcr(sh_chan, cfg->chcr); | |
1384 | } else { | |
1385 | dmae_init(sh_chan); | |
1386 | } | |
1387 | } | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | #else | |
1392 | #define sh_dmae_suspend NULL | |
1393 | #define sh_dmae_resume NULL | |
1394 | #endif | |
1395 | ||
1396 | const struct dev_pm_ops sh_dmae_pm = { | |
1397 | .suspend = sh_dmae_suspend, | |
1398 | .resume = sh_dmae_resume, | |
1399 | .runtime_suspend = sh_dmae_runtime_suspend, | |
1400 | .runtime_resume = sh_dmae_runtime_resume, | |
1401 | }; | |
1402 | ||
d8902adc NI |
1403 | static struct platform_driver sh_dmae_driver = { |
1404 | .remove = __exit_p(sh_dmae_remove), | |
1405 | .shutdown = sh_dmae_shutdown, | |
1406 | .driver = { | |
7a5c106a | 1407 | .owner = THIS_MODULE, |
d8902adc | 1408 | .name = "sh-dma-engine", |
467017b8 | 1409 | .pm = &sh_dmae_pm, |
d8902adc NI |
1410 | }, |
1411 | }; | |
1412 | ||
1413 | static int __init sh_dmae_init(void) | |
1414 | { | |
661382fe GL |
1415 | /* Wire up NMI handling */ |
1416 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | |
1417 | if (err) | |
1418 | return err; | |
1419 | ||
d8902adc NI |
1420 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); |
1421 | } | |
1422 | module_init(sh_dmae_init); | |
1423 | ||
1424 | static void __exit sh_dmae_exit(void) | |
1425 | { | |
1426 | platform_driver_unregister(&sh_dmae_driver); | |
661382fe GL |
1427 | |
1428 | unregister_die_notifier(&sh_dmae_nmi_notifier); | |
d8902adc NI |
1429 | } |
1430 | module_exit(sh_dmae_exit); | |
1431 | ||
1432 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
1433 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
1434 | MODULE_LICENSE("GPL"); | |
e5843341 | 1435 | MODULE_ALIAS("platform:sh-dma-engine"); |