Commit | Line | Data |
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9a7b8e00 GL |
1 | /* |
2 | * Dmaengine driver base library for DMA controllers, found on SH-based SoCs | |
3 | * | |
4 | * extracted from shdma.c | |
5 | * | |
6 | * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
7 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
8 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
9 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/delay.h> | |
17 | #include <linux/shdma-base.h> | |
18 | #include <linux/dmaengine.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/spinlock.h> | |
25 | ||
26 | #include "../dmaengine.h" | |
27 | ||
28 | /* DMA descriptor control */ | |
29 | enum shdma_desc_status { | |
30 | DESC_IDLE, | |
31 | DESC_PREPARED, | |
32 | DESC_SUBMITTED, | |
33 | DESC_COMPLETED, /* completed, have to call callback */ | |
34 | DESC_WAITING, /* callback called, waiting for ack / re-submit */ | |
35 | }; | |
36 | ||
37 | #define NR_DESCS_PER_CHANNEL 32 | |
38 | ||
39 | #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan) | |
40 | #define to_shdma_dev(d) container_of(d, struct shdma_dev, dma_dev) | |
41 | ||
42 | /* | |
43 | * For slave DMA we assume, that there is a finite number of DMA slaves in the | |
44 | * system, and that each such slave can only use a finite number of channels. | |
45 | * We use slave channel IDs to make sure, that no such slave channel ID is | |
46 | * allocated more than once. | |
47 | */ | |
48 | static unsigned int slave_num = 256; | |
49 | module_param(slave_num, uint, 0444); | |
50 | ||
51 | /* A bitmask with slave_num bits */ | |
52 | static unsigned long *shdma_slave_used; | |
53 | ||
54 | /* Called under spin_lock_irq(&schan->chan_lock") */ | |
55 | static void shdma_chan_xfer_ld_queue(struct shdma_chan *schan) | |
56 | { | |
57 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | |
58 | const struct shdma_ops *ops = sdev->ops; | |
59 | struct shdma_desc *sdesc; | |
60 | ||
61 | /* DMA work check */ | |
62 | if (ops->channel_busy(schan)) | |
63 | return; | |
64 | ||
65 | /* Find the first not transferred descriptor */ | |
66 | list_for_each_entry(sdesc, &schan->ld_queue, node) | |
67 | if (sdesc->mark == DESC_SUBMITTED) { | |
68 | ops->start_xfer(schan, sdesc); | |
69 | break; | |
70 | } | |
71 | } | |
72 | ||
73 | static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
74 | { | |
75 | struct shdma_desc *chunk, *c, *desc = | |
76 | container_of(tx, struct shdma_desc, async_tx), | |
77 | *last = desc; | |
78 | struct shdma_chan *schan = to_shdma_chan(tx->chan); | |
9a7b8e00 GL |
79 | dma_async_tx_callback callback = tx->callback; |
80 | dma_cookie_t cookie; | |
81 | bool power_up; | |
82 | ||
83 | spin_lock_irq(&schan->chan_lock); | |
84 | ||
85 | power_up = list_empty(&schan->ld_queue); | |
86 | ||
87 | cookie = dma_cookie_assign(tx); | |
88 | ||
89 | /* Mark all chunks of this descriptor as submitted, move to the queue */ | |
90 | list_for_each_entry_safe(chunk, c, desc->node.prev, node) { | |
91 | /* | |
92 | * All chunks are on the global ld_free, so, we have to find | |
93 | * the end of the chain ourselves | |
94 | */ | |
95 | if (chunk != desc && (chunk->mark == DESC_IDLE || | |
96 | chunk->async_tx.cookie > 0 || | |
97 | chunk->async_tx.cookie == -EBUSY || | |
98 | &chunk->node == &schan->ld_free)) | |
99 | break; | |
100 | chunk->mark = DESC_SUBMITTED; | |
101 | /* Callback goes to the last chunk */ | |
102 | chunk->async_tx.callback = NULL; | |
103 | chunk->cookie = cookie; | |
104 | list_move_tail(&chunk->node, &schan->ld_queue); | |
105 | last = chunk; | |
106 | ||
107 | dev_dbg(schan->dev, "submit #%d@%p on %d\n", | |
108 | tx->cookie, &last->async_tx, schan->id); | |
109 | } | |
110 | ||
111 | last->async_tx.callback = callback; | |
112 | last->async_tx.callback_param = tx->callback_param; | |
113 | ||
114 | if (power_up) { | |
115 | int ret; | |
116 | schan->pm_state = SHDMA_PM_BUSY; | |
117 | ||
118 | ret = pm_runtime_get(schan->dev); | |
119 | ||
120 | spin_unlock_irq(&schan->chan_lock); | |
121 | if (ret < 0) | |
122 | dev_err(schan->dev, "%s(): GET = %d\n", __func__, ret); | |
123 | ||
124 | pm_runtime_barrier(schan->dev); | |
125 | ||
126 | spin_lock_irq(&schan->chan_lock); | |
127 | ||
128 | /* Have we been reset, while waiting? */ | |
129 | if (schan->pm_state != SHDMA_PM_ESTABLISHED) { | |
130 | struct shdma_dev *sdev = | |
131 | to_shdma_dev(schan->dma_chan.device); | |
132 | const struct shdma_ops *ops = sdev->ops; | |
133 | dev_dbg(schan->dev, "Bring up channel %d\n", | |
134 | schan->id); | |
135 | /* | |
136 | * TODO: .xfer_setup() might fail on some platforms. | |
137 | * Make it int then, on error remove chunks from the | |
138 | * queue again | |
139 | */ | |
c2cdb7e4 | 140 | ops->setup_xfer(schan, schan->slave_id); |
9a7b8e00 GL |
141 | |
142 | if (schan->pm_state == SHDMA_PM_PENDING) | |
143 | shdma_chan_xfer_ld_queue(schan); | |
144 | schan->pm_state = SHDMA_PM_ESTABLISHED; | |
145 | } | |
146 | } else { | |
147 | /* | |
148 | * Tell .device_issue_pending() not to run the queue, interrupts | |
149 | * will do it anyway | |
150 | */ | |
151 | schan->pm_state = SHDMA_PM_PENDING; | |
152 | } | |
153 | ||
154 | spin_unlock_irq(&schan->chan_lock); | |
155 | ||
156 | return cookie; | |
157 | } | |
158 | ||
159 | /* Called with desc_lock held */ | |
160 | static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan) | |
161 | { | |
162 | struct shdma_desc *sdesc; | |
163 | ||
164 | list_for_each_entry(sdesc, &schan->ld_free, node) | |
165 | if (sdesc->mark != DESC_PREPARED) { | |
166 | BUG_ON(sdesc->mark != DESC_IDLE); | |
167 | list_del(&sdesc->node); | |
168 | return sdesc; | |
169 | } | |
170 | ||
171 | return NULL; | |
172 | } | |
173 | ||
4981c4dc GL |
174 | static int shdma_setup_slave(struct shdma_chan *schan, int slave_id, |
175 | dma_addr_t slave_addr) | |
1ff8df4f GL |
176 | { |
177 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | |
178 | const struct shdma_ops *ops = sdev->ops; | |
67eacc15 GL |
179 | int ret, match; |
180 | ||
181 | if (schan->dev->of_node) { | |
182 | match = schan->hw_req; | |
4981c4dc | 183 | ret = ops->set_slave(schan, match, slave_addr, true); |
67eacc15 GL |
184 | if (ret < 0) |
185 | return ret; | |
186 | ||
187 | slave_id = schan->slave_id; | |
188 | } else { | |
189 | match = slave_id; | |
190 | } | |
1ff8df4f GL |
191 | |
192 | if (slave_id < 0 || slave_id >= slave_num) | |
193 | return -EINVAL; | |
194 | ||
195 | if (test_and_set_bit(slave_id, shdma_slave_used)) | |
196 | return -EBUSY; | |
197 | ||
4981c4dc | 198 | ret = ops->set_slave(schan, match, slave_addr, false); |
1ff8df4f GL |
199 | if (ret < 0) { |
200 | clear_bit(slave_id, shdma_slave_used); | |
201 | return ret; | |
202 | } | |
203 | ||
204 | schan->slave_id = slave_id; | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | /* | |
210 | * This is the standard shdma filter function to be used as a replacement to the | |
211 | * "old" method, using the .private pointer. If for some reason you allocate a | |
212 | * channel without slave data, use something like ERR_PTR(-EINVAL) as a filter | |
213 | * parameter. If this filter is used, the slave driver, after calling | |
214 | * dma_request_channel(), will also have to call dmaengine_slave_config() with | |
215 | * .slave_id, .direction, and either .src_addr or .dst_addr set. | |
216 | * NOTE: this filter doesn't support multiple DMAC drivers with the DMA_SLAVE | |
217 | * capability! If this becomes a requirement, hardware glue drivers, using this | |
218 | * services would have to provide their own filters, which first would check | |
219 | * the device driver, similar to how other DMAC drivers, e.g., sa11x0-dma.c, do | |
220 | * this, and only then, in case of a match, call this common filter. | |
67eacc15 GL |
221 | * NOTE 2: This filter function is also used in the DT case by shdma_of_xlate(). |
222 | * In that case the MID-RID value is used for slave channel filtering and is | |
223 | * passed to this function in the "arg" parameter. | |
1ff8df4f GL |
224 | */ |
225 | bool shdma_chan_filter(struct dma_chan *chan, void *arg) | |
226 | { | |
227 | struct shdma_chan *schan = to_shdma_chan(chan); | |
228 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | |
229 | const struct shdma_ops *ops = sdev->ops; | |
42e4a12a | 230 | int match = (long)arg; |
1ff8df4f GL |
231 | int ret; |
232 | ||
67eacc15 | 233 | if (match < 0) |
1ff8df4f GL |
234 | /* No slave requested - arbitrary channel */ |
235 | return true; | |
236 | ||
67eacc15 | 237 | if (!schan->dev->of_node && match >= slave_num) |
1ff8df4f GL |
238 | return false; |
239 | ||
4981c4dc | 240 | ret = ops->set_slave(schan, match, 0, true); |
1ff8df4f GL |
241 | if (ret < 0) |
242 | return false; | |
243 | ||
244 | return true; | |
245 | } | |
246 | EXPORT_SYMBOL(shdma_chan_filter); | |
247 | ||
9a7b8e00 GL |
248 | static int shdma_alloc_chan_resources(struct dma_chan *chan) |
249 | { | |
250 | struct shdma_chan *schan = to_shdma_chan(chan); | |
251 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | |
252 | const struct shdma_ops *ops = sdev->ops; | |
253 | struct shdma_desc *desc; | |
254 | struct shdma_slave *slave = chan->private; | |
255 | int ret, i; | |
256 | ||
257 | /* | |
258 | * This relies on the guarantee from dmaengine that alloc_chan_resources | |
259 | * never runs concurrently with itself or free_chan_resources. | |
260 | */ | |
261 | if (slave) { | |
1ff8df4f | 262 | /* Legacy mode: .private is set in filter */ |
4981c4dc | 263 | ret = shdma_setup_slave(schan, slave->slave_id, 0); |
9a7b8e00 GL |
264 | if (ret < 0) |
265 | goto esetslave; | |
c2cdb7e4 GL |
266 | } else { |
267 | schan->slave_id = -EINVAL; | |
9a7b8e00 GL |
268 | } |
269 | ||
270 | schan->desc = kcalloc(NR_DESCS_PER_CHANNEL, | |
271 | sdev->desc_size, GFP_KERNEL); | |
272 | if (!schan->desc) { | |
273 | ret = -ENOMEM; | |
274 | goto edescalloc; | |
275 | } | |
276 | schan->desc_num = NR_DESCS_PER_CHANNEL; | |
277 | ||
278 | for (i = 0; i < NR_DESCS_PER_CHANNEL; i++) { | |
279 | desc = ops->embedded_desc(schan->desc, i); | |
280 | dma_async_tx_descriptor_init(&desc->async_tx, | |
281 | &schan->dma_chan); | |
282 | desc->async_tx.tx_submit = shdma_tx_submit; | |
283 | desc->mark = DESC_IDLE; | |
284 | ||
285 | list_add(&desc->node, &schan->ld_free); | |
286 | } | |
287 | ||
288 | return NR_DESCS_PER_CHANNEL; | |
289 | ||
290 | edescalloc: | |
291 | if (slave) | |
292 | esetslave: | |
293 | clear_bit(slave->slave_id, shdma_slave_used); | |
9a7b8e00 GL |
294 | chan->private = NULL; |
295 | return ret; | |
296 | } | |
297 | ||
298 | static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all) | |
299 | { | |
300 | struct shdma_desc *desc, *_desc; | |
301 | /* Is the "exposed" head of a chain acked? */ | |
302 | bool head_acked = false; | |
303 | dma_cookie_t cookie = 0; | |
304 | dma_async_tx_callback callback = NULL; | |
305 | void *param = NULL; | |
306 | unsigned long flags; | |
307 | ||
308 | spin_lock_irqsave(&schan->chan_lock, flags); | |
309 | list_for_each_entry_safe(desc, _desc, &schan->ld_queue, node) { | |
310 | struct dma_async_tx_descriptor *tx = &desc->async_tx; | |
311 | ||
312 | BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie); | |
313 | BUG_ON(desc->mark != DESC_SUBMITTED && | |
314 | desc->mark != DESC_COMPLETED && | |
315 | desc->mark != DESC_WAITING); | |
316 | ||
317 | /* | |
318 | * queue is ordered, and we use this loop to (1) clean up all | |
319 | * completed descriptors, and to (2) update descriptor flags of | |
320 | * any chunks in a (partially) completed chain | |
321 | */ | |
322 | if (!all && desc->mark == DESC_SUBMITTED && | |
323 | desc->cookie != cookie) | |
324 | break; | |
325 | ||
326 | if (tx->cookie > 0) | |
327 | cookie = tx->cookie; | |
328 | ||
329 | if (desc->mark == DESC_COMPLETED && desc->chunks == 1) { | |
330 | if (schan->dma_chan.completed_cookie != desc->cookie - 1) | |
331 | dev_dbg(schan->dev, | |
332 | "Completing cookie %d, expected %d\n", | |
333 | desc->cookie, | |
334 | schan->dma_chan.completed_cookie + 1); | |
335 | schan->dma_chan.completed_cookie = desc->cookie; | |
336 | } | |
337 | ||
338 | /* Call callback on the last chunk */ | |
339 | if (desc->mark == DESC_COMPLETED && tx->callback) { | |
340 | desc->mark = DESC_WAITING; | |
341 | callback = tx->callback; | |
342 | param = tx->callback_param; | |
343 | dev_dbg(schan->dev, "descriptor #%d@%p on %d callback\n", | |
344 | tx->cookie, tx, schan->id); | |
345 | BUG_ON(desc->chunks != 1); | |
346 | break; | |
347 | } | |
348 | ||
349 | if (tx->cookie > 0 || tx->cookie == -EBUSY) { | |
350 | if (desc->mark == DESC_COMPLETED) { | |
351 | BUG_ON(tx->cookie < 0); | |
352 | desc->mark = DESC_WAITING; | |
353 | } | |
354 | head_acked = async_tx_test_ack(tx); | |
355 | } else { | |
356 | switch (desc->mark) { | |
357 | case DESC_COMPLETED: | |
358 | desc->mark = DESC_WAITING; | |
359 | /* Fall through */ | |
360 | case DESC_WAITING: | |
361 | if (head_acked) | |
362 | async_tx_ack(&desc->async_tx); | |
363 | } | |
364 | } | |
365 | ||
366 | dev_dbg(schan->dev, "descriptor %p #%d completed.\n", | |
367 | tx, tx->cookie); | |
368 | ||
369 | if (((desc->mark == DESC_COMPLETED || | |
370 | desc->mark == DESC_WAITING) && | |
371 | async_tx_test_ack(&desc->async_tx)) || all) { | |
372 | /* Remove from ld_queue list */ | |
373 | desc->mark = DESC_IDLE; | |
374 | ||
375 | list_move(&desc->node, &schan->ld_free); | |
376 | ||
377 | if (list_empty(&schan->ld_queue)) { | |
378 | dev_dbg(schan->dev, "Bring down channel %d\n", schan->id); | |
379 | pm_runtime_put(schan->dev); | |
380 | schan->pm_state = SHDMA_PM_ESTABLISHED; | |
381 | } | |
382 | } | |
383 | } | |
384 | ||
385 | if (all && !callback) | |
386 | /* | |
387 | * Terminating and the loop completed normally: forgive | |
388 | * uncompleted cookies | |
389 | */ | |
390 | schan->dma_chan.completed_cookie = schan->dma_chan.cookie; | |
391 | ||
392 | spin_unlock_irqrestore(&schan->chan_lock, flags); | |
393 | ||
394 | if (callback) | |
395 | callback(param); | |
396 | ||
397 | return callback; | |
398 | } | |
399 | ||
400 | /* | |
401 | * shdma_chan_ld_cleanup - Clean up link descriptors | |
402 | * | |
403 | * Clean up the ld_queue of DMA channel. | |
404 | */ | |
405 | static void shdma_chan_ld_cleanup(struct shdma_chan *schan, bool all) | |
406 | { | |
407 | while (__ld_cleanup(schan, all)) | |
408 | ; | |
409 | } | |
410 | ||
411 | /* | |
412 | * shdma_free_chan_resources - Free all resources of the channel. | |
413 | */ | |
414 | static void shdma_free_chan_resources(struct dma_chan *chan) | |
415 | { | |
416 | struct shdma_chan *schan = to_shdma_chan(chan); | |
417 | struct shdma_dev *sdev = to_shdma_dev(chan->device); | |
418 | const struct shdma_ops *ops = sdev->ops; | |
419 | LIST_HEAD(list); | |
420 | ||
421 | /* Protect against ISR */ | |
422 | spin_lock_irq(&schan->chan_lock); | |
423 | ops->halt_channel(schan); | |
424 | spin_unlock_irq(&schan->chan_lock); | |
425 | ||
426 | /* Now no new interrupts will occur */ | |
427 | ||
428 | /* Prepared and not submitted descriptors can still be on the queue */ | |
429 | if (!list_empty(&schan->ld_queue)) | |
430 | shdma_chan_ld_cleanup(schan, true); | |
431 | ||
c2cdb7e4 | 432 | if (schan->slave_id >= 0) { |
9a7b8e00 | 433 | /* The caller is holding dma_list_mutex */ |
c2cdb7e4 | 434 | clear_bit(schan->slave_id, shdma_slave_used); |
9a7b8e00 GL |
435 | chan->private = NULL; |
436 | } | |
437 | ||
438 | spin_lock_irq(&schan->chan_lock); | |
439 | ||
440 | list_splice_init(&schan->ld_free, &list); | |
441 | schan->desc_num = 0; | |
442 | ||
443 | spin_unlock_irq(&schan->chan_lock); | |
444 | ||
445 | kfree(schan->desc); | |
446 | } | |
447 | ||
448 | /** | |
449 | * shdma_add_desc - get, set up and return one transfer descriptor | |
450 | * @schan: DMA channel | |
451 | * @flags: DMA transfer flags | |
452 | * @dst: destination DMA address, incremented when direction equals | |
453 | * DMA_DEV_TO_MEM or DMA_MEM_TO_MEM | |
454 | * @src: source DMA address, incremented when direction equals | |
455 | * DMA_MEM_TO_DEV or DMA_MEM_TO_MEM | |
456 | * @len: DMA transfer length | |
457 | * @first: if NULL, set to the current descriptor and cookie set to -EBUSY | |
458 | * @direction: needed for slave DMA to decide which address to keep constant, | |
459 | * equals DMA_MEM_TO_MEM for MEMCPY | |
460 | * Returns 0 or an error | |
461 | * Locks: called with desc_lock held | |
462 | */ | |
463 | static struct shdma_desc *shdma_add_desc(struct shdma_chan *schan, | |
464 | unsigned long flags, dma_addr_t *dst, dma_addr_t *src, size_t *len, | |
465 | struct shdma_desc **first, enum dma_transfer_direction direction) | |
466 | { | |
467 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | |
468 | const struct shdma_ops *ops = sdev->ops; | |
469 | struct shdma_desc *new; | |
470 | size_t copy_size = *len; | |
471 | ||
472 | if (!copy_size) | |
473 | return NULL; | |
474 | ||
475 | /* Allocate the link descriptor from the free list */ | |
476 | new = shdma_get_desc(schan); | |
477 | if (!new) { | |
478 | dev_err(schan->dev, "No free link descriptor available\n"); | |
479 | return NULL; | |
480 | } | |
481 | ||
482 | ops->desc_setup(schan, new, *src, *dst, ©_size); | |
483 | ||
484 | if (!*first) { | |
485 | /* First desc */ | |
486 | new->async_tx.cookie = -EBUSY; | |
487 | *first = new; | |
488 | } else { | |
489 | /* Other desc - invisible to the user */ | |
490 | new->async_tx.cookie = -EINVAL; | |
491 | } | |
492 | ||
493 | dev_dbg(schan->dev, | |
42e4a12a LP |
494 | "chaining (%zu/%zu)@%pad -> %pad with %p, cookie %d\n", |
495 | copy_size, *len, src, dst, &new->async_tx, | |
9a7b8e00 GL |
496 | new->async_tx.cookie); |
497 | ||
498 | new->mark = DESC_PREPARED; | |
499 | new->async_tx.flags = flags; | |
500 | new->direction = direction; | |
4f46f8ac | 501 | new->partial = 0; |
9a7b8e00 GL |
502 | |
503 | *len -= copy_size; | |
504 | if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV) | |
505 | *src += copy_size; | |
506 | if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM) | |
507 | *dst += copy_size; | |
508 | ||
509 | return new; | |
510 | } | |
511 | ||
512 | /* | |
513 | * shdma_prep_sg - prepare transfer descriptors from an SG list | |
514 | * | |
515 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
516 | * converted to scatter-gather to guarantee consistent locking and a correct | |
517 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
518 | * logically, the SG list is RAM and the addr variable contains slave address, | |
519 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM | |
520 | * and the SG list contains only one element and points at the source buffer. | |
521 | */ | |
522 | static struct dma_async_tx_descriptor *shdma_prep_sg(struct shdma_chan *schan, | |
523 | struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, | |
524 | enum dma_transfer_direction direction, unsigned long flags) | |
525 | { | |
526 | struct scatterlist *sg; | |
527 | struct shdma_desc *first = NULL, *new = NULL /* compiler... */; | |
528 | LIST_HEAD(tx_list); | |
529 | int chunks = 0; | |
530 | unsigned long irq_flags; | |
531 | int i; | |
532 | ||
533 | for_each_sg(sgl, sg, sg_len, i) | |
534 | chunks += DIV_ROUND_UP(sg_dma_len(sg), schan->max_xfer_len); | |
535 | ||
536 | /* Have to lock the whole loop to protect against concurrent release */ | |
537 | spin_lock_irqsave(&schan->chan_lock, irq_flags); | |
538 | ||
539 | /* | |
540 | * Chaining: | |
541 | * first descriptor is what user is dealing with in all API calls, its | |
542 | * cookie is at first set to -EBUSY, at tx-submit to a positive | |
543 | * number | |
544 | * if more than one chunk is needed further chunks have cookie = -EINVAL | |
545 | * the last chunk, if not equal to the first, has cookie = -ENOSPC | |
546 | * all chunks are linked onto the tx_list head with their .node heads | |
547 | * only during this function, then they are immediately spliced | |
548 | * back onto the free list in form of a chain | |
549 | */ | |
550 | for_each_sg(sgl, sg, sg_len, i) { | |
551 | dma_addr_t sg_addr = sg_dma_address(sg); | |
552 | size_t len = sg_dma_len(sg); | |
553 | ||
554 | if (!len) | |
555 | goto err_get_desc; | |
556 | ||
557 | do { | |
42e4a12a LP |
558 | dev_dbg(schan->dev, "Add SG #%d@%p[%zu], dma %pad\n", |
559 | i, sg, len, &sg_addr); | |
9a7b8e00 GL |
560 | |
561 | if (direction == DMA_DEV_TO_MEM) | |
562 | new = shdma_add_desc(schan, flags, | |
563 | &sg_addr, addr, &len, &first, | |
564 | direction); | |
565 | else | |
566 | new = shdma_add_desc(schan, flags, | |
567 | addr, &sg_addr, &len, &first, | |
568 | direction); | |
569 | if (!new) | |
570 | goto err_get_desc; | |
571 | ||
572 | new->chunks = chunks--; | |
573 | list_add_tail(&new->node, &tx_list); | |
574 | } while (len); | |
575 | } | |
576 | ||
577 | if (new != first) | |
578 | new->async_tx.cookie = -ENOSPC; | |
579 | ||
580 | /* Put them back on the free list, so, they don't get lost */ | |
581 | list_splice_tail(&tx_list, &schan->ld_free); | |
582 | ||
583 | spin_unlock_irqrestore(&schan->chan_lock, irq_flags); | |
584 | ||
585 | return &first->async_tx; | |
586 | ||
587 | err_get_desc: | |
588 | list_for_each_entry(new, &tx_list, node) | |
589 | new->mark = DESC_IDLE; | |
590 | list_splice(&tx_list, &schan->ld_free); | |
591 | ||
592 | spin_unlock_irqrestore(&schan->chan_lock, irq_flags); | |
593 | ||
594 | return NULL; | |
595 | } | |
596 | ||
597 | static struct dma_async_tx_descriptor *shdma_prep_memcpy( | |
598 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, | |
599 | size_t len, unsigned long flags) | |
600 | { | |
601 | struct shdma_chan *schan = to_shdma_chan(chan); | |
602 | struct scatterlist sg; | |
603 | ||
604 | if (!chan || !len) | |
605 | return NULL; | |
606 | ||
607 | BUG_ON(!schan->desc_num); | |
608 | ||
609 | sg_init_table(&sg, 1); | |
610 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len, | |
611 | offset_in_page(dma_src)); | |
612 | sg_dma_address(&sg) = dma_src; | |
613 | sg_dma_len(&sg) = len; | |
614 | ||
615 | return shdma_prep_sg(schan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM, flags); | |
616 | } | |
617 | ||
618 | static struct dma_async_tx_descriptor *shdma_prep_slave_sg( | |
619 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
620 | enum dma_transfer_direction direction, unsigned long flags, void *context) | |
621 | { | |
622 | struct shdma_chan *schan = to_shdma_chan(chan); | |
623 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); | |
624 | const struct shdma_ops *ops = sdev->ops; | |
c2cdb7e4 | 625 | int slave_id = schan->slave_id; |
9a7b8e00 GL |
626 | dma_addr_t slave_addr; |
627 | ||
628 | if (!chan) | |
629 | return NULL; | |
630 | ||
631 | BUG_ON(!schan->desc_num); | |
632 | ||
633 | /* Someone calling slave DMA on a generic channel? */ | |
c2cdb7e4 GL |
634 | if (slave_id < 0 || !sg_len) { |
635 | dev_warn(schan->dev, "%s: bad parameter: len=%d, id=%d\n", | |
636 | __func__, sg_len, slave_id); | |
9a7b8e00 GL |
637 | return NULL; |
638 | } | |
639 | ||
640 | slave_addr = ops->slave_addr(schan); | |
641 | ||
642 | return shdma_prep_sg(schan, sgl, sg_len, &slave_addr, | |
643 | direction, flags); | |
644 | } | |
645 | ||
646 | static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
647 | unsigned long arg) | |
648 | { | |
649 | struct shdma_chan *schan = to_shdma_chan(chan); | |
650 | struct shdma_dev *sdev = to_shdma_dev(chan->device); | |
651 | const struct shdma_ops *ops = sdev->ops; | |
1ff8df4f | 652 | struct dma_slave_config *config; |
9a7b8e00 | 653 | unsigned long flags; |
1ff8df4f | 654 | int ret; |
9a7b8e00 | 655 | |
1ff8df4f GL |
656 | switch (cmd) { |
657 | case DMA_TERMINATE_ALL: | |
658 | spin_lock_irqsave(&schan->chan_lock, flags); | |
659 | ops->halt_channel(schan); | |
4f46f8ac GL |
660 | |
661 | if (ops->get_partial && !list_empty(&schan->ld_queue)) { | |
662 | /* Record partial transfer */ | |
663 | struct shdma_desc *desc = list_first_entry(&schan->ld_queue, | |
664 | struct shdma_desc, node); | |
665 | desc->partial = ops->get_partial(schan, desc); | |
666 | } | |
667 | ||
1ff8df4f | 668 | spin_unlock_irqrestore(&schan->chan_lock, flags); |
9a7b8e00 | 669 | |
1ff8df4f GL |
670 | shdma_chan_ld_cleanup(schan, true); |
671 | break; | |
672 | case DMA_SLAVE_CONFIG: | |
673 | /* | |
674 | * So far only .slave_id is used, but the slave drivers are | |
675 | * encouraged to also set a transfer direction and an address. | |
676 | */ | |
677 | if (!arg) | |
678 | return -EINVAL; | |
679 | /* | |
680 | * We could lock this, but you shouldn't be configuring the | |
681 | * channel, while using it... | |
682 | */ | |
683 | config = (struct dma_slave_config *)arg; | |
4981c4dc GL |
684 | ret = shdma_setup_slave(schan, config->slave_id, |
685 | config->direction == DMA_DEV_TO_MEM ? | |
686 | config->src_addr : config->dst_addr); | |
1ff8df4f GL |
687 | if (ret < 0) |
688 | return ret; | |
689 | break; | |
690 | default: | |
691 | return -ENXIO; | |
692 | } | |
9a7b8e00 GL |
693 | |
694 | return 0; | |
695 | } | |
696 | ||
697 | static void shdma_issue_pending(struct dma_chan *chan) | |
698 | { | |
699 | struct shdma_chan *schan = to_shdma_chan(chan); | |
700 | ||
701 | spin_lock_irq(&schan->chan_lock); | |
702 | if (schan->pm_state == SHDMA_PM_ESTABLISHED) | |
703 | shdma_chan_xfer_ld_queue(schan); | |
704 | else | |
705 | schan->pm_state = SHDMA_PM_PENDING; | |
706 | spin_unlock_irq(&schan->chan_lock); | |
707 | } | |
708 | ||
709 | static enum dma_status shdma_tx_status(struct dma_chan *chan, | |
710 | dma_cookie_t cookie, | |
711 | struct dma_tx_state *txstate) | |
712 | { | |
713 | struct shdma_chan *schan = to_shdma_chan(chan); | |
714 | enum dma_status status; | |
715 | unsigned long flags; | |
716 | ||
717 | shdma_chan_ld_cleanup(schan, false); | |
718 | ||
719 | spin_lock_irqsave(&schan->chan_lock, flags); | |
720 | ||
721 | status = dma_cookie_status(chan, cookie, txstate); | |
722 | ||
723 | /* | |
724 | * If we don't find cookie on the queue, it has been aborted and we have | |
725 | * to report error | |
726 | */ | |
a8d8d268 | 727 | if (status != DMA_COMPLETE) { |
9a7b8e00 GL |
728 | struct shdma_desc *sdesc; |
729 | status = DMA_ERROR; | |
730 | list_for_each_entry(sdesc, &schan->ld_queue, node) | |
731 | if (sdesc->cookie == cookie) { | |
732 | status = DMA_IN_PROGRESS; | |
733 | break; | |
734 | } | |
735 | } | |
736 | ||
737 | spin_unlock_irqrestore(&schan->chan_lock, flags); | |
738 | ||
739 | return status; | |
740 | } | |
741 | ||
742 | /* Called from error IRQ or NMI */ | |
743 | bool shdma_reset(struct shdma_dev *sdev) | |
744 | { | |
745 | const struct shdma_ops *ops = sdev->ops; | |
746 | struct shdma_chan *schan; | |
747 | unsigned int handled = 0; | |
748 | int i; | |
749 | ||
750 | /* Reset all channels */ | |
751 | shdma_for_each_chan(schan, sdev, i) { | |
752 | struct shdma_desc *sdesc; | |
753 | LIST_HEAD(dl); | |
754 | ||
755 | if (!schan) | |
756 | continue; | |
757 | ||
758 | spin_lock(&schan->chan_lock); | |
759 | ||
760 | /* Stop the channel */ | |
761 | ops->halt_channel(schan); | |
762 | ||
763 | list_splice_init(&schan->ld_queue, &dl); | |
764 | ||
765 | if (!list_empty(&dl)) { | |
766 | dev_dbg(schan->dev, "Bring down channel %d\n", schan->id); | |
767 | pm_runtime_put(schan->dev); | |
768 | } | |
769 | schan->pm_state = SHDMA_PM_ESTABLISHED; | |
770 | ||
771 | spin_unlock(&schan->chan_lock); | |
772 | ||
773 | /* Complete all */ | |
774 | list_for_each_entry(sdesc, &dl, node) { | |
775 | struct dma_async_tx_descriptor *tx = &sdesc->async_tx; | |
776 | sdesc->mark = DESC_IDLE; | |
777 | if (tx->callback) | |
778 | tx->callback(tx->callback_param); | |
779 | } | |
780 | ||
781 | spin_lock(&schan->chan_lock); | |
782 | list_splice(&dl, &schan->ld_free); | |
783 | spin_unlock(&schan->chan_lock); | |
784 | ||
785 | handled++; | |
786 | } | |
787 | ||
788 | return !!handled; | |
789 | } | |
790 | EXPORT_SYMBOL(shdma_reset); | |
791 | ||
792 | static irqreturn_t chan_irq(int irq, void *dev) | |
793 | { | |
794 | struct shdma_chan *schan = dev; | |
795 | const struct shdma_ops *ops = | |
796 | to_shdma_dev(schan->dma_chan.device)->ops; | |
797 | irqreturn_t ret; | |
798 | ||
799 | spin_lock(&schan->chan_lock); | |
800 | ||
801 | ret = ops->chan_irq(schan, irq) ? IRQ_WAKE_THREAD : IRQ_NONE; | |
802 | ||
803 | spin_unlock(&schan->chan_lock); | |
804 | ||
805 | return ret; | |
806 | } | |
807 | ||
808 | static irqreturn_t chan_irqt(int irq, void *dev) | |
809 | { | |
810 | struct shdma_chan *schan = dev; | |
811 | const struct shdma_ops *ops = | |
812 | to_shdma_dev(schan->dma_chan.device)->ops; | |
813 | struct shdma_desc *sdesc; | |
814 | ||
815 | spin_lock_irq(&schan->chan_lock); | |
816 | list_for_each_entry(sdesc, &schan->ld_queue, node) { | |
817 | if (sdesc->mark == DESC_SUBMITTED && | |
818 | ops->desc_completed(schan, sdesc)) { | |
819 | dev_dbg(schan->dev, "done #%d@%p\n", | |
820 | sdesc->async_tx.cookie, &sdesc->async_tx); | |
821 | sdesc->mark = DESC_COMPLETED; | |
822 | break; | |
823 | } | |
824 | } | |
825 | /* Next desc */ | |
826 | shdma_chan_xfer_ld_queue(schan); | |
827 | spin_unlock_irq(&schan->chan_lock); | |
828 | ||
829 | shdma_chan_ld_cleanup(schan, false); | |
830 | ||
831 | return IRQ_HANDLED; | |
832 | } | |
833 | ||
834 | int shdma_request_irq(struct shdma_chan *schan, int irq, | |
835 | unsigned long flags, const char *name) | |
836 | { | |
c1c63a14 GL |
837 | int ret = devm_request_threaded_irq(schan->dev, irq, chan_irq, |
838 | chan_irqt, flags, name, schan); | |
9a7b8e00 GL |
839 | |
840 | schan->irq = ret < 0 ? ret : irq; | |
841 | ||
842 | return ret; | |
843 | } | |
844 | EXPORT_SYMBOL(shdma_request_irq); | |
845 | ||
9a7b8e00 GL |
846 | void shdma_chan_probe(struct shdma_dev *sdev, |
847 | struct shdma_chan *schan, int id) | |
848 | { | |
849 | schan->pm_state = SHDMA_PM_ESTABLISHED; | |
850 | ||
851 | /* reference struct dma_device */ | |
852 | schan->dma_chan.device = &sdev->dma_dev; | |
853 | dma_cookie_init(&schan->dma_chan); | |
854 | ||
855 | schan->dev = sdev->dma_dev.dev; | |
856 | schan->id = id; | |
857 | ||
858 | if (!schan->max_xfer_len) | |
859 | schan->max_xfer_len = PAGE_SIZE; | |
860 | ||
861 | spin_lock_init(&schan->chan_lock); | |
862 | ||
863 | /* Init descripter manage list */ | |
864 | INIT_LIST_HEAD(&schan->ld_queue); | |
865 | INIT_LIST_HEAD(&schan->ld_free); | |
866 | ||
867 | /* Add the channel to DMA device channel list */ | |
868 | list_add_tail(&schan->dma_chan.device_node, | |
869 | &sdev->dma_dev.channels); | |
870 | sdev->schan[sdev->dma_dev.chancnt++] = schan; | |
871 | } | |
872 | EXPORT_SYMBOL(shdma_chan_probe); | |
873 | ||
874 | void shdma_chan_remove(struct shdma_chan *schan) | |
875 | { | |
876 | list_del(&schan->dma_chan.device_node); | |
877 | } | |
878 | EXPORT_SYMBOL(shdma_chan_remove); | |
879 | ||
880 | int shdma_init(struct device *dev, struct shdma_dev *sdev, | |
881 | int chan_num) | |
882 | { | |
883 | struct dma_device *dma_dev = &sdev->dma_dev; | |
884 | ||
885 | /* | |
886 | * Require all call-backs for now, they can trivially be made optional | |
887 | * later as required | |
888 | */ | |
889 | if (!sdev->ops || | |
890 | !sdev->desc_size || | |
891 | !sdev->ops->embedded_desc || | |
892 | !sdev->ops->start_xfer || | |
893 | !sdev->ops->setup_xfer || | |
894 | !sdev->ops->set_slave || | |
895 | !sdev->ops->desc_setup || | |
896 | !sdev->ops->slave_addr || | |
897 | !sdev->ops->channel_busy || | |
898 | !sdev->ops->halt_channel || | |
899 | !sdev->ops->desc_completed) | |
900 | return -EINVAL; | |
901 | ||
902 | sdev->schan = kcalloc(chan_num, sizeof(*sdev->schan), GFP_KERNEL); | |
903 | if (!sdev->schan) | |
904 | return -ENOMEM; | |
905 | ||
906 | INIT_LIST_HEAD(&dma_dev->channels); | |
907 | ||
908 | /* Common and MEMCPY operations */ | |
909 | dma_dev->device_alloc_chan_resources | |
910 | = shdma_alloc_chan_resources; | |
911 | dma_dev->device_free_chan_resources = shdma_free_chan_resources; | |
912 | dma_dev->device_prep_dma_memcpy = shdma_prep_memcpy; | |
913 | dma_dev->device_tx_status = shdma_tx_status; | |
914 | dma_dev->device_issue_pending = shdma_issue_pending; | |
915 | ||
916 | /* Compulsory for DMA_SLAVE fields */ | |
917 | dma_dev->device_prep_slave_sg = shdma_prep_slave_sg; | |
918 | dma_dev->device_control = shdma_control; | |
919 | ||
920 | dma_dev->dev = dev; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | EXPORT_SYMBOL(shdma_init); | |
925 | ||
926 | void shdma_cleanup(struct shdma_dev *sdev) | |
927 | { | |
928 | kfree(sdev->schan); | |
929 | } | |
930 | EXPORT_SYMBOL(shdma_cleanup); | |
931 | ||
932 | static int __init shdma_enter(void) | |
933 | { | |
934 | shdma_slave_used = kzalloc(DIV_ROUND_UP(slave_num, BITS_PER_LONG) * | |
935 | sizeof(long), GFP_KERNEL); | |
936 | if (!shdma_slave_used) | |
937 | return -ENOMEM; | |
938 | return 0; | |
939 | } | |
940 | module_init(shdma_enter); | |
941 | ||
942 | static void __exit shdma_exit(void) | |
943 | { | |
944 | kfree(shdma_slave_used); | |
945 | } | |
946 | module_exit(shdma_exit); | |
947 | ||
948 | MODULE_LICENSE("GPL v2"); | |
949 | MODULE_DESCRIPTION("SH-DMA driver base library"); | |
950 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); |