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87244fe5 LP |
1 | /* |
2 | * Renesas R-Car Gen2 DMA Controller Driver | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Inc. | |
5 | * | |
6 | * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
7 | * | |
8 | * This is free software; you can redistribute it and/or modify | |
9 | * it under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
ccadee9b | 13 | #include <linux/dma-mapping.h> |
87244fe5 LP |
14 | #include <linux/dmaengine.h> |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_dma.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
27 | #include "../dmaengine.h" | |
28 | ||
29 | /* | |
30 | * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer | |
31 | * @node: entry in the parent's chunks list | |
32 | * @src_addr: device source address | |
33 | * @dst_addr: device destination address | |
34 | * @size: transfer size in bytes | |
35 | */ | |
36 | struct rcar_dmac_xfer_chunk { | |
37 | struct list_head node; | |
38 | ||
39 | dma_addr_t src_addr; | |
40 | dma_addr_t dst_addr; | |
41 | u32 size; | |
42 | }; | |
43 | ||
ccadee9b LP |
44 | /* |
45 | * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk | |
46 | * @sar: value of the SAR register (source address) | |
47 | * @dar: value of the DAR register (destination address) | |
48 | * @tcr: value of the TCR register (transfer count) | |
49 | */ | |
50 | struct rcar_dmac_hw_desc { | |
51 | u32 sar; | |
52 | u32 dar; | |
53 | u32 tcr; | |
54 | u32 reserved; | |
55 | } __attribute__((__packed__)); | |
56 | ||
87244fe5 LP |
57 | /* |
58 | * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor | |
59 | * @async_tx: base DMA asynchronous transaction descriptor | |
60 | * @direction: direction of the DMA transfer | |
61 | * @xfer_shift: log2 of the transfer size | |
62 | * @chcr: value of the channel configuration register for this transfer | |
63 | * @node: entry in the channel's descriptors lists | |
64 | * @chunks: list of transfer chunks for this transfer | |
65 | * @running: the transfer chunk being currently processed | |
ccadee9b | 66 | * @nchunks: number of transfer chunks for this transfer |
1ed1315f | 67 | * @hwdescs.use: whether the transfer descriptor uses hardware descriptors |
ccadee9b LP |
68 | * @hwdescs.mem: hardware descriptors memory for the transfer |
69 | * @hwdescs.dma: device address of the hardware descriptors memory | |
70 | * @hwdescs.size: size of the hardware descriptors in bytes | |
87244fe5 LP |
71 | * @size: transfer size in bytes |
72 | * @cyclic: when set indicates that the DMA transfer is cyclic | |
73 | */ | |
74 | struct rcar_dmac_desc { | |
75 | struct dma_async_tx_descriptor async_tx; | |
76 | enum dma_transfer_direction direction; | |
77 | unsigned int xfer_shift; | |
78 | u32 chcr; | |
79 | ||
80 | struct list_head node; | |
81 | struct list_head chunks; | |
82 | struct rcar_dmac_xfer_chunk *running; | |
ccadee9b LP |
83 | unsigned int nchunks; |
84 | ||
85 | struct { | |
1ed1315f | 86 | bool use; |
ccadee9b LP |
87 | struct rcar_dmac_hw_desc *mem; |
88 | dma_addr_t dma; | |
89 | size_t size; | |
90 | } hwdescs; | |
87244fe5 LP |
91 | |
92 | unsigned int size; | |
93 | bool cyclic; | |
94 | }; | |
95 | ||
96 | #define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx) | |
97 | ||
98 | /* | |
99 | * struct rcar_dmac_desc_page - One page worth of descriptors | |
100 | * @node: entry in the channel's pages list | |
101 | * @descs: array of DMA descriptors | |
102 | * @chunks: array of transfer chunk descriptors | |
103 | */ | |
104 | struct rcar_dmac_desc_page { | |
105 | struct list_head node; | |
106 | ||
107 | union { | |
108 | struct rcar_dmac_desc descs[0]; | |
109 | struct rcar_dmac_xfer_chunk chunks[0]; | |
110 | }; | |
111 | }; | |
112 | ||
113 | #define RCAR_DMAC_DESCS_PER_PAGE \ | |
114 | ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \ | |
115 | sizeof(struct rcar_dmac_desc)) | |
116 | #define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \ | |
117 | ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \ | |
118 | sizeof(struct rcar_dmac_xfer_chunk)) | |
119 | ||
120 | /* | |
121 | * struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel | |
122 | * @chan: base DMA channel object | |
123 | * @iomem: channel I/O memory base | |
124 | * @index: index of this channel in the controller | |
125 | * @src_xfer_size: size (in bytes) of hardware transfers on the source side | |
126 | * @dst_xfer_size: size (in bytes) of hardware transfers on the destination side | |
127 | * @src_slave_addr: slave source memory address | |
128 | * @dst_slave_addr: slave destination memory address | |
129 | * @mid_rid: hardware MID/RID for the DMA client using this channel | |
130 | * @lock: protects the channel CHCR register and the desc members | |
131 | * @desc.free: list of free descriptors | |
132 | * @desc.pending: list of pending descriptors (submitted with tx_submit) | |
133 | * @desc.active: list of active descriptors (activated with issue_pending) | |
134 | * @desc.done: list of completed descriptors | |
135 | * @desc.wait: list of descriptors waiting for an ack | |
136 | * @desc.running: the descriptor being processed (a member of the active list) | |
137 | * @desc.chunks_free: list of free transfer chunk descriptors | |
138 | * @desc.pages: list of pages used by allocated descriptors | |
139 | */ | |
140 | struct rcar_dmac_chan { | |
141 | struct dma_chan chan; | |
142 | void __iomem *iomem; | |
143 | unsigned int index; | |
144 | ||
145 | unsigned int src_xfer_size; | |
146 | unsigned int dst_xfer_size; | |
147 | dma_addr_t src_slave_addr; | |
148 | dma_addr_t dst_slave_addr; | |
149 | int mid_rid; | |
150 | ||
151 | spinlock_t lock; | |
152 | ||
153 | struct { | |
154 | struct list_head free; | |
155 | struct list_head pending; | |
156 | struct list_head active; | |
157 | struct list_head done; | |
158 | struct list_head wait; | |
159 | struct rcar_dmac_desc *running; | |
160 | ||
161 | struct list_head chunks_free; | |
162 | ||
163 | struct list_head pages; | |
164 | } desc; | |
165 | }; | |
166 | ||
167 | #define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan) | |
168 | ||
169 | /* | |
170 | * struct rcar_dmac - R-Car Gen2 DMA Controller | |
171 | * @engine: base DMA engine object | |
172 | * @dev: the hardware device | |
173 | * @iomem: remapped I/O memory base | |
174 | * @n_channels: number of available channels | |
175 | * @channels: array of DMAC channels | |
176 | * @modules: bitmask of client modules in use | |
177 | */ | |
178 | struct rcar_dmac { | |
179 | struct dma_device engine; | |
180 | struct device *dev; | |
181 | void __iomem *iomem; | |
182 | ||
183 | unsigned int n_channels; | |
184 | struct rcar_dmac_chan *channels; | |
185 | ||
186 | unsigned long modules[256 / BITS_PER_LONG]; | |
187 | }; | |
188 | ||
189 | #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine) | |
190 | ||
191 | /* ----------------------------------------------------------------------------- | |
192 | * Registers | |
193 | */ | |
194 | ||
195 | #define RCAR_DMAC_CHAN_OFFSET(i) (0x8000 + 0x80 * (i)) | |
196 | ||
197 | #define RCAR_DMAISTA 0x0020 | |
198 | #define RCAR_DMASEC 0x0030 | |
199 | #define RCAR_DMAOR 0x0060 | |
200 | #define RCAR_DMAOR_PRI_FIXED (0 << 8) | |
201 | #define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8) | |
202 | #define RCAR_DMAOR_AE (1 << 2) | |
203 | #define RCAR_DMAOR_DME (1 << 0) | |
204 | #define RCAR_DMACHCLR 0x0080 | |
205 | #define RCAR_DMADPSEC 0x00a0 | |
206 | ||
207 | #define RCAR_DMASAR 0x0000 | |
208 | #define RCAR_DMADAR 0x0004 | |
209 | #define RCAR_DMATCR 0x0008 | |
210 | #define RCAR_DMATCR_MASK 0x00ffffff | |
211 | #define RCAR_DMATSR 0x0028 | |
212 | #define RCAR_DMACHCR 0x000c | |
213 | #define RCAR_DMACHCR_CAE (1 << 31) | |
214 | #define RCAR_DMACHCR_CAIE (1 << 30) | |
215 | #define RCAR_DMACHCR_DPM_DISABLED (0 << 28) | |
216 | #define RCAR_DMACHCR_DPM_ENABLED (1 << 28) | |
217 | #define RCAR_DMACHCR_DPM_REPEAT (2 << 28) | |
218 | #define RCAR_DMACHCR_DPM_INFINITE (3 << 28) | |
219 | #define RCAR_DMACHCR_RPT_SAR (1 << 27) | |
220 | #define RCAR_DMACHCR_RPT_DAR (1 << 26) | |
221 | #define RCAR_DMACHCR_RPT_TCR (1 << 25) | |
222 | #define RCAR_DMACHCR_DPB (1 << 22) | |
223 | #define RCAR_DMACHCR_DSE (1 << 19) | |
224 | #define RCAR_DMACHCR_DSIE (1 << 18) | |
225 | #define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3)) | |
226 | #define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3)) | |
227 | #define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3)) | |
228 | #define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3)) | |
229 | #define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3)) | |
230 | #define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3)) | |
231 | #define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3)) | |
232 | #define RCAR_DMACHCR_DM_FIXED (0 << 14) | |
233 | #define RCAR_DMACHCR_DM_INC (1 << 14) | |
234 | #define RCAR_DMACHCR_DM_DEC (2 << 14) | |
235 | #define RCAR_DMACHCR_SM_FIXED (0 << 12) | |
236 | #define RCAR_DMACHCR_SM_INC (1 << 12) | |
237 | #define RCAR_DMACHCR_SM_DEC (2 << 12) | |
238 | #define RCAR_DMACHCR_RS_AUTO (4 << 8) | |
239 | #define RCAR_DMACHCR_RS_DMARS (8 << 8) | |
240 | #define RCAR_DMACHCR_IE (1 << 2) | |
241 | #define RCAR_DMACHCR_TE (1 << 1) | |
242 | #define RCAR_DMACHCR_DE (1 << 0) | |
243 | #define RCAR_DMATCRB 0x0018 | |
244 | #define RCAR_DMATSRB 0x0038 | |
245 | #define RCAR_DMACHCRB 0x001c | |
246 | #define RCAR_DMACHCRB_DCNT(n) ((n) << 24) | |
ccadee9b LP |
247 | #define RCAR_DMACHCRB_DPTR_MASK (0xff << 16) |
248 | #define RCAR_DMACHCRB_DPTR_SHIFT 16 | |
87244fe5 LP |
249 | #define RCAR_DMACHCRB_DRST (1 << 15) |
250 | #define RCAR_DMACHCRB_DTS (1 << 8) | |
251 | #define RCAR_DMACHCRB_SLM_NORMAL (0 << 4) | |
252 | #define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4) | |
253 | #define RCAR_DMACHCRB_PRI(n) ((n) << 0) | |
254 | #define RCAR_DMARS 0x0040 | |
255 | #define RCAR_DMABUFCR 0x0048 | |
256 | #define RCAR_DMABUFCR_MBU(n) ((n) << 16) | |
257 | #define RCAR_DMABUFCR_ULB(n) ((n) << 0) | |
258 | #define RCAR_DMADPBASE 0x0050 | |
259 | #define RCAR_DMADPBASE_MASK 0xfffffff0 | |
260 | #define RCAR_DMADPBASE_SEL (1 << 0) | |
261 | #define RCAR_DMADPCR 0x0054 | |
262 | #define RCAR_DMADPCR_DIPT(n) ((n) << 24) | |
263 | #define RCAR_DMAFIXSAR 0x0010 | |
264 | #define RCAR_DMAFIXDAR 0x0014 | |
265 | #define RCAR_DMAFIXDPBASE 0x0060 | |
266 | ||
267 | /* Hardcode the MEMCPY transfer size to 4 bytes. */ | |
268 | #define RCAR_DMAC_MEMCPY_XFER_SIZE 4 | |
269 | ||
270 | /* ----------------------------------------------------------------------------- | |
271 | * Device access | |
272 | */ | |
273 | ||
274 | static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data) | |
275 | { | |
276 | if (reg == RCAR_DMAOR) | |
277 | writew(data, dmac->iomem + reg); | |
278 | else | |
279 | writel(data, dmac->iomem + reg); | |
280 | } | |
281 | ||
282 | static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg) | |
283 | { | |
284 | if (reg == RCAR_DMAOR) | |
285 | return readw(dmac->iomem + reg); | |
286 | else | |
287 | return readl(dmac->iomem + reg); | |
288 | } | |
289 | ||
290 | static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg) | |
291 | { | |
292 | if (reg == RCAR_DMARS) | |
293 | return readw(chan->iomem + reg); | |
294 | else | |
295 | return readl(chan->iomem + reg); | |
296 | } | |
297 | ||
298 | static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data) | |
299 | { | |
300 | if (reg == RCAR_DMARS) | |
301 | writew(data, chan->iomem + reg); | |
302 | else | |
303 | writel(data, chan->iomem + reg); | |
304 | } | |
305 | ||
306 | /* ----------------------------------------------------------------------------- | |
307 | * Initialization and configuration | |
308 | */ | |
309 | ||
310 | static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan) | |
311 | { | |
312 | u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
313 | ||
314 | return (chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE)) == RCAR_DMACHCR_DE; | |
315 | } | |
316 | ||
317 | static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan) | |
318 | { | |
319 | struct rcar_dmac_desc *desc = chan->desc.running; | |
ccadee9b | 320 | u32 chcr = desc->chcr; |
87244fe5 LP |
321 | |
322 | WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan)); | |
323 | ||
ccadee9b LP |
324 | if (chan->mid_rid >= 0) |
325 | rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid); | |
326 | ||
1ed1315f | 327 | if (desc->hwdescs.use) { |
ccadee9b LP |
328 | dev_dbg(chan->chan.device->dev, |
329 | "chan%u: queue desc %p: %u@%pad\n", | |
330 | chan->index, desc, desc->nchunks, &desc->hwdescs.dma); | |
331 | ||
87244fe5 | 332 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
ccadee9b LP |
333 | rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE, |
334 | desc->hwdescs.dma >> 32); | |
87244fe5 | 335 | #endif |
ccadee9b LP |
336 | rcar_dmac_chan_write(chan, RCAR_DMADPBASE, |
337 | (desc->hwdescs.dma & 0xfffffff0) | | |
338 | RCAR_DMADPBASE_SEL); | |
339 | rcar_dmac_chan_write(chan, RCAR_DMACHCRB, | |
340 | RCAR_DMACHCRB_DCNT(desc->nchunks - 1) | | |
341 | RCAR_DMACHCRB_DRST); | |
87244fe5 | 342 | |
ccadee9b LP |
343 | /* |
344 | * Program the descriptor stage interrupt to occur after the end | |
345 | * of the first stage. | |
346 | */ | |
347 | rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1)); | |
348 | ||
349 | chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR | |
350 | | RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB; | |
351 | ||
352 | /* | |
353 | * If the descriptor isn't cyclic enable normal descriptor mode | |
354 | * and the transfer completion interrupt. | |
355 | */ | |
356 | if (!desc->cyclic) | |
357 | chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE; | |
358 | /* | |
359 | * If the descriptor is cyclic and has a callback enable the | |
360 | * descriptor stage interrupt in infinite repeat mode. | |
361 | */ | |
362 | else if (desc->async_tx.callback) | |
363 | chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE; | |
364 | /* | |
365 | * Otherwise just select infinite repeat mode without any | |
366 | * interrupt. | |
367 | */ | |
368 | else | |
369 | chcr |= RCAR_DMACHCR_DPM_INFINITE; | |
370 | } else { | |
371 | struct rcar_dmac_xfer_chunk *chunk = desc->running; | |
87244fe5 | 372 | |
ccadee9b LP |
373 | dev_dbg(chan->chan.device->dev, |
374 | "chan%u: queue chunk %p: %u@%pad -> %pad\n", | |
375 | chan->index, chunk, chunk->size, &chunk->src_addr, | |
376 | &chunk->dst_addr); | |
87244fe5 | 377 | |
ccadee9b LP |
378 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
379 | rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR, | |
380 | chunk->src_addr >> 32); | |
381 | rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR, | |
382 | chunk->dst_addr >> 32); | |
383 | #endif | |
384 | rcar_dmac_chan_write(chan, RCAR_DMASAR, | |
385 | chunk->src_addr & 0xffffffff); | |
386 | rcar_dmac_chan_write(chan, RCAR_DMADAR, | |
387 | chunk->dst_addr & 0xffffffff); | |
388 | rcar_dmac_chan_write(chan, RCAR_DMATCR, | |
389 | chunk->size >> desc->xfer_shift); | |
390 | ||
391 | chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE; | |
392 | } | |
393 | ||
394 | rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE); | |
87244fe5 LP |
395 | } |
396 | ||
397 | static int rcar_dmac_init(struct rcar_dmac *dmac) | |
398 | { | |
399 | u16 dmaor; | |
400 | ||
401 | /* Clear all channels and enable the DMAC globally. */ | |
402 | rcar_dmac_write(dmac, RCAR_DMACHCLR, 0x7fff); | |
403 | rcar_dmac_write(dmac, RCAR_DMAOR, | |
404 | RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME); | |
405 | ||
406 | dmaor = rcar_dmac_read(dmac, RCAR_DMAOR); | |
407 | if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) { | |
408 | dev_warn(dmac->dev, "DMAOR initialization failed.\n"); | |
409 | return -EIO; | |
410 | } | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | /* ----------------------------------------------------------------------------- | |
416 | * Descriptors submission | |
417 | */ | |
418 | ||
419 | static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx) | |
420 | { | |
421 | struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan); | |
422 | struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx); | |
423 | unsigned long flags; | |
424 | dma_cookie_t cookie; | |
425 | ||
426 | spin_lock_irqsave(&chan->lock, flags); | |
427 | ||
428 | cookie = dma_cookie_assign(tx); | |
429 | ||
430 | dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n", | |
431 | chan->index, tx->cookie, desc); | |
432 | ||
433 | list_add_tail(&desc->node, &chan->desc.pending); | |
434 | desc->running = list_first_entry(&desc->chunks, | |
435 | struct rcar_dmac_xfer_chunk, node); | |
436 | ||
437 | spin_unlock_irqrestore(&chan->lock, flags); | |
438 | ||
439 | return cookie; | |
440 | } | |
441 | ||
442 | /* ----------------------------------------------------------------------------- | |
443 | * Descriptors allocation and free | |
444 | */ | |
445 | ||
446 | /* | |
447 | * rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors | |
448 | * @chan: the DMA channel | |
449 | * @gfp: allocation flags | |
450 | */ | |
451 | static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp) | |
452 | { | |
453 | struct rcar_dmac_desc_page *page; | |
454 | LIST_HEAD(list); | |
455 | unsigned int i; | |
456 | ||
457 | page = (void *)get_zeroed_page(gfp); | |
458 | if (!page) | |
459 | return -ENOMEM; | |
460 | ||
461 | for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) { | |
462 | struct rcar_dmac_desc *desc = &page->descs[i]; | |
463 | ||
464 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan); | |
465 | desc->async_tx.tx_submit = rcar_dmac_tx_submit; | |
466 | INIT_LIST_HEAD(&desc->chunks); | |
467 | ||
468 | list_add_tail(&desc->node, &list); | |
469 | } | |
470 | ||
471 | spin_lock_irq(&chan->lock); | |
472 | list_splice_tail(&list, &chan->desc.free); | |
473 | list_add_tail(&page->node, &chan->desc.pages); | |
474 | spin_unlock_irq(&chan->lock); | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | /* | |
480 | * rcar_dmac_desc_put - Release a DMA transfer descriptor | |
481 | * @chan: the DMA channel | |
482 | * @desc: the descriptor | |
483 | * | |
484 | * Put the descriptor and its transfer chunk descriptors back in the channel's | |
1ed1315f LP |
485 | * free descriptors lists. The descriptor's chunks list will be reinitialized to |
486 | * an empty list as a result. | |
87244fe5 | 487 | * |
ccadee9b LP |
488 | * The descriptor must have been removed from the channel's lists before calling |
489 | * this function. | |
87244fe5 LP |
490 | */ |
491 | static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan, | |
492 | struct rcar_dmac_desc *desc) | |
493 | { | |
f3915072 LP |
494 | unsigned long flags; |
495 | ||
496 | spin_lock_irqsave(&chan->lock, flags); | |
87244fe5 LP |
497 | list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free); |
498 | list_add_tail(&desc->node, &chan->desc.free); | |
f3915072 | 499 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
500 | } |
501 | ||
502 | static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan) | |
503 | { | |
504 | struct rcar_dmac_desc *desc, *_desc; | |
ccadee9b | 505 | LIST_HEAD(list); |
87244fe5 | 506 | |
ccadee9b LP |
507 | /* |
508 | * We have to temporarily move all descriptors from the wait list to a | |
509 | * local list as iterating over the wait list, even with | |
510 | * list_for_each_entry_safe, isn't safe if we release the channel lock | |
511 | * around the rcar_dmac_desc_put() call. | |
512 | */ | |
513 | spin_lock_irq(&chan->lock); | |
514 | list_splice_init(&chan->desc.wait, &list); | |
515 | spin_unlock_irq(&chan->lock); | |
516 | ||
517 | list_for_each_entry_safe(desc, _desc, &list, node) { | |
87244fe5 LP |
518 | if (async_tx_test_ack(&desc->async_tx)) { |
519 | list_del(&desc->node); | |
520 | rcar_dmac_desc_put(chan, desc); | |
521 | } | |
522 | } | |
ccadee9b LP |
523 | |
524 | if (list_empty(&list)) | |
525 | return; | |
526 | ||
527 | /* Put the remaining descriptors back in the wait list. */ | |
528 | spin_lock_irq(&chan->lock); | |
529 | list_splice(&list, &chan->desc.wait); | |
530 | spin_unlock_irq(&chan->lock); | |
87244fe5 LP |
531 | } |
532 | ||
533 | /* | |
534 | * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer | |
535 | * @chan: the DMA channel | |
536 | * | |
537 | * Locking: This function must be called in a non-atomic context. | |
538 | * | |
539 | * Return: A pointer to the allocated descriptor or NULL if no descriptor can | |
540 | * be allocated. | |
541 | */ | |
542 | static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan) | |
543 | { | |
544 | struct rcar_dmac_desc *desc; | |
545 | int ret; | |
546 | ||
87244fe5 LP |
547 | /* Recycle acked descriptors before attempting allocation. */ |
548 | rcar_dmac_desc_recycle_acked(chan); | |
549 | ||
ccadee9b LP |
550 | spin_lock_irq(&chan->lock); |
551 | ||
a55e07c8 LP |
552 | while (list_empty(&chan->desc.free)) { |
553 | /* | |
554 | * No free descriptors, allocate a page worth of them and try | |
555 | * again, as someone else could race us to get the newly | |
556 | * allocated descriptors. If the allocation fails return an | |
557 | * error. | |
558 | */ | |
559 | spin_unlock_irq(&chan->lock); | |
560 | ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT); | |
561 | if (ret < 0) | |
562 | return NULL; | |
563 | spin_lock_irq(&chan->lock); | |
564 | } | |
87244fe5 | 565 | |
a55e07c8 LP |
566 | desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc, node); |
567 | list_del(&desc->node); | |
87244fe5 LP |
568 | |
569 | spin_unlock_irq(&chan->lock); | |
570 | ||
571 | return desc; | |
572 | } | |
573 | ||
574 | /* | |
575 | * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks | |
576 | * @chan: the DMA channel | |
577 | * @gfp: allocation flags | |
578 | */ | |
579 | static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp) | |
580 | { | |
581 | struct rcar_dmac_desc_page *page; | |
582 | LIST_HEAD(list); | |
583 | unsigned int i; | |
584 | ||
585 | page = (void *)get_zeroed_page(gfp); | |
586 | if (!page) | |
587 | return -ENOMEM; | |
588 | ||
589 | for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) { | |
590 | struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i]; | |
591 | ||
592 | list_add_tail(&chunk->node, &list); | |
593 | } | |
594 | ||
595 | spin_lock_irq(&chan->lock); | |
596 | list_splice_tail(&list, &chan->desc.chunks_free); | |
597 | list_add_tail(&page->node, &chan->desc.pages); | |
598 | spin_unlock_irq(&chan->lock); | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
603 | /* | |
604 | * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer | |
605 | * @chan: the DMA channel | |
606 | * | |
607 | * Locking: This function must be called in a non-atomic context. | |
608 | * | |
609 | * Return: A pointer to the allocated transfer chunk descriptor or NULL if no | |
610 | * descriptor can be allocated. | |
611 | */ | |
612 | static struct rcar_dmac_xfer_chunk * | |
613 | rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan) | |
614 | { | |
615 | struct rcar_dmac_xfer_chunk *chunk; | |
616 | int ret; | |
617 | ||
618 | spin_lock_irq(&chan->lock); | |
619 | ||
a55e07c8 LP |
620 | while (list_empty(&chan->desc.chunks_free)) { |
621 | /* | |
622 | * No free descriptors, allocate a page worth of them and try | |
623 | * again, as someone else could race us to get the newly | |
624 | * allocated descriptors. If the allocation fails return an | |
625 | * error. | |
626 | */ | |
627 | spin_unlock_irq(&chan->lock); | |
628 | ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT); | |
629 | if (ret < 0) | |
630 | return NULL; | |
631 | spin_lock_irq(&chan->lock); | |
632 | } | |
87244fe5 | 633 | |
a55e07c8 LP |
634 | chunk = list_first_entry(&chan->desc.chunks_free, |
635 | struct rcar_dmac_xfer_chunk, node); | |
636 | list_del(&chunk->node); | |
87244fe5 LP |
637 | |
638 | spin_unlock_irq(&chan->lock); | |
639 | ||
640 | return chunk; | |
641 | } | |
642 | ||
1ed1315f LP |
643 | static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan, |
644 | struct rcar_dmac_desc *desc, size_t size) | |
645 | { | |
646 | /* | |
647 | * dma_alloc_coherent() allocates memory in page size increments. To | |
648 | * avoid reallocating the hardware descriptors when the allocated size | |
649 | * wouldn't change align the requested size to a multiple of the page | |
650 | * size. | |
651 | */ | |
652 | size = PAGE_ALIGN(size); | |
653 | ||
654 | if (desc->hwdescs.size == size) | |
655 | return; | |
656 | ||
657 | if (desc->hwdescs.mem) { | |
658 | dma_free_coherent(NULL, desc->hwdescs.size, desc->hwdescs.mem, | |
659 | desc->hwdescs.dma); | |
660 | desc->hwdescs.mem = NULL; | |
661 | desc->hwdescs.size = 0; | |
662 | } | |
663 | ||
664 | if (!size) | |
665 | return; | |
666 | ||
667 | desc->hwdescs.mem = dma_alloc_coherent(NULL, size, &desc->hwdescs.dma, | |
668 | GFP_NOWAIT); | |
669 | if (!desc->hwdescs.mem) | |
670 | return; | |
671 | ||
672 | desc->hwdescs.size = size; | |
673 | } | |
674 | ||
ee4b876b JB |
675 | static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan, |
676 | struct rcar_dmac_desc *desc) | |
ccadee9b LP |
677 | { |
678 | struct rcar_dmac_xfer_chunk *chunk; | |
679 | struct rcar_dmac_hw_desc *hwdesc; | |
ccadee9b | 680 | |
1ed1315f LP |
681 | rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc)); |
682 | ||
683 | hwdesc = desc->hwdescs.mem; | |
ccadee9b | 684 | if (!hwdesc) |
ee4b876b | 685 | return -ENOMEM; |
ccadee9b | 686 | |
ccadee9b LP |
687 | list_for_each_entry(chunk, &desc->chunks, node) { |
688 | hwdesc->sar = chunk->src_addr; | |
689 | hwdesc->dar = chunk->dst_addr; | |
690 | hwdesc->tcr = chunk->size >> desc->xfer_shift; | |
691 | hwdesc++; | |
692 | } | |
ee4b876b JB |
693 | |
694 | return 0; | |
ccadee9b LP |
695 | } |
696 | ||
87244fe5 LP |
697 | /* ----------------------------------------------------------------------------- |
698 | * Stop and reset | |
699 | */ | |
700 | ||
701 | static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan) | |
702 | { | |
703 | u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
704 | ||
ccadee9b LP |
705 | chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE | |
706 | RCAR_DMACHCR_TE | RCAR_DMACHCR_DE); | |
87244fe5 LP |
707 | rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr); |
708 | } | |
709 | ||
710 | static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan) | |
711 | { | |
712 | struct rcar_dmac_desc *desc, *_desc; | |
713 | unsigned long flags; | |
714 | LIST_HEAD(descs); | |
715 | ||
716 | spin_lock_irqsave(&chan->lock, flags); | |
717 | ||
718 | /* Move all non-free descriptors to the local lists. */ | |
719 | list_splice_init(&chan->desc.pending, &descs); | |
720 | list_splice_init(&chan->desc.active, &descs); | |
721 | list_splice_init(&chan->desc.done, &descs); | |
722 | list_splice_init(&chan->desc.wait, &descs); | |
723 | ||
724 | chan->desc.running = NULL; | |
725 | ||
726 | spin_unlock_irqrestore(&chan->lock, flags); | |
727 | ||
728 | list_for_each_entry_safe(desc, _desc, &descs, node) { | |
729 | list_del(&desc->node); | |
730 | rcar_dmac_desc_put(chan, desc); | |
731 | } | |
732 | } | |
733 | ||
734 | static void rcar_dmac_stop(struct rcar_dmac *dmac) | |
735 | { | |
736 | rcar_dmac_write(dmac, RCAR_DMAOR, 0); | |
737 | } | |
738 | ||
739 | static void rcar_dmac_abort(struct rcar_dmac *dmac) | |
740 | { | |
741 | unsigned int i; | |
742 | ||
743 | /* Stop all channels. */ | |
744 | for (i = 0; i < dmac->n_channels; ++i) { | |
745 | struct rcar_dmac_chan *chan = &dmac->channels[i]; | |
746 | ||
747 | /* Stop and reinitialize the channel. */ | |
748 | spin_lock(&chan->lock); | |
749 | rcar_dmac_chan_halt(chan); | |
750 | spin_unlock(&chan->lock); | |
751 | ||
752 | rcar_dmac_chan_reinit(chan); | |
753 | } | |
754 | } | |
755 | ||
756 | /* ----------------------------------------------------------------------------- | |
757 | * Descriptors preparation | |
758 | */ | |
759 | ||
760 | static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan, | |
761 | struct rcar_dmac_desc *desc) | |
762 | { | |
763 | static const u32 chcr_ts[] = { | |
764 | RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B, | |
765 | RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B, | |
766 | RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B, | |
767 | RCAR_DMACHCR_TS_64B, | |
768 | }; | |
769 | ||
770 | unsigned int xfer_size; | |
771 | u32 chcr; | |
772 | ||
773 | switch (desc->direction) { | |
774 | case DMA_DEV_TO_MEM: | |
775 | chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED | |
776 | | RCAR_DMACHCR_RS_DMARS; | |
777 | xfer_size = chan->src_xfer_size; | |
778 | break; | |
779 | ||
780 | case DMA_MEM_TO_DEV: | |
781 | chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC | |
782 | | RCAR_DMACHCR_RS_DMARS; | |
783 | xfer_size = chan->dst_xfer_size; | |
784 | break; | |
785 | ||
786 | case DMA_MEM_TO_MEM: | |
787 | default: | |
788 | chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC | |
789 | | RCAR_DMACHCR_RS_AUTO; | |
790 | xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE; | |
791 | break; | |
792 | } | |
793 | ||
794 | desc->xfer_shift = ilog2(xfer_size); | |
795 | desc->chcr = chcr | chcr_ts[desc->xfer_shift]; | |
796 | } | |
797 | ||
798 | /* | |
799 | * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list | |
800 | * | |
801 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
802 | * converted to scatter-gather to guarantee consistent locking and a correct | |
803 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
804 | * logically, the SG list is RAM and the addr variable contains slave address, | |
805 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM | |
806 | * and the SG list contains only one element and points at the source buffer. | |
807 | */ | |
808 | static struct dma_async_tx_descriptor * | |
809 | rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl, | |
810 | unsigned int sg_len, dma_addr_t dev_addr, | |
811 | enum dma_transfer_direction dir, unsigned long dma_flags, | |
812 | bool cyclic) | |
813 | { | |
814 | struct rcar_dmac_xfer_chunk *chunk; | |
815 | struct rcar_dmac_desc *desc; | |
816 | struct scatterlist *sg; | |
ccadee9b | 817 | unsigned int nchunks = 0; |
87244fe5 LP |
818 | unsigned int max_chunk_size; |
819 | unsigned int full_size = 0; | |
ccadee9b | 820 | bool highmem = false; |
87244fe5 LP |
821 | unsigned int i; |
822 | ||
823 | desc = rcar_dmac_desc_get(chan); | |
824 | if (!desc) | |
825 | return NULL; | |
826 | ||
827 | desc->async_tx.flags = dma_flags; | |
828 | desc->async_tx.cookie = -EBUSY; | |
829 | ||
830 | desc->cyclic = cyclic; | |
831 | desc->direction = dir; | |
832 | ||
833 | rcar_dmac_chan_configure_desc(chan, desc); | |
834 | ||
835 | max_chunk_size = (RCAR_DMATCR_MASK + 1) << desc->xfer_shift; | |
836 | ||
837 | /* | |
838 | * Allocate and fill the transfer chunk descriptors. We own the only | |
839 | * reference to the DMA descriptor, there's no need for locking. | |
840 | */ | |
841 | for_each_sg(sgl, sg, sg_len, i) { | |
842 | dma_addr_t mem_addr = sg_dma_address(sg); | |
843 | unsigned int len = sg_dma_len(sg); | |
844 | ||
845 | full_size += len; | |
846 | ||
847 | while (len) { | |
848 | unsigned int size = min(len, max_chunk_size); | |
849 | ||
850 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
851 | /* | |
852 | * Prevent individual transfers from crossing 4GB | |
853 | * boundaries. | |
854 | */ | |
855 | if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) | |
856 | size = ALIGN(dev_addr, 1ULL << 32) - dev_addr; | |
857 | if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) | |
858 | size = ALIGN(mem_addr, 1ULL << 32) - mem_addr; | |
ccadee9b LP |
859 | |
860 | /* | |
861 | * Check if either of the source or destination address | |
862 | * can't be expressed in 32 bits. If so we can't use | |
863 | * hardware descriptor lists. | |
864 | */ | |
865 | if (dev_addr >> 32 || mem_addr >> 32) | |
866 | highmem = true; | |
87244fe5 LP |
867 | #endif |
868 | ||
869 | chunk = rcar_dmac_xfer_chunk_get(chan); | |
870 | if (!chunk) { | |
871 | rcar_dmac_desc_put(chan, desc); | |
872 | return NULL; | |
873 | } | |
874 | ||
875 | if (dir == DMA_DEV_TO_MEM) { | |
876 | chunk->src_addr = dev_addr; | |
877 | chunk->dst_addr = mem_addr; | |
878 | } else { | |
879 | chunk->src_addr = mem_addr; | |
880 | chunk->dst_addr = dev_addr; | |
881 | } | |
882 | ||
883 | chunk->size = size; | |
884 | ||
885 | dev_dbg(chan->chan.device->dev, | |
886 | "chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n", | |
887 | chan->index, chunk, desc, i, sg, size, len, | |
888 | &chunk->src_addr, &chunk->dst_addr); | |
889 | ||
890 | mem_addr += size; | |
891 | if (dir == DMA_MEM_TO_MEM) | |
892 | dev_addr += size; | |
893 | ||
894 | len -= size; | |
895 | ||
896 | list_add_tail(&chunk->node, &desc->chunks); | |
ccadee9b | 897 | nchunks++; |
87244fe5 LP |
898 | } |
899 | } | |
900 | ||
ccadee9b | 901 | desc->nchunks = nchunks; |
87244fe5 LP |
902 | desc->size = full_size; |
903 | ||
ccadee9b LP |
904 | /* |
905 | * Use hardware descriptor lists if possible when more than one chunk | |
906 | * needs to be transferred (otherwise they don't make much sense). | |
907 | * | |
908 | * The highmem check currently covers the whole transfer. As an | |
909 | * optimization we could use descriptor lists for consecutive lowmem | |
910 | * chunks and direct manual mode for highmem chunks. Whether the | |
911 | * performance improvement would be significant enough compared to the | |
912 | * additional complexity remains to be investigated. | |
913 | */ | |
1ed1315f | 914 | desc->hwdescs.use = !highmem && nchunks > 1; |
ee4b876b JB |
915 | if (desc->hwdescs.use) { |
916 | if (rcar_dmac_fill_hwdesc(chan, desc) < 0) | |
917 | desc->hwdescs.use = false; | |
918 | } | |
ccadee9b | 919 | |
87244fe5 LP |
920 | return &desc->async_tx; |
921 | } | |
922 | ||
923 | /* ----------------------------------------------------------------------------- | |
924 | * DMA engine operations | |
925 | */ | |
926 | ||
927 | static int rcar_dmac_alloc_chan_resources(struct dma_chan *chan) | |
928 | { | |
929 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
930 | int ret; | |
931 | ||
87244fe5 LP |
932 | INIT_LIST_HEAD(&rchan->desc.chunks_free); |
933 | INIT_LIST_HEAD(&rchan->desc.pages); | |
934 | ||
935 | /* Preallocate descriptors. */ | |
936 | ret = rcar_dmac_xfer_chunk_alloc(rchan, GFP_KERNEL); | |
937 | if (ret < 0) | |
938 | return -ENOMEM; | |
939 | ||
940 | ret = rcar_dmac_desc_alloc(rchan, GFP_KERNEL); | |
941 | if (ret < 0) | |
942 | return -ENOMEM; | |
943 | ||
944 | return pm_runtime_get_sync(chan->device->dev); | |
945 | } | |
946 | ||
947 | static void rcar_dmac_free_chan_resources(struct dma_chan *chan) | |
948 | { | |
949 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
950 | struct rcar_dmac *dmac = to_rcar_dmac(chan->device); | |
951 | struct rcar_dmac_desc_page *page, *_page; | |
1ed1315f LP |
952 | struct rcar_dmac_desc *desc; |
953 | LIST_HEAD(list); | |
87244fe5 LP |
954 | |
955 | /* Protect against ISR */ | |
956 | spin_lock_irq(&rchan->lock); | |
957 | rcar_dmac_chan_halt(rchan); | |
958 | spin_unlock_irq(&rchan->lock); | |
959 | ||
960 | /* Now no new interrupts will occur */ | |
961 | ||
962 | if (rchan->mid_rid >= 0) { | |
963 | /* The caller is holding dma_list_mutex */ | |
964 | clear_bit(rchan->mid_rid, dmac->modules); | |
965 | rchan->mid_rid = -EINVAL; | |
966 | } | |
967 | ||
f7638c90 LP |
968 | list_splice_init(&rchan->desc.free, &list); |
969 | list_splice_init(&rchan->desc.pending, &list); | |
970 | list_splice_init(&rchan->desc.active, &list); | |
971 | list_splice_init(&rchan->desc.done, &list); | |
972 | list_splice_init(&rchan->desc.wait, &list); | |
1ed1315f LP |
973 | |
974 | list_for_each_entry(desc, &list, node) | |
975 | rcar_dmac_realloc_hwdesc(rchan, desc, 0); | |
976 | ||
87244fe5 LP |
977 | list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) { |
978 | list_del(&page->node); | |
979 | free_page((unsigned long)page); | |
980 | } | |
981 | ||
982 | pm_runtime_put(chan->device->dev); | |
983 | } | |
984 | ||
985 | static struct dma_async_tx_descriptor * | |
986 | rcar_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, | |
987 | dma_addr_t dma_src, size_t len, unsigned long flags) | |
988 | { | |
989 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
990 | struct scatterlist sgl; | |
991 | ||
992 | if (!len) | |
993 | return NULL; | |
994 | ||
995 | sg_init_table(&sgl, 1); | |
996 | sg_set_page(&sgl, pfn_to_page(PFN_DOWN(dma_src)), len, | |
997 | offset_in_page(dma_src)); | |
998 | sg_dma_address(&sgl) = dma_src; | |
999 | sg_dma_len(&sgl) = len; | |
1000 | ||
1001 | return rcar_dmac_chan_prep_sg(rchan, &sgl, 1, dma_dest, | |
1002 | DMA_MEM_TO_MEM, flags, false); | |
1003 | } | |
1004 | ||
1005 | static struct dma_async_tx_descriptor * | |
1006 | rcar_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
1007 | unsigned int sg_len, enum dma_transfer_direction dir, | |
1008 | unsigned long flags, void *context) | |
1009 | { | |
1010 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1011 | dma_addr_t dev_addr; | |
1012 | ||
1013 | /* Someone calling slave DMA on a generic channel? */ | |
1014 | if (rchan->mid_rid < 0 || !sg_len) { | |
1015 | dev_warn(chan->device->dev, | |
1016 | "%s: bad parameter: len=%d, id=%d\n", | |
1017 | __func__, sg_len, rchan->mid_rid); | |
1018 | return NULL; | |
1019 | } | |
1020 | ||
1021 | dev_addr = dir == DMA_DEV_TO_MEM | |
1022 | ? rchan->src_slave_addr : rchan->dst_slave_addr; | |
1023 | return rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, dev_addr, | |
1024 | dir, flags, false); | |
1025 | } | |
1026 | ||
1027 | #define RCAR_DMAC_MAX_SG_LEN 32 | |
1028 | ||
1029 | static struct dma_async_tx_descriptor * | |
1030 | rcar_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, | |
1031 | size_t buf_len, size_t period_len, | |
1032 | enum dma_transfer_direction dir, unsigned long flags) | |
1033 | { | |
1034 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1035 | struct dma_async_tx_descriptor *desc; | |
1036 | struct scatterlist *sgl; | |
1037 | dma_addr_t dev_addr; | |
1038 | unsigned int sg_len; | |
1039 | unsigned int i; | |
1040 | ||
1041 | /* Someone calling slave DMA on a generic channel? */ | |
1042 | if (rchan->mid_rid < 0 || buf_len < period_len) { | |
1043 | dev_warn(chan->device->dev, | |
1044 | "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n", | |
1045 | __func__, buf_len, period_len, rchan->mid_rid); | |
1046 | return NULL; | |
1047 | } | |
1048 | ||
1049 | sg_len = buf_len / period_len; | |
1050 | if (sg_len > RCAR_DMAC_MAX_SG_LEN) { | |
1051 | dev_err(chan->device->dev, | |
1052 | "chan%u: sg length %d exceds limit %d", | |
1053 | rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN); | |
1054 | return NULL; | |
1055 | } | |
1056 | ||
1057 | /* | |
1058 | * Allocate the sg list dynamically as it would consume too much stack | |
1059 | * space. | |
1060 | */ | |
1061 | sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT); | |
1062 | if (!sgl) | |
1063 | return NULL; | |
1064 | ||
1065 | sg_init_table(sgl, sg_len); | |
1066 | ||
1067 | for (i = 0; i < sg_len; ++i) { | |
1068 | dma_addr_t src = buf_addr + (period_len * i); | |
1069 | ||
1070 | sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len, | |
1071 | offset_in_page(src)); | |
1072 | sg_dma_address(&sgl[i]) = src; | |
1073 | sg_dma_len(&sgl[i]) = period_len; | |
1074 | } | |
1075 | ||
1076 | dev_addr = dir == DMA_DEV_TO_MEM | |
1077 | ? rchan->src_slave_addr : rchan->dst_slave_addr; | |
1078 | desc = rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, dev_addr, | |
1079 | dir, flags, true); | |
1080 | ||
1081 | kfree(sgl); | |
1082 | return desc; | |
1083 | } | |
1084 | ||
1085 | static int rcar_dmac_device_config(struct dma_chan *chan, | |
1086 | struct dma_slave_config *cfg) | |
1087 | { | |
1088 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1089 | ||
1090 | /* | |
1091 | * We could lock this, but you shouldn't be configuring the | |
1092 | * channel, while using it... | |
1093 | */ | |
1094 | rchan->src_slave_addr = cfg->src_addr; | |
1095 | rchan->dst_slave_addr = cfg->dst_addr; | |
1096 | rchan->src_xfer_size = cfg->src_addr_width; | |
1097 | rchan->dst_xfer_size = cfg->dst_addr_width; | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int rcar_dmac_chan_terminate_all(struct dma_chan *chan) | |
1103 | { | |
1104 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1105 | unsigned long flags; | |
1106 | ||
1107 | spin_lock_irqsave(&rchan->lock, flags); | |
1108 | rcar_dmac_chan_halt(rchan); | |
1109 | spin_unlock_irqrestore(&rchan->lock, flags); | |
1110 | ||
1111 | /* | |
1112 | * FIXME: No new interrupt can occur now, but the IRQ thread might still | |
1113 | * be running. | |
1114 | */ | |
1115 | ||
1116 | rcar_dmac_chan_reinit(rchan); | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan, | |
1122 | dma_cookie_t cookie) | |
1123 | { | |
1124 | struct rcar_dmac_desc *desc = chan->desc.running; | |
ccadee9b | 1125 | struct rcar_dmac_xfer_chunk *running = NULL; |
87244fe5 LP |
1126 | struct rcar_dmac_xfer_chunk *chunk; |
1127 | unsigned int residue = 0; | |
ccadee9b | 1128 | unsigned int dptr = 0; |
87244fe5 LP |
1129 | |
1130 | if (!desc) | |
1131 | return 0; | |
1132 | ||
1133 | /* | |
1134 | * If the cookie doesn't correspond to the currently running transfer | |
1135 | * then the descriptor hasn't been processed yet, and the residue is | |
1136 | * equal to the full descriptor size. | |
1137 | */ | |
1138 | if (cookie != desc->async_tx.cookie) | |
1139 | return desc->size; | |
1140 | ||
ccadee9b LP |
1141 | /* |
1142 | * In descriptor mode the descriptor running pointer is not maintained | |
1143 | * by the interrupt handler, find the running descriptor from the | |
1144 | * descriptor pointer field in the CHCRB register. In non-descriptor | |
1145 | * mode just use the running descriptor pointer. | |
1146 | */ | |
1ed1315f | 1147 | if (desc->hwdescs.use) { |
ccadee9b LP |
1148 | dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) & |
1149 | RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT; | |
1150 | WARN_ON(dptr >= desc->nchunks); | |
1151 | } else { | |
1152 | running = desc->running; | |
1153 | } | |
1154 | ||
87244fe5 LP |
1155 | /* Compute the size of all chunks still to be transferred. */ |
1156 | list_for_each_entry_reverse(chunk, &desc->chunks, node) { | |
ccadee9b | 1157 | if (chunk == running || ++dptr == desc->nchunks) |
87244fe5 LP |
1158 | break; |
1159 | ||
1160 | residue += chunk->size; | |
1161 | } | |
1162 | ||
1163 | /* Add the residue for the current chunk. */ | |
1164 | residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift; | |
1165 | ||
1166 | return residue; | |
1167 | } | |
1168 | ||
1169 | static enum dma_status rcar_dmac_tx_status(struct dma_chan *chan, | |
1170 | dma_cookie_t cookie, | |
1171 | struct dma_tx_state *txstate) | |
1172 | { | |
1173 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1174 | enum dma_status status; | |
1175 | unsigned long flags; | |
1176 | unsigned int residue; | |
1177 | ||
1178 | status = dma_cookie_status(chan, cookie, txstate); | |
1179 | if (status == DMA_COMPLETE || !txstate) | |
1180 | return status; | |
1181 | ||
1182 | spin_lock_irqsave(&rchan->lock, flags); | |
1183 | residue = rcar_dmac_chan_get_residue(rchan, cookie); | |
1184 | spin_unlock_irqrestore(&rchan->lock, flags); | |
1185 | ||
1186 | dma_set_residue(txstate, residue); | |
1187 | ||
1188 | return status; | |
1189 | } | |
1190 | ||
1191 | static void rcar_dmac_issue_pending(struct dma_chan *chan) | |
1192 | { | |
1193 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1194 | unsigned long flags; | |
1195 | ||
1196 | spin_lock_irqsave(&rchan->lock, flags); | |
1197 | ||
1198 | if (list_empty(&rchan->desc.pending)) | |
1199 | goto done; | |
1200 | ||
1201 | /* Append the pending list to the active list. */ | |
1202 | list_splice_tail_init(&rchan->desc.pending, &rchan->desc.active); | |
1203 | ||
1204 | /* | |
1205 | * If no transfer is running pick the first descriptor from the active | |
1206 | * list and start the transfer. | |
1207 | */ | |
1208 | if (!rchan->desc.running) { | |
1209 | struct rcar_dmac_desc *desc; | |
1210 | ||
1211 | desc = list_first_entry(&rchan->desc.active, | |
1212 | struct rcar_dmac_desc, node); | |
1213 | rchan->desc.running = desc; | |
1214 | ||
1215 | rcar_dmac_chan_start_xfer(rchan); | |
1216 | } | |
1217 | ||
1218 | done: | |
1219 | spin_unlock_irqrestore(&rchan->lock, flags); | |
1220 | } | |
1221 | ||
1222 | /* ----------------------------------------------------------------------------- | |
1223 | * IRQ handling | |
1224 | */ | |
1225 | ||
ccadee9b LP |
1226 | static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan) |
1227 | { | |
1228 | struct rcar_dmac_desc *desc = chan->desc.running; | |
1229 | unsigned int stage; | |
1230 | ||
1231 | if (WARN_ON(!desc || !desc->cyclic)) { | |
1232 | /* | |
1233 | * This should never happen, there should always be a running | |
1234 | * cyclic descriptor when a descriptor stage end interrupt is | |
1235 | * triggered. Warn and return. | |
1236 | */ | |
1237 | return IRQ_NONE; | |
1238 | } | |
1239 | ||
1240 | /* Program the interrupt pointer to the next stage. */ | |
1241 | stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) & | |
1242 | RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT; | |
1243 | rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage)); | |
1244 | ||
1245 | return IRQ_WAKE_THREAD; | |
1246 | } | |
1247 | ||
87244fe5 LP |
1248 | static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan) |
1249 | { | |
1250 | struct rcar_dmac_desc *desc = chan->desc.running; | |
87244fe5 LP |
1251 | irqreturn_t ret = IRQ_WAKE_THREAD; |
1252 | ||
1253 | if (WARN_ON_ONCE(!desc)) { | |
1254 | /* | |
ccadee9b LP |
1255 | * This should never happen, there should always be a running |
1256 | * descriptor when a transfer end interrupt is triggered. Warn | |
1257 | * and return. | |
87244fe5 LP |
1258 | */ |
1259 | return IRQ_NONE; | |
1260 | } | |
1261 | ||
1262 | /* | |
ccadee9b LP |
1263 | * The transfer end interrupt isn't generated for each chunk when using |
1264 | * descriptor mode. Only update the running chunk pointer in | |
1265 | * non-descriptor mode. | |
87244fe5 | 1266 | */ |
1ed1315f | 1267 | if (!desc->hwdescs.use) { |
ccadee9b LP |
1268 | /* |
1269 | * If we haven't completed the last transfer chunk simply move | |
1270 | * to the next one. Only wake the IRQ thread if the transfer is | |
1271 | * cyclic. | |
1272 | */ | |
1273 | if (!list_is_last(&desc->running->node, &desc->chunks)) { | |
1274 | desc->running = list_next_entry(desc->running, node); | |
1275 | if (!desc->cyclic) | |
1276 | ret = IRQ_HANDLED; | |
1277 | goto done; | |
1278 | } | |
87244fe5 | 1279 | |
ccadee9b LP |
1280 | /* |
1281 | * We've completed the last transfer chunk. If the transfer is | |
1282 | * cyclic, move back to the first one. | |
1283 | */ | |
1284 | if (desc->cyclic) { | |
1285 | desc->running = | |
1286 | list_first_entry(&desc->chunks, | |
87244fe5 LP |
1287 | struct rcar_dmac_xfer_chunk, |
1288 | node); | |
ccadee9b LP |
1289 | goto done; |
1290 | } | |
87244fe5 LP |
1291 | } |
1292 | ||
1293 | /* The descriptor is complete, move it to the done list. */ | |
1294 | list_move_tail(&desc->node, &chan->desc.done); | |
1295 | ||
1296 | /* Queue the next descriptor, if any. */ | |
1297 | if (!list_empty(&chan->desc.active)) | |
1298 | chan->desc.running = list_first_entry(&chan->desc.active, | |
1299 | struct rcar_dmac_desc, | |
1300 | node); | |
1301 | else | |
1302 | chan->desc.running = NULL; | |
1303 | ||
1304 | done: | |
1305 | if (chan->desc.running) | |
1306 | rcar_dmac_chan_start_xfer(chan); | |
1307 | ||
1308 | return ret; | |
1309 | } | |
1310 | ||
1311 | static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev) | |
1312 | { | |
ccadee9b | 1313 | u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE; |
87244fe5 LP |
1314 | struct rcar_dmac_chan *chan = dev; |
1315 | irqreturn_t ret = IRQ_NONE; | |
1316 | u32 chcr; | |
1317 | ||
1318 | spin_lock(&chan->lock); | |
1319 | ||
1320 | chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
ccadee9b LP |
1321 | if (chcr & RCAR_DMACHCR_TE) |
1322 | mask |= RCAR_DMACHCR_DE; | |
1323 | rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask); | |
1324 | ||
1325 | if (chcr & RCAR_DMACHCR_DSE) | |
1326 | ret |= rcar_dmac_isr_desc_stage_end(chan); | |
87244fe5 LP |
1327 | |
1328 | if (chcr & RCAR_DMACHCR_TE) | |
1329 | ret |= rcar_dmac_isr_transfer_end(chan); | |
1330 | ||
1331 | spin_unlock(&chan->lock); | |
1332 | ||
1333 | return ret; | |
1334 | } | |
1335 | ||
1336 | static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev) | |
1337 | { | |
1338 | struct rcar_dmac_chan *chan = dev; | |
1339 | struct rcar_dmac_desc *desc; | |
1340 | ||
1341 | spin_lock_irq(&chan->lock); | |
1342 | ||
1343 | /* For cyclic transfers notify the user after every chunk. */ | |
1344 | if (chan->desc.running && chan->desc.running->cyclic) { | |
1345 | dma_async_tx_callback callback; | |
1346 | void *callback_param; | |
1347 | ||
1348 | desc = chan->desc.running; | |
1349 | callback = desc->async_tx.callback; | |
1350 | callback_param = desc->async_tx.callback_param; | |
1351 | ||
1352 | if (callback) { | |
1353 | spin_unlock_irq(&chan->lock); | |
1354 | callback(callback_param); | |
1355 | spin_lock_irq(&chan->lock); | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | /* | |
1360 | * Call the callback function for all descriptors on the done list and | |
1361 | * move them to the ack wait list. | |
1362 | */ | |
1363 | while (!list_empty(&chan->desc.done)) { | |
1364 | desc = list_first_entry(&chan->desc.done, struct rcar_dmac_desc, | |
1365 | node); | |
1366 | dma_cookie_complete(&desc->async_tx); | |
1367 | list_del(&desc->node); | |
1368 | ||
1369 | if (desc->async_tx.callback) { | |
1370 | spin_unlock_irq(&chan->lock); | |
1371 | /* | |
1372 | * We own the only reference to this descriptor, we can | |
1373 | * safely dereference it without holding the channel | |
1374 | * lock. | |
1375 | */ | |
1376 | desc->async_tx.callback(desc->async_tx.callback_param); | |
1377 | spin_lock_irq(&chan->lock); | |
1378 | } | |
1379 | ||
1380 | list_add_tail(&desc->node, &chan->desc.wait); | |
1381 | } | |
1382 | ||
ccadee9b LP |
1383 | spin_unlock_irq(&chan->lock); |
1384 | ||
87244fe5 LP |
1385 | /* Recycle all acked descriptors. */ |
1386 | rcar_dmac_desc_recycle_acked(chan); | |
1387 | ||
87244fe5 LP |
1388 | return IRQ_HANDLED; |
1389 | } | |
1390 | ||
1391 | static irqreturn_t rcar_dmac_isr_error(int irq, void *data) | |
1392 | { | |
1393 | struct rcar_dmac *dmac = data; | |
1394 | ||
1395 | if (!(rcar_dmac_read(dmac, RCAR_DMAOR) & RCAR_DMAOR_AE)) | |
1396 | return IRQ_NONE; | |
1397 | ||
1398 | /* | |
1399 | * An unrecoverable error occurred on an unknown channel. Halt the DMAC, | |
1400 | * abort transfers on all channels, and reinitialize the DMAC. | |
1401 | */ | |
1402 | rcar_dmac_stop(dmac); | |
1403 | rcar_dmac_abort(dmac); | |
1404 | rcar_dmac_init(dmac); | |
1405 | ||
1406 | return IRQ_HANDLED; | |
1407 | } | |
1408 | ||
1409 | /* ----------------------------------------------------------------------------- | |
1410 | * OF xlate and channel filter | |
1411 | */ | |
1412 | ||
1413 | static bool rcar_dmac_chan_filter(struct dma_chan *chan, void *arg) | |
1414 | { | |
1415 | struct rcar_dmac *dmac = to_rcar_dmac(chan->device); | |
1416 | struct of_phandle_args *dma_spec = arg; | |
1417 | ||
1418 | /* | |
1419 | * FIXME: Using a filter on OF platforms is a nonsense. The OF xlate | |
1420 | * function knows from which device it wants to allocate a channel from, | |
1421 | * and would be perfectly capable of selecting the channel it wants. | |
1422 | * Forcing it to call dma_request_channel() and iterate through all | |
1423 | * channels from all controllers is just pointless. | |
1424 | */ | |
1425 | if (chan->device->device_config != rcar_dmac_device_config || | |
1426 | dma_spec->np != chan->device->dev->of_node) | |
1427 | return false; | |
1428 | ||
1429 | return !test_and_set_bit(dma_spec->args[0], dmac->modules); | |
1430 | } | |
1431 | ||
1432 | static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec, | |
1433 | struct of_dma *ofdma) | |
1434 | { | |
1435 | struct rcar_dmac_chan *rchan; | |
1436 | struct dma_chan *chan; | |
1437 | dma_cap_mask_t mask; | |
1438 | ||
1439 | if (dma_spec->args_count != 1) | |
1440 | return NULL; | |
1441 | ||
1442 | /* Only slave DMA channels can be allocated via DT */ | |
1443 | dma_cap_zero(mask); | |
1444 | dma_cap_set(DMA_SLAVE, mask); | |
1445 | ||
1446 | chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec); | |
1447 | if (!chan) | |
1448 | return NULL; | |
1449 | ||
1450 | rchan = to_rcar_dmac_chan(chan); | |
1451 | rchan->mid_rid = dma_spec->args[0]; | |
1452 | ||
1453 | return chan; | |
1454 | } | |
1455 | ||
1456 | /* ----------------------------------------------------------------------------- | |
1457 | * Power management | |
1458 | */ | |
1459 | ||
1460 | #ifdef CONFIG_PM_SLEEP | |
1461 | static int rcar_dmac_sleep_suspend(struct device *dev) | |
1462 | { | |
1463 | /* | |
1464 | * TODO: Wait for the current transfer to complete and stop the device. | |
1465 | */ | |
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | static int rcar_dmac_sleep_resume(struct device *dev) | |
1470 | { | |
1471 | /* TODO: Resume transfers, if any. */ | |
1472 | return 0; | |
1473 | } | |
1474 | #endif | |
1475 | ||
1476 | #ifdef CONFIG_PM | |
1477 | static int rcar_dmac_runtime_suspend(struct device *dev) | |
1478 | { | |
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | static int rcar_dmac_runtime_resume(struct device *dev) | |
1483 | { | |
1484 | struct rcar_dmac *dmac = dev_get_drvdata(dev); | |
1485 | ||
1486 | return rcar_dmac_init(dmac); | |
1487 | } | |
1488 | #endif | |
1489 | ||
1490 | static const struct dev_pm_ops rcar_dmac_pm = { | |
1491 | SET_SYSTEM_SLEEP_PM_OPS(rcar_dmac_sleep_suspend, rcar_dmac_sleep_resume) | |
1492 | SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume, | |
1493 | NULL) | |
1494 | }; | |
1495 | ||
1496 | /* ----------------------------------------------------------------------------- | |
1497 | * Probe and remove | |
1498 | */ | |
1499 | ||
1500 | static int rcar_dmac_chan_probe(struct rcar_dmac *dmac, | |
1501 | struct rcar_dmac_chan *rchan, | |
1502 | unsigned int index) | |
1503 | { | |
1504 | struct platform_device *pdev = to_platform_device(dmac->dev); | |
1505 | struct dma_chan *chan = &rchan->chan; | |
1506 | char pdev_irqname[5]; | |
1507 | char *irqname; | |
1508 | int irq; | |
1509 | int ret; | |
1510 | ||
1511 | rchan->index = index; | |
1512 | rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index); | |
1513 | rchan->mid_rid = -EINVAL; | |
1514 | ||
1515 | spin_lock_init(&rchan->lock); | |
1516 | ||
f7638c90 LP |
1517 | INIT_LIST_HEAD(&rchan->desc.free); |
1518 | INIT_LIST_HEAD(&rchan->desc.pending); | |
1519 | INIT_LIST_HEAD(&rchan->desc.active); | |
1520 | INIT_LIST_HEAD(&rchan->desc.done); | |
1521 | INIT_LIST_HEAD(&rchan->desc.wait); | |
1522 | ||
87244fe5 LP |
1523 | /* Request the channel interrupt. */ |
1524 | sprintf(pdev_irqname, "ch%u", index); | |
1525 | irq = platform_get_irq_byname(pdev, pdev_irqname); | |
1526 | if (irq < 0) { | |
1527 | dev_err(dmac->dev, "no IRQ specified for channel %u\n", index); | |
1528 | return -ENODEV; | |
1529 | } | |
1530 | ||
1531 | irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u", | |
1532 | dev_name(dmac->dev), index); | |
1533 | if (!irqname) | |
1534 | return -ENOMEM; | |
1535 | ||
1536 | ret = devm_request_threaded_irq(dmac->dev, irq, rcar_dmac_isr_channel, | |
1537 | rcar_dmac_isr_channel_thread, 0, | |
1538 | irqname, rchan); | |
1539 | if (ret) { | |
1540 | dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", irq, ret); | |
1541 | return ret; | |
1542 | } | |
1543 | ||
1544 | /* | |
1545 | * Initialize the DMA engine channel and add it to the DMA engine | |
1546 | * channels list. | |
1547 | */ | |
1548 | chan->device = &dmac->engine; | |
1549 | dma_cookie_init(chan); | |
1550 | ||
1551 | list_add_tail(&chan->device_node, &dmac->engine.channels); | |
1552 | ||
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac) | |
1557 | { | |
1558 | struct device_node *np = dev->of_node; | |
1559 | int ret; | |
1560 | ||
1561 | ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels); | |
1562 | if (ret < 0) { | |
1563 | dev_err(dev, "unable to read dma-channels property\n"); | |
1564 | return ret; | |
1565 | } | |
1566 | ||
1567 | if (dmac->n_channels <= 0 || dmac->n_channels >= 100) { | |
1568 | dev_err(dev, "invalid number of channels %u\n", | |
1569 | dmac->n_channels); | |
1570 | return -EINVAL; | |
1571 | } | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | static int rcar_dmac_probe(struct platform_device *pdev) | |
1577 | { | |
1578 | const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE | | |
1579 | DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES | | |
1580 | DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES | | |
1581 | DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES; | |
1582 | struct dma_device *engine; | |
1583 | struct rcar_dmac *dmac; | |
1584 | struct resource *mem; | |
1585 | unsigned int i; | |
1586 | char *irqname; | |
1587 | int irq; | |
1588 | int ret; | |
1589 | ||
1590 | dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL); | |
1591 | if (!dmac) | |
1592 | return -ENOMEM; | |
1593 | ||
1594 | dmac->dev = &pdev->dev; | |
1595 | platform_set_drvdata(pdev, dmac); | |
1596 | ||
1597 | ret = rcar_dmac_parse_of(&pdev->dev, dmac); | |
1598 | if (ret < 0) | |
1599 | return ret; | |
1600 | ||
1601 | dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels, | |
1602 | sizeof(*dmac->channels), GFP_KERNEL); | |
1603 | if (!dmac->channels) | |
1604 | return -ENOMEM; | |
1605 | ||
1606 | /* Request resources. */ | |
1607 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1608 | dmac->iomem = devm_ioremap_resource(&pdev->dev, mem); | |
1609 | if (IS_ERR(dmac->iomem)) | |
1610 | return PTR_ERR(dmac->iomem); | |
1611 | ||
1612 | irq = platform_get_irq_byname(pdev, "error"); | |
1613 | if (irq < 0) { | |
1614 | dev_err(&pdev->dev, "no error IRQ specified\n"); | |
1615 | return -ENODEV; | |
1616 | } | |
1617 | ||
1618 | irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:error", | |
1619 | dev_name(dmac->dev)); | |
1620 | if (!irqname) | |
1621 | return -ENOMEM; | |
1622 | ||
1623 | ret = devm_request_irq(&pdev->dev, irq, rcar_dmac_isr_error, 0, | |
1624 | irqname, dmac); | |
1625 | if (ret) { | |
1626 | dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n", | |
1627 | irq, ret); | |
1628 | return ret; | |
1629 | } | |
1630 | ||
1631 | /* Enable runtime PM and initialize the device. */ | |
1632 | pm_runtime_enable(&pdev->dev); | |
1633 | ret = pm_runtime_get_sync(&pdev->dev); | |
1634 | if (ret < 0) { | |
1635 | dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret); | |
1636 | return ret; | |
1637 | } | |
1638 | ||
1639 | ret = rcar_dmac_init(dmac); | |
1640 | pm_runtime_put(&pdev->dev); | |
1641 | ||
1642 | if (ret) { | |
1643 | dev_err(&pdev->dev, "failed to reset device\n"); | |
1644 | goto error; | |
1645 | } | |
1646 | ||
1647 | /* Initialize the channels. */ | |
1648 | INIT_LIST_HEAD(&dmac->engine.channels); | |
1649 | ||
1650 | for (i = 0; i < dmac->n_channels; ++i) { | |
1651 | ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], i); | |
1652 | if (ret < 0) | |
1653 | goto error; | |
1654 | } | |
1655 | ||
1656 | /* Register the DMAC as a DMA provider for DT. */ | |
1657 | ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate, | |
1658 | NULL); | |
1659 | if (ret < 0) | |
1660 | goto error; | |
1661 | ||
1662 | /* | |
1663 | * Register the DMA engine device. | |
1664 | * | |
1665 | * Default transfer size of 32 bytes requires 32-byte alignment. | |
1666 | */ | |
1667 | engine = &dmac->engine; | |
1668 | dma_cap_set(DMA_MEMCPY, engine->cap_mask); | |
1669 | dma_cap_set(DMA_SLAVE, engine->cap_mask); | |
1670 | ||
1671 | engine->dev = &pdev->dev; | |
1672 | engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE); | |
1673 | ||
1674 | engine->src_addr_widths = widths; | |
1675 | engine->dst_addr_widths = widths; | |
1676 | engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); | |
1677 | engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1678 | ||
1679 | engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources; | |
1680 | engine->device_free_chan_resources = rcar_dmac_free_chan_resources; | |
1681 | engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy; | |
1682 | engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg; | |
1683 | engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic; | |
1684 | engine->device_config = rcar_dmac_device_config; | |
1685 | engine->device_terminate_all = rcar_dmac_chan_terminate_all; | |
1686 | engine->device_tx_status = rcar_dmac_tx_status; | |
1687 | engine->device_issue_pending = rcar_dmac_issue_pending; | |
1688 | ||
1689 | ret = dma_async_device_register(engine); | |
1690 | if (ret < 0) | |
1691 | goto error; | |
1692 | ||
1693 | return 0; | |
1694 | ||
1695 | error: | |
1696 | of_dma_controller_free(pdev->dev.of_node); | |
1697 | pm_runtime_disable(&pdev->dev); | |
1698 | return ret; | |
1699 | } | |
1700 | ||
1701 | static int rcar_dmac_remove(struct platform_device *pdev) | |
1702 | { | |
1703 | struct rcar_dmac *dmac = platform_get_drvdata(pdev); | |
1704 | ||
1705 | of_dma_controller_free(pdev->dev.of_node); | |
1706 | dma_async_device_unregister(&dmac->engine); | |
1707 | ||
1708 | pm_runtime_disable(&pdev->dev); | |
1709 | ||
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | static void rcar_dmac_shutdown(struct platform_device *pdev) | |
1714 | { | |
1715 | struct rcar_dmac *dmac = platform_get_drvdata(pdev); | |
1716 | ||
1717 | rcar_dmac_stop(dmac); | |
1718 | } | |
1719 | ||
1720 | static const struct of_device_id rcar_dmac_of_ids[] = { | |
1721 | { .compatible = "renesas,rcar-dmac", }, | |
1722 | { /* Sentinel */ } | |
1723 | }; | |
1724 | MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids); | |
1725 | ||
1726 | static struct platform_driver rcar_dmac_driver = { | |
1727 | .driver = { | |
1728 | .pm = &rcar_dmac_pm, | |
1729 | .name = "rcar-dmac", | |
1730 | .of_match_table = rcar_dmac_of_ids, | |
1731 | }, | |
1732 | .probe = rcar_dmac_probe, | |
1733 | .remove = rcar_dmac_remove, | |
1734 | .shutdown = rcar_dmac_shutdown, | |
1735 | }; | |
1736 | ||
1737 | module_platform_driver(rcar_dmac_driver); | |
1738 | ||
1739 | MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver"); | |
1740 | MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); | |
1741 | MODULE_LICENSE("GPL v2"); |