Commit | Line | Data |
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87244fe5 LP |
1 | /* |
2 | * Renesas R-Car Gen2 DMA Controller Driver | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Inc. | |
5 | * | |
6 | * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
7 | * | |
8 | * This is free software; you can redistribute it and/or modify | |
9 | * it under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
a8d46a7f | 13 | #include <linux/delay.h> |
ccadee9b | 14 | #include <linux/dma-mapping.h> |
87244fe5 LP |
15 | #include <linux/dmaengine.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/mutex.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_dma.h> | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
28 | #include "../dmaengine.h" | |
29 | ||
30 | /* | |
31 | * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer | |
32 | * @node: entry in the parent's chunks list | |
33 | * @src_addr: device source address | |
34 | * @dst_addr: device destination address | |
35 | * @size: transfer size in bytes | |
36 | */ | |
37 | struct rcar_dmac_xfer_chunk { | |
38 | struct list_head node; | |
39 | ||
40 | dma_addr_t src_addr; | |
41 | dma_addr_t dst_addr; | |
42 | u32 size; | |
43 | }; | |
44 | ||
ccadee9b LP |
45 | /* |
46 | * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk | |
47 | * @sar: value of the SAR register (source address) | |
48 | * @dar: value of the DAR register (destination address) | |
49 | * @tcr: value of the TCR register (transfer count) | |
50 | */ | |
51 | struct rcar_dmac_hw_desc { | |
52 | u32 sar; | |
53 | u32 dar; | |
54 | u32 tcr; | |
55 | u32 reserved; | |
56 | } __attribute__((__packed__)); | |
57 | ||
87244fe5 LP |
58 | /* |
59 | * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor | |
60 | * @async_tx: base DMA asynchronous transaction descriptor | |
61 | * @direction: direction of the DMA transfer | |
62 | * @xfer_shift: log2 of the transfer size | |
63 | * @chcr: value of the channel configuration register for this transfer | |
64 | * @node: entry in the channel's descriptors lists | |
65 | * @chunks: list of transfer chunks for this transfer | |
66 | * @running: the transfer chunk being currently processed | |
ccadee9b | 67 | * @nchunks: number of transfer chunks for this transfer |
1ed1315f | 68 | * @hwdescs.use: whether the transfer descriptor uses hardware descriptors |
ccadee9b LP |
69 | * @hwdescs.mem: hardware descriptors memory for the transfer |
70 | * @hwdescs.dma: device address of the hardware descriptors memory | |
71 | * @hwdescs.size: size of the hardware descriptors in bytes | |
87244fe5 LP |
72 | * @size: transfer size in bytes |
73 | * @cyclic: when set indicates that the DMA transfer is cyclic | |
74 | */ | |
75 | struct rcar_dmac_desc { | |
76 | struct dma_async_tx_descriptor async_tx; | |
77 | enum dma_transfer_direction direction; | |
78 | unsigned int xfer_shift; | |
79 | u32 chcr; | |
80 | ||
81 | struct list_head node; | |
82 | struct list_head chunks; | |
83 | struct rcar_dmac_xfer_chunk *running; | |
ccadee9b LP |
84 | unsigned int nchunks; |
85 | ||
86 | struct { | |
1ed1315f | 87 | bool use; |
ccadee9b LP |
88 | struct rcar_dmac_hw_desc *mem; |
89 | dma_addr_t dma; | |
90 | size_t size; | |
91 | } hwdescs; | |
87244fe5 LP |
92 | |
93 | unsigned int size; | |
94 | bool cyclic; | |
95 | }; | |
96 | ||
97 | #define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx) | |
98 | ||
99 | /* | |
100 | * struct rcar_dmac_desc_page - One page worth of descriptors | |
101 | * @node: entry in the channel's pages list | |
102 | * @descs: array of DMA descriptors | |
103 | * @chunks: array of transfer chunk descriptors | |
104 | */ | |
105 | struct rcar_dmac_desc_page { | |
106 | struct list_head node; | |
107 | ||
108 | union { | |
109 | struct rcar_dmac_desc descs[0]; | |
110 | struct rcar_dmac_xfer_chunk chunks[0]; | |
111 | }; | |
112 | }; | |
113 | ||
114 | #define RCAR_DMAC_DESCS_PER_PAGE \ | |
115 | ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \ | |
116 | sizeof(struct rcar_dmac_desc)) | |
117 | #define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \ | |
118 | ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \ | |
119 | sizeof(struct rcar_dmac_xfer_chunk)) | |
120 | ||
c5ed08e9 NS |
121 | /* |
122 | * struct rcar_dmac_chan_slave - Slave configuration | |
123 | * @slave_addr: slave memory address | |
124 | * @xfer_size: size (in bytes) of hardware transfers | |
125 | */ | |
126 | struct rcar_dmac_chan_slave { | |
127 | phys_addr_t slave_addr; | |
128 | unsigned int xfer_size; | |
129 | }; | |
130 | ||
9f878603 NS |
131 | /* |
132 | * struct rcar_dmac_chan_map - Map of slave device phys to dma address | |
133 | * @addr: slave dma address | |
134 | * @dir: direction of mapping | |
135 | * @slave: slave configuration that is mapped | |
136 | */ | |
137 | struct rcar_dmac_chan_map { | |
138 | dma_addr_t addr; | |
139 | enum dma_data_direction dir; | |
140 | struct rcar_dmac_chan_slave slave; | |
141 | }; | |
142 | ||
87244fe5 LP |
143 | /* |
144 | * struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel | |
145 | * @chan: base DMA channel object | |
146 | * @iomem: channel I/O memory base | |
147 | * @index: index of this channel in the controller | |
427d5ecd | 148 | * @irq: channel IRQ |
c5ed08e9 NS |
149 | * @src: slave memory address and size on the source side |
150 | * @dst: slave memory address and size on the destination side | |
87244fe5 LP |
151 | * @mid_rid: hardware MID/RID for the DMA client using this channel |
152 | * @lock: protects the channel CHCR register and the desc members | |
153 | * @desc.free: list of free descriptors | |
154 | * @desc.pending: list of pending descriptors (submitted with tx_submit) | |
155 | * @desc.active: list of active descriptors (activated with issue_pending) | |
156 | * @desc.done: list of completed descriptors | |
157 | * @desc.wait: list of descriptors waiting for an ack | |
158 | * @desc.running: the descriptor being processed (a member of the active list) | |
159 | * @desc.chunks_free: list of free transfer chunk descriptors | |
160 | * @desc.pages: list of pages used by allocated descriptors | |
161 | */ | |
162 | struct rcar_dmac_chan { | |
163 | struct dma_chan chan; | |
164 | void __iomem *iomem; | |
165 | unsigned int index; | |
427d5ecd | 166 | int irq; |
87244fe5 | 167 | |
c5ed08e9 NS |
168 | struct rcar_dmac_chan_slave src; |
169 | struct rcar_dmac_chan_slave dst; | |
9f878603 | 170 | struct rcar_dmac_chan_map map; |
87244fe5 LP |
171 | int mid_rid; |
172 | ||
173 | spinlock_t lock; | |
174 | ||
175 | struct { | |
176 | struct list_head free; | |
177 | struct list_head pending; | |
178 | struct list_head active; | |
179 | struct list_head done; | |
180 | struct list_head wait; | |
181 | struct rcar_dmac_desc *running; | |
182 | ||
183 | struct list_head chunks_free; | |
184 | ||
185 | struct list_head pages; | |
186 | } desc; | |
187 | }; | |
188 | ||
189 | #define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan) | |
190 | ||
191 | /* | |
192 | * struct rcar_dmac - R-Car Gen2 DMA Controller | |
193 | * @engine: base DMA engine object | |
194 | * @dev: the hardware device | |
195 | * @iomem: remapped I/O memory base | |
196 | * @n_channels: number of available channels | |
197 | * @channels: array of DMAC channels | |
198 | * @modules: bitmask of client modules in use | |
199 | */ | |
200 | struct rcar_dmac { | |
201 | struct dma_device engine; | |
202 | struct device *dev; | |
203 | void __iomem *iomem; | |
204 | ||
205 | unsigned int n_channels; | |
206 | struct rcar_dmac_chan *channels; | |
207 | ||
08acf38e | 208 | DECLARE_BITMAP(modules, 256); |
87244fe5 LP |
209 | }; |
210 | ||
211 | #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine) | |
212 | ||
213 | /* ----------------------------------------------------------------------------- | |
214 | * Registers | |
215 | */ | |
216 | ||
217 | #define RCAR_DMAC_CHAN_OFFSET(i) (0x8000 + 0x80 * (i)) | |
218 | ||
219 | #define RCAR_DMAISTA 0x0020 | |
220 | #define RCAR_DMASEC 0x0030 | |
221 | #define RCAR_DMAOR 0x0060 | |
222 | #define RCAR_DMAOR_PRI_FIXED (0 << 8) | |
223 | #define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8) | |
224 | #define RCAR_DMAOR_AE (1 << 2) | |
225 | #define RCAR_DMAOR_DME (1 << 0) | |
226 | #define RCAR_DMACHCLR 0x0080 | |
227 | #define RCAR_DMADPSEC 0x00a0 | |
228 | ||
229 | #define RCAR_DMASAR 0x0000 | |
230 | #define RCAR_DMADAR 0x0004 | |
231 | #define RCAR_DMATCR 0x0008 | |
232 | #define RCAR_DMATCR_MASK 0x00ffffff | |
233 | #define RCAR_DMATSR 0x0028 | |
234 | #define RCAR_DMACHCR 0x000c | |
235 | #define RCAR_DMACHCR_CAE (1 << 31) | |
236 | #define RCAR_DMACHCR_CAIE (1 << 30) | |
237 | #define RCAR_DMACHCR_DPM_DISABLED (0 << 28) | |
238 | #define RCAR_DMACHCR_DPM_ENABLED (1 << 28) | |
239 | #define RCAR_DMACHCR_DPM_REPEAT (2 << 28) | |
240 | #define RCAR_DMACHCR_DPM_INFINITE (3 << 28) | |
241 | #define RCAR_DMACHCR_RPT_SAR (1 << 27) | |
242 | #define RCAR_DMACHCR_RPT_DAR (1 << 26) | |
243 | #define RCAR_DMACHCR_RPT_TCR (1 << 25) | |
244 | #define RCAR_DMACHCR_DPB (1 << 22) | |
245 | #define RCAR_DMACHCR_DSE (1 << 19) | |
246 | #define RCAR_DMACHCR_DSIE (1 << 18) | |
247 | #define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3)) | |
248 | #define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3)) | |
249 | #define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3)) | |
250 | #define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3)) | |
251 | #define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3)) | |
252 | #define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3)) | |
253 | #define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3)) | |
254 | #define RCAR_DMACHCR_DM_FIXED (0 << 14) | |
255 | #define RCAR_DMACHCR_DM_INC (1 << 14) | |
256 | #define RCAR_DMACHCR_DM_DEC (2 << 14) | |
257 | #define RCAR_DMACHCR_SM_FIXED (0 << 12) | |
258 | #define RCAR_DMACHCR_SM_INC (1 << 12) | |
259 | #define RCAR_DMACHCR_SM_DEC (2 << 12) | |
260 | #define RCAR_DMACHCR_RS_AUTO (4 << 8) | |
261 | #define RCAR_DMACHCR_RS_DMARS (8 << 8) | |
262 | #define RCAR_DMACHCR_IE (1 << 2) | |
263 | #define RCAR_DMACHCR_TE (1 << 1) | |
264 | #define RCAR_DMACHCR_DE (1 << 0) | |
265 | #define RCAR_DMATCRB 0x0018 | |
266 | #define RCAR_DMATSRB 0x0038 | |
267 | #define RCAR_DMACHCRB 0x001c | |
268 | #define RCAR_DMACHCRB_DCNT(n) ((n) << 24) | |
ccadee9b LP |
269 | #define RCAR_DMACHCRB_DPTR_MASK (0xff << 16) |
270 | #define RCAR_DMACHCRB_DPTR_SHIFT 16 | |
87244fe5 LP |
271 | #define RCAR_DMACHCRB_DRST (1 << 15) |
272 | #define RCAR_DMACHCRB_DTS (1 << 8) | |
273 | #define RCAR_DMACHCRB_SLM_NORMAL (0 << 4) | |
274 | #define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4) | |
275 | #define RCAR_DMACHCRB_PRI(n) ((n) << 0) | |
276 | #define RCAR_DMARS 0x0040 | |
277 | #define RCAR_DMABUFCR 0x0048 | |
278 | #define RCAR_DMABUFCR_MBU(n) ((n) << 16) | |
279 | #define RCAR_DMABUFCR_ULB(n) ((n) << 0) | |
280 | #define RCAR_DMADPBASE 0x0050 | |
281 | #define RCAR_DMADPBASE_MASK 0xfffffff0 | |
282 | #define RCAR_DMADPBASE_SEL (1 << 0) | |
283 | #define RCAR_DMADPCR 0x0054 | |
284 | #define RCAR_DMADPCR_DIPT(n) ((n) << 24) | |
285 | #define RCAR_DMAFIXSAR 0x0010 | |
286 | #define RCAR_DMAFIXDAR 0x0014 | |
287 | #define RCAR_DMAFIXDPBASE 0x0060 | |
288 | ||
289 | /* Hardcode the MEMCPY transfer size to 4 bytes. */ | |
290 | #define RCAR_DMAC_MEMCPY_XFER_SIZE 4 | |
291 | ||
292 | /* ----------------------------------------------------------------------------- | |
293 | * Device access | |
294 | */ | |
295 | ||
296 | static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data) | |
297 | { | |
298 | if (reg == RCAR_DMAOR) | |
299 | writew(data, dmac->iomem + reg); | |
300 | else | |
301 | writel(data, dmac->iomem + reg); | |
302 | } | |
303 | ||
304 | static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg) | |
305 | { | |
306 | if (reg == RCAR_DMAOR) | |
307 | return readw(dmac->iomem + reg); | |
308 | else | |
309 | return readl(dmac->iomem + reg); | |
310 | } | |
311 | ||
312 | static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg) | |
313 | { | |
314 | if (reg == RCAR_DMARS) | |
315 | return readw(chan->iomem + reg); | |
316 | else | |
317 | return readl(chan->iomem + reg); | |
318 | } | |
319 | ||
320 | static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data) | |
321 | { | |
322 | if (reg == RCAR_DMARS) | |
323 | writew(data, chan->iomem + reg); | |
324 | else | |
325 | writel(data, chan->iomem + reg); | |
326 | } | |
327 | ||
328 | /* ----------------------------------------------------------------------------- | |
329 | * Initialization and configuration | |
330 | */ | |
331 | ||
332 | static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan) | |
333 | { | |
334 | u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
335 | ||
0f78e3b5 | 336 | return !!(chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE)); |
87244fe5 LP |
337 | } |
338 | ||
339 | static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan) | |
340 | { | |
341 | struct rcar_dmac_desc *desc = chan->desc.running; | |
ccadee9b | 342 | u32 chcr = desc->chcr; |
87244fe5 LP |
343 | |
344 | WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan)); | |
345 | ||
ccadee9b LP |
346 | if (chan->mid_rid >= 0) |
347 | rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid); | |
348 | ||
1ed1315f | 349 | if (desc->hwdescs.use) { |
1175f83c KM |
350 | struct rcar_dmac_xfer_chunk *chunk = |
351 | list_first_entry(&desc->chunks, | |
352 | struct rcar_dmac_xfer_chunk, node); | |
3f463061 | 353 | |
ccadee9b LP |
354 | dev_dbg(chan->chan.device->dev, |
355 | "chan%u: queue desc %p: %u@%pad\n", | |
356 | chan->index, desc, desc->nchunks, &desc->hwdescs.dma); | |
357 | ||
87244fe5 | 358 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
1175f83c KM |
359 | rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR, |
360 | chunk->src_addr >> 32); | |
361 | rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR, | |
362 | chunk->dst_addr >> 32); | |
ccadee9b LP |
363 | rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE, |
364 | desc->hwdescs.dma >> 32); | |
87244fe5 | 365 | #endif |
ccadee9b LP |
366 | rcar_dmac_chan_write(chan, RCAR_DMADPBASE, |
367 | (desc->hwdescs.dma & 0xfffffff0) | | |
368 | RCAR_DMADPBASE_SEL); | |
369 | rcar_dmac_chan_write(chan, RCAR_DMACHCRB, | |
370 | RCAR_DMACHCRB_DCNT(desc->nchunks - 1) | | |
371 | RCAR_DMACHCRB_DRST); | |
87244fe5 | 372 | |
3f463061 LP |
373 | /* |
374 | * Errata: When descriptor memory is accessed through an IOMMU | |
375 | * the DMADAR register isn't initialized automatically from the | |
376 | * first descriptor at beginning of transfer by the DMAC like it | |
377 | * should. Initialize it manually with the destination address | |
378 | * of the first chunk. | |
379 | */ | |
3f463061 LP |
380 | rcar_dmac_chan_write(chan, RCAR_DMADAR, |
381 | chunk->dst_addr & 0xffffffff); | |
382 | ||
ccadee9b LP |
383 | /* |
384 | * Program the descriptor stage interrupt to occur after the end | |
385 | * of the first stage. | |
386 | */ | |
387 | rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1)); | |
388 | ||
389 | chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR | |
390 | | RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB; | |
391 | ||
392 | /* | |
393 | * If the descriptor isn't cyclic enable normal descriptor mode | |
394 | * and the transfer completion interrupt. | |
395 | */ | |
396 | if (!desc->cyclic) | |
397 | chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE; | |
398 | /* | |
399 | * If the descriptor is cyclic and has a callback enable the | |
400 | * descriptor stage interrupt in infinite repeat mode. | |
401 | */ | |
402 | else if (desc->async_tx.callback) | |
403 | chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE; | |
404 | /* | |
405 | * Otherwise just select infinite repeat mode without any | |
406 | * interrupt. | |
407 | */ | |
408 | else | |
409 | chcr |= RCAR_DMACHCR_DPM_INFINITE; | |
410 | } else { | |
411 | struct rcar_dmac_xfer_chunk *chunk = desc->running; | |
87244fe5 | 412 | |
ccadee9b LP |
413 | dev_dbg(chan->chan.device->dev, |
414 | "chan%u: queue chunk %p: %u@%pad -> %pad\n", | |
415 | chan->index, chunk, chunk->size, &chunk->src_addr, | |
416 | &chunk->dst_addr); | |
87244fe5 | 417 | |
ccadee9b LP |
418 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
419 | rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR, | |
420 | chunk->src_addr >> 32); | |
421 | rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR, | |
422 | chunk->dst_addr >> 32); | |
423 | #endif | |
424 | rcar_dmac_chan_write(chan, RCAR_DMASAR, | |
425 | chunk->src_addr & 0xffffffff); | |
426 | rcar_dmac_chan_write(chan, RCAR_DMADAR, | |
427 | chunk->dst_addr & 0xffffffff); | |
428 | rcar_dmac_chan_write(chan, RCAR_DMATCR, | |
429 | chunk->size >> desc->xfer_shift); | |
430 | ||
431 | chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE; | |
432 | } | |
433 | ||
434 | rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE); | |
87244fe5 LP |
435 | } |
436 | ||
437 | static int rcar_dmac_init(struct rcar_dmac *dmac) | |
438 | { | |
439 | u16 dmaor; | |
440 | ||
441 | /* Clear all channels and enable the DMAC globally. */ | |
20c169ac | 442 | rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0)); |
87244fe5 LP |
443 | rcar_dmac_write(dmac, RCAR_DMAOR, |
444 | RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME); | |
445 | ||
446 | dmaor = rcar_dmac_read(dmac, RCAR_DMAOR); | |
447 | if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) { | |
448 | dev_warn(dmac->dev, "DMAOR initialization failed.\n"); | |
449 | return -EIO; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | /* ----------------------------------------------------------------------------- | |
456 | * Descriptors submission | |
457 | */ | |
458 | ||
459 | static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx) | |
460 | { | |
461 | struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan); | |
462 | struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx); | |
463 | unsigned long flags; | |
464 | dma_cookie_t cookie; | |
465 | ||
466 | spin_lock_irqsave(&chan->lock, flags); | |
467 | ||
468 | cookie = dma_cookie_assign(tx); | |
469 | ||
470 | dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n", | |
471 | chan->index, tx->cookie, desc); | |
472 | ||
473 | list_add_tail(&desc->node, &chan->desc.pending); | |
474 | desc->running = list_first_entry(&desc->chunks, | |
475 | struct rcar_dmac_xfer_chunk, node); | |
476 | ||
477 | spin_unlock_irqrestore(&chan->lock, flags); | |
478 | ||
479 | return cookie; | |
480 | } | |
481 | ||
482 | /* ----------------------------------------------------------------------------- | |
483 | * Descriptors allocation and free | |
484 | */ | |
485 | ||
486 | /* | |
487 | * rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors | |
488 | * @chan: the DMA channel | |
489 | * @gfp: allocation flags | |
490 | */ | |
491 | static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp) | |
492 | { | |
493 | struct rcar_dmac_desc_page *page; | |
d23c9a0a | 494 | unsigned long flags; |
87244fe5 LP |
495 | LIST_HEAD(list); |
496 | unsigned int i; | |
497 | ||
498 | page = (void *)get_zeroed_page(gfp); | |
499 | if (!page) | |
500 | return -ENOMEM; | |
501 | ||
502 | for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) { | |
503 | struct rcar_dmac_desc *desc = &page->descs[i]; | |
504 | ||
505 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan); | |
506 | desc->async_tx.tx_submit = rcar_dmac_tx_submit; | |
507 | INIT_LIST_HEAD(&desc->chunks); | |
508 | ||
509 | list_add_tail(&desc->node, &list); | |
510 | } | |
511 | ||
d23c9a0a | 512 | spin_lock_irqsave(&chan->lock, flags); |
87244fe5 LP |
513 | list_splice_tail(&list, &chan->desc.free); |
514 | list_add_tail(&page->node, &chan->desc.pages); | |
d23c9a0a | 515 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
520 | /* | |
521 | * rcar_dmac_desc_put - Release a DMA transfer descriptor | |
522 | * @chan: the DMA channel | |
523 | * @desc: the descriptor | |
524 | * | |
525 | * Put the descriptor and its transfer chunk descriptors back in the channel's | |
1ed1315f LP |
526 | * free descriptors lists. The descriptor's chunks list will be reinitialized to |
527 | * an empty list as a result. | |
87244fe5 | 528 | * |
ccadee9b LP |
529 | * The descriptor must have been removed from the channel's lists before calling |
530 | * this function. | |
87244fe5 LP |
531 | */ |
532 | static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan, | |
533 | struct rcar_dmac_desc *desc) | |
534 | { | |
f3915072 LP |
535 | unsigned long flags; |
536 | ||
537 | spin_lock_irqsave(&chan->lock, flags); | |
87244fe5 | 538 | list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free); |
3565fe53 | 539 | list_add(&desc->node, &chan->desc.free); |
f3915072 | 540 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
541 | } |
542 | ||
543 | static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan) | |
544 | { | |
545 | struct rcar_dmac_desc *desc, *_desc; | |
d23c9a0a | 546 | unsigned long flags; |
ccadee9b | 547 | LIST_HEAD(list); |
87244fe5 | 548 | |
ccadee9b LP |
549 | /* |
550 | * We have to temporarily move all descriptors from the wait list to a | |
551 | * local list as iterating over the wait list, even with | |
552 | * list_for_each_entry_safe, isn't safe if we release the channel lock | |
553 | * around the rcar_dmac_desc_put() call. | |
554 | */ | |
d23c9a0a | 555 | spin_lock_irqsave(&chan->lock, flags); |
ccadee9b | 556 | list_splice_init(&chan->desc.wait, &list); |
d23c9a0a | 557 | spin_unlock_irqrestore(&chan->lock, flags); |
ccadee9b LP |
558 | |
559 | list_for_each_entry_safe(desc, _desc, &list, node) { | |
87244fe5 LP |
560 | if (async_tx_test_ack(&desc->async_tx)) { |
561 | list_del(&desc->node); | |
562 | rcar_dmac_desc_put(chan, desc); | |
563 | } | |
564 | } | |
ccadee9b LP |
565 | |
566 | if (list_empty(&list)) | |
567 | return; | |
568 | ||
569 | /* Put the remaining descriptors back in the wait list. */ | |
d23c9a0a | 570 | spin_lock_irqsave(&chan->lock, flags); |
ccadee9b | 571 | list_splice(&list, &chan->desc.wait); |
d23c9a0a | 572 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
573 | } |
574 | ||
575 | /* | |
576 | * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer | |
577 | * @chan: the DMA channel | |
578 | * | |
579 | * Locking: This function must be called in a non-atomic context. | |
580 | * | |
581 | * Return: A pointer to the allocated descriptor or NULL if no descriptor can | |
582 | * be allocated. | |
583 | */ | |
584 | static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan) | |
585 | { | |
586 | struct rcar_dmac_desc *desc; | |
d23c9a0a | 587 | unsigned long flags; |
87244fe5 LP |
588 | int ret; |
589 | ||
87244fe5 LP |
590 | /* Recycle acked descriptors before attempting allocation. */ |
591 | rcar_dmac_desc_recycle_acked(chan); | |
592 | ||
d23c9a0a | 593 | spin_lock_irqsave(&chan->lock, flags); |
ccadee9b | 594 | |
a55e07c8 LP |
595 | while (list_empty(&chan->desc.free)) { |
596 | /* | |
597 | * No free descriptors, allocate a page worth of them and try | |
598 | * again, as someone else could race us to get the newly | |
599 | * allocated descriptors. If the allocation fails return an | |
600 | * error. | |
601 | */ | |
d23c9a0a | 602 | spin_unlock_irqrestore(&chan->lock, flags); |
a55e07c8 LP |
603 | ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT); |
604 | if (ret < 0) | |
605 | return NULL; | |
d23c9a0a | 606 | spin_lock_irqsave(&chan->lock, flags); |
a55e07c8 | 607 | } |
87244fe5 | 608 | |
a55e07c8 LP |
609 | desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc, node); |
610 | list_del(&desc->node); | |
87244fe5 | 611 | |
d23c9a0a | 612 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
613 | |
614 | return desc; | |
615 | } | |
616 | ||
617 | /* | |
618 | * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks | |
619 | * @chan: the DMA channel | |
620 | * @gfp: allocation flags | |
621 | */ | |
622 | static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp) | |
623 | { | |
624 | struct rcar_dmac_desc_page *page; | |
d23c9a0a | 625 | unsigned long flags; |
87244fe5 LP |
626 | LIST_HEAD(list); |
627 | unsigned int i; | |
628 | ||
629 | page = (void *)get_zeroed_page(gfp); | |
630 | if (!page) | |
631 | return -ENOMEM; | |
632 | ||
633 | for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) { | |
634 | struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i]; | |
635 | ||
636 | list_add_tail(&chunk->node, &list); | |
637 | } | |
638 | ||
d23c9a0a | 639 | spin_lock_irqsave(&chan->lock, flags); |
87244fe5 LP |
640 | list_splice_tail(&list, &chan->desc.chunks_free); |
641 | list_add_tail(&page->node, &chan->desc.pages); | |
d23c9a0a | 642 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
643 | |
644 | return 0; | |
645 | } | |
646 | ||
647 | /* | |
648 | * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer | |
649 | * @chan: the DMA channel | |
650 | * | |
651 | * Locking: This function must be called in a non-atomic context. | |
652 | * | |
653 | * Return: A pointer to the allocated transfer chunk descriptor or NULL if no | |
654 | * descriptor can be allocated. | |
655 | */ | |
656 | static struct rcar_dmac_xfer_chunk * | |
657 | rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan) | |
658 | { | |
659 | struct rcar_dmac_xfer_chunk *chunk; | |
d23c9a0a | 660 | unsigned long flags; |
87244fe5 LP |
661 | int ret; |
662 | ||
d23c9a0a | 663 | spin_lock_irqsave(&chan->lock, flags); |
87244fe5 | 664 | |
a55e07c8 LP |
665 | while (list_empty(&chan->desc.chunks_free)) { |
666 | /* | |
667 | * No free descriptors, allocate a page worth of them and try | |
668 | * again, as someone else could race us to get the newly | |
669 | * allocated descriptors. If the allocation fails return an | |
670 | * error. | |
671 | */ | |
d23c9a0a | 672 | spin_unlock_irqrestore(&chan->lock, flags); |
a55e07c8 LP |
673 | ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT); |
674 | if (ret < 0) | |
675 | return NULL; | |
d23c9a0a | 676 | spin_lock_irqsave(&chan->lock, flags); |
a55e07c8 | 677 | } |
87244fe5 | 678 | |
a55e07c8 LP |
679 | chunk = list_first_entry(&chan->desc.chunks_free, |
680 | struct rcar_dmac_xfer_chunk, node); | |
681 | list_del(&chunk->node); | |
87244fe5 | 682 | |
d23c9a0a | 683 | spin_unlock_irqrestore(&chan->lock, flags); |
87244fe5 LP |
684 | |
685 | return chunk; | |
686 | } | |
687 | ||
1ed1315f LP |
688 | static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan, |
689 | struct rcar_dmac_desc *desc, size_t size) | |
690 | { | |
691 | /* | |
692 | * dma_alloc_coherent() allocates memory in page size increments. To | |
693 | * avoid reallocating the hardware descriptors when the allocated size | |
694 | * wouldn't change align the requested size to a multiple of the page | |
695 | * size. | |
696 | */ | |
697 | size = PAGE_ALIGN(size); | |
698 | ||
699 | if (desc->hwdescs.size == size) | |
700 | return; | |
701 | ||
702 | if (desc->hwdescs.mem) { | |
6a634808 LP |
703 | dma_free_coherent(chan->chan.device->dev, desc->hwdescs.size, |
704 | desc->hwdescs.mem, desc->hwdescs.dma); | |
1ed1315f LP |
705 | desc->hwdescs.mem = NULL; |
706 | desc->hwdescs.size = 0; | |
707 | } | |
708 | ||
709 | if (!size) | |
710 | return; | |
711 | ||
6a634808 LP |
712 | desc->hwdescs.mem = dma_alloc_coherent(chan->chan.device->dev, size, |
713 | &desc->hwdescs.dma, GFP_NOWAIT); | |
1ed1315f LP |
714 | if (!desc->hwdescs.mem) |
715 | return; | |
716 | ||
717 | desc->hwdescs.size = size; | |
718 | } | |
719 | ||
ee4b876b JB |
720 | static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan, |
721 | struct rcar_dmac_desc *desc) | |
ccadee9b LP |
722 | { |
723 | struct rcar_dmac_xfer_chunk *chunk; | |
724 | struct rcar_dmac_hw_desc *hwdesc; | |
ccadee9b | 725 | |
1ed1315f LP |
726 | rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc)); |
727 | ||
728 | hwdesc = desc->hwdescs.mem; | |
ccadee9b | 729 | if (!hwdesc) |
ee4b876b | 730 | return -ENOMEM; |
ccadee9b | 731 | |
ccadee9b LP |
732 | list_for_each_entry(chunk, &desc->chunks, node) { |
733 | hwdesc->sar = chunk->src_addr; | |
734 | hwdesc->dar = chunk->dst_addr; | |
735 | hwdesc->tcr = chunk->size >> desc->xfer_shift; | |
736 | hwdesc++; | |
737 | } | |
ee4b876b JB |
738 | |
739 | return 0; | |
ccadee9b LP |
740 | } |
741 | ||
87244fe5 LP |
742 | /* ----------------------------------------------------------------------------- |
743 | * Stop and reset | |
744 | */ | |
a8d46a7f KM |
745 | static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan) |
746 | { | |
747 | u32 chcr; | |
748 | unsigned int i; | |
749 | ||
750 | /* | |
751 | * Ensure that the setting of the DE bit is actually 0 after | |
752 | * clearing it. | |
753 | */ | |
754 | for (i = 0; i < 1024; i++) { | |
755 | chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
756 | if (!(chcr & RCAR_DMACHCR_DE)) | |
757 | return; | |
758 | udelay(1); | |
759 | } | |
760 | ||
761 | dev_err(chan->chan.device->dev, "CHCR DE check error\n"); | |
762 | } | |
87244fe5 LP |
763 | |
764 | static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan) | |
765 | { | |
766 | u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
767 | ||
ccadee9b LP |
768 | chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE | |
769 | RCAR_DMACHCR_TE | RCAR_DMACHCR_DE); | |
87244fe5 | 770 | rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr); |
a8d46a7f | 771 | rcar_dmac_chcr_de_barrier(chan); |
87244fe5 LP |
772 | } |
773 | ||
774 | static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan) | |
775 | { | |
776 | struct rcar_dmac_desc *desc, *_desc; | |
777 | unsigned long flags; | |
778 | LIST_HEAD(descs); | |
779 | ||
780 | spin_lock_irqsave(&chan->lock, flags); | |
781 | ||
782 | /* Move all non-free descriptors to the local lists. */ | |
783 | list_splice_init(&chan->desc.pending, &descs); | |
784 | list_splice_init(&chan->desc.active, &descs); | |
785 | list_splice_init(&chan->desc.done, &descs); | |
786 | list_splice_init(&chan->desc.wait, &descs); | |
787 | ||
788 | chan->desc.running = NULL; | |
789 | ||
790 | spin_unlock_irqrestore(&chan->lock, flags); | |
791 | ||
792 | list_for_each_entry_safe(desc, _desc, &descs, node) { | |
793 | list_del(&desc->node); | |
794 | rcar_dmac_desc_put(chan, desc); | |
795 | } | |
796 | } | |
797 | ||
798 | static void rcar_dmac_stop(struct rcar_dmac *dmac) | |
799 | { | |
800 | rcar_dmac_write(dmac, RCAR_DMAOR, 0); | |
801 | } | |
802 | ||
803 | static void rcar_dmac_abort(struct rcar_dmac *dmac) | |
804 | { | |
805 | unsigned int i; | |
806 | ||
807 | /* Stop all channels. */ | |
808 | for (i = 0; i < dmac->n_channels; ++i) { | |
809 | struct rcar_dmac_chan *chan = &dmac->channels[i]; | |
810 | ||
811 | /* Stop and reinitialize the channel. */ | |
812 | spin_lock(&chan->lock); | |
813 | rcar_dmac_chan_halt(chan); | |
814 | spin_unlock(&chan->lock); | |
815 | ||
816 | rcar_dmac_chan_reinit(chan); | |
817 | } | |
818 | } | |
819 | ||
820 | /* ----------------------------------------------------------------------------- | |
821 | * Descriptors preparation | |
822 | */ | |
823 | ||
824 | static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan, | |
825 | struct rcar_dmac_desc *desc) | |
826 | { | |
827 | static const u32 chcr_ts[] = { | |
828 | RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B, | |
829 | RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B, | |
830 | RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B, | |
831 | RCAR_DMACHCR_TS_64B, | |
832 | }; | |
833 | ||
834 | unsigned int xfer_size; | |
835 | u32 chcr; | |
836 | ||
837 | switch (desc->direction) { | |
838 | case DMA_DEV_TO_MEM: | |
839 | chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED | |
840 | | RCAR_DMACHCR_RS_DMARS; | |
c5ed08e9 | 841 | xfer_size = chan->src.xfer_size; |
87244fe5 LP |
842 | break; |
843 | ||
844 | case DMA_MEM_TO_DEV: | |
845 | chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC | |
846 | | RCAR_DMACHCR_RS_DMARS; | |
c5ed08e9 | 847 | xfer_size = chan->dst.xfer_size; |
87244fe5 LP |
848 | break; |
849 | ||
850 | case DMA_MEM_TO_MEM: | |
851 | default: | |
852 | chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC | |
853 | | RCAR_DMACHCR_RS_AUTO; | |
854 | xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE; | |
855 | break; | |
856 | } | |
857 | ||
858 | desc->xfer_shift = ilog2(xfer_size); | |
859 | desc->chcr = chcr | chcr_ts[desc->xfer_shift]; | |
860 | } | |
861 | ||
862 | /* | |
863 | * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list | |
864 | * | |
865 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
866 | * converted to scatter-gather to guarantee consistent locking and a correct | |
867 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
868 | * logically, the SG list is RAM and the addr variable contains slave address, | |
869 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM | |
870 | * and the SG list contains only one element and points at the source buffer. | |
871 | */ | |
872 | static struct dma_async_tx_descriptor * | |
873 | rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl, | |
874 | unsigned int sg_len, dma_addr_t dev_addr, | |
875 | enum dma_transfer_direction dir, unsigned long dma_flags, | |
876 | bool cyclic) | |
877 | { | |
878 | struct rcar_dmac_xfer_chunk *chunk; | |
879 | struct rcar_dmac_desc *desc; | |
880 | struct scatterlist *sg; | |
ccadee9b | 881 | unsigned int nchunks = 0; |
87244fe5 LP |
882 | unsigned int max_chunk_size; |
883 | unsigned int full_size = 0; | |
1175f83c | 884 | bool cross_boundary = false; |
87244fe5 | 885 | unsigned int i; |
1175f83c KM |
886 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
887 | u32 high_dev_addr; | |
888 | u32 high_mem_addr; | |
889 | #endif | |
87244fe5 LP |
890 | |
891 | desc = rcar_dmac_desc_get(chan); | |
892 | if (!desc) | |
893 | return NULL; | |
894 | ||
895 | desc->async_tx.flags = dma_flags; | |
896 | desc->async_tx.cookie = -EBUSY; | |
897 | ||
898 | desc->cyclic = cyclic; | |
899 | desc->direction = dir; | |
900 | ||
901 | rcar_dmac_chan_configure_desc(chan, desc); | |
902 | ||
903 | max_chunk_size = (RCAR_DMATCR_MASK + 1) << desc->xfer_shift; | |
904 | ||
905 | /* | |
906 | * Allocate and fill the transfer chunk descriptors. We own the only | |
907 | * reference to the DMA descriptor, there's no need for locking. | |
908 | */ | |
909 | for_each_sg(sgl, sg, sg_len, i) { | |
910 | dma_addr_t mem_addr = sg_dma_address(sg); | |
911 | unsigned int len = sg_dma_len(sg); | |
912 | ||
913 | full_size += len; | |
914 | ||
1175f83c KM |
915 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
916 | if (i == 0) { | |
917 | high_dev_addr = dev_addr >> 32; | |
918 | high_mem_addr = mem_addr >> 32; | |
919 | } | |
920 | ||
921 | if ((dev_addr >> 32 != high_dev_addr) || | |
922 | (mem_addr >> 32 != high_mem_addr)) | |
923 | cross_boundary = true; | |
924 | #endif | |
87244fe5 LP |
925 | while (len) { |
926 | unsigned int size = min(len, max_chunk_size); | |
927 | ||
928 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
929 | /* | |
930 | * Prevent individual transfers from crossing 4GB | |
931 | * boundaries. | |
932 | */ | |
1175f83c | 933 | if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) { |
87244fe5 | 934 | size = ALIGN(dev_addr, 1ULL << 32) - dev_addr; |
1175f83c KM |
935 | cross_boundary = true; |
936 | } | |
937 | if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) { | |
87244fe5 | 938 | size = ALIGN(mem_addr, 1ULL << 32) - mem_addr; |
1175f83c KM |
939 | cross_boundary = true; |
940 | } | |
87244fe5 LP |
941 | #endif |
942 | ||
943 | chunk = rcar_dmac_xfer_chunk_get(chan); | |
944 | if (!chunk) { | |
945 | rcar_dmac_desc_put(chan, desc); | |
946 | return NULL; | |
947 | } | |
948 | ||
949 | if (dir == DMA_DEV_TO_MEM) { | |
950 | chunk->src_addr = dev_addr; | |
951 | chunk->dst_addr = mem_addr; | |
952 | } else { | |
953 | chunk->src_addr = mem_addr; | |
954 | chunk->dst_addr = dev_addr; | |
955 | } | |
956 | ||
957 | chunk->size = size; | |
958 | ||
959 | dev_dbg(chan->chan.device->dev, | |
960 | "chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n", | |
961 | chan->index, chunk, desc, i, sg, size, len, | |
962 | &chunk->src_addr, &chunk->dst_addr); | |
963 | ||
964 | mem_addr += size; | |
965 | if (dir == DMA_MEM_TO_MEM) | |
966 | dev_addr += size; | |
967 | ||
968 | len -= size; | |
969 | ||
970 | list_add_tail(&chunk->node, &desc->chunks); | |
ccadee9b | 971 | nchunks++; |
87244fe5 LP |
972 | } |
973 | } | |
974 | ||
ccadee9b | 975 | desc->nchunks = nchunks; |
87244fe5 LP |
976 | desc->size = full_size; |
977 | ||
ccadee9b LP |
978 | /* |
979 | * Use hardware descriptor lists if possible when more than one chunk | |
980 | * needs to be transferred (otherwise they don't make much sense). | |
981 | * | |
1175f83c KM |
982 | * Source/Destination address should be located in same 4GiB region |
983 | * in the 40bit address space when it uses Hardware descriptor, | |
984 | * and cross_boundary is checking it. | |
ccadee9b | 985 | */ |
1175f83c | 986 | desc->hwdescs.use = !cross_boundary && nchunks > 1; |
ee4b876b JB |
987 | if (desc->hwdescs.use) { |
988 | if (rcar_dmac_fill_hwdesc(chan, desc) < 0) | |
989 | desc->hwdescs.use = false; | |
990 | } | |
ccadee9b | 991 | |
87244fe5 LP |
992 | return &desc->async_tx; |
993 | } | |
994 | ||
995 | /* ----------------------------------------------------------------------------- | |
996 | * DMA engine operations | |
997 | */ | |
998 | ||
999 | static int rcar_dmac_alloc_chan_resources(struct dma_chan *chan) | |
1000 | { | |
1001 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1002 | int ret; | |
1003 | ||
87244fe5 LP |
1004 | INIT_LIST_HEAD(&rchan->desc.chunks_free); |
1005 | INIT_LIST_HEAD(&rchan->desc.pages); | |
1006 | ||
1007 | /* Preallocate descriptors. */ | |
1008 | ret = rcar_dmac_xfer_chunk_alloc(rchan, GFP_KERNEL); | |
1009 | if (ret < 0) | |
1010 | return -ENOMEM; | |
1011 | ||
1012 | ret = rcar_dmac_desc_alloc(rchan, GFP_KERNEL); | |
1013 | if (ret < 0) | |
1014 | return -ENOMEM; | |
1015 | ||
1016 | return pm_runtime_get_sync(chan->device->dev); | |
1017 | } | |
1018 | ||
1019 | static void rcar_dmac_free_chan_resources(struct dma_chan *chan) | |
1020 | { | |
1021 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1022 | struct rcar_dmac *dmac = to_rcar_dmac(chan->device); | |
3139dc8d | 1023 | struct rcar_dmac_chan_map *map = &rchan->map; |
87244fe5 | 1024 | struct rcar_dmac_desc_page *page, *_page; |
1ed1315f LP |
1025 | struct rcar_dmac_desc *desc; |
1026 | LIST_HEAD(list); | |
87244fe5 LP |
1027 | |
1028 | /* Protect against ISR */ | |
1029 | spin_lock_irq(&rchan->lock); | |
1030 | rcar_dmac_chan_halt(rchan); | |
1031 | spin_unlock_irq(&rchan->lock); | |
1032 | ||
a1ed64ef NS |
1033 | /* |
1034 | * Now no new interrupts will occur, but one might already be | |
1035 | * running. Wait for it to finish before freeing resources. | |
1036 | */ | |
1037 | synchronize_irq(rchan->irq); | |
87244fe5 LP |
1038 | |
1039 | if (rchan->mid_rid >= 0) { | |
1040 | /* The caller is holding dma_list_mutex */ | |
1041 | clear_bit(rchan->mid_rid, dmac->modules); | |
1042 | rchan->mid_rid = -EINVAL; | |
1043 | } | |
1044 | ||
f7638c90 LP |
1045 | list_splice_init(&rchan->desc.free, &list); |
1046 | list_splice_init(&rchan->desc.pending, &list); | |
1047 | list_splice_init(&rchan->desc.active, &list); | |
1048 | list_splice_init(&rchan->desc.done, &list); | |
1049 | list_splice_init(&rchan->desc.wait, &list); | |
1ed1315f | 1050 | |
48c73659 MHF |
1051 | rchan->desc.running = NULL; |
1052 | ||
1ed1315f LP |
1053 | list_for_each_entry(desc, &list, node) |
1054 | rcar_dmac_realloc_hwdesc(rchan, desc, 0); | |
1055 | ||
87244fe5 LP |
1056 | list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) { |
1057 | list_del(&page->node); | |
1058 | free_page((unsigned long)page); | |
1059 | } | |
1060 | ||
3139dc8d NS |
1061 | /* Remove slave mapping if present. */ |
1062 | if (map->slave.xfer_size) { | |
1063 | dma_unmap_resource(chan->device->dev, map->addr, | |
1064 | map->slave.xfer_size, map->dir, 0); | |
1065 | map->slave.xfer_size = 0; | |
1066 | } | |
1067 | ||
87244fe5 LP |
1068 | pm_runtime_put(chan->device->dev); |
1069 | } | |
1070 | ||
1071 | static struct dma_async_tx_descriptor * | |
1072 | rcar_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, | |
1073 | dma_addr_t dma_src, size_t len, unsigned long flags) | |
1074 | { | |
1075 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1076 | struct scatterlist sgl; | |
1077 | ||
1078 | if (!len) | |
1079 | return NULL; | |
1080 | ||
1081 | sg_init_table(&sgl, 1); | |
1082 | sg_set_page(&sgl, pfn_to_page(PFN_DOWN(dma_src)), len, | |
1083 | offset_in_page(dma_src)); | |
1084 | sg_dma_address(&sgl) = dma_src; | |
1085 | sg_dma_len(&sgl) = len; | |
1086 | ||
1087 | return rcar_dmac_chan_prep_sg(rchan, &sgl, 1, dma_dest, | |
1088 | DMA_MEM_TO_MEM, flags, false); | |
1089 | } | |
1090 | ||
9f878603 NS |
1091 | static int rcar_dmac_map_slave_addr(struct dma_chan *chan, |
1092 | enum dma_transfer_direction dir) | |
1093 | { | |
1094 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1095 | struct rcar_dmac_chan_map *map = &rchan->map; | |
1096 | phys_addr_t dev_addr; | |
1097 | size_t dev_size; | |
1098 | enum dma_data_direction dev_dir; | |
1099 | ||
1100 | if (dir == DMA_DEV_TO_MEM) { | |
1101 | dev_addr = rchan->src.slave_addr; | |
1102 | dev_size = rchan->src.xfer_size; | |
1103 | dev_dir = DMA_TO_DEVICE; | |
1104 | } else { | |
1105 | dev_addr = rchan->dst.slave_addr; | |
1106 | dev_size = rchan->dst.xfer_size; | |
1107 | dev_dir = DMA_FROM_DEVICE; | |
1108 | } | |
1109 | ||
1110 | /* Reuse current map if possible. */ | |
1111 | if (dev_addr == map->slave.slave_addr && | |
1112 | dev_size == map->slave.xfer_size && | |
1113 | dev_dir == map->dir) | |
1114 | return 0; | |
1115 | ||
1116 | /* Remove old mapping if present. */ | |
1117 | if (map->slave.xfer_size) | |
1118 | dma_unmap_resource(chan->device->dev, map->addr, | |
1119 | map->slave.xfer_size, map->dir, 0); | |
1120 | map->slave.xfer_size = 0; | |
1121 | ||
1122 | /* Create new slave address map. */ | |
1123 | map->addr = dma_map_resource(chan->device->dev, dev_addr, dev_size, | |
1124 | dev_dir, 0); | |
1125 | ||
1126 | if (dma_mapping_error(chan->device->dev, map->addr)) { | |
1127 | dev_err(chan->device->dev, | |
1128 | "chan%u: failed to map %zx@%pap", rchan->index, | |
1129 | dev_size, &dev_addr); | |
1130 | return -EIO; | |
1131 | } | |
1132 | ||
1133 | dev_dbg(chan->device->dev, "chan%u: map %zx@%pap to %pad dir: %s\n", | |
1134 | rchan->index, dev_size, &dev_addr, &map->addr, | |
1135 | dev_dir == DMA_TO_DEVICE ? "DMA_TO_DEVICE" : "DMA_FROM_DEVICE"); | |
1136 | ||
1137 | map->slave.slave_addr = dev_addr; | |
1138 | map->slave.xfer_size = dev_size; | |
1139 | map->dir = dev_dir; | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
87244fe5 LP |
1144 | static struct dma_async_tx_descriptor * |
1145 | rcar_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
1146 | unsigned int sg_len, enum dma_transfer_direction dir, | |
1147 | unsigned long flags, void *context) | |
1148 | { | |
1149 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
87244fe5 LP |
1150 | |
1151 | /* Someone calling slave DMA on a generic channel? */ | |
1152 | if (rchan->mid_rid < 0 || !sg_len) { | |
1153 | dev_warn(chan->device->dev, | |
1154 | "%s: bad parameter: len=%d, id=%d\n", | |
1155 | __func__, sg_len, rchan->mid_rid); | |
1156 | return NULL; | |
1157 | } | |
1158 | ||
9f878603 NS |
1159 | if (rcar_dmac_map_slave_addr(chan, dir)) |
1160 | return NULL; | |
1161 | ||
1162 | return rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, rchan->map.addr, | |
87244fe5 LP |
1163 | dir, flags, false); |
1164 | } | |
1165 | ||
1166 | #define RCAR_DMAC_MAX_SG_LEN 32 | |
1167 | ||
1168 | static struct dma_async_tx_descriptor * | |
1169 | rcar_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, | |
1170 | size_t buf_len, size_t period_len, | |
1171 | enum dma_transfer_direction dir, unsigned long flags) | |
1172 | { | |
1173 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1174 | struct dma_async_tx_descriptor *desc; | |
1175 | struct scatterlist *sgl; | |
87244fe5 LP |
1176 | unsigned int sg_len; |
1177 | unsigned int i; | |
1178 | ||
1179 | /* Someone calling slave DMA on a generic channel? */ | |
1180 | if (rchan->mid_rid < 0 || buf_len < period_len) { | |
1181 | dev_warn(chan->device->dev, | |
1182 | "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n", | |
1183 | __func__, buf_len, period_len, rchan->mid_rid); | |
1184 | return NULL; | |
1185 | } | |
1186 | ||
9f878603 NS |
1187 | if (rcar_dmac_map_slave_addr(chan, dir)) |
1188 | return NULL; | |
1189 | ||
87244fe5 LP |
1190 | sg_len = buf_len / period_len; |
1191 | if (sg_len > RCAR_DMAC_MAX_SG_LEN) { | |
1192 | dev_err(chan->device->dev, | |
1193 | "chan%u: sg length %d exceds limit %d", | |
1194 | rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN); | |
1195 | return NULL; | |
1196 | } | |
1197 | ||
1198 | /* | |
1199 | * Allocate the sg list dynamically as it would consume too much stack | |
1200 | * space. | |
1201 | */ | |
1202 | sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT); | |
1203 | if (!sgl) | |
1204 | return NULL; | |
1205 | ||
1206 | sg_init_table(sgl, sg_len); | |
1207 | ||
1208 | for (i = 0; i < sg_len; ++i) { | |
1209 | dma_addr_t src = buf_addr + (period_len * i); | |
1210 | ||
1211 | sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len, | |
1212 | offset_in_page(src)); | |
1213 | sg_dma_address(&sgl[i]) = src; | |
1214 | sg_dma_len(&sgl[i]) = period_len; | |
1215 | } | |
1216 | ||
9f878603 | 1217 | desc = rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, rchan->map.addr, |
87244fe5 LP |
1218 | dir, flags, true); |
1219 | ||
1220 | kfree(sgl); | |
1221 | return desc; | |
1222 | } | |
1223 | ||
1224 | static int rcar_dmac_device_config(struct dma_chan *chan, | |
1225 | struct dma_slave_config *cfg) | |
1226 | { | |
1227 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1228 | ||
1229 | /* | |
1230 | * We could lock this, but you shouldn't be configuring the | |
1231 | * channel, while using it... | |
1232 | */ | |
c5ed08e9 NS |
1233 | rchan->src.slave_addr = cfg->src_addr; |
1234 | rchan->dst.slave_addr = cfg->dst_addr; | |
1235 | rchan->src.xfer_size = cfg->src_addr_width; | |
1236 | rchan->dst.xfer_size = cfg->dst_addr_width; | |
87244fe5 LP |
1237 | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | static int rcar_dmac_chan_terminate_all(struct dma_chan *chan) | |
1242 | { | |
1243 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1244 | unsigned long flags; | |
1245 | ||
1246 | spin_lock_irqsave(&rchan->lock, flags); | |
1247 | rcar_dmac_chan_halt(rchan); | |
1248 | spin_unlock_irqrestore(&rchan->lock, flags); | |
1249 | ||
1250 | /* | |
1251 | * FIXME: No new interrupt can occur now, but the IRQ thread might still | |
1252 | * be running. | |
1253 | */ | |
1254 | ||
1255 | rcar_dmac_chan_reinit(rchan); | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan, | |
1261 | dma_cookie_t cookie) | |
1262 | { | |
1263 | struct rcar_dmac_desc *desc = chan->desc.running; | |
ccadee9b | 1264 | struct rcar_dmac_xfer_chunk *running = NULL; |
87244fe5 | 1265 | struct rcar_dmac_xfer_chunk *chunk; |
55bd582b | 1266 | enum dma_status status; |
87244fe5 | 1267 | unsigned int residue = 0; |
ccadee9b | 1268 | unsigned int dptr = 0; |
87244fe5 LP |
1269 | |
1270 | if (!desc) | |
1271 | return 0; | |
1272 | ||
55bd582b LP |
1273 | /* |
1274 | * If the cookie corresponds to a descriptor that has been completed | |
1275 | * there is no residue. The same check has already been performed by the | |
1276 | * caller but without holding the channel lock, so the descriptor could | |
1277 | * now be complete. | |
1278 | */ | |
1279 | status = dma_cookie_status(&chan->chan, cookie, NULL); | |
1280 | if (status == DMA_COMPLETE) | |
1281 | return 0; | |
1282 | ||
87244fe5 LP |
1283 | /* |
1284 | * If the cookie doesn't correspond to the currently running transfer | |
1285 | * then the descriptor hasn't been processed yet, and the residue is | |
1286 | * equal to the full descriptor size. | |
1287 | */ | |
55bd582b LP |
1288 | if (cookie != desc->async_tx.cookie) { |
1289 | list_for_each_entry(desc, &chan->desc.pending, node) { | |
1290 | if (cookie == desc->async_tx.cookie) | |
1291 | return desc->size; | |
1292 | } | |
1293 | list_for_each_entry(desc, &chan->desc.active, node) { | |
1294 | if (cookie == desc->async_tx.cookie) | |
1295 | return desc->size; | |
1296 | } | |
1297 | ||
1298 | /* | |
1299 | * No descriptor found for the cookie, there's thus no residue. | |
1300 | * This shouldn't happen if the calling driver passes a correct | |
1301 | * cookie value. | |
1302 | */ | |
1303 | WARN(1, "No descriptor for cookie!"); | |
1304 | return 0; | |
1305 | } | |
87244fe5 | 1306 | |
ccadee9b LP |
1307 | /* |
1308 | * In descriptor mode the descriptor running pointer is not maintained | |
1309 | * by the interrupt handler, find the running descriptor from the | |
1310 | * descriptor pointer field in the CHCRB register. In non-descriptor | |
1311 | * mode just use the running descriptor pointer. | |
1312 | */ | |
1ed1315f | 1313 | if (desc->hwdescs.use) { |
ccadee9b LP |
1314 | dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) & |
1315 | RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT; | |
56b17705 KM |
1316 | if (dptr == 0) |
1317 | dptr = desc->nchunks; | |
1318 | dptr--; | |
ccadee9b LP |
1319 | WARN_ON(dptr >= desc->nchunks); |
1320 | } else { | |
1321 | running = desc->running; | |
1322 | } | |
1323 | ||
87244fe5 LP |
1324 | /* Compute the size of all chunks still to be transferred. */ |
1325 | list_for_each_entry_reverse(chunk, &desc->chunks, node) { | |
ccadee9b | 1326 | if (chunk == running || ++dptr == desc->nchunks) |
87244fe5 LP |
1327 | break; |
1328 | ||
1329 | residue += chunk->size; | |
1330 | } | |
1331 | ||
1332 | /* Add the residue for the current chunk. */ | |
1333 | residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift; | |
1334 | ||
1335 | return residue; | |
1336 | } | |
1337 | ||
1338 | static enum dma_status rcar_dmac_tx_status(struct dma_chan *chan, | |
1339 | dma_cookie_t cookie, | |
1340 | struct dma_tx_state *txstate) | |
1341 | { | |
1342 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1343 | enum dma_status status; | |
1344 | unsigned long flags; | |
1345 | unsigned int residue; | |
1346 | ||
1347 | status = dma_cookie_status(chan, cookie, txstate); | |
1348 | if (status == DMA_COMPLETE || !txstate) | |
1349 | return status; | |
1350 | ||
1351 | spin_lock_irqsave(&rchan->lock, flags); | |
1352 | residue = rcar_dmac_chan_get_residue(rchan, cookie); | |
1353 | spin_unlock_irqrestore(&rchan->lock, flags); | |
1354 | ||
3544d287 MHF |
1355 | /* if there's no residue, the cookie is complete */ |
1356 | if (!residue) | |
1357 | return DMA_COMPLETE; | |
1358 | ||
87244fe5 LP |
1359 | dma_set_residue(txstate, residue); |
1360 | ||
1361 | return status; | |
1362 | } | |
1363 | ||
1364 | static void rcar_dmac_issue_pending(struct dma_chan *chan) | |
1365 | { | |
1366 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1367 | unsigned long flags; | |
1368 | ||
1369 | spin_lock_irqsave(&rchan->lock, flags); | |
1370 | ||
1371 | if (list_empty(&rchan->desc.pending)) | |
1372 | goto done; | |
1373 | ||
1374 | /* Append the pending list to the active list. */ | |
1375 | list_splice_tail_init(&rchan->desc.pending, &rchan->desc.active); | |
1376 | ||
1377 | /* | |
1378 | * If no transfer is running pick the first descriptor from the active | |
1379 | * list and start the transfer. | |
1380 | */ | |
1381 | if (!rchan->desc.running) { | |
1382 | struct rcar_dmac_desc *desc; | |
1383 | ||
1384 | desc = list_first_entry(&rchan->desc.active, | |
1385 | struct rcar_dmac_desc, node); | |
1386 | rchan->desc.running = desc; | |
1387 | ||
1388 | rcar_dmac_chan_start_xfer(rchan); | |
1389 | } | |
1390 | ||
1391 | done: | |
1392 | spin_unlock_irqrestore(&rchan->lock, flags); | |
1393 | } | |
1394 | ||
30c45005 NS |
1395 | static void rcar_dmac_device_synchronize(struct dma_chan *chan) |
1396 | { | |
1397 | struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan); | |
1398 | ||
1399 | synchronize_irq(rchan->irq); | |
1400 | } | |
1401 | ||
87244fe5 LP |
1402 | /* ----------------------------------------------------------------------------- |
1403 | * IRQ handling | |
1404 | */ | |
1405 | ||
ccadee9b LP |
1406 | static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan) |
1407 | { | |
1408 | struct rcar_dmac_desc *desc = chan->desc.running; | |
1409 | unsigned int stage; | |
1410 | ||
1411 | if (WARN_ON(!desc || !desc->cyclic)) { | |
1412 | /* | |
1413 | * This should never happen, there should always be a running | |
1414 | * cyclic descriptor when a descriptor stage end interrupt is | |
1415 | * triggered. Warn and return. | |
1416 | */ | |
1417 | return IRQ_NONE; | |
1418 | } | |
1419 | ||
1420 | /* Program the interrupt pointer to the next stage. */ | |
1421 | stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) & | |
1422 | RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT; | |
1423 | rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage)); | |
1424 | ||
1425 | return IRQ_WAKE_THREAD; | |
1426 | } | |
1427 | ||
87244fe5 LP |
1428 | static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan) |
1429 | { | |
1430 | struct rcar_dmac_desc *desc = chan->desc.running; | |
87244fe5 LP |
1431 | irqreturn_t ret = IRQ_WAKE_THREAD; |
1432 | ||
1433 | if (WARN_ON_ONCE(!desc)) { | |
1434 | /* | |
ccadee9b LP |
1435 | * This should never happen, there should always be a running |
1436 | * descriptor when a transfer end interrupt is triggered. Warn | |
1437 | * and return. | |
87244fe5 LP |
1438 | */ |
1439 | return IRQ_NONE; | |
1440 | } | |
1441 | ||
1442 | /* | |
ccadee9b LP |
1443 | * The transfer end interrupt isn't generated for each chunk when using |
1444 | * descriptor mode. Only update the running chunk pointer in | |
1445 | * non-descriptor mode. | |
87244fe5 | 1446 | */ |
1ed1315f | 1447 | if (!desc->hwdescs.use) { |
ccadee9b LP |
1448 | /* |
1449 | * If we haven't completed the last transfer chunk simply move | |
1450 | * to the next one. Only wake the IRQ thread if the transfer is | |
1451 | * cyclic. | |
1452 | */ | |
1453 | if (!list_is_last(&desc->running->node, &desc->chunks)) { | |
1454 | desc->running = list_next_entry(desc->running, node); | |
1455 | if (!desc->cyclic) | |
1456 | ret = IRQ_HANDLED; | |
1457 | goto done; | |
1458 | } | |
87244fe5 | 1459 | |
ccadee9b LP |
1460 | /* |
1461 | * We've completed the last transfer chunk. If the transfer is | |
1462 | * cyclic, move back to the first one. | |
1463 | */ | |
1464 | if (desc->cyclic) { | |
1465 | desc->running = | |
1466 | list_first_entry(&desc->chunks, | |
87244fe5 LP |
1467 | struct rcar_dmac_xfer_chunk, |
1468 | node); | |
ccadee9b LP |
1469 | goto done; |
1470 | } | |
87244fe5 LP |
1471 | } |
1472 | ||
1473 | /* The descriptor is complete, move it to the done list. */ | |
1474 | list_move_tail(&desc->node, &chan->desc.done); | |
1475 | ||
1476 | /* Queue the next descriptor, if any. */ | |
1477 | if (!list_empty(&chan->desc.active)) | |
1478 | chan->desc.running = list_first_entry(&chan->desc.active, | |
1479 | struct rcar_dmac_desc, | |
1480 | node); | |
1481 | else | |
1482 | chan->desc.running = NULL; | |
1483 | ||
1484 | done: | |
1485 | if (chan->desc.running) | |
1486 | rcar_dmac_chan_start_xfer(chan); | |
1487 | ||
1488 | return ret; | |
1489 | } | |
1490 | ||
1491 | static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev) | |
1492 | { | |
ccadee9b | 1493 | u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE; |
87244fe5 LP |
1494 | struct rcar_dmac_chan *chan = dev; |
1495 | irqreturn_t ret = IRQ_NONE; | |
1496 | u32 chcr; | |
1497 | ||
1498 | spin_lock(&chan->lock); | |
1499 | ||
1500 | chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR); | |
ccadee9b LP |
1501 | if (chcr & RCAR_DMACHCR_TE) |
1502 | mask |= RCAR_DMACHCR_DE; | |
1503 | rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask); | |
a8d46a7f KM |
1504 | if (mask & RCAR_DMACHCR_DE) |
1505 | rcar_dmac_chcr_de_barrier(chan); | |
ccadee9b LP |
1506 | |
1507 | if (chcr & RCAR_DMACHCR_DSE) | |
1508 | ret |= rcar_dmac_isr_desc_stage_end(chan); | |
87244fe5 LP |
1509 | |
1510 | if (chcr & RCAR_DMACHCR_TE) | |
1511 | ret |= rcar_dmac_isr_transfer_end(chan); | |
1512 | ||
1513 | spin_unlock(&chan->lock); | |
1514 | ||
1515 | return ret; | |
1516 | } | |
1517 | ||
1518 | static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev) | |
1519 | { | |
1520 | struct rcar_dmac_chan *chan = dev; | |
1521 | struct rcar_dmac_desc *desc; | |
964b2fd8 | 1522 | struct dmaengine_desc_callback cb; |
87244fe5 LP |
1523 | |
1524 | spin_lock_irq(&chan->lock); | |
1525 | ||
1526 | /* For cyclic transfers notify the user after every chunk. */ | |
1527 | if (chan->desc.running && chan->desc.running->cyclic) { | |
87244fe5 | 1528 | desc = chan->desc.running; |
964b2fd8 | 1529 | dmaengine_desc_get_callback(&desc->async_tx, &cb); |
87244fe5 | 1530 | |
964b2fd8 | 1531 | if (dmaengine_desc_callback_valid(&cb)) { |
87244fe5 | 1532 | spin_unlock_irq(&chan->lock); |
964b2fd8 | 1533 | dmaengine_desc_callback_invoke(&cb, NULL); |
87244fe5 LP |
1534 | spin_lock_irq(&chan->lock); |
1535 | } | |
1536 | } | |
1537 | ||
1538 | /* | |
1539 | * Call the callback function for all descriptors on the done list and | |
1540 | * move them to the ack wait list. | |
1541 | */ | |
1542 | while (!list_empty(&chan->desc.done)) { | |
1543 | desc = list_first_entry(&chan->desc.done, struct rcar_dmac_desc, | |
1544 | node); | |
1545 | dma_cookie_complete(&desc->async_tx); | |
1546 | list_del(&desc->node); | |
1547 | ||
964b2fd8 DJ |
1548 | dmaengine_desc_get_callback(&desc->async_tx, &cb); |
1549 | if (dmaengine_desc_callback_valid(&cb)) { | |
87244fe5 LP |
1550 | spin_unlock_irq(&chan->lock); |
1551 | /* | |
1552 | * We own the only reference to this descriptor, we can | |
1553 | * safely dereference it without holding the channel | |
1554 | * lock. | |
1555 | */ | |
964b2fd8 | 1556 | dmaengine_desc_callback_invoke(&cb, NULL); |
87244fe5 LP |
1557 | spin_lock_irq(&chan->lock); |
1558 | } | |
1559 | ||
1560 | list_add_tail(&desc->node, &chan->desc.wait); | |
1561 | } | |
1562 | ||
ccadee9b LP |
1563 | spin_unlock_irq(&chan->lock); |
1564 | ||
87244fe5 LP |
1565 | /* Recycle all acked descriptors. */ |
1566 | rcar_dmac_desc_recycle_acked(chan); | |
1567 | ||
87244fe5 LP |
1568 | return IRQ_HANDLED; |
1569 | } | |
1570 | ||
1571 | static irqreturn_t rcar_dmac_isr_error(int irq, void *data) | |
1572 | { | |
1573 | struct rcar_dmac *dmac = data; | |
1574 | ||
1575 | if (!(rcar_dmac_read(dmac, RCAR_DMAOR) & RCAR_DMAOR_AE)) | |
1576 | return IRQ_NONE; | |
1577 | ||
1578 | /* | |
1579 | * An unrecoverable error occurred on an unknown channel. Halt the DMAC, | |
1580 | * abort transfers on all channels, and reinitialize the DMAC. | |
1581 | */ | |
1582 | rcar_dmac_stop(dmac); | |
1583 | rcar_dmac_abort(dmac); | |
1584 | rcar_dmac_init(dmac); | |
1585 | ||
1586 | return IRQ_HANDLED; | |
1587 | } | |
1588 | ||
1589 | /* ----------------------------------------------------------------------------- | |
1590 | * OF xlate and channel filter | |
1591 | */ | |
1592 | ||
1593 | static bool rcar_dmac_chan_filter(struct dma_chan *chan, void *arg) | |
1594 | { | |
1595 | struct rcar_dmac *dmac = to_rcar_dmac(chan->device); | |
1596 | struct of_phandle_args *dma_spec = arg; | |
1597 | ||
1598 | /* | |
1599 | * FIXME: Using a filter on OF platforms is a nonsense. The OF xlate | |
1600 | * function knows from which device it wants to allocate a channel from, | |
1601 | * and would be perfectly capable of selecting the channel it wants. | |
1602 | * Forcing it to call dma_request_channel() and iterate through all | |
1603 | * channels from all controllers is just pointless. | |
1604 | */ | |
1605 | if (chan->device->device_config != rcar_dmac_device_config || | |
1606 | dma_spec->np != chan->device->dev->of_node) | |
1607 | return false; | |
1608 | ||
1609 | return !test_and_set_bit(dma_spec->args[0], dmac->modules); | |
1610 | } | |
1611 | ||
1612 | static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec, | |
1613 | struct of_dma *ofdma) | |
1614 | { | |
1615 | struct rcar_dmac_chan *rchan; | |
1616 | struct dma_chan *chan; | |
1617 | dma_cap_mask_t mask; | |
1618 | ||
1619 | if (dma_spec->args_count != 1) | |
1620 | return NULL; | |
1621 | ||
1622 | /* Only slave DMA channels can be allocated via DT */ | |
1623 | dma_cap_zero(mask); | |
1624 | dma_cap_set(DMA_SLAVE, mask); | |
1625 | ||
1626 | chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec); | |
1627 | if (!chan) | |
1628 | return NULL; | |
1629 | ||
1630 | rchan = to_rcar_dmac_chan(chan); | |
1631 | rchan->mid_rid = dma_spec->args[0]; | |
1632 | ||
1633 | return chan; | |
1634 | } | |
1635 | ||
1636 | /* ----------------------------------------------------------------------------- | |
1637 | * Power management | |
1638 | */ | |
1639 | ||
1640 | #ifdef CONFIG_PM_SLEEP | |
1641 | static int rcar_dmac_sleep_suspend(struct device *dev) | |
1642 | { | |
1643 | /* | |
1644 | * TODO: Wait for the current transfer to complete and stop the device. | |
1645 | */ | |
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | static int rcar_dmac_sleep_resume(struct device *dev) | |
1650 | { | |
1651 | /* TODO: Resume transfers, if any. */ | |
1652 | return 0; | |
1653 | } | |
1654 | #endif | |
1655 | ||
1656 | #ifdef CONFIG_PM | |
1657 | static int rcar_dmac_runtime_suspend(struct device *dev) | |
1658 | { | |
1659 | return 0; | |
1660 | } | |
1661 | ||
1662 | static int rcar_dmac_runtime_resume(struct device *dev) | |
1663 | { | |
1664 | struct rcar_dmac *dmac = dev_get_drvdata(dev); | |
1665 | ||
1666 | return rcar_dmac_init(dmac); | |
1667 | } | |
1668 | #endif | |
1669 | ||
1670 | static const struct dev_pm_ops rcar_dmac_pm = { | |
1671 | SET_SYSTEM_SLEEP_PM_OPS(rcar_dmac_sleep_suspend, rcar_dmac_sleep_resume) | |
1672 | SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume, | |
1673 | NULL) | |
1674 | }; | |
1675 | ||
1676 | /* ----------------------------------------------------------------------------- | |
1677 | * Probe and remove | |
1678 | */ | |
1679 | ||
1680 | static int rcar_dmac_chan_probe(struct rcar_dmac *dmac, | |
1681 | struct rcar_dmac_chan *rchan, | |
1682 | unsigned int index) | |
1683 | { | |
1684 | struct platform_device *pdev = to_platform_device(dmac->dev); | |
1685 | struct dma_chan *chan = &rchan->chan; | |
1686 | char pdev_irqname[5]; | |
1687 | char *irqname; | |
87244fe5 LP |
1688 | int ret; |
1689 | ||
1690 | rchan->index = index; | |
1691 | rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index); | |
1692 | rchan->mid_rid = -EINVAL; | |
1693 | ||
1694 | spin_lock_init(&rchan->lock); | |
1695 | ||
f7638c90 LP |
1696 | INIT_LIST_HEAD(&rchan->desc.free); |
1697 | INIT_LIST_HEAD(&rchan->desc.pending); | |
1698 | INIT_LIST_HEAD(&rchan->desc.active); | |
1699 | INIT_LIST_HEAD(&rchan->desc.done); | |
1700 | INIT_LIST_HEAD(&rchan->desc.wait); | |
1701 | ||
87244fe5 LP |
1702 | /* Request the channel interrupt. */ |
1703 | sprintf(pdev_irqname, "ch%u", index); | |
427d5ecd NS |
1704 | rchan->irq = platform_get_irq_byname(pdev, pdev_irqname); |
1705 | if (rchan->irq < 0) { | |
87244fe5 LP |
1706 | dev_err(dmac->dev, "no IRQ specified for channel %u\n", index); |
1707 | return -ENODEV; | |
1708 | } | |
1709 | ||
1710 | irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u", | |
1711 | dev_name(dmac->dev), index); | |
1712 | if (!irqname) | |
1713 | return -ENOMEM; | |
1714 | ||
5e857047 KM |
1715 | /* |
1716 | * Initialize the DMA engine channel and add it to the DMA engine | |
1717 | * channels list. | |
1718 | */ | |
1719 | chan->device = &dmac->engine; | |
1720 | dma_cookie_init(chan); | |
1721 | ||
1722 | list_add_tail(&chan->device_node, &dmac->engine.channels); | |
1723 | ||
427d5ecd NS |
1724 | ret = devm_request_threaded_irq(dmac->dev, rchan->irq, |
1725 | rcar_dmac_isr_channel, | |
87244fe5 LP |
1726 | rcar_dmac_isr_channel_thread, 0, |
1727 | irqname, rchan); | |
1728 | if (ret) { | |
427d5ecd NS |
1729 | dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", |
1730 | rchan->irq, ret); | |
87244fe5 LP |
1731 | return ret; |
1732 | } | |
1733 | ||
87244fe5 LP |
1734 | return 0; |
1735 | } | |
1736 | ||
1737 | static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac) | |
1738 | { | |
1739 | struct device_node *np = dev->of_node; | |
1740 | int ret; | |
1741 | ||
1742 | ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels); | |
1743 | if (ret < 0) { | |
1744 | dev_err(dev, "unable to read dma-channels property\n"); | |
1745 | return ret; | |
1746 | } | |
1747 | ||
1748 | if (dmac->n_channels <= 0 || dmac->n_channels >= 100) { | |
1749 | dev_err(dev, "invalid number of channels %u\n", | |
1750 | dmac->n_channels); | |
1751 | return -EINVAL; | |
1752 | } | |
1753 | ||
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | static int rcar_dmac_probe(struct platform_device *pdev) | |
1758 | { | |
1759 | const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE | | |
1760 | DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES | | |
1761 | DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES | | |
1762 | DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES; | |
be6893e1 | 1763 | unsigned int channels_offset = 0; |
87244fe5 LP |
1764 | struct dma_device *engine; |
1765 | struct rcar_dmac *dmac; | |
1766 | struct resource *mem; | |
1767 | unsigned int i; | |
1768 | char *irqname; | |
1769 | int irq; | |
1770 | int ret; | |
1771 | ||
1772 | dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL); | |
1773 | if (!dmac) | |
1774 | return -ENOMEM; | |
1775 | ||
1776 | dmac->dev = &pdev->dev; | |
1777 | platform_set_drvdata(pdev, dmac); | |
dc312349 | 1778 | dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40)); |
87244fe5 LP |
1779 | |
1780 | ret = rcar_dmac_parse_of(&pdev->dev, dmac); | |
1781 | if (ret < 0) | |
1782 | return ret; | |
1783 | ||
be6893e1 LP |
1784 | /* |
1785 | * A still unconfirmed hardware bug prevents the IPMMU microTLB 0 to be | |
1786 | * flushed correctly, resulting in memory corruption. DMAC 0 channel 0 | |
1787 | * is connected to microTLB 0 on currently supported platforms, so we | |
1788 | * can't use it with the IPMMU. As the IOMMU API operates at the device | |
1789 | * level we can't disable it selectively, so ignore channel 0 for now if | |
1790 | * the device is part of an IOMMU group. | |
1791 | */ | |
1792 | if (pdev->dev.iommu_group) { | |
1793 | dmac->n_channels--; | |
1794 | channels_offset = 1; | |
1795 | } | |
1796 | ||
87244fe5 LP |
1797 | dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels, |
1798 | sizeof(*dmac->channels), GFP_KERNEL); | |
1799 | if (!dmac->channels) | |
1800 | return -ENOMEM; | |
1801 | ||
1802 | /* Request resources. */ | |
1803 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1804 | dmac->iomem = devm_ioremap_resource(&pdev->dev, mem); | |
1805 | if (IS_ERR(dmac->iomem)) | |
1806 | return PTR_ERR(dmac->iomem); | |
1807 | ||
1808 | irq = platform_get_irq_byname(pdev, "error"); | |
1809 | if (irq < 0) { | |
1810 | dev_err(&pdev->dev, "no error IRQ specified\n"); | |
1811 | return -ENODEV; | |
1812 | } | |
1813 | ||
1814 | irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:error", | |
1815 | dev_name(dmac->dev)); | |
1816 | if (!irqname) | |
1817 | return -ENOMEM; | |
1818 | ||
87244fe5 LP |
1819 | /* Enable runtime PM and initialize the device. */ |
1820 | pm_runtime_enable(&pdev->dev); | |
1821 | ret = pm_runtime_get_sync(&pdev->dev); | |
1822 | if (ret < 0) { | |
1823 | dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret); | |
1824 | return ret; | |
1825 | } | |
1826 | ||
1827 | ret = rcar_dmac_init(dmac); | |
1828 | pm_runtime_put(&pdev->dev); | |
1829 | ||
1830 | if (ret) { | |
1831 | dev_err(&pdev->dev, "failed to reset device\n"); | |
1832 | goto error; | |
1833 | } | |
1834 | ||
5e857047 KM |
1835 | /* Initialize engine */ |
1836 | engine = &dmac->engine; | |
1837 | ||
1838 | dma_cap_set(DMA_MEMCPY, engine->cap_mask); | |
1839 | dma_cap_set(DMA_SLAVE, engine->cap_mask); | |
1840 | ||
1841 | engine->dev = &pdev->dev; | |
1842 | engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE); | |
1843 | ||
1844 | engine->src_addr_widths = widths; | |
1845 | engine->dst_addr_widths = widths; | |
1846 | engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); | |
1847 | engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1848 | ||
1849 | engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources; | |
1850 | engine->device_free_chan_resources = rcar_dmac_free_chan_resources; | |
1851 | engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy; | |
1852 | engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg; | |
1853 | engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic; | |
1854 | engine->device_config = rcar_dmac_device_config; | |
1855 | engine->device_terminate_all = rcar_dmac_chan_terminate_all; | |
1856 | engine->device_tx_status = rcar_dmac_tx_status; | |
1857 | engine->device_issue_pending = rcar_dmac_issue_pending; | |
1858 | engine->device_synchronize = rcar_dmac_device_synchronize; | |
1859 | ||
1860 | INIT_LIST_HEAD(&engine->channels); | |
87244fe5 LP |
1861 | |
1862 | for (i = 0; i < dmac->n_channels; ++i) { | |
be6893e1 LP |
1863 | ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], |
1864 | i + channels_offset); | |
87244fe5 LP |
1865 | if (ret < 0) |
1866 | goto error; | |
1867 | } | |
1868 | ||
5e857047 KM |
1869 | ret = devm_request_irq(&pdev->dev, irq, rcar_dmac_isr_error, 0, |
1870 | irqname, dmac); | |
1871 | if (ret) { | |
1872 | dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n", | |
1873 | irq, ret); | |
1874 | return ret; | |
1875 | } | |
1876 | ||
87244fe5 LP |
1877 | /* Register the DMAC as a DMA provider for DT. */ |
1878 | ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate, | |
1879 | NULL); | |
1880 | if (ret < 0) | |
1881 | goto error; | |
1882 | ||
1883 | /* | |
1884 | * Register the DMA engine device. | |
1885 | * | |
1886 | * Default transfer size of 32 bytes requires 32-byte alignment. | |
1887 | */ | |
87244fe5 LP |
1888 | ret = dma_async_device_register(engine); |
1889 | if (ret < 0) | |
1890 | goto error; | |
1891 | ||
1892 | return 0; | |
1893 | ||
1894 | error: | |
1895 | of_dma_controller_free(pdev->dev.of_node); | |
1896 | pm_runtime_disable(&pdev->dev); | |
1897 | return ret; | |
1898 | } | |
1899 | ||
1900 | static int rcar_dmac_remove(struct platform_device *pdev) | |
1901 | { | |
1902 | struct rcar_dmac *dmac = platform_get_drvdata(pdev); | |
1903 | ||
1904 | of_dma_controller_free(pdev->dev.of_node); | |
1905 | dma_async_device_unregister(&dmac->engine); | |
1906 | ||
1907 | pm_runtime_disable(&pdev->dev); | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | static void rcar_dmac_shutdown(struct platform_device *pdev) | |
1913 | { | |
1914 | struct rcar_dmac *dmac = platform_get_drvdata(pdev); | |
1915 | ||
1916 | rcar_dmac_stop(dmac); | |
1917 | } | |
1918 | ||
1919 | static const struct of_device_id rcar_dmac_of_ids[] = { | |
1920 | { .compatible = "renesas,rcar-dmac", }, | |
1921 | { /* Sentinel */ } | |
1922 | }; | |
1923 | MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids); | |
1924 | ||
1925 | static struct platform_driver rcar_dmac_driver = { | |
1926 | .driver = { | |
1927 | .pm = &rcar_dmac_pm, | |
1928 | .name = "rcar-dmac", | |
1929 | .of_match_table = rcar_dmac_of_ids, | |
1930 | }, | |
1931 | .probe = rcar_dmac_probe, | |
1932 | .remove = rcar_dmac_remove, | |
1933 | .shutdown = rcar_dmac_shutdown, | |
1934 | }; | |
1935 | ||
1936 | module_platform_driver(rcar_dmac_driver); | |
1937 | ||
1938 | MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver"); | |
1939 | MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); | |
1940 | MODULE_LICENSE("GPL v2"); |