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b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 JB |
24 | #include <linux/amba/bus.h> |
25 | #include <linux/amba/pl330.h> | |
1b9bb715 | 26 | #include <linux/scatterlist.h> |
93ed5544 | 27 | #include <linux/of.h> |
a80258f9 | 28 | #include <linux/of_dma.h> |
bcc7fa95 | 29 | #include <linux/err.h> |
ae43b328 | 30 | #include <linux/pm_runtime.h> |
b3040e40 | 31 | |
d2ebfb33 | 32 | #include "dmaengine.h" |
b7d861d9 BK |
33 | #define PL330_MAX_CHAN 8 |
34 | #define PL330_MAX_IRQS 32 | |
35 | #define PL330_MAX_PERI 32 | |
86a8ce7d | 36 | #define PL330_MAX_BURST 16 |
b7d861d9 | 37 | |
271e1b86 AK |
38 | #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) |
39 | ||
f0564c7e LPC |
40 | enum pl330_cachectrl { |
41 | CCTRL0, /* Noncacheable and nonbufferable */ | |
42 | CCTRL1, /* Bufferable only */ | |
43 | CCTRL2, /* Cacheable, but do not allocate */ | |
44 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
45 | INVALID1, /* AWCACHE = 0x1000 */ | |
46 | INVALID2, | |
47 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
48 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
49 | }; |
50 | ||
51 | enum pl330_byteswap { | |
52 | SWAP_NO, | |
53 | SWAP_2, | |
54 | SWAP_4, | |
55 | SWAP_8, | |
56 | SWAP_16, | |
57 | }; | |
58 | ||
b7d861d9 BK |
59 | /* Register and Bit field Definitions */ |
60 | #define DS 0x0 | |
61 | #define DS_ST_STOP 0x0 | |
62 | #define DS_ST_EXEC 0x1 | |
63 | #define DS_ST_CMISS 0x2 | |
64 | #define DS_ST_UPDTPC 0x3 | |
65 | #define DS_ST_WFE 0x4 | |
66 | #define DS_ST_ATBRR 0x5 | |
67 | #define DS_ST_QBUSY 0x6 | |
68 | #define DS_ST_WFP 0x7 | |
69 | #define DS_ST_KILL 0x8 | |
70 | #define DS_ST_CMPLT 0x9 | |
71 | #define DS_ST_FLTCMP 0xe | |
72 | #define DS_ST_FAULT 0xf | |
73 | ||
74 | #define DPC 0x4 | |
75 | #define INTEN 0x20 | |
76 | #define ES 0x24 | |
77 | #define INTSTATUS 0x28 | |
78 | #define INTCLR 0x2c | |
79 | #define FSM 0x30 | |
80 | #define FSC 0x34 | |
81 | #define FTM 0x38 | |
82 | ||
83 | #define _FTC 0x40 | |
84 | #define FTC(n) (_FTC + (n)*0x4) | |
85 | ||
86 | #define _CS 0x100 | |
87 | #define CS(n) (_CS + (n)*0x8) | |
88 | #define CS_CNS (1 << 21) | |
89 | ||
90 | #define _CPC 0x104 | |
91 | #define CPC(n) (_CPC + (n)*0x8) | |
92 | ||
93 | #define _SA 0x400 | |
94 | #define SA(n) (_SA + (n)*0x20) | |
95 | ||
96 | #define _DA 0x404 | |
97 | #define DA(n) (_DA + (n)*0x20) | |
98 | ||
99 | #define _CC 0x408 | |
100 | #define CC(n) (_CC + (n)*0x20) | |
101 | ||
102 | #define CC_SRCINC (1 << 0) | |
103 | #define CC_DSTINC (1 << 14) | |
104 | #define CC_SRCPRI (1 << 8) | |
105 | #define CC_DSTPRI (1 << 22) | |
106 | #define CC_SRCNS (1 << 9) | |
107 | #define CC_DSTNS (1 << 23) | |
108 | #define CC_SRCIA (1 << 10) | |
109 | #define CC_DSTIA (1 << 24) | |
110 | #define CC_SRCBRSTLEN_SHFT 4 | |
111 | #define CC_DSTBRSTLEN_SHFT 18 | |
112 | #define CC_SRCBRSTSIZE_SHFT 1 | |
113 | #define CC_DSTBRSTSIZE_SHFT 15 | |
114 | #define CC_SRCCCTRL_SHFT 11 | |
115 | #define CC_SRCCCTRL_MASK 0x7 | |
116 | #define CC_DSTCCTRL_SHFT 25 | |
117 | #define CC_DRCCCTRL_MASK 0x7 | |
118 | #define CC_SWAP_SHFT 28 | |
119 | ||
120 | #define _LC0 0x40c | |
121 | #define LC0(n) (_LC0 + (n)*0x20) | |
122 | ||
123 | #define _LC1 0x410 | |
124 | #define LC1(n) (_LC1 + (n)*0x20) | |
125 | ||
126 | #define DBGSTATUS 0xd00 | |
127 | #define DBG_BUSY (1 << 0) | |
128 | ||
129 | #define DBGCMD 0xd04 | |
130 | #define DBGINST0 0xd08 | |
131 | #define DBGINST1 0xd0c | |
132 | ||
133 | #define CR0 0xe00 | |
134 | #define CR1 0xe04 | |
135 | #define CR2 0xe08 | |
136 | #define CR3 0xe0c | |
137 | #define CR4 0xe10 | |
138 | #define CRD 0xe14 | |
139 | ||
140 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
141 | #define PERIPH_REV_SHIFT 20 |
142 | #define PERIPH_REV_MASK 0xf | |
143 | #define PERIPH_REV_R0P0 0 | |
144 | #define PERIPH_REV_R1P0 1 | |
145 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
146 | |
147 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
148 | #define CR0_BOOT_EN_SET (1 << 1) | |
149 | #define CR0_BOOT_MAN_NS (1 << 2) | |
150 | #define CR0_NUM_CHANS_SHIFT 4 | |
151 | #define CR0_NUM_CHANS_MASK 0x7 | |
152 | #define CR0_NUM_PERIPH_SHIFT 12 | |
153 | #define CR0_NUM_PERIPH_MASK 0x1f | |
154 | #define CR0_NUM_EVENTS_SHIFT 17 | |
155 | #define CR0_NUM_EVENTS_MASK 0x1f | |
156 | ||
157 | #define CR1_ICACHE_LEN_SHIFT 0 | |
158 | #define CR1_ICACHE_LEN_MASK 0x7 | |
159 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
160 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
161 | ||
162 | #define CRD_DATA_WIDTH_SHIFT 0 | |
163 | #define CRD_DATA_WIDTH_MASK 0x7 | |
164 | #define CRD_WR_CAP_SHIFT 4 | |
165 | #define CRD_WR_CAP_MASK 0x7 | |
166 | #define CRD_WR_Q_DEP_SHIFT 8 | |
167 | #define CRD_WR_Q_DEP_MASK 0xf | |
168 | #define CRD_RD_CAP_SHIFT 12 | |
169 | #define CRD_RD_CAP_MASK 0x7 | |
170 | #define CRD_RD_Q_DEP_SHIFT 16 | |
171 | #define CRD_RD_Q_DEP_MASK 0xf | |
172 | #define CRD_DATA_BUFF_SHIFT 20 | |
173 | #define CRD_DATA_BUFF_MASK 0x3ff | |
174 | ||
175 | #define PART 0x330 | |
176 | #define DESIGNER 0x41 | |
177 | #define REVISION 0x0 | |
178 | #define INTEG_CFG 0x0 | |
179 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
180 | ||
b7d861d9 BK |
181 | #define PL330_STATE_STOPPED (1 << 0) |
182 | #define PL330_STATE_EXECUTING (1 << 1) | |
183 | #define PL330_STATE_WFE (1 << 2) | |
184 | #define PL330_STATE_FAULTING (1 << 3) | |
185 | #define PL330_STATE_COMPLETING (1 << 4) | |
186 | #define PL330_STATE_WFP (1 << 5) | |
187 | #define PL330_STATE_KILLING (1 << 6) | |
188 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
189 | #define PL330_STATE_CACHEMISS (1 << 8) | |
190 | #define PL330_STATE_UPDTPC (1 << 9) | |
191 | #define PL330_STATE_ATBARRIER (1 << 10) | |
192 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
193 | #define PL330_STATE_INVALID (1 << 15) | |
194 | ||
195 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
196 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
197 | ||
198 | #define CMD_DMAADDH 0x54 | |
199 | #define CMD_DMAEND 0x00 | |
200 | #define CMD_DMAFLUSHP 0x35 | |
201 | #define CMD_DMAGO 0xa0 | |
202 | #define CMD_DMALD 0x04 | |
203 | #define CMD_DMALDP 0x25 | |
204 | #define CMD_DMALP 0x20 | |
205 | #define CMD_DMALPEND 0x28 | |
206 | #define CMD_DMAKILL 0x01 | |
207 | #define CMD_DMAMOV 0xbc | |
208 | #define CMD_DMANOP 0x18 | |
209 | #define CMD_DMARMB 0x12 | |
210 | #define CMD_DMASEV 0x34 | |
211 | #define CMD_DMAST 0x08 | |
212 | #define CMD_DMASTP 0x29 | |
213 | #define CMD_DMASTZ 0x0c | |
214 | #define CMD_DMAWFE 0x36 | |
215 | #define CMD_DMAWFP 0x30 | |
216 | #define CMD_DMAWMB 0x13 | |
217 | ||
218 | #define SZ_DMAADDH 3 | |
219 | #define SZ_DMAEND 1 | |
220 | #define SZ_DMAFLUSHP 2 | |
221 | #define SZ_DMALD 1 | |
222 | #define SZ_DMALDP 2 | |
223 | #define SZ_DMALP 2 | |
224 | #define SZ_DMALPEND 2 | |
225 | #define SZ_DMAKILL 1 | |
226 | #define SZ_DMAMOV 6 | |
227 | #define SZ_DMANOP 1 | |
228 | #define SZ_DMARMB 1 | |
229 | #define SZ_DMASEV 2 | |
230 | #define SZ_DMAST 1 | |
231 | #define SZ_DMASTP 2 | |
232 | #define SZ_DMASTZ 1 | |
233 | #define SZ_DMAWFE 2 | |
234 | #define SZ_DMAWFP 2 | |
235 | #define SZ_DMAWMB 1 | |
236 | #define SZ_DMAGO 6 | |
237 | ||
238 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
239 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
240 | ||
241 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
242 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
243 | ||
244 | /* | |
245 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
246 | * at 1byte/burst for P<->M and M<->M respectively. | |
247 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
248 | * should be enough for P<->M and M<->M respectively. | |
249 | */ | |
250 | #define MCODE_BUFF_PER_REQ 256 | |
251 | ||
b7d861d9 BK |
252 | /* Use this _only_ to wait on transient states */ |
253 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
254 | ||
255 | #ifdef PL330_DEBUG_MCGEN | |
256 | static unsigned cmd_line; | |
257 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
258 | printk("%x:", cmd_line); \ | |
259 | printk(x); \ | |
260 | cmd_line += off; \ | |
261 | } while (0) | |
262 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
263 | #else | |
264 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
265 | #define PL330_DBGMC_START(addr) do {} while (0) | |
266 | #endif | |
267 | ||
268 | /* The number of default descriptors */ | |
d2ebfb33 | 269 | |
b3040e40 JB |
270 | #define NR_DEFAULT_DESC 16 |
271 | ||
ae43b328 KK |
272 | /* Delay for runtime PM autosuspend, ms */ |
273 | #define PL330_AUTOSUSPEND_DELAY 20 | |
274 | ||
b7d861d9 BK |
275 | /* Populated by the PL330 core driver for DMA API driver's info */ |
276 | struct pl330_config { | |
277 | u32 periph_id; | |
b7d861d9 BK |
278 | #define DMAC_MODE_NS (1 << 0) |
279 | unsigned int mode; | |
280 | unsigned int data_bus_width:10; /* In number of bits */ | |
1f0a5cbf | 281 | unsigned int data_buf_dep:11; |
b7d861d9 BK |
282 | unsigned int num_chan:4; |
283 | unsigned int num_peri:6; | |
284 | u32 peri_ns; | |
285 | unsigned int num_events:6; | |
286 | u32 irq_ns; | |
287 | }; | |
288 | ||
b7d861d9 BK |
289 | /** |
290 | * Request Configuration. | |
291 | * The PL330 core does not modify this and uses the last | |
292 | * working configuration if the request doesn't provide any. | |
293 | * | |
294 | * The Client may want to provide this info only for the | |
295 | * first request and a request with new settings. | |
296 | */ | |
297 | struct pl330_reqcfg { | |
298 | /* Address Incrementing */ | |
299 | unsigned dst_inc:1; | |
300 | unsigned src_inc:1; | |
301 | ||
302 | /* | |
303 | * For now, the SRC & DST protection levels | |
304 | * and burst size/length are assumed same. | |
305 | */ | |
306 | bool nonsecure; | |
307 | bool privileged; | |
308 | bool insnaccess; | |
309 | unsigned brst_len:5; | |
310 | unsigned brst_size:3; /* in power of 2 */ | |
311 | ||
f0564c7e LPC |
312 | enum pl330_cachectrl dcctl; |
313 | enum pl330_cachectrl scctl; | |
b7d861d9 | 314 | enum pl330_byteswap swap; |
3ecf51a4 | 315 | struct pl330_config *pcfg; |
b7d861d9 BK |
316 | }; |
317 | ||
318 | /* | |
319 | * One cycle of DMAC operation. | |
320 | * There may be more than one xfer in a request. | |
321 | */ | |
322 | struct pl330_xfer { | |
323 | u32 src_addr; | |
324 | u32 dst_addr; | |
325 | /* Size to xfer */ | |
326 | u32 bytes; | |
b7d861d9 BK |
327 | }; |
328 | ||
329 | /* The xfer callbacks are made with one of these arguments. */ | |
330 | enum pl330_op_err { | |
331 | /* The all xfers in the request were success. */ | |
332 | PL330_ERR_NONE, | |
333 | /* If req aborted due to global error. */ | |
334 | PL330_ERR_ABORT, | |
335 | /* If req failed due to problem with Channel. */ | |
336 | PL330_ERR_FAIL, | |
337 | }; | |
338 | ||
b7d861d9 BK |
339 | enum dmamov_dst { |
340 | SAR = 0, | |
341 | CCR, | |
342 | DAR, | |
343 | }; | |
344 | ||
345 | enum pl330_dst { | |
346 | SRC = 0, | |
347 | DST, | |
348 | }; | |
349 | ||
350 | enum pl330_cond { | |
351 | SINGLE, | |
352 | BURST, | |
353 | ALWAYS, | |
354 | }; | |
355 | ||
9dc5a315 LPC |
356 | struct dma_pl330_desc; |
357 | ||
b7d861d9 BK |
358 | struct _pl330_req { |
359 | u32 mc_bus; | |
360 | void *mc_cpu; | |
9dc5a315 | 361 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
362 | }; |
363 | ||
364 | /* ToBeDone for tasklet */ | |
365 | struct _pl330_tbd { | |
366 | bool reset_dmac; | |
367 | bool reset_mngr; | |
368 | u8 reset_chan; | |
369 | }; | |
370 | ||
371 | /* A DMAC Thread */ | |
372 | struct pl330_thread { | |
373 | u8 id; | |
374 | int ev; | |
375 | /* If the channel is not yet acquired by any client */ | |
376 | bool free; | |
377 | /* Parent DMAC */ | |
378 | struct pl330_dmac *dmac; | |
379 | /* Only two at a time */ | |
380 | struct _pl330_req req[2]; | |
381 | /* Index of the last enqueued request */ | |
382 | unsigned lstenq; | |
383 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
384 | int req_running; | |
385 | }; | |
386 | ||
387 | enum pl330_dmac_state { | |
388 | UNINIT, | |
389 | INIT, | |
390 | DYING, | |
391 | }; | |
392 | ||
b3040e40 JB |
393 | enum desc_status { |
394 | /* In the DMAC pool */ | |
395 | FREE, | |
396 | /* | |
d73111c6 | 397 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
398 | * Also may be sitting on the work_list. |
399 | */ | |
400 | PREP, | |
401 | /* | |
402 | * Sitting on the work_list and already submitted | |
403 | * to the PL330 core. Not more than two descriptors | |
404 | * of a channel can be BUSY at any time. | |
405 | */ | |
406 | BUSY, | |
407 | /* | |
408 | * Sitting on the channel work_list but xfer done | |
409 | * by PL330 core | |
410 | */ | |
411 | DONE, | |
412 | }; | |
413 | ||
414 | struct dma_pl330_chan { | |
415 | /* Schedule desc completion */ | |
416 | struct tasklet_struct task; | |
417 | ||
418 | /* DMA-Engine Channel */ | |
419 | struct dma_chan chan; | |
420 | ||
04abf5da LPC |
421 | /* List of submitted descriptors */ |
422 | struct list_head submitted_list; | |
423 | /* List of issued descriptors */ | |
b3040e40 | 424 | struct list_head work_list; |
39ff8613 LPC |
425 | /* List of completed descriptors */ |
426 | struct list_head completed_list; | |
b3040e40 JB |
427 | |
428 | /* Pointer to the DMAC that manages this channel, | |
429 | * NULL if the channel is available to be acquired. | |
430 | * As the parent, this DMAC also provides descriptors | |
431 | * to the channel. | |
432 | */ | |
f6f2421c | 433 | struct pl330_dmac *dmac; |
b3040e40 JB |
434 | |
435 | /* To protect channel manipulation */ | |
436 | spinlock_t lock; | |
437 | ||
65ad6060 LPC |
438 | /* |
439 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
440 | * available. | |
b3040e40 | 441 | */ |
65ad6060 | 442 | struct pl330_thread *thread; |
1b9bb715 BK |
443 | |
444 | /* For D-to-M and M-to-D channels */ | |
445 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 446 | int burst_len; /* the number of burst */ |
1b9bb715 | 447 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
448 | |
449 | /* for cyclic capability */ | |
450 | bool cyclic; | |
b3040e40 JB |
451 | }; |
452 | ||
f6f2421c | 453 | struct pl330_dmac { |
b3040e40 JB |
454 | /* DMA-Engine Device */ |
455 | struct dma_device ddma; | |
456 | ||
b714b84e LPC |
457 | /* Holds info about sg limitations */ |
458 | struct device_dma_parameters dma_parms; | |
459 | ||
b3040e40 JB |
460 | /* Pool of descriptors available for the DMAC's channels */ |
461 | struct list_head desc_pool; | |
462 | /* To protect desc_pool manipulation */ | |
463 | spinlock_t pool_lock; | |
464 | ||
f6f2421c LPC |
465 | /* Size of MicroCode buffers for each channel. */ |
466 | unsigned mcbufsz; | |
467 | /* ioremap'ed address of PL330 registers. */ | |
468 | void __iomem *base; | |
469 | /* Populated by the PL330 core driver during pl330_add */ | |
470 | struct pl330_config pcfg; | |
471 | ||
472 | spinlock_t lock; | |
473 | /* Maximum possible events/irqs */ | |
474 | int events[32]; | |
475 | /* BUS address of MicroCode buffer */ | |
476 | dma_addr_t mcode_bus; | |
477 | /* CPU address of MicroCode buffer */ | |
478 | void *mcode_cpu; | |
479 | /* List of all Channel threads */ | |
480 | struct pl330_thread *channels; | |
481 | /* Pointer to the MANAGER thread */ | |
482 | struct pl330_thread *manager; | |
483 | /* To handle bad news in interrupt */ | |
484 | struct tasklet_struct tasks; | |
485 | struct _pl330_tbd dmac_tbd; | |
486 | /* State of DMAC operation */ | |
487 | enum pl330_dmac_state state; | |
488 | /* Holds list of reqs with due callbacks */ | |
489 | struct list_head req_done; | |
490 | ||
b3040e40 | 491 | /* Peripheral channels connected to this DMAC */ |
70cbb163 | 492 | unsigned int num_peripherals; |
4e0e6109 | 493 | struct dma_pl330_chan *peripherals; /* keep at end */ |
271e1b86 AK |
494 | int quirks; |
495 | }; | |
496 | ||
497 | static struct pl330_of_quirks { | |
498 | char *quirk; | |
499 | int id; | |
500 | } of_quirks[] = { | |
501 | { | |
502 | .quirk = "arm,pl330-broken-no-flushp", | |
503 | .id = PL330_QUIRK_BROKEN_NO_FLUSHP, | |
504 | } | |
b3040e40 JB |
505 | }; |
506 | ||
507 | struct dma_pl330_desc { | |
508 | /* To attach to a queue as child */ | |
509 | struct list_head node; | |
510 | ||
511 | /* Descriptor for the DMA Engine API */ | |
512 | struct dma_async_tx_descriptor txd; | |
513 | ||
514 | /* Xfer for PL330 core */ | |
515 | struct pl330_xfer px; | |
516 | ||
517 | struct pl330_reqcfg rqcfg; | |
b3040e40 JB |
518 | |
519 | enum desc_status status; | |
520 | ||
aee4d1fa RB |
521 | int bytes_requested; |
522 | bool last; | |
523 | ||
b3040e40 JB |
524 | /* The channel which currently holds this desc */ |
525 | struct dma_pl330_chan *pchan; | |
9dc5a315 LPC |
526 | |
527 | enum dma_transfer_direction rqtype; | |
528 | /* Index of peripheral for the xfer. */ | |
529 | unsigned peri:5; | |
530 | /* Hook to attach to DMAC's list of reqs with due callback */ | |
531 | struct list_head rqd; | |
532 | }; | |
533 | ||
534 | struct _xfer_spec { | |
535 | u32 ccr; | |
536 | struct dma_pl330_desc *desc; | |
b3040e40 JB |
537 | }; |
538 | ||
b7d861d9 BK |
539 | static inline bool _queue_empty(struct pl330_thread *thrd) |
540 | { | |
8ed30a14 | 541 | return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL; |
b7d861d9 BK |
542 | } |
543 | ||
544 | static inline bool _queue_full(struct pl330_thread *thrd) | |
545 | { | |
8ed30a14 | 546 | return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; |
b7d861d9 BK |
547 | } |
548 | ||
549 | static inline bool is_manager(struct pl330_thread *thrd) | |
550 | { | |
fbbcd9be | 551 | return thrd->dmac->manager == thrd; |
b7d861d9 BK |
552 | } |
553 | ||
554 | /* If manager of the thread is in Non-Secure mode */ | |
555 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
556 | { | |
f6f2421c | 557 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
b7d861d9 BK |
558 | } |
559 | ||
3ecf51a4 BK |
560 | static inline u32 get_revision(u32 periph_id) |
561 | { | |
562 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
563 | } | |
564 | ||
b7d861d9 BK |
565 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
566 | enum pl330_dst da, u16 val) | |
567 | { | |
568 | if (dry_run) | |
569 | return SZ_DMAADDH; | |
570 | ||
571 | buf[0] = CMD_DMAADDH; | |
572 | buf[0] |= (da << 1); | |
d07c9e1e VM |
573 | buf[1] = val; |
574 | buf[2] = val >> 8; | |
b7d861d9 BK |
575 | |
576 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", | |
577 | da == 1 ? "DA" : "SA", val); | |
578 | ||
579 | return SZ_DMAADDH; | |
580 | } | |
581 | ||
582 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) | |
583 | { | |
584 | if (dry_run) | |
585 | return SZ_DMAEND; | |
586 | ||
587 | buf[0] = CMD_DMAEND; | |
588 | ||
589 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
590 | ||
591 | return SZ_DMAEND; | |
592 | } | |
593 | ||
594 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
595 | { | |
596 | if (dry_run) | |
597 | return SZ_DMAFLUSHP; | |
598 | ||
599 | buf[0] = CMD_DMAFLUSHP; | |
600 | ||
601 | peri &= 0x1f; | |
602 | peri <<= 3; | |
603 | buf[1] = peri; | |
604 | ||
605 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
606 | ||
607 | return SZ_DMAFLUSHP; | |
608 | } | |
609 | ||
610 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
611 | { | |
612 | if (dry_run) | |
613 | return SZ_DMALD; | |
614 | ||
615 | buf[0] = CMD_DMALD; | |
616 | ||
617 | if (cond == SINGLE) | |
618 | buf[0] |= (0 << 1) | (1 << 0); | |
619 | else if (cond == BURST) | |
620 | buf[0] |= (1 << 1) | (1 << 0); | |
621 | ||
622 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
623 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
624 | ||
625 | return SZ_DMALD; | |
626 | } | |
627 | ||
628 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
629 | enum pl330_cond cond, u8 peri) | |
630 | { | |
631 | if (dry_run) | |
632 | return SZ_DMALDP; | |
633 | ||
634 | buf[0] = CMD_DMALDP; | |
635 | ||
636 | if (cond == BURST) | |
637 | buf[0] |= (1 << 1); | |
638 | ||
639 | peri &= 0x1f; | |
640 | peri <<= 3; | |
641 | buf[1] = peri; | |
642 | ||
643 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
644 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
645 | ||
646 | return SZ_DMALDP; | |
647 | } | |
648 | ||
649 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
650 | unsigned loop, u8 cnt) | |
651 | { | |
652 | if (dry_run) | |
653 | return SZ_DMALP; | |
654 | ||
655 | buf[0] = CMD_DMALP; | |
656 | ||
657 | if (loop) | |
658 | buf[0] |= (1 << 1); | |
659 | ||
660 | cnt--; /* DMAC increments by 1 internally */ | |
661 | buf[1] = cnt; | |
662 | ||
663 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
664 | ||
665 | return SZ_DMALP; | |
666 | } | |
667 | ||
668 | struct _arg_LPEND { | |
669 | enum pl330_cond cond; | |
670 | bool forever; | |
671 | unsigned loop; | |
672 | u8 bjump; | |
673 | }; | |
674 | ||
675 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
676 | const struct _arg_LPEND *arg) | |
677 | { | |
678 | enum pl330_cond cond = arg->cond; | |
679 | bool forever = arg->forever; | |
680 | unsigned loop = arg->loop; | |
681 | u8 bjump = arg->bjump; | |
682 | ||
683 | if (dry_run) | |
684 | return SZ_DMALPEND; | |
685 | ||
686 | buf[0] = CMD_DMALPEND; | |
687 | ||
688 | if (loop) | |
689 | buf[0] |= (1 << 2); | |
690 | ||
691 | if (!forever) | |
692 | buf[0] |= (1 << 4); | |
693 | ||
694 | if (cond == SINGLE) | |
695 | buf[0] |= (0 << 1) | (1 << 0); | |
696 | else if (cond == BURST) | |
697 | buf[0] |= (1 << 1) | (1 << 0); | |
698 | ||
699 | buf[1] = bjump; | |
700 | ||
701 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
702 | forever ? "FE" : "END", | |
703 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
704 | loop ? '1' : '0', | |
705 | bjump); | |
706 | ||
707 | return SZ_DMALPEND; | |
708 | } | |
709 | ||
710 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
711 | { | |
712 | if (dry_run) | |
713 | return SZ_DMAKILL; | |
714 | ||
715 | buf[0] = CMD_DMAKILL; | |
716 | ||
717 | return SZ_DMAKILL; | |
718 | } | |
719 | ||
720 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
721 | enum dmamov_dst dst, u32 val) | |
722 | { | |
723 | if (dry_run) | |
724 | return SZ_DMAMOV; | |
725 | ||
726 | buf[0] = CMD_DMAMOV; | |
727 | buf[1] = dst; | |
d07c9e1e VM |
728 | buf[2] = val; |
729 | buf[3] = val >> 8; | |
730 | buf[4] = val >> 16; | |
731 | buf[5] = val >> 24; | |
b7d861d9 BK |
732 | |
733 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
734 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
735 | ||
736 | return SZ_DMAMOV; | |
737 | } | |
738 | ||
739 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) | |
740 | { | |
741 | if (dry_run) | |
742 | return SZ_DMANOP; | |
743 | ||
744 | buf[0] = CMD_DMANOP; | |
745 | ||
746 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); | |
747 | ||
748 | return SZ_DMANOP; | |
749 | } | |
750 | ||
751 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) | |
752 | { | |
753 | if (dry_run) | |
754 | return SZ_DMARMB; | |
755 | ||
756 | buf[0] = CMD_DMARMB; | |
757 | ||
758 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
759 | ||
760 | return SZ_DMARMB; | |
761 | } | |
762 | ||
763 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
764 | { | |
765 | if (dry_run) | |
766 | return SZ_DMASEV; | |
767 | ||
768 | buf[0] = CMD_DMASEV; | |
769 | ||
770 | ev &= 0x1f; | |
771 | ev <<= 3; | |
772 | buf[1] = ev; | |
773 | ||
774 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
775 | ||
776 | return SZ_DMASEV; | |
777 | } | |
778 | ||
779 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
780 | { | |
781 | if (dry_run) | |
782 | return SZ_DMAST; | |
783 | ||
784 | buf[0] = CMD_DMAST; | |
785 | ||
786 | if (cond == SINGLE) | |
787 | buf[0] |= (0 << 1) | (1 << 0); | |
788 | else if (cond == BURST) | |
789 | buf[0] |= (1 << 1) | (1 << 0); | |
790 | ||
791 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
792 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
793 | ||
794 | return SZ_DMAST; | |
795 | } | |
796 | ||
797 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
798 | enum pl330_cond cond, u8 peri) | |
799 | { | |
800 | if (dry_run) | |
801 | return SZ_DMASTP; | |
802 | ||
803 | buf[0] = CMD_DMASTP; | |
804 | ||
805 | if (cond == BURST) | |
806 | buf[0] |= (1 << 1); | |
807 | ||
808 | peri &= 0x1f; | |
809 | peri <<= 3; | |
810 | buf[1] = peri; | |
811 | ||
812 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
813 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
814 | ||
815 | return SZ_DMASTP; | |
816 | } | |
817 | ||
818 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) | |
819 | { | |
820 | if (dry_run) | |
821 | return SZ_DMASTZ; | |
822 | ||
823 | buf[0] = CMD_DMASTZ; | |
824 | ||
825 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); | |
826 | ||
827 | return SZ_DMASTZ; | |
828 | } | |
829 | ||
830 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, | |
831 | unsigned invalidate) | |
832 | { | |
833 | if (dry_run) | |
834 | return SZ_DMAWFE; | |
835 | ||
836 | buf[0] = CMD_DMAWFE; | |
837 | ||
838 | ev &= 0x1f; | |
839 | ev <<= 3; | |
840 | buf[1] = ev; | |
841 | ||
842 | if (invalidate) | |
843 | buf[1] |= (1 << 1); | |
844 | ||
845 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", | |
846 | ev >> 3, invalidate ? ", I" : ""); | |
847 | ||
848 | return SZ_DMAWFE; | |
849 | } | |
850 | ||
851 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], | |
852 | enum pl330_cond cond, u8 peri) | |
853 | { | |
854 | if (dry_run) | |
855 | return SZ_DMAWFP; | |
856 | ||
857 | buf[0] = CMD_DMAWFP; | |
858 | ||
859 | if (cond == SINGLE) | |
860 | buf[0] |= (0 << 1) | (0 << 0); | |
861 | else if (cond == BURST) | |
862 | buf[0] |= (1 << 1) | (0 << 0); | |
863 | else | |
864 | buf[0] |= (0 << 1) | (1 << 0); | |
865 | ||
866 | peri &= 0x1f; | |
867 | peri <<= 3; | |
868 | buf[1] = peri; | |
869 | ||
870 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
871 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
872 | ||
873 | return SZ_DMAWFP; | |
874 | } | |
875 | ||
876 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
877 | { | |
878 | if (dry_run) | |
879 | return SZ_DMAWMB; | |
880 | ||
881 | buf[0] = CMD_DMAWMB; | |
882 | ||
883 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
884 | ||
885 | return SZ_DMAWMB; | |
886 | } | |
887 | ||
888 | struct _arg_GO { | |
889 | u8 chan; | |
890 | u32 addr; | |
891 | unsigned ns; | |
892 | }; | |
893 | ||
894 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
895 | const struct _arg_GO *arg) | |
896 | { | |
897 | u8 chan = arg->chan; | |
898 | u32 addr = arg->addr; | |
899 | unsigned ns = arg->ns; | |
900 | ||
901 | if (dry_run) | |
902 | return SZ_DMAGO; | |
903 | ||
904 | buf[0] = CMD_DMAGO; | |
905 | buf[0] |= (ns << 1); | |
b7d861d9 | 906 | buf[1] = chan & 0x7; |
d07c9e1e VM |
907 | buf[2] = addr; |
908 | buf[3] = addr >> 8; | |
909 | buf[4] = addr >> 16; | |
910 | buf[5] = addr >> 24; | |
b7d861d9 BK |
911 | |
912 | return SZ_DMAGO; | |
913 | } | |
914 | ||
915 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
916 | ||
917 | /* Returns Time-Out */ | |
918 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
919 | { | |
f6f2421c | 920 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
921 | unsigned long loops = msecs_to_loops(5); |
922 | ||
923 | do { | |
924 | /* Until Manager is Idle */ | |
925 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
926 | break; | |
927 | ||
928 | cpu_relax(); | |
929 | } while (--loops); | |
930 | ||
931 | if (!loops) | |
932 | return true; | |
933 | ||
934 | return false; | |
935 | } | |
936 | ||
937 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
938 | u8 insn[], bool as_manager) | |
939 | { | |
f6f2421c | 940 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
941 | u32 val; |
942 | ||
943 | val = (insn[0] << 16) | (insn[1] << 24); | |
944 | if (!as_manager) { | |
945 | val |= (1 << 0); | |
946 | val |= (thrd->id << 8); /* Channel Number */ | |
947 | } | |
948 | writel(val, regs + DBGINST0); | |
949 | ||
3a2307f7 | 950 | val = le32_to_cpu(*((__le32 *)&insn[2])); |
b7d861d9 BK |
951 | writel(val, regs + DBGINST1); |
952 | ||
953 | /* If timed out due to halted state-machine */ | |
954 | if (_until_dmac_idle(thrd)) { | |
f6f2421c | 955 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
b7d861d9 BK |
956 | return; |
957 | } | |
958 | ||
959 | /* Get going */ | |
960 | writel(0, regs + DBGCMD); | |
961 | } | |
962 | ||
b7d861d9 BK |
963 | static inline u32 _state(struct pl330_thread *thrd) |
964 | { | |
f6f2421c | 965 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
966 | u32 val; |
967 | ||
968 | if (is_manager(thrd)) | |
969 | val = readl(regs + DS) & 0xf; | |
970 | else | |
971 | val = readl(regs + CS(thrd->id)) & 0xf; | |
972 | ||
973 | switch (val) { | |
974 | case DS_ST_STOP: | |
975 | return PL330_STATE_STOPPED; | |
976 | case DS_ST_EXEC: | |
977 | return PL330_STATE_EXECUTING; | |
978 | case DS_ST_CMISS: | |
979 | return PL330_STATE_CACHEMISS; | |
980 | case DS_ST_UPDTPC: | |
981 | return PL330_STATE_UPDTPC; | |
982 | case DS_ST_WFE: | |
983 | return PL330_STATE_WFE; | |
984 | case DS_ST_FAULT: | |
985 | return PL330_STATE_FAULTING; | |
986 | case DS_ST_ATBRR: | |
987 | if (is_manager(thrd)) | |
988 | return PL330_STATE_INVALID; | |
989 | else | |
990 | return PL330_STATE_ATBARRIER; | |
991 | case DS_ST_QBUSY: | |
992 | if (is_manager(thrd)) | |
993 | return PL330_STATE_INVALID; | |
994 | else | |
995 | return PL330_STATE_QUEUEBUSY; | |
996 | case DS_ST_WFP: | |
997 | if (is_manager(thrd)) | |
998 | return PL330_STATE_INVALID; | |
999 | else | |
1000 | return PL330_STATE_WFP; | |
1001 | case DS_ST_KILL: | |
1002 | if (is_manager(thrd)) | |
1003 | return PL330_STATE_INVALID; | |
1004 | else | |
1005 | return PL330_STATE_KILLING; | |
1006 | case DS_ST_CMPLT: | |
1007 | if (is_manager(thrd)) | |
1008 | return PL330_STATE_INVALID; | |
1009 | else | |
1010 | return PL330_STATE_COMPLETING; | |
1011 | case DS_ST_FLTCMP: | |
1012 | if (is_manager(thrd)) | |
1013 | return PL330_STATE_INVALID; | |
1014 | else | |
1015 | return PL330_STATE_FAULT_COMPLETING; | |
1016 | default: | |
1017 | return PL330_STATE_INVALID; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | static void _stop(struct pl330_thread *thrd) | |
1022 | { | |
f6f2421c | 1023 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
1024 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
1025 | ||
1026 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
1027 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1028 | ||
1029 | /* Return if nothing needs to be done */ | |
1030 | if (_state(thrd) == PL330_STATE_COMPLETING | |
1031 | || _state(thrd) == PL330_STATE_KILLING | |
1032 | || _state(thrd) == PL330_STATE_STOPPED) | |
1033 | return; | |
1034 | ||
1035 | _emit_KILL(0, insn); | |
1036 | ||
1037 | /* Stop generating interrupts for SEV */ | |
1038 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
1039 | ||
1040 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
1041 | } | |
1042 | ||
1043 | /* Start doing req 'idx' of thread 'thrd' */ | |
1044 | static bool _trigger(struct pl330_thread *thrd) | |
1045 | { | |
f6f2421c | 1046 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 1047 | struct _pl330_req *req; |
9dc5a315 | 1048 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
1049 | struct _arg_GO go; |
1050 | unsigned ns; | |
1051 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1052 | int idx; | |
1053 | ||
1054 | /* Return if already ACTIVE */ | |
1055 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1056 | return true; | |
1057 | ||
1058 | idx = 1 - thrd->lstenq; | |
8ed30a14 | 1059 | if (thrd->req[idx].desc != NULL) { |
b7d861d9 | 1060 | req = &thrd->req[idx]; |
8ed30a14 | 1061 | } else { |
b7d861d9 | 1062 | idx = thrd->lstenq; |
8ed30a14 | 1063 | if (thrd->req[idx].desc != NULL) |
b7d861d9 BK |
1064 | req = &thrd->req[idx]; |
1065 | else | |
1066 | req = NULL; | |
1067 | } | |
1068 | ||
1069 | /* Return if no request */ | |
8ed30a14 | 1070 | if (!req) |
b7d861d9 BK |
1071 | return true; |
1072 | ||
0091b9d6 AK |
1073 | /* Return if req is running */ |
1074 | if (idx == thrd->req_running) | |
1075 | return true; | |
1076 | ||
9dc5a315 | 1077 | desc = req->desc; |
b7d861d9 | 1078 | |
9dc5a315 | 1079 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
b7d861d9 BK |
1080 | |
1081 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1082 | if (_manager_ns(thrd) && !ns) | |
f6f2421c | 1083 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
b7d861d9 BK |
1084 | __func__, __LINE__); |
1085 | ||
1086 | go.chan = thrd->id; | |
1087 | go.addr = req->mc_bus; | |
1088 | go.ns = ns; | |
1089 | _emit_GO(0, insn, &go); | |
1090 | ||
1091 | /* Set to generate interrupts for SEV */ | |
1092 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1093 | ||
1094 | /* Only manager can execute GO */ | |
1095 | _execute_DBGINSN(thrd, insn, true); | |
1096 | ||
1097 | thrd->req_running = idx; | |
1098 | ||
1099 | return true; | |
1100 | } | |
1101 | ||
1102 | static bool _start(struct pl330_thread *thrd) | |
1103 | { | |
1104 | switch (_state(thrd)) { | |
1105 | case PL330_STATE_FAULT_COMPLETING: | |
1106 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1107 | ||
1108 | if (_state(thrd) == PL330_STATE_KILLING) | |
1109 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1110 | ||
1111 | case PL330_STATE_FAULTING: | |
1112 | _stop(thrd); | |
1113 | ||
1114 | case PL330_STATE_KILLING: | |
1115 | case PL330_STATE_COMPLETING: | |
1116 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1117 | ||
1118 | case PL330_STATE_STOPPED: | |
1119 | return _trigger(thrd); | |
1120 | ||
1121 | case PL330_STATE_WFP: | |
1122 | case PL330_STATE_QUEUEBUSY: | |
1123 | case PL330_STATE_ATBARRIER: | |
1124 | case PL330_STATE_UPDTPC: | |
1125 | case PL330_STATE_CACHEMISS: | |
1126 | case PL330_STATE_EXECUTING: | |
1127 | return true; | |
1128 | ||
1129 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1130 | default: | |
1131 | return false; | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1136 | const struct _xfer_spec *pxs, int cyc) | |
1137 | { | |
1138 | int off = 0; | |
9dc5a315 | 1139 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
b7d861d9 | 1140 | |
3ecf51a4 BK |
1141 | /* check lock-up free version */ |
1142 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1143 | while (cyc--) { | |
1144 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1145 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1146 | } | |
1147 | } else { | |
1148 | while (cyc--) { | |
1149 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1150 | off += _emit_RMB(dry_run, &buf[off]); | |
1151 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1152 | off += _emit_WMB(dry_run, &buf[off]); | |
1153 | } | |
b7d861d9 BK |
1154 | } |
1155 | ||
1156 | return off; | |
1157 | } | |
1158 | ||
271e1b86 AK |
1159 | static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run, |
1160 | u8 buf[], const struct _xfer_spec *pxs, | |
1161 | int cyc) | |
b7d861d9 BK |
1162 | { |
1163 | int off = 0; | |
848e9776 BK |
1164 | enum pl330_cond cond; |
1165 | ||
271e1b86 AK |
1166 | if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) |
1167 | cond = BURST; | |
1168 | else | |
0a18f9b2 | 1169 | cond = SINGLE; |
b7d861d9 BK |
1170 | |
1171 | while (cyc--) { | |
848e9776 BK |
1172 | off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); |
1173 | off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri); | |
b7d861d9 | 1174 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
271e1b86 AK |
1175 | |
1176 | if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) | |
1177 | off += _emit_FLUSHP(dry_run, &buf[off], | |
1178 | pxs->desc->peri); | |
b7d861d9 BK |
1179 | } |
1180 | ||
1181 | return off; | |
1182 | } | |
1183 | ||
271e1b86 AK |
1184 | static inline int _ldst_memtodev(struct pl330_dmac *pl330, |
1185 | unsigned dry_run, u8 buf[], | |
1186 | const struct _xfer_spec *pxs, int cyc) | |
b7d861d9 BK |
1187 | { |
1188 | int off = 0; | |
848e9776 BK |
1189 | enum pl330_cond cond; |
1190 | ||
271e1b86 AK |
1191 | if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) |
1192 | cond = BURST; | |
1193 | else | |
0a18f9b2 | 1194 | cond = SINGLE; |
b7d861d9 BK |
1195 | |
1196 | while (cyc--) { | |
848e9776 | 1197 | off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); |
b7d861d9 | 1198 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
848e9776 | 1199 | off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri); |
271e1b86 AK |
1200 | |
1201 | if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) | |
1202 | off += _emit_FLUSHP(dry_run, &buf[off], | |
1203 | pxs->desc->peri); | |
b7d861d9 BK |
1204 | } |
1205 | ||
1206 | return off; | |
1207 | } | |
1208 | ||
271e1b86 | 1209 | static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
b7d861d9 BK |
1210 | const struct _xfer_spec *pxs, int cyc) |
1211 | { | |
1212 | int off = 0; | |
1213 | ||
9dc5a315 | 1214 | switch (pxs->desc->rqtype) { |
585a9d0b | 1215 | case DMA_MEM_TO_DEV: |
271e1b86 | 1216 | off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc); |
b7d861d9 | 1217 | break; |
585a9d0b | 1218 | case DMA_DEV_TO_MEM: |
271e1b86 | 1219 | off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc); |
b7d861d9 | 1220 | break; |
585a9d0b | 1221 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1222 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1223 | break; | |
1224 | default: | |
1225 | off += 0x40000000; /* Scare off the Client */ | |
1226 | break; | |
1227 | } | |
1228 | ||
1229 | return off; | |
1230 | } | |
1231 | ||
1232 | /* Returns bytes consumed and updates bursts */ | |
271e1b86 | 1233 | static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
b7d861d9 BK |
1234 | unsigned long *bursts, const struct _xfer_spec *pxs) |
1235 | { | |
1236 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1237 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1238 | struct _arg_LPEND lpend; | |
1239 | ||
31495d60 | 1240 | if (*bursts == 1) |
848e9776 | 1241 | return _bursts(pl330, dry_run, buf, pxs, 1); |
31495d60 | 1242 | |
b7d861d9 BK |
1243 | /* Max iterations possible in DMALP is 256 */ |
1244 | if (*bursts >= 256*256) { | |
1245 | lcnt1 = 256; | |
1246 | lcnt0 = 256; | |
1247 | cyc = *bursts / lcnt1 / lcnt0; | |
1248 | } else if (*bursts > 256) { | |
1249 | lcnt1 = 256; | |
1250 | lcnt0 = *bursts / lcnt1; | |
1251 | cyc = 1; | |
1252 | } else { | |
1253 | lcnt1 = *bursts; | |
1254 | lcnt0 = 0; | |
1255 | cyc = 1; | |
1256 | } | |
1257 | ||
1258 | szlp = _emit_LP(1, buf, 0, 0); | |
271e1b86 | 1259 | szbrst = _bursts(pl330, 1, buf, pxs, 1); |
b7d861d9 BK |
1260 | |
1261 | lpend.cond = ALWAYS; | |
1262 | lpend.forever = false; | |
1263 | lpend.loop = 0; | |
1264 | lpend.bjump = 0; | |
1265 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1266 | ||
1267 | if (lcnt0) { | |
1268 | szlp *= 2; | |
1269 | szlpend *= 2; | |
1270 | } | |
1271 | ||
1272 | /* | |
1273 | * Max bursts that we can unroll due to limit on the | |
1274 | * size of backward jump that can be encoded in DMALPEND | |
1275 | * which is 8-bits and hence 255 | |
1276 | */ | |
1277 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1278 | ||
1279 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1280 | ||
1281 | off = 0; | |
1282 | ||
1283 | if (lcnt0) { | |
1284 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1285 | ljmp0 = off; | |
1286 | } | |
1287 | ||
1288 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1289 | ljmp1 = off; | |
1290 | ||
271e1b86 | 1291 | off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); |
b7d861d9 BK |
1292 | |
1293 | lpend.cond = ALWAYS; | |
1294 | lpend.forever = false; | |
1295 | lpend.loop = 1; | |
1296 | lpend.bjump = off - ljmp1; | |
1297 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1298 | ||
1299 | if (lcnt0) { | |
1300 | lpend.cond = ALWAYS; | |
1301 | lpend.forever = false; | |
1302 | lpend.loop = 0; | |
1303 | lpend.bjump = off - ljmp0; | |
1304 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1305 | } | |
1306 | ||
1307 | *bursts = lcnt1 * cyc; | |
1308 | if (lcnt0) | |
1309 | *bursts *= lcnt0; | |
1310 | ||
1311 | return off; | |
1312 | } | |
1313 | ||
271e1b86 AK |
1314 | static inline int _setup_loops(struct pl330_dmac *pl330, |
1315 | unsigned dry_run, u8 buf[], | |
1316 | const struct _xfer_spec *pxs) | |
b7d861d9 | 1317 | { |
9dc5a315 | 1318 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1319 | u32 ccr = pxs->ccr; |
1320 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1321 | int off = 0; | |
1322 | ||
1323 | while (bursts) { | |
1324 | c = bursts; | |
271e1b86 | 1325 | off += _loop(pl330, dry_run, &buf[off], &c, pxs); |
b7d861d9 BK |
1326 | bursts -= c; |
1327 | } | |
1328 | ||
1329 | return off; | |
1330 | } | |
1331 | ||
271e1b86 AK |
1332 | static inline int _setup_xfer(struct pl330_dmac *pl330, |
1333 | unsigned dry_run, u8 buf[], | |
1334 | const struct _xfer_spec *pxs) | |
b7d861d9 | 1335 | { |
9dc5a315 | 1336 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1337 | int off = 0; |
1338 | ||
1339 | /* DMAMOV SAR, x->src_addr */ | |
1340 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1341 | /* DMAMOV DAR, x->dst_addr */ | |
1342 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1343 | ||
1344 | /* Setup Loop(s) */ | |
271e1b86 | 1345 | off += _setup_loops(pl330, dry_run, &buf[off], pxs); |
b7d861d9 BK |
1346 | |
1347 | return off; | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * A req is a sequence of one or more xfer units. | |
1352 | * Returns the number of bytes taken to setup the MC for the req. | |
1353 | */ | |
271e1b86 AK |
1354 | static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, |
1355 | struct pl330_thread *thrd, unsigned index, | |
1356 | struct _xfer_spec *pxs) | |
b7d861d9 BK |
1357 | { |
1358 | struct _pl330_req *req = &thrd->req[index]; | |
1359 | struct pl330_xfer *x; | |
1360 | u8 *buf = req->mc_cpu; | |
1361 | int off = 0; | |
1362 | ||
1363 | PL330_DBGMC_START(req->mc_bus); | |
1364 | ||
1365 | /* DMAMOV CCR, ccr */ | |
1366 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1367 | ||
9dc5a315 | 1368 | x = &pxs->desc->px; |
d5cef121 LPC |
1369 | /* Error if xfer length is not aligned at burst size */ |
1370 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) | |
1371 | return -EINVAL; | |
b7d861d9 | 1372 | |
271e1b86 | 1373 | off += _setup_xfer(pl330, dry_run, &buf[off], pxs); |
b7d861d9 BK |
1374 | |
1375 | /* DMASEV peripheral/event */ | |
1376 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1377 | /* DMAEND */ | |
1378 | off += _emit_END(dry_run, &buf[off]); | |
1379 | ||
1380 | return off; | |
1381 | } | |
1382 | ||
1383 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1384 | { | |
1385 | u32 ccr = 0; | |
1386 | ||
1387 | if (rqc->src_inc) | |
1388 | ccr |= CC_SRCINC; | |
1389 | ||
1390 | if (rqc->dst_inc) | |
1391 | ccr |= CC_DSTINC; | |
1392 | ||
1393 | /* We set same protection levels for Src and DST for now */ | |
1394 | if (rqc->privileged) | |
1395 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1396 | if (rqc->nonsecure) | |
1397 | ccr |= CC_SRCNS | CC_DSTNS; | |
1398 | if (rqc->insnaccess) | |
1399 | ccr |= CC_SRCIA | CC_DSTIA; | |
1400 | ||
1401 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1402 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1403 | ||
1404 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1405 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1406 | ||
1407 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1408 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1409 | ||
1410 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1411 | ||
1412 | return ccr; | |
1413 | } | |
1414 | ||
b7d861d9 BK |
1415 | /* |
1416 | * Submit a list of xfers after which the client wants notification. | |
1417 | * Client is not notified after each xfer unit, just once after all | |
1418 | * xfer units are done or some error occurs. | |
1419 | */ | |
9dc5a315 LPC |
1420 | static int pl330_submit_req(struct pl330_thread *thrd, |
1421 | struct dma_pl330_desc *desc) | |
b7d861d9 | 1422 | { |
f6f2421c | 1423 | struct pl330_dmac *pl330 = thrd->dmac; |
b7d861d9 BK |
1424 | struct _xfer_spec xs; |
1425 | unsigned long flags; | |
b7d861d9 BK |
1426 | unsigned idx; |
1427 | u32 ccr; | |
1428 | int ret = 0; | |
1429 | ||
b7d861d9 BK |
1430 | if (pl330->state == DYING |
1431 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
f6f2421c | 1432 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
b7d861d9 BK |
1433 | __func__, __LINE__); |
1434 | return -EAGAIN; | |
1435 | } | |
1436 | ||
1437 | /* If request for non-existing peripheral */ | |
9dc5a315 LPC |
1438 | if (desc->rqtype != DMA_MEM_TO_MEM && |
1439 | desc->peri >= pl330->pcfg.num_peri) { | |
f6f2421c | 1440 | dev_info(thrd->dmac->ddma.dev, |
b7d861d9 | 1441 | "%s:%d Invalid peripheral(%u)!\n", |
9dc5a315 | 1442 | __func__, __LINE__, desc->peri); |
b7d861d9 BK |
1443 | return -EINVAL; |
1444 | } | |
1445 | ||
1446 | spin_lock_irqsave(&pl330->lock, flags); | |
1447 | ||
1448 | if (_queue_full(thrd)) { | |
1449 | ret = -EAGAIN; | |
1450 | goto xfer_exit; | |
1451 | } | |
1452 | ||
9dc5a315 LPC |
1453 | /* Prefer Secure Channel */ |
1454 | if (!_manager_ns(thrd)) | |
1455 | desc->rqcfg.nonsecure = 0; | |
1456 | else | |
1457 | desc->rqcfg.nonsecure = 1; | |
b7d861d9 | 1458 | |
9dc5a315 | 1459 | ccr = _prepare_ccr(&desc->rqcfg); |
b7d861d9 | 1460 | |
8ed30a14 | 1461 | idx = thrd->req[0].desc == NULL ? 0 : 1; |
b7d861d9 BK |
1462 | |
1463 | xs.ccr = ccr; | |
9dc5a315 | 1464 | xs.desc = desc; |
b7d861d9 BK |
1465 | |
1466 | /* First dry run to check if req is acceptable */ | |
271e1b86 | 1467 | ret = _setup_req(pl330, 1, thrd, idx, &xs); |
b7d861d9 BK |
1468 | if (ret < 0) |
1469 | goto xfer_exit; | |
1470 | ||
f6f2421c | 1471 | if (ret > pl330->mcbufsz / 2) { |
e5489d5e MS |
1472 | dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", |
1473 | __func__, __LINE__, ret, pl330->mcbufsz / 2); | |
b7d861d9 BK |
1474 | ret = -ENOMEM; |
1475 | goto xfer_exit; | |
1476 | } | |
1477 | ||
1478 | /* Hook the request */ | |
1479 | thrd->lstenq = idx; | |
9dc5a315 | 1480 | thrd->req[idx].desc = desc; |
271e1b86 | 1481 | _setup_req(pl330, 0, thrd, idx, &xs); |
b7d861d9 BK |
1482 | |
1483 | ret = 0; | |
1484 | ||
1485 | xfer_exit: | |
1486 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1487 | ||
1488 | return ret; | |
1489 | } | |
1490 | ||
9dc5a315 | 1491 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
6079d38c | 1492 | { |
b1e51d77 | 1493 | struct dma_pl330_chan *pch; |
6079d38c LPC |
1494 | unsigned long flags; |
1495 | ||
b1e51d77 JMC |
1496 | if (!desc) |
1497 | return; | |
1498 | ||
1499 | pch = desc->pchan; | |
1500 | ||
6079d38c LPC |
1501 | /* If desc aborted */ |
1502 | if (!pch) | |
1503 | return; | |
1504 | ||
1505 | spin_lock_irqsave(&pch->lock, flags); | |
1506 | ||
1507 | desc->status = DONE; | |
1508 | ||
1509 | spin_unlock_irqrestore(&pch->lock, flags); | |
1510 | ||
1511 | tasklet_schedule(&pch->task); | |
1512 | } | |
1513 | ||
b7d861d9 BK |
1514 | static void pl330_dotask(unsigned long data) |
1515 | { | |
1516 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
b7d861d9 BK |
1517 | unsigned long flags; |
1518 | int i; | |
1519 | ||
1520 | spin_lock_irqsave(&pl330->lock, flags); | |
1521 | ||
1522 | /* The DMAC itself gone nuts */ | |
1523 | if (pl330->dmac_tbd.reset_dmac) { | |
1524 | pl330->state = DYING; | |
1525 | /* Reset the manager too */ | |
1526 | pl330->dmac_tbd.reset_mngr = true; | |
1527 | /* Clear the reset flag */ | |
1528 | pl330->dmac_tbd.reset_dmac = false; | |
1529 | } | |
1530 | ||
1531 | if (pl330->dmac_tbd.reset_mngr) { | |
1532 | _stop(pl330->manager); | |
1533 | /* Reset all channels */ | |
f6f2421c | 1534 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
b7d861d9 BK |
1535 | /* Clear the reset flag */ |
1536 | pl330->dmac_tbd.reset_mngr = false; | |
1537 | } | |
1538 | ||
f6f2421c | 1539 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 BK |
1540 | |
1541 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1542 | struct pl330_thread *thrd = &pl330->channels[i]; | |
f6f2421c | 1543 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1544 | enum pl330_op_err err; |
1545 | ||
1546 | _stop(thrd); | |
1547 | ||
1548 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1549 | err = PL330_ERR_FAIL; | |
1550 | else | |
1551 | err = PL330_ERR_ABORT; | |
1552 | ||
1553 | spin_unlock_irqrestore(&pl330->lock, flags); | |
9dc5a315 LPC |
1554 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
1555 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); | |
b7d861d9 BK |
1556 | spin_lock_irqsave(&pl330->lock, flags); |
1557 | ||
9dc5a315 LPC |
1558 | thrd->req[0].desc = NULL; |
1559 | thrd->req[1].desc = NULL; | |
8ed30a14 | 1560 | thrd->req_running = -1; |
b7d861d9 BK |
1561 | |
1562 | /* Clear the reset flag */ | |
1563 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1564 | } | |
1565 | } | |
1566 | ||
1567 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1568 | ||
1569 | return; | |
1570 | } | |
1571 | ||
1572 | /* Returns 1 if state was updated, 0 otherwise */ | |
f6f2421c | 1573 | static int pl330_update(struct pl330_dmac *pl330) |
b7d861d9 | 1574 | { |
9dc5a315 | 1575 | struct dma_pl330_desc *descdone, *tmp; |
b7d861d9 BK |
1576 | unsigned long flags; |
1577 | void __iomem *regs; | |
1578 | u32 val; | |
1579 | int id, ev, ret = 0; | |
1580 | ||
f6f2421c | 1581 | regs = pl330->base; |
b7d861d9 BK |
1582 | |
1583 | spin_lock_irqsave(&pl330->lock, flags); | |
1584 | ||
1585 | val = readl(regs + FSM) & 0x1; | |
1586 | if (val) | |
1587 | pl330->dmac_tbd.reset_mngr = true; | |
1588 | else | |
1589 | pl330->dmac_tbd.reset_mngr = false; | |
1590 | ||
f6f2421c | 1591 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
b7d861d9 BK |
1592 | pl330->dmac_tbd.reset_chan |= val; |
1593 | if (val) { | |
1594 | int i = 0; | |
f6f2421c | 1595 | while (i < pl330->pcfg.num_chan) { |
b7d861d9 | 1596 | if (val & (1 << i)) { |
f6f2421c | 1597 | dev_info(pl330->ddma.dev, |
b7d861d9 BK |
1598 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
1599 | i, readl(regs + CS(i)), | |
1600 | readl(regs + FTC(i))); | |
1601 | _stop(&pl330->channels[i]); | |
1602 | } | |
1603 | i++; | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | /* Check which event happened i.e, thread notified */ | |
1608 | val = readl(regs + ES); | |
f6f2421c LPC |
1609 | if (pl330->pcfg.num_events < 32 |
1610 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { | |
b7d861d9 | 1611 | pl330->dmac_tbd.reset_dmac = true; |
f6f2421c LPC |
1612 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
1613 | __LINE__); | |
b7d861d9 BK |
1614 | ret = 1; |
1615 | goto updt_exit; | |
1616 | } | |
1617 | ||
f6f2421c | 1618 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
b7d861d9 BK |
1619 | if (val & (1 << ev)) { /* Event occurred */ |
1620 | struct pl330_thread *thrd; | |
1621 | u32 inten = readl(regs + INTEN); | |
1622 | int active; | |
1623 | ||
1624 | /* Clear the event */ | |
1625 | if (inten & (1 << ev)) | |
1626 | writel(1 << ev, regs + INTCLR); | |
1627 | ||
1628 | ret = 1; | |
1629 | ||
1630 | id = pl330->events[ev]; | |
1631 | ||
1632 | thrd = &pl330->channels[id]; | |
1633 | ||
1634 | active = thrd->req_running; | |
1635 | if (active == -1) /* Aborted */ | |
1636 | continue; | |
1637 | ||
fdec53d5 | 1638 | /* Detach the req */ |
9dc5a315 LPC |
1639 | descdone = thrd->req[active].desc; |
1640 | thrd->req[active].desc = NULL; | |
fdec53d5 | 1641 | |
0091b9d6 AK |
1642 | thrd->req_running = -1; |
1643 | ||
b7d861d9 BK |
1644 | /* Get going again ASAP */ |
1645 | _start(thrd); | |
1646 | ||
1647 | /* For now, just make a list of callbacks to be done */ | |
9dc5a315 | 1648 | list_add_tail(&descdone->rqd, &pl330->req_done); |
b7d861d9 BK |
1649 | } |
1650 | } | |
1651 | ||
1652 | /* Now that we are in no hurry, do the callbacks */ | |
9dc5a315 LPC |
1653 | list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { |
1654 | list_del(&descdone->rqd); | |
b7d861d9 | 1655 | spin_unlock_irqrestore(&pl330->lock, flags); |
9dc5a315 | 1656 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
b7d861d9 BK |
1657 | spin_lock_irqsave(&pl330->lock, flags); |
1658 | } | |
1659 | ||
1660 | updt_exit: | |
1661 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1662 | ||
1663 | if (pl330->dmac_tbd.reset_dmac | |
1664 | || pl330->dmac_tbd.reset_mngr | |
1665 | || pl330->dmac_tbd.reset_chan) { | |
1666 | ret = 1; | |
1667 | tasklet_schedule(&pl330->tasks); | |
1668 | } | |
1669 | ||
1670 | return ret; | |
1671 | } | |
1672 | ||
b7d861d9 BK |
1673 | /* Reserve an event */ |
1674 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1675 | { | |
1676 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1677 | int ev; |
1678 | ||
f6f2421c | 1679 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
b7d861d9 BK |
1680 | if (pl330->events[ev] == -1) { |
1681 | pl330->events[ev] = thrd->id; | |
1682 | return ev; | |
1683 | } | |
1684 | ||
1685 | return -1; | |
1686 | } | |
1687 | ||
f6f2421c | 1688 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
b7d861d9 | 1689 | { |
f6f2421c | 1690 | return pl330->pcfg.irq_ns & (1 << i); |
b7d861d9 BK |
1691 | } |
1692 | ||
1693 | /* Upon success, returns IdentityToken for the | |
1694 | * allocated channel, NULL otherwise. | |
1695 | */ | |
f6f2421c | 1696 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
b7d861d9 BK |
1697 | { |
1698 | struct pl330_thread *thrd = NULL; | |
b7d861d9 BK |
1699 | unsigned long flags; |
1700 | int chans, i; | |
1701 | ||
b7d861d9 BK |
1702 | if (pl330->state == DYING) |
1703 | return NULL; | |
1704 | ||
f6f2421c | 1705 | chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1706 | |
1707 | spin_lock_irqsave(&pl330->lock, flags); | |
1708 | ||
1709 | for (i = 0; i < chans; i++) { | |
1710 | thrd = &pl330->channels[i]; | |
1711 | if ((thrd->free) && (!_manager_ns(thrd) || | |
f6f2421c | 1712 | _chan_ns(pl330, i))) { |
b7d861d9 BK |
1713 | thrd->ev = _alloc_event(thrd); |
1714 | if (thrd->ev >= 0) { | |
1715 | thrd->free = false; | |
1716 | thrd->lstenq = 1; | |
9dc5a315 | 1717 | thrd->req[0].desc = NULL; |
9dc5a315 | 1718 | thrd->req[1].desc = NULL; |
8ed30a14 | 1719 | thrd->req_running = -1; |
b7d861d9 BK |
1720 | break; |
1721 | } | |
1722 | } | |
1723 | thrd = NULL; | |
1724 | } | |
1725 | ||
1726 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1727 | ||
1728 | return thrd; | |
1729 | } | |
1730 | ||
1731 | /* Release an event */ | |
1732 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1733 | { | |
1734 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1735 | |
1736 | /* If the event is valid and was held by the thread */ | |
f6f2421c | 1737 | if (ev >= 0 && ev < pl330->pcfg.num_events |
b7d861d9 BK |
1738 | && pl330->events[ev] == thrd->id) |
1739 | pl330->events[ev] = -1; | |
1740 | } | |
1741 | ||
65ad6060 | 1742 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1743 | { |
b7d861d9 BK |
1744 | struct pl330_dmac *pl330; |
1745 | unsigned long flags; | |
1746 | ||
1747 | if (!thrd || thrd->free) | |
1748 | return; | |
1749 | ||
1750 | _stop(thrd); | |
1751 | ||
9dc5a315 LPC |
1752 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
1753 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); | |
b7d861d9 BK |
1754 | |
1755 | pl330 = thrd->dmac; | |
1756 | ||
1757 | spin_lock_irqsave(&pl330->lock, flags); | |
1758 | _free_event(thrd, thrd->ev); | |
1759 | thrd->free = true; | |
1760 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1761 | } | |
1762 | ||
1763 | /* Initialize the structure for PL330 configuration, that can be used | |
1764 | * by the client driver the make best use of the DMAC | |
1765 | */ | |
f6f2421c | 1766 | static void read_dmac_config(struct pl330_dmac *pl330) |
b7d861d9 | 1767 | { |
f6f2421c | 1768 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1769 | u32 val; |
1770 | ||
1771 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1772 | val &= CRD_DATA_WIDTH_MASK; | |
f6f2421c | 1773 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
b7d861d9 BK |
1774 | |
1775 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1776 | val &= CRD_DATA_BUFF_MASK; | |
f6f2421c | 1777 | pl330->pcfg.data_buf_dep = val + 1; |
b7d861d9 BK |
1778 | |
1779 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1780 | val &= CR0_NUM_CHANS_MASK; | |
1781 | val += 1; | |
f6f2421c | 1782 | pl330->pcfg.num_chan = val; |
b7d861d9 BK |
1783 | |
1784 | val = readl(regs + CR0); | |
1785 | if (val & CR0_PERIPH_REQ_SET) { | |
1786 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1787 | val += 1; | |
f6f2421c LPC |
1788 | pl330->pcfg.num_peri = val; |
1789 | pl330->pcfg.peri_ns = readl(regs + CR4); | |
b7d861d9 | 1790 | } else { |
f6f2421c | 1791 | pl330->pcfg.num_peri = 0; |
b7d861d9 BK |
1792 | } |
1793 | ||
1794 | val = readl(regs + CR0); | |
1795 | if (val & CR0_BOOT_MAN_NS) | |
f6f2421c | 1796 | pl330->pcfg.mode |= DMAC_MODE_NS; |
b7d861d9 | 1797 | else |
f6f2421c | 1798 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
b7d861d9 BK |
1799 | |
1800 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1801 | val &= CR0_NUM_EVENTS_MASK; | |
1802 | val += 1; | |
f6f2421c | 1803 | pl330->pcfg.num_events = val; |
b7d861d9 | 1804 | |
f6f2421c | 1805 | pl330->pcfg.irq_ns = readl(regs + CR3); |
b7d861d9 BK |
1806 | } |
1807 | ||
1808 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1809 | { | |
1810 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1811 | |
1812 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
f6f2421c | 1813 | + (thrd->id * pl330->mcbufsz); |
b7d861d9 | 1814 | thrd->req[0].mc_bus = pl330->mcode_bus |
f6f2421c | 1815 | + (thrd->id * pl330->mcbufsz); |
9dc5a315 | 1816 | thrd->req[0].desc = NULL; |
b7d861d9 BK |
1817 | |
1818 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
f6f2421c | 1819 | + pl330->mcbufsz / 2; |
b7d861d9 | 1820 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
f6f2421c | 1821 | + pl330->mcbufsz / 2; |
9dc5a315 | 1822 | thrd->req[1].desc = NULL; |
8ed30a14 LPC |
1823 | |
1824 | thrd->req_running = -1; | |
b7d861d9 BK |
1825 | } |
1826 | ||
1827 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1828 | { | |
f6f2421c | 1829 | int chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1830 | struct pl330_thread *thrd; |
1831 | int i; | |
1832 | ||
1833 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
1834 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), | |
1835 | GFP_KERNEL); | |
1836 | if (!pl330->channels) | |
1837 | return -ENOMEM; | |
1838 | ||
1839 | /* Init Channel threads */ | |
1840 | for (i = 0; i < chans; i++) { | |
1841 | thrd = &pl330->channels[i]; | |
1842 | thrd->id = i; | |
1843 | thrd->dmac = pl330; | |
1844 | _reset_thread(thrd); | |
1845 | thrd->free = true; | |
1846 | } | |
1847 | ||
1848 | /* MANAGER is indexed at the end */ | |
1849 | thrd = &pl330->channels[chans]; | |
1850 | thrd->id = chans; | |
1851 | thrd->dmac = pl330; | |
1852 | thrd->free = false; | |
1853 | pl330->manager = thrd; | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1859 | { | |
f6f2421c | 1860 | int chans = pl330->pcfg.num_chan; |
b7d861d9 | 1861 | int ret; |
b3040e40 | 1862 | |
b3040e40 | 1863 | /* |
b7d861d9 BK |
1864 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1865 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1866 | */ |
f6f2421c LPC |
1867 | pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, |
1868 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1869 | &pl330->mcode_bus, GFP_KERNEL); |
1870 | if (!pl330->mcode_cpu) { | |
f6f2421c | 1871 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
b7d861d9 BK |
1872 | __func__, __LINE__); |
1873 | return -ENOMEM; | |
1874 | } | |
1875 | ||
1876 | ret = dmac_alloc_threads(pl330); | |
1877 | if (ret) { | |
f6f2421c | 1878 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
b7d861d9 | 1879 | __func__, __LINE__); |
f6f2421c LPC |
1880 | dma_free_coherent(pl330->ddma.dev, |
1881 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1882 | pl330->mcode_cpu, pl330->mcode_bus); |
1883 | return ret; | |
1884 | } | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
f6f2421c | 1889 | static int pl330_add(struct pl330_dmac *pl330) |
b7d861d9 | 1890 | { |
b7d861d9 BK |
1891 | int i, ret; |
1892 | ||
b7d861d9 | 1893 | /* Check if we can handle this DMAC */ |
f6f2421c LPC |
1894 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1895 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", | |
1896 | pl330->pcfg.periph_id); | |
b7d861d9 BK |
1897 | return -EINVAL; |
1898 | } | |
b3040e40 | 1899 | |
b7d861d9 | 1900 | /* Read the configuration of the DMAC */ |
f6f2421c | 1901 | read_dmac_config(pl330); |
b3040e40 | 1902 | |
f6f2421c LPC |
1903 | if (pl330->pcfg.num_events == 0) { |
1904 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", | |
b7d861d9 BK |
1905 | __func__, __LINE__); |
1906 | return -EINVAL; | |
1907 | } | |
b3040e40 | 1908 | |
b7d861d9 | 1909 | spin_lock_init(&pl330->lock); |
1b9bb715 | 1910 | |
b7d861d9 | 1911 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 1912 | |
b7d861d9 | 1913 | /* Use default MC buffer size if not provided */ |
f6f2421c LPC |
1914 | if (!pl330->mcbufsz) |
1915 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 1916 | |
b7d861d9 | 1917 | /* Mark all events as free */ |
f6f2421c | 1918 | for (i = 0; i < pl330->pcfg.num_events; i++) |
b7d861d9 | 1919 | pl330->events[i] = -1; |
b3040e40 | 1920 | |
b7d861d9 BK |
1921 | /* Allocate resources needed by the DMAC */ |
1922 | ret = dmac_alloc_resources(pl330); | |
1923 | if (ret) { | |
f6f2421c | 1924 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
b7d861d9 BK |
1925 | return ret; |
1926 | } | |
b3040e40 | 1927 | |
b7d861d9 | 1928 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 1929 | |
b7d861d9 | 1930 | pl330->state = INIT; |
a2f5203f | 1931 | |
b7d861d9 BK |
1932 | return 0; |
1933 | } | |
b3040e40 | 1934 | |
b7d861d9 BK |
1935 | static int dmac_free_threads(struct pl330_dmac *pl330) |
1936 | { | |
b7d861d9 BK |
1937 | struct pl330_thread *thrd; |
1938 | int i; | |
b3040e40 | 1939 | |
b7d861d9 | 1940 | /* Release Channel threads */ |
f6f2421c | 1941 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 | 1942 | thrd = &pl330->channels[i]; |
65ad6060 | 1943 | pl330_release_channel(thrd); |
b7d861d9 | 1944 | } |
b3040e40 | 1945 | |
b7d861d9 BK |
1946 | /* Free memory */ |
1947 | kfree(pl330->channels); | |
b3040e40 | 1948 | |
b7d861d9 BK |
1949 | return 0; |
1950 | } | |
b3040e40 | 1951 | |
f6f2421c | 1952 | static void pl330_del(struct pl330_dmac *pl330) |
b7d861d9 | 1953 | { |
b7d861d9 BK |
1954 | pl330->state = UNINIT; |
1955 | ||
1956 | tasklet_kill(&pl330->tasks); | |
1957 | ||
1958 | /* Free DMAC resources */ | |
f6f2421c | 1959 | dmac_free_threads(pl330); |
b7d861d9 | 1960 | |
f6f2421c LPC |
1961 | dma_free_coherent(pl330->ddma.dev, |
1962 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, | |
1963 | pl330->mcode_bus); | |
b7d861d9 | 1964 | } |
b3040e40 | 1965 | |
3e2ec13a TA |
1966 | /* forward declaration */ |
1967 | static struct amba_driver pl330_driver; | |
1968 | ||
b3040e40 JB |
1969 | static inline struct dma_pl330_chan * |
1970 | to_pchan(struct dma_chan *ch) | |
1971 | { | |
1972 | if (!ch) | |
1973 | return NULL; | |
1974 | ||
1975 | return container_of(ch, struct dma_pl330_chan, chan); | |
1976 | } | |
1977 | ||
1978 | static inline struct dma_pl330_desc * | |
1979 | to_desc(struct dma_async_tx_descriptor *tx) | |
1980 | { | |
1981 | return container_of(tx, struct dma_pl330_desc, txd); | |
1982 | } | |
1983 | ||
b3040e40 JB |
1984 | static inline void fill_queue(struct dma_pl330_chan *pch) |
1985 | { | |
1986 | struct dma_pl330_desc *desc; | |
1987 | int ret; | |
1988 | ||
1989 | list_for_each_entry(desc, &pch->work_list, node) { | |
1990 | ||
1991 | /* If already submitted */ | |
1992 | if (desc->status == BUSY) | |
30fb980b | 1993 | continue; |
b3040e40 | 1994 | |
9dc5a315 | 1995 | ret = pl330_submit_req(pch->thread, desc); |
b3040e40 JB |
1996 | if (!ret) { |
1997 | desc->status = BUSY; | |
b3040e40 JB |
1998 | } else if (ret == -EAGAIN) { |
1999 | /* QFull or DMAC Dying */ | |
2000 | break; | |
2001 | } else { | |
2002 | /* Unacceptable request */ | |
2003 | desc->status = DONE; | |
f6f2421c | 2004 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
b3040e40 JB |
2005 | __func__, __LINE__, desc->txd.cookie); |
2006 | tasklet_schedule(&pch->task); | |
2007 | } | |
2008 | } | |
2009 | } | |
2010 | ||
2011 | static void pl330_tasklet(unsigned long data) | |
2012 | { | |
2013 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
2014 | struct dma_pl330_desc *desc, *_dt; | |
2015 | unsigned long flags; | |
ae43b328 | 2016 | bool power_down = false; |
b3040e40 JB |
2017 | |
2018 | spin_lock_irqsave(&pch->lock, flags); | |
2019 | ||
2020 | /* Pick up ripe tomatoes */ | |
2021 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
2022 | if (desc->status == DONE) { | |
30c1dc0f | 2023 | if (!pch->cyclic) |
eab21585 | 2024 | dma_cookie_complete(&desc->txd); |
39ff8613 | 2025 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
2026 | } |
2027 | ||
2028 | /* Try to submit a req imm. next to the last completed cookie */ | |
2029 | fill_queue(pch); | |
2030 | ||
ae43b328 KK |
2031 | if (list_empty(&pch->work_list)) { |
2032 | spin_lock(&pch->thread->dmac->lock); | |
2033 | _stop(pch->thread); | |
2034 | spin_unlock(&pch->thread->dmac->lock); | |
2035 | power_down = true; | |
2036 | } else { | |
2037 | /* Make sure the PL330 Channel thread is active */ | |
2038 | spin_lock(&pch->thread->dmac->lock); | |
2039 | _start(pch->thread); | |
2040 | spin_unlock(&pch->thread->dmac->lock); | |
2041 | } | |
b3040e40 | 2042 | |
39ff8613 | 2043 | while (!list_empty(&pch->completed_list)) { |
f08462c6 | 2044 | struct dmaengine_desc_callback cb; |
b3040e40 | 2045 | |
39ff8613 LPC |
2046 | desc = list_first_entry(&pch->completed_list, |
2047 | struct dma_pl330_desc, node); | |
2048 | ||
f08462c6 | 2049 | dmaengine_desc_get_callback(&desc->txd, &cb); |
39ff8613 LPC |
2050 | |
2051 | if (pch->cyclic) { | |
2052 | desc->status = PREP; | |
2053 | list_move_tail(&desc->node, &pch->work_list); | |
ae43b328 KK |
2054 | if (power_down) { |
2055 | spin_lock(&pch->thread->dmac->lock); | |
2056 | _start(pch->thread); | |
2057 | spin_unlock(&pch->thread->dmac->lock); | |
2058 | power_down = false; | |
2059 | } | |
39ff8613 LPC |
2060 | } else { |
2061 | desc->status = FREE; | |
2062 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2063 | } | |
2064 | ||
d38a8c62 DW |
2065 | dma_descriptor_unmap(&desc->txd); |
2066 | ||
f08462c6 | 2067 | if (dmaengine_desc_callback_valid(&cb)) { |
39ff8613 | 2068 | spin_unlock_irqrestore(&pch->lock, flags); |
f08462c6 | 2069 | dmaengine_desc_callback_invoke(&cb, NULL); |
39ff8613 LPC |
2070 | spin_lock_irqsave(&pch->lock, flags); |
2071 | } | |
2072 | } | |
2073 | spin_unlock_irqrestore(&pch->lock, flags); | |
ae43b328 KK |
2074 | |
2075 | /* If work list empty, power down */ | |
2076 | if (power_down) { | |
2077 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2078 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
2079 | } | |
b3040e40 JB |
2080 | } |
2081 | ||
3e2ec13a TA |
2082 | bool pl330_filter(struct dma_chan *chan, void *param) |
2083 | { | |
cd072515 | 2084 | u8 *peri_id; |
3e2ec13a TA |
2085 | |
2086 | if (chan->device->dev->driver != &pl330_driver.drv) | |
2087 | return false; | |
2088 | ||
cd072515 | 2089 | peri_id = chan->private; |
2f986ec6 | 2090 | return *peri_id == (unsigned long)param; |
3e2ec13a TA |
2091 | } |
2092 | EXPORT_SYMBOL(pl330_filter); | |
2093 | ||
a80258f9 PV |
2094 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2095 | struct of_dma *ofdma) | |
2096 | { | |
2097 | int count = dma_spec->args_count; | |
f6f2421c | 2098 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
70cbb163 | 2099 | unsigned int chan_id; |
a80258f9 | 2100 | |
f6f2421c LPC |
2101 | if (!pl330) |
2102 | return NULL; | |
2103 | ||
a80258f9 PV |
2104 | if (count != 1) |
2105 | return NULL; | |
2106 | ||
70cbb163 | 2107 | chan_id = dma_spec->args[0]; |
f6f2421c | 2108 | if (chan_id >= pl330->num_peripherals) |
70cbb163 | 2109 | return NULL; |
a80258f9 | 2110 | |
f6f2421c | 2111 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
a80258f9 PV |
2112 | } |
2113 | ||
b3040e40 JB |
2114 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2115 | { | |
2116 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2117 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2118 | unsigned long flags; |
2119 | ||
2120 | spin_lock_irqsave(&pch->lock, flags); | |
2121 | ||
d3ee98cd | 2122 | dma_cookie_init(chan); |
42bc9cf4 | 2123 | pch->cyclic = false; |
b3040e40 | 2124 | |
f6f2421c | 2125 | pch->thread = pl330_request_channel(pl330); |
65ad6060 | 2126 | if (!pch->thread) { |
b3040e40 | 2127 | spin_unlock_irqrestore(&pch->lock, flags); |
02747885 | 2128 | return -ENOMEM; |
b3040e40 JB |
2129 | } |
2130 | ||
2131 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2132 | ||
2133 | spin_unlock_irqrestore(&pch->lock, flags); | |
2134 | ||
2135 | return 1; | |
2136 | } | |
2137 | ||
740aa957 MR |
2138 | static int pl330_config(struct dma_chan *chan, |
2139 | struct dma_slave_config *slave_config) | |
2140 | { | |
2141 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2142 | ||
2143 | if (slave_config->direction == DMA_MEM_TO_DEV) { | |
2144 | if (slave_config->dst_addr) | |
2145 | pch->fifo_addr = slave_config->dst_addr; | |
2146 | if (slave_config->dst_addr_width) | |
2147 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
2148 | if (slave_config->dst_maxburst) | |
2149 | pch->burst_len = slave_config->dst_maxburst; | |
2150 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { | |
2151 | if (slave_config->src_addr) | |
2152 | pch->fifo_addr = slave_config->src_addr; | |
2153 | if (slave_config->src_addr_width) | |
2154 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
2155 | if (slave_config->src_maxburst) | |
2156 | pch->burst_len = slave_config->src_maxburst; | |
2157 | } | |
2158 | ||
2159 | return 0; | |
2160 | } | |
2161 | ||
2162 | static int pl330_terminate_all(struct dma_chan *chan) | |
b3040e40 JB |
2163 | { |
2164 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2165 | struct dma_pl330_desc *desc; |
b3040e40 | 2166 | unsigned long flags; |
f6f2421c | 2167 | struct pl330_dmac *pl330 = pch->dmac; |
ae43b886 | 2168 | LIST_HEAD(list); |
b3040e40 | 2169 | |
81cc6edc | 2170 | pm_runtime_get_sync(pl330->ddma.dev); |
740aa957 MR |
2171 | spin_lock_irqsave(&pch->lock, flags); |
2172 | spin_lock(&pl330->lock); | |
2173 | _stop(pch->thread); | |
2174 | spin_unlock(&pl330->lock); | |
2175 | ||
2176 | pch->thread->req[0].desc = NULL; | |
2177 | pch->thread->req[1].desc = NULL; | |
2178 | pch->thread->req_running = -1; | |
2179 | ||
2180 | /* Mark all desc done */ | |
2181 | list_for_each_entry(desc, &pch->submitted_list, node) { | |
2182 | desc->status = FREE; | |
2183 | dma_cookie_complete(&desc->txd); | |
2184 | } | |
ae43b328 | 2185 | |
740aa957 MR |
2186 | list_for_each_entry(desc, &pch->work_list , node) { |
2187 | desc->status = FREE; | |
2188 | dma_cookie_complete(&desc->txd); | |
1d0c1d60 | 2189 | } |
b3040e40 | 2190 | |
740aa957 MR |
2191 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
2192 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); | |
2193 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); | |
2194 | spin_unlock_irqrestore(&pch->lock, flags); | |
81cc6edc KK |
2195 | pm_runtime_mark_last_busy(pl330->ddma.dev); |
2196 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
740aa957 | 2197 | |
b3040e40 JB |
2198 | return 0; |
2199 | } | |
2200 | ||
88987d2c RB |
2201 | /* |
2202 | * We don't support DMA_RESUME command because of hardware | |
2203 | * limitations, so after pausing the channel we cannot restore | |
2204 | * it to active state. We have to terminate channel and setup | |
2205 | * DMA transfer again. This pause feature was implemented to | |
2206 | * allow safely read residue before channel termination. | |
2207 | */ | |
5503aed8 | 2208 | static int pl330_pause(struct dma_chan *chan) |
88987d2c RB |
2209 | { |
2210 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2211 | struct pl330_dmac *pl330 = pch->dmac; | |
2212 | unsigned long flags; | |
2213 | ||
2214 | pm_runtime_get_sync(pl330->ddma.dev); | |
2215 | spin_lock_irqsave(&pch->lock, flags); | |
2216 | ||
2217 | spin_lock(&pl330->lock); | |
2218 | _stop(pch->thread); | |
2219 | spin_unlock(&pl330->lock); | |
2220 | ||
2221 | spin_unlock_irqrestore(&pch->lock, flags); | |
2222 | pm_runtime_mark_last_busy(pl330->ddma.dev); | |
2223 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
b3040e40 JB |
2228 | static void pl330_free_chan_resources(struct dma_chan *chan) |
2229 | { | |
2230 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2231 | unsigned long flags; | |
2232 | ||
b3040e40 JB |
2233 | tasklet_kill(&pch->task); |
2234 | ||
ae43b328 | 2235 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
da331ba8 BZ |
2236 | spin_lock_irqsave(&pch->lock, flags); |
2237 | ||
65ad6060 LPC |
2238 | pl330_release_channel(pch->thread); |
2239 | pch->thread = NULL; | |
b3040e40 | 2240 | |
42bc9cf4 BK |
2241 | if (pch->cyclic) |
2242 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2243 | ||
b3040e40 | 2244 | spin_unlock_irqrestore(&pch->lock, flags); |
ae43b328 KK |
2245 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
2246 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
b3040e40 JB |
2247 | } |
2248 | ||
5503aed8 BD |
2249 | static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, |
2250 | struct dma_pl330_desc *desc) | |
aee4d1fa RB |
2251 | { |
2252 | struct pl330_thread *thrd = pch->thread; | |
2253 | struct pl330_dmac *pl330 = pch->dmac; | |
2254 | void __iomem *regs = thrd->dmac->base; | |
2255 | u32 val, addr; | |
2256 | ||
2257 | pm_runtime_get_sync(pl330->ddma.dev); | |
2258 | val = addr = 0; | |
2259 | if (desc->rqcfg.src_inc) { | |
2260 | val = readl(regs + SA(thrd->id)); | |
2261 | addr = desc->px.src_addr; | |
2262 | } else { | |
2263 | val = readl(regs + DA(thrd->id)); | |
2264 | addr = desc->px.dst_addr; | |
2265 | } | |
2266 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2267 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
c44da03d SB |
2268 | |
2269 | /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ | |
2270 | if (!val) | |
2271 | return 0; | |
2272 | ||
aee4d1fa RB |
2273 | return val - addr; |
2274 | } | |
2275 | ||
b3040e40 JB |
2276 | static enum dma_status |
2277 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2278 | struct dma_tx_state *txstate) | |
2279 | { | |
aee4d1fa RB |
2280 | enum dma_status ret; |
2281 | unsigned long flags; | |
d64e9a2c | 2282 | struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; |
aee4d1fa RB |
2283 | struct dma_pl330_chan *pch = to_pchan(chan); |
2284 | unsigned int transferred, residual = 0; | |
2285 | ||
2286 | ret = dma_cookie_status(chan, cookie, txstate); | |
2287 | ||
2288 | if (!txstate) | |
2289 | return ret; | |
2290 | ||
2291 | if (ret == DMA_COMPLETE) | |
2292 | goto out; | |
2293 | ||
2294 | spin_lock_irqsave(&pch->lock, flags); | |
a40235a2 | 2295 | spin_lock(&pch->thread->dmac->lock); |
aee4d1fa RB |
2296 | |
2297 | if (pch->thread->req_running != -1) | |
2298 | running = pch->thread->req[pch->thread->req_running].desc; | |
2299 | ||
d64e9a2c SB |
2300 | last_enq = pch->thread->req[pch->thread->lstenq].desc; |
2301 | ||
aee4d1fa RB |
2302 | /* Check in pending list */ |
2303 | list_for_each_entry(desc, &pch->work_list, node) { | |
2304 | if (desc->status == DONE) | |
2305 | transferred = desc->bytes_requested; | |
2306 | else if (running && desc == running) | |
2307 | transferred = | |
2308 | pl330_get_current_xferred_count(pch, desc); | |
d64e9a2c SB |
2309 | else if (desc->status == BUSY) |
2310 | /* | |
2311 | * Busy but not running means either just enqueued, | |
2312 | * or finished and not yet marked done | |
2313 | */ | |
2314 | if (desc == last_enq) | |
2315 | transferred = 0; | |
2316 | else | |
2317 | transferred = desc->bytes_requested; | |
aee4d1fa RB |
2318 | else |
2319 | transferred = 0; | |
2320 | residual += desc->bytes_requested - transferred; | |
2321 | if (desc->txd.cookie == cookie) { | |
75967b78 BD |
2322 | switch (desc->status) { |
2323 | case DONE: | |
2324 | ret = DMA_COMPLETE; | |
2325 | break; | |
2326 | case PREP: | |
2327 | case BUSY: | |
2328 | ret = DMA_IN_PROGRESS; | |
2329 | break; | |
2330 | default: | |
2331 | WARN_ON(1); | |
2332 | } | |
aee4d1fa RB |
2333 | break; |
2334 | } | |
2335 | if (desc->last) | |
2336 | residual = 0; | |
2337 | } | |
a40235a2 | 2338 | spin_unlock(&pch->thread->dmac->lock); |
aee4d1fa RB |
2339 | spin_unlock_irqrestore(&pch->lock, flags); |
2340 | ||
2341 | out: | |
2342 | dma_set_residue(txstate, residual); | |
2343 | ||
2344 | return ret; | |
b3040e40 JB |
2345 | } |
2346 | ||
2347 | static void pl330_issue_pending(struct dma_chan *chan) | |
2348 | { | |
04abf5da LPC |
2349 | struct dma_pl330_chan *pch = to_pchan(chan); |
2350 | unsigned long flags; | |
2351 | ||
2352 | spin_lock_irqsave(&pch->lock, flags); | |
ae43b328 KK |
2353 | if (list_empty(&pch->work_list)) { |
2354 | /* | |
2355 | * Warn on nothing pending. Empty submitted_list may | |
2356 | * break our pm_runtime usage counter as it is | |
2357 | * updated on work_list emptiness status. | |
2358 | */ | |
2359 | WARN_ON(list_empty(&pch->submitted_list)); | |
2360 | pm_runtime_get_sync(pch->dmac->ddma.dev); | |
2361 | } | |
04abf5da LPC |
2362 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); |
2363 | spin_unlock_irqrestore(&pch->lock, flags); | |
2364 | ||
2365 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2366 | } |
2367 | ||
2368 | /* | |
2369 | * We returned the last one of the circular list of descriptor(s) | |
2370 | * from prep_xxx, so the argument to submit corresponds to the last | |
2371 | * descriptor of the list. | |
2372 | */ | |
2373 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2374 | { | |
2375 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2376 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2377 | dma_cookie_t cookie; | |
2378 | unsigned long flags; | |
2379 | ||
2380 | spin_lock_irqsave(&pch->lock, flags); | |
2381 | ||
2382 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2383 | while (!list_empty(&last->node)) { |
2384 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2385 | if (pch->cyclic) { |
2386 | desc->txd.callback = last->txd.callback; | |
2387 | desc->txd.callback_param = last->txd.callback_param; | |
2388 | } | |
5dd90e5b | 2389 | desc->last = false; |
b3040e40 | 2390 | |
884485e1 | 2391 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2392 | |
04abf5da | 2393 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2394 | } |
2395 | ||
aee4d1fa | 2396 | last->last = true; |
884485e1 | 2397 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2398 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2399 | spin_unlock_irqrestore(&pch->lock, flags); |
2400 | ||
2401 | return cookie; | |
2402 | } | |
2403 | ||
2404 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2405 | { | |
b3040e40 | 2406 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2407 | desc->rqcfg.scctl = CCTRL0; |
2408 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 JB |
2409 | desc->txd.tx_submit = pl330_tx_submit; |
2410 | ||
2411 | INIT_LIST_HEAD(&desc->node); | |
2412 | } | |
2413 | ||
2414 | /* Returns the number of descriptors added to the DMAC pool */ | |
f6f2421c | 2415 | static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) |
b3040e40 JB |
2416 | { |
2417 | struct dma_pl330_desc *desc; | |
2418 | unsigned long flags; | |
2419 | int i; | |
2420 | ||
0baf8f6a | 2421 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2422 | if (!desc) |
2423 | return 0; | |
2424 | ||
f6f2421c | 2425 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 JB |
2426 | |
2427 | for (i = 0; i < count; i++) { | |
2428 | _init_desc(&desc[i]); | |
f6f2421c | 2429 | list_add_tail(&desc[i].node, &pl330->desc_pool); |
b3040e40 JB |
2430 | } |
2431 | ||
f6f2421c | 2432 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2433 | |
2434 | return count; | |
2435 | } | |
2436 | ||
f6f2421c | 2437 | static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) |
b3040e40 JB |
2438 | { |
2439 | struct dma_pl330_desc *desc = NULL; | |
2440 | unsigned long flags; | |
2441 | ||
f6f2421c | 2442 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 | 2443 | |
f6f2421c LPC |
2444 | if (!list_empty(&pl330->desc_pool)) { |
2445 | desc = list_entry(pl330->desc_pool.next, | |
b3040e40 JB |
2446 | struct dma_pl330_desc, node); |
2447 | ||
2448 | list_del_init(&desc->node); | |
2449 | ||
2450 | desc->status = PREP; | |
2451 | desc->txd.callback = NULL; | |
2452 | } | |
2453 | ||
f6f2421c | 2454 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2455 | |
2456 | return desc; | |
2457 | } | |
2458 | ||
2459 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2460 | { | |
f6f2421c | 2461 | struct pl330_dmac *pl330 = pch->dmac; |
cd072515 | 2462 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2463 | struct dma_pl330_desc *desc; |
2464 | ||
2465 | /* Pluck one desc from the pool of DMAC */ | |
f6f2421c | 2466 | desc = pluck_desc(pl330); |
b3040e40 JB |
2467 | |
2468 | /* If the DMAC pool is empty, alloc new */ | |
2469 | if (!desc) { | |
f6f2421c | 2470 | if (!add_desc(pl330, GFP_ATOMIC, 1)) |
b3040e40 JB |
2471 | return NULL; |
2472 | ||
2473 | /* Try again */ | |
f6f2421c | 2474 | desc = pluck_desc(pl330); |
b3040e40 | 2475 | if (!desc) { |
f6f2421c | 2476 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2477 | "%s:%d ALERT!\n", __func__, __LINE__); |
2478 | return NULL; | |
2479 | } | |
2480 | } | |
2481 | ||
2482 | /* Initialize the descriptor */ | |
2483 | desc->pchan = pch; | |
2484 | desc->txd.cookie = 0; | |
2485 | async_tx_ack(&desc->txd); | |
2486 | ||
9dc5a315 | 2487 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
f6f2421c | 2488 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
b3040e40 JB |
2489 | |
2490 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2491 | ||
2492 | return desc; | |
2493 | } | |
2494 | ||
2495 | static inline void fill_px(struct pl330_xfer *px, | |
2496 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2497 | { | |
b3040e40 JB |
2498 | px->bytes = len; |
2499 | px->dst_addr = dst; | |
2500 | px->src_addr = src; | |
2501 | } | |
2502 | ||
2503 | static struct dma_pl330_desc * | |
2504 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2505 | dma_addr_t src, size_t len) | |
2506 | { | |
2507 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2508 | ||
2509 | if (!desc) { | |
f6f2421c | 2510 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
b3040e40 JB |
2511 | __func__, __LINE__); |
2512 | return NULL; | |
2513 | } | |
2514 | ||
2515 | /* | |
2516 | * Ideally we should lookout for reqs bigger than | |
2517 | * those that can be programmed with 256 bytes of | |
2518 | * MC buffer, but considering a req size is seldom | |
2519 | * going to be word-unaligned and more than 200MB, | |
2520 | * we take it easy. | |
2521 | * Also, should the limit is reached we'd rather | |
2522 | * have the platform increase MC buffer size than | |
2523 | * complicating this API driver. | |
2524 | */ | |
2525 | fill_px(&desc->px, dst, src, len); | |
2526 | ||
2527 | return desc; | |
2528 | } | |
2529 | ||
2530 | /* Call after fixing burst size */ | |
2531 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2532 | { | |
2533 | struct dma_pl330_chan *pch = desc->pchan; | |
f6f2421c | 2534 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2535 | int burst_len; |
2536 | ||
f6f2421c | 2537 | burst_len = pl330->pcfg.data_bus_width / 8; |
c27f9556 | 2538 | burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; |
b3040e40 JB |
2539 | burst_len >>= desc->rqcfg.brst_size; |
2540 | ||
2541 | /* src/dst_burst_len can't be more than 16 */ | |
2542 | if (burst_len > 16) | |
2543 | burst_len = 16; | |
2544 | ||
2545 | while (burst_len > 1) { | |
2546 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
2547 | break; | |
2548 | burst_len--; | |
2549 | } | |
2550 | ||
2551 | return burst_len; | |
2552 | } | |
2553 | ||
42bc9cf4 BK |
2554 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2555 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2556 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 2557 | unsigned long flags) |
42bc9cf4 | 2558 | { |
fc514460 | 2559 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2560 | struct dma_pl330_chan *pch = to_pchan(chan); |
f6f2421c | 2561 | struct pl330_dmac *pl330 = pch->dmac; |
fc514460 | 2562 | unsigned int i; |
42bc9cf4 BK |
2563 | dma_addr_t dst; |
2564 | dma_addr_t src; | |
2565 | ||
fc514460 | 2566 | if (len % period_len != 0) |
42bc9cf4 | 2567 | return NULL; |
42bc9cf4 | 2568 | |
fc514460 | 2569 | if (!is_slave_direction(direction)) { |
f6f2421c | 2570 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
42bc9cf4 BK |
2571 | __func__, __LINE__); |
2572 | return NULL; | |
2573 | } | |
2574 | ||
fc514460 LPC |
2575 | for (i = 0; i < len / period_len; i++) { |
2576 | desc = pl330_get_desc(pch); | |
2577 | if (!desc) { | |
f6f2421c | 2578 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
fc514460 | 2579 | __func__, __LINE__); |
42bc9cf4 | 2580 | |
fc514460 LPC |
2581 | if (!first) |
2582 | return NULL; | |
2583 | ||
f6f2421c | 2584 | spin_lock_irqsave(&pl330->pool_lock, flags); |
fc514460 LPC |
2585 | |
2586 | while (!list_empty(&first->node)) { | |
2587 | desc = list_entry(first->node.next, | |
2588 | struct dma_pl330_desc, node); | |
f6f2421c | 2589 | list_move_tail(&desc->node, &pl330->desc_pool); |
fc514460 LPC |
2590 | } |
2591 | ||
f6f2421c | 2592 | list_move_tail(&first->node, &pl330->desc_pool); |
fc514460 | 2593 | |
f6f2421c | 2594 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
42bc9cf4 | 2595 | |
fc514460 LPC |
2596 | return NULL; |
2597 | } | |
2598 | ||
2599 | switch (direction) { | |
2600 | case DMA_MEM_TO_DEV: | |
2601 | desc->rqcfg.src_inc = 1; | |
2602 | desc->rqcfg.dst_inc = 0; | |
fc514460 LPC |
2603 | src = dma_addr; |
2604 | dst = pch->fifo_addr; | |
2605 | break; | |
2606 | case DMA_DEV_TO_MEM: | |
2607 | desc->rqcfg.src_inc = 0; | |
2608 | desc->rqcfg.dst_inc = 1; | |
fc514460 LPC |
2609 | src = pch->fifo_addr; |
2610 | dst = dma_addr; | |
2611 | break; | |
2612 | default: | |
2613 | break; | |
2614 | } | |
2615 | ||
9dc5a315 | 2616 | desc->rqtype = direction; |
fc514460 | 2617 | desc->rqcfg.brst_size = pch->burst_sz; |
0a18f9b2 | 2618 | desc->rqcfg.brst_len = 1; |
aee4d1fa | 2619 | desc->bytes_requested = period_len; |
fc514460 LPC |
2620 | fill_px(&desc->px, dst, src, period_len); |
2621 | ||
2622 | if (!first) | |
2623 | first = desc; | |
2624 | else | |
2625 | list_add_tail(&desc->node, &first->node); | |
2626 | ||
2627 | dma_addr += period_len; | |
2628 | } | |
2629 | ||
2630 | if (!desc) | |
2631 | return NULL; | |
2632 | ||
2633 | pch->cyclic = true; | |
2634 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2635 | |
2636 | return &desc->txd; | |
2637 | } | |
2638 | ||
b3040e40 JB |
2639 | static struct dma_async_tx_descriptor * |
2640 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2641 | dma_addr_t src, size_t len, unsigned long flags) | |
2642 | { | |
2643 | struct dma_pl330_desc *desc; | |
2644 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f5636854 | 2645 | struct pl330_dmac *pl330; |
b3040e40 JB |
2646 | int burst; |
2647 | ||
4e0e6109 | 2648 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2649 | return NULL; |
2650 | ||
f5636854 MS |
2651 | pl330 = pch->dmac; |
2652 | ||
b3040e40 JB |
2653 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
2654 | if (!desc) | |
2655 | return NULL; | |
2656 | ||
2657 | desc->rqcfg.src_inc = 1; | |
2658 | desc->rqcfg.dst_inc = 1; | |
9dc5a315 | 2659 | desc->rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2660 | |
2661 | /* Select max possible burst size */ | |
f6f2421c | 2662 | burst = pl330->pcfg.data_bus_width / 8; |
b3040e40 | 2663 | |
137bd110 JM |
2664 | /* |
2665 | * Make sure we use a burst size that aligns with all the memcpy | |
2666 | * parameters because our DMA programming algorithm doesn't cope with | |
2667 | * transfers which straddle an entry in the DMA device's MFIFO. | |
2668 | */ | |
2669 | while ((src | dst | len) & (burst - 1)) | |
b3040e40 | 2670 | burst /= 2; |
b3040e40 JB |
2671 | |
2672 | desc->rqcfg.brst_size = 0; | |
2673 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2674 | desc->rqcfg.brst_size++; | |
2675 | ||
137bd110 JM |
2676 | /* |
2677 | * If burst size is smaller than bus width then make sure we only | |
2678 | * transfer one at a time to avoid a burst stradling an MFIFO entry. | |
2679 | */ | |
2680 | if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) | |
2681 | desc->rqcfg.brst_len = 1; | |
2682 | ||
b3040e40 | 2683 | desc->rqcfg.brst_len = get_burst_len(desc, len); |
ae128293 | 2684 | desc->bytes_requested = len; |
b3040e40 JB |
2685 | |
2686 | desc->txd.flags = flags; | |
2687 | ||
2688 | return &desc->txd; | |
2689 | } | |
2690 | ||
f6f2421c | 2691 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
52a9d179 CP |
2692 | struct dma_pl330_desc *first) |
2693 | { | |
2694 | unsigned long flags; | |
2695 | struct dma_pl330_desc *desc; | |
2696 | ||
2697 | if (!first) | |
2698 | return; | |
2699 | ||
f6f2421c | 2700 | spin_lock_irqsave(&pl330->pool_lock, flags); |
52a9d179 CP |
2701 | |
2702 | while (!list_empty(&first->node)) { | |
2703 | desc = list_entry(first->node.next, | |
2704 | struct dma_pl330_desc, node); | |
f6f2421c | 2705 | list_move_tail(&desc->node, &pl330->desc_pool); |
52a9d179 CP |
2706 | } |
2707 | ||
f6f2421c | 2708 | list_move_tail(&first->node, &pl330->desc_pool); |
52a9d179 | 2709 | |
f6f2421c | 2710 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
52a9d179 CP |
2711 | } |
2712 | ||
b3040e40 JB |
2713 | static struct dma_async_tx_descriptor * |
2714 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2715 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2716 | unsigned long flg, void *context) |
b3040e40 JB |
2717 | { |
2718 | struct dma_pl330_desc *first, *desc = NULL; | |
2719 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2720 | struct scatterlist *sg; |
1b9bb715 | 2721 | int i; |
b3040e40 JB |
2722 | dma_addr_t addr; |
2723 | ||
cd072515 | 2724 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2725 | return NULL; |
2726 | ||
1b9bb715 | 2727 | addr = pch->fifo_addr; |
b3040e40 JB |
2728 | |
2729 | first = NULL; | |
2730 | ||
2731 | for_each_sg(sgl, sg, sg_len, i) { | |
2732 | ||
2733 | desc = pl330_get_desc(pch); | |
2734 | if (!desc) { | |
f6f2421c | 2735 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 | 2736 | |
f6f2421c | 2737 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2738 | "%s:%d Unable to fetch desc\n", |
2739 | __func__, __LINE__); | |
f6f2421c | 2740 | __pl330_giveback_desc(pl330, first); |
b3040e40 JB |
2741 | |
2742 | return NULL; | |
2743 | } | |
2744 | ||
2745 | if (!first) | |
2746 | first = desc; | |
2747 | else | |
2748 | list_add_tail(&desc->node, &first->node); | |
2749 | ||
db8196df | 2750 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2751 | desc->rqcfg.src_inc = 1; |
2752 | desc->rqcfg.dst_inc = 0; | |
2753 | fill_px(&desc->px, | |
2754 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
2755 | } else { | |
2756 | desc->rqcfg.src_inc = 0; | |
2757 | desc->rqcfg.dst_inc = 1; | |
2758 | fill_px(&desc->px, | |
2759 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
2760 | } | |
2761 | ||
1b9bb715 | 2762 | desc->rqcfg.brst_size = pch->burst_sz; |
0a18f9b2 | 2763 | desc->rqcfg.brst_len = 1; |
9dc5a315 | 2764 | desc->rqtype = direction; |
aee4d1fa | 2765 | desc->bytes_requested = sg_dma_len(sg); |
b3040e40 JB |
2766 | } |
2767 | ||
2768 | /* Return the last desc in the chain */ | |
2769 | desc->txd.flags = flg; | |
2770 | return &desc->txd; | |
2771 | } | |
2772 | ||
2773 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2774 | { | |
2775 | if (pl330_update(data)) | |
2776 | return IRQ_HANDLED; | |
2777 | else | |
2778 | return IRQ_NONE; | |
2779 | } | |
2780 | ||
ca38ff13 LPC |
2781 | #define PL330_DMA_BUSWIDTHS \ |
2782 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2783 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2784 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2785 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2786 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2787 | ||
b816ccc5 KK |
2788 | /* |
2789 | * Runtime PM callbacks are provided by amba/bus.c driver. | |
2790 | * | |
2791 | * It is assumed here that IRQ safe runtime PM is chosen in probe and amba | |
2792 | * bus driver will only disable/enable the clock in runtime PM callbacks. | |
2793 | */ | |
2794 | static int __maybe_unused pl330_suspend(struct device *dev) | |
2795 | { | |
2796 | struct amba_device *pcdev = to_amba_device(dev); | |
2797 | ||
2798 | pm_runtime_disable(dev); | |
2799 | ||
2800 | if (!pm_runtime_status_suspended(dev)) { | |
2801 | /* amba did not disable the clock */ | |
2802 | amba_pclk_disable(pcdev); | |
2803 | } | |
2804 | amba_pclk_unprepare(pcdev); | |
2805 | ||
2806 | return 0; | |
2807 | } | |
2808 | ||
2809 | static int __maybe_unused pl330_resume(struct device *dev) | |
2810 | { | |
2811 | struct amba_device *pcdev = to_amba_device(dev); | |
2812 | int ret; | |
2813 | ||
2814 | ret = amba_pclk_prepare(pcdev); | |
2815 | if (ret) | |
2816 | return ret; | |
2817 | ||
2818 | if (!pm_runtime_status_suspended(dev)) | |
2819 | ret = amba_pclk_enable(pcdev); | |
2820 | ||
2821 | pm_runtime_enable(dev); | |
2822 | ||
2823 | return ret; | |
2824 | } | |
2825 | ||
2826 | static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); | |
2827 | ||
463a1f8b | 2828 | static int |
aa25afad | 2829 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
2830 | { |
2831 | struct dma_pl330_platdata *pdat; | |
f6f2421c LPC |
2832 | struct pl330_config *pcfg; |
2833 | struct pl330_dmac *pl330; | |
0b94c577 | 2834 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2835 | struct dma_device *pd; |
2836 | struct resource *res; | |
2837 | int i, ret, irq; | |
4e0e6109 | 2838 | int num_chan; |
271e1b86 | 2839 | struct device_node *np = adev->dev.of_node; |
b3040e40 | 2840 | |
d4adcc01 | 2841 | pdat = dev_get_platdata(&adev->dev); |
b3040e40 | 2842 | |
64113016 RK |
2843 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2844 | if (ret) | |
2845 | return ret; | |
2846 | ||
b3040e40 | 2847 | /* Allocate a new DMAC and its Channels */ |
f6f2421c | 2848 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
aef94fea | 2849 | if (!pl330) |
b3040e40 | 2850 | return -ENOMEM; |
b3040e40 | 2851 | |
cee42392 AJ |
2852 | pd = &pl330->ddma; |
2853 | pd->dev = &adev->dev; | |
2854 | ||
f6f2421c | 2855 | pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 | 2856 | |
271e1b86 AK |
2857 | /* get quirk */ |
2858 | for (i = 0; i < ARRAY_SIZE(of_quirks); i++) | |
2859 | if (of_property_read_bool(np, of_quirks[i].quirk)) | |
2860 | pl330->quirks |= of_quirks[i].id; | |
2861 | ||
b3040e40 | 2862 | res = &adev->res; |
f6f2421c LPC |
2863 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
2864 | if (IS_ERR(pl330->base)) | |
2865 | return PTR_ERR(pl330->base); | |
b3040e40 | 2866 | |
f6f2421c | 2867 | amba_set_drvdata(adev, pl330); |
a2f5203f | 2868 | |
02808b42 | 2869 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2870 | irq = adev->irq[i]; |
2871 | if (irq) { | |
2872 | ret = devm_request_irq(&adev->dev, irq, | |
2873 | pl330_irq_handler, 0, | |
f6f2421c | 2874 | dev_name(&adev->dev), pl330); |
e98b3caf MS |
2875 | if (ret) |
2876 | return ret; | |
2877 | } else { | |
2878 | break; | |
2879 | } | |
2880 | } | |
b3040e40 | 2881 | |
f6f2421c LPC |
2882 | pcfg = &pl330->pcfg; |
2883 | ||
2884 | pcfg->periph_id = adev->periphid; | |
2885 | ret = pl330_add(pl330); | |
b3040e40 | 2886 | if (ret) |
173e838c | 2887 | return ret; |
b3040e40 | 2888 | |
f6f2421c LPC |
2889 | INIT_LIST_HEAD(&pl330->desc_pool); |
2890 | spin_lock_init(&pl330->pool_lock); | |
b3040e40 JB |
2891 | |
2892 | /* Create a descriptor pool of default size */ | |
f6f2421c | 2893 | if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) |
b3040e40 JB |
2894 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
2895 | ||
b3040e40 JB |
2896 | INIT_LIST_HEAD(&pd->channels); |
2897 | ||
2898 | /* Initialize channel parameters */ | |
c8473828 | 2899 | if (pdat) |
f6f2421c | 2900 | num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); |
c8473828 | 2901 | else |
f6f2421c | 2902 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
c8473828 | 2903 | |
f6f2421c | 2904 | pl330->num_peripherals = num_chan; |
70cbb163 | 2905 | |
f6f2421c LPC |
2906 | pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
2907 | if (!pl330->peripherals) { | |
61c6e753 | 2908 | ret = -ENOMEM; |
e4d43c17 | 2909 | goto probe_err2; |
61c6e753 | 2910 | } |
b3040e40 | 2911 | |
4e0e6109 | 2912 | for (i = 0; i < num_chan; i++) { |
f6f2421c | 2913 | pch = &pl330->peripherals[i]; |
93ed5544 TA |
2914 | if (!adev->dev.of_node) |
2915 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
2916 | else | |
2917 | pch->chan.private = adev->dev.of_node; | |
b3040e40 | 2918 | |
04abf5da | 2919 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 2920 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 2921 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 2922 | spin_lock_init(&pch->lock); |
65ad6060 | 2923 | pch->thread = NULL; |
b3040e40 | 2924 | pch->chan.device = pd; |
f6f2421c | 2925 | pch->dmac = pl330; |
b3040e40 JB |
2926 | |
2927 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
2928 | list_add_tail(&pch->chan.device_node, &pd->channels); |
2929 | } | |
2930 | ||
93ed5544 | 2931 | if (pdat) { |
cd072515 | 2932 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 2933 | } else { |
cd072515 | 2934 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
f6f2421c | 2935 | if (pcfg->num_peri) { |
93ed5544 TA |
2936 | dma_cap_set(DMA_SLAVE, pd->cap_mask); |
2937 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
5557a419 | 2938 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
93ed5544 TA |
2939 | } |
2940 | } | |
b3040e40 JB |
2941 | |
2942 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
2943 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
2944 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 2945 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
2946 | pd->device_tx_status = pl330_tx_status; |
2947 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
740aa957 | 2948 | pd->device_config = pl330_config; |
88987d2c | 2949 | pd->device_pause = pl330_pause; |
740aa957 | 2950 | pd->device_terminate_all = pl330_terminate_all; |
b3040e40 | 2951 | pd->device_issue_pending = pl330_issue_pending; |
dcabe456 MR |
2952 | pd->src_addr_widths = PL330_DMA_BUSWIDTHS; |
2953 | pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; | |
2954 | pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
aee4d1fa | 2955 | pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; |
86a8ce7d SL |
2956 | pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ? |
2957 | 1 : PL330_MAX_BURST); | |
b3040e40 JB |
2958 | |
2959 | ret = dma_async_device_register(pd); | |
2960 | if (ret) { | |
2961 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
2962 | goto probe_err3; |
2963 | } | |
2964 | ||
2965 | if (adev->dev.of_node) { | |
2966 | ret = of_dma_controller_register(adev->dev.of_node, | |
f6f2421c | 2967 | of_dma_pl330_xlate, pl330); |
0b94c577 PV |
2968 | if (ret) { |
2969 | dev_err(&adev->dev, | |
2970 | "unable to register DMA to the generic DT DMA helpers\n"); | |
2971 | } | |
b3040e40 | 2972 | } |
b714b84e | 2973 | |
f6f2421c | 2974 | adev->dev.dma_parms = &pl330->dma_parms; |
b714b84e | 2975 | |
dbaf6d85 VK |
2976 | /* |
2977 | * This is the limit for transfers with a buswidth of 1, larger | |
2978 | * buswidths will have larger limits. | |
2979 | */ | |
2980 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
2981 | if (ret) | |
2982 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
2983 | ||
b3040e40 | 2984 | |
b3040e40 | 2985 | dev_info(&adev->dev, |
1f0a5cbf | 2986 | "Loaded driver for PL330 DMAC-%x\n", adev->periphid); |
b3040e40 JB |
2987 | dev_info(&adev->dev, |
2988 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
f6f2421c LPC |
2989 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
2990 | pcfg->num_peri, pcfg->num_events); | |
b3040e40 | 2991 | |
ae43b328 KK |
2992 | pm_runtime_irq_safe(&adev->dev); |
2993 | pm_runtime_use_autosuspend(&adev->dev); | |
2994 | pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); | |
2995 | pm_runtime_mark_last_busy(&adev->dev); | |
2996 | pm_runtime_put_autosuspend(&adev->dev); | |
2997 | ||
b3040e40 | 2998 | return 0; |
0b94c577 | 2999 | probe_err3: |
0b94c577 | 3000 | /* Idle the DMAC */ |
f6f2421c | 3001 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
0b94c577 PV |
3002 | chan.device_node) { |
3003 | ||
3004 | /* Remove the channel */ | |
3005 | list_del(&pch->chan.device_node); | |
3006 | ||
3007 | /* Flush the channel */ | |
0f5ebabd | 3008 | if (pch->thread) { |
740aa957 | 3009 | pl330_terminate_all(&pch->chan); |
0f5ebabd KK |
3010 | pl330_free_chan_resources(&pch->chan); |
3011 | } | |
0b94c577 | 3012 | } |
b3040e40 | 3013 | probe_err2: |
f6f2421c | 3014 | pl330_del(pl330); |
b3040e40 JB |
3015 | |
3016 | return ret; | |
3017 | } | |
3018 | ||
4bf27b8b | 3019 | static int pl330_remove(struct amba_device *adev) |
b3040e40 | 3020 | { |
f6f2421c | 3021 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
b3040e40 | 3022 | struct dma_pl330_chan *pch, *_p; |
46cf94d6 | 3023 | int i, irq; |
b3040e40 | 3024 | |
ae43b328 KK |
3025 | pm_runtime_get_noresume(pl330->ddma.dev); |
3026 | ||
0b94c577 PV |
3027 | if (adev->dev.of_node) |
3028 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 3029 | |
46cf94d6 VK |
3030 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
3031 | irq = adev->irq[i]; | |
3032 | devm_free_irq(&adev->dev, irq, pl330); | |
3033 | } | |
3034 | ||
f6f2421c | 3035 | dma_async_device_unregister(&pl330->ddma); |
b3040e40 JB |
3036 | |
3037 | /* Idle the DMAC */ | |
f6f2421c | 3038 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
b3040e40 JB |
3039 | chan.device_node) { |
3040 | ||
3041 | /* Remove the channel */ | |
3042 | list_del(&pch->chan.device_node); | |
3043 | ||
3044 | /* Flush the channel */ | |
6e4a2a83 | 3045 | if (pch->thread) { |
740aa957 | 3046 | pl330_terminate_all(&pch->chan); |
6e4a2a83 KK |
3047 | pl330_free_chan_resources(&pch->chan); |
3048 | } | |
b3040e40 JB |
3049 | } |
3050 | ||
f6f2421c | 3051 | pl330_del(pl330); |
b3040e40 | 3052 | |
b3040e40 JB |
3053 | return 0; |
3054 | } | |
3055 | ||
3056 | static struct amba_id pl330_ids[] = { | |
3057 | { | |
3058 | .id = 0x00041330, | |
3059 | .mask = 0x000fffff, | |
3060 | }, | |
3061 | { 0, 0 }, | |
3062 | }; | |
3063 | ||
e8fa516a DM |
3064 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
3065 | ||
b3040e40 JB |
3066 | static struct amba_driver pl330_driver = { |
3067 | .drv = { | |
3068 | .owner = THIS_MODULE, | |
3069 | .name = "dma-pl330", | |
b816ccc5 | 3070 | .pm = &pl330_pm, |
b3040e40 JB |
3071 | }, |
3072 | .id_table = pl330_ids, | |
3073 | .probe = pl330_probe, | |
3074 | .remove = pl330_remove, | |
3075 | }; | |
3076 | ||
9e5ed094 | 3077 | module_amba_driver(pl330_driver); |
b3040e40 | 3078 | |
046209f6 | 3079 | MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); |
b3040e40 JB |
3080 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); |
3081 | MODULE_LICENSE("GPL"); |