Commit | Line | Data |
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7bedaa55 RK |
1 | /* |
2 | * OMAP DMAengine support | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
fa3ad86a | 8 | #include <linux/delay.h> |
7bedaa55 RK |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/omap-dma.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/spinlock.h> | |
8d30662a JH |
20 | #include <linux/of_dma.h> |
21 | #include <linux/of_device.h> | |
7bedaa55 RK |
22 | |
23 | #include "virt-dma.h" | |
7d7e1eba | 24 | |
341ce712 PU |
25 | #define OMAP_SDMA_REQUESTS 127 |
26 | #define OMAP_SDMA_CHANNELS 32 | |
27 | ||
7bedaa55 RK |
28 | struct omap_dmadev { |
29 | struct dma_device ddev; | |
30 | spinlock_t lock; | |
596c471b RK |
31 | void __iomem *base; |
32 | const struct omap_dma_reg *reg_map; | |
1b416c4b | 33 | struct omap_system_dma_plat_info *plat; |
6ddeb6d8 | 34 | bool legacy; |
de506089 | 35 | unsigned dma_requests; |
6ddeb6d8 RK |
36 | spinlock_t irq_lock; |
37 | uint32_t irq_enable_mask; | |
341ce712 | 38 | struct omap_chan *lch_map[OMAP_SDMA_CHANNELS]; |
7bedaa55 RK |
39 | }; |
40 | ||
41 | struct omap_chan { | |
42 | struct virt_dma_chan vc; | |
596c471b RK |
43 | void __iomem *channel_base; |
44 | const struct omap_dma_reg *reg_map; | |
aa4c5b96 | 45 | uint32_t ccr; |
7bedaa55 RK |
46 | |
47 | struct dma_slave_config cfg; | |
48 | unsigned dma_sig; | |
3a774ea9 | 49 | bool cyclic; |
2dcdf570 | 50 | bool paused; |
7bedaa55 RK |
51 | |
52 | int dma_ch; | |
53 | struct omap_desc *desc; | |
54 | unsigned sgidx; | |
55 | }; | |
56 | ||
57 | struct omap_sg { | |
58 | dma_addr_t addr; | |
59 | uint32_t en; /* number of elements (24-bit) */ | |
60 | uint32_t fn; /* number of frames (16-bit) */ | |
61 | }; | |
62 | ||
63 | struct omap_desc { | |
64 | struct virt_dma_desc vd; | |
65 | enum dma_transfer_direction dir; | |
66 | dma_addr_t dev_addr; | |
67 | ||
7c836bc7 | 68 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
9043826d | 69 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
3ed4d18f | 70 | uint32_t ccr; /* CCR value */ |
965aeb4d | 71 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
fa3ad86a | 72 | uint16_t cicr; /* CICR value */ |
2f0d13bd | 73 | uint32_t csdp; /* CSDP value */ |
7bedaa55 RK |
74 | |
75 | unsigned sglen; | |
76 | struct omap_sg sg[0]; | |
77 | }; | |
78 | ||
9043826d RK |
79 | enum { |
80 | CCR_FS = BIT(5), | |
81 | CCR_READ_PRIORITY = BIT(6), | |
82 | CCR_ENABLE = BIT(7), | |
83 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ | |
84 | CCR_REPEAT = BIT(9), /* OMAP1 only */ | |
85 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ | |
86 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ | |
87 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ | |
88 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ | |
89 | CCR_SRC_AMODE_CONSTANT = 0 << 12, | |
90 | CCR_SRC_AMODE_POSTINC = 1 << 12, | |
91 | CCR_SRC_AMODE_SGLIDX = 2 << 12, | |
92 | CCR_SRC_AMODE_DBLIDX = 3 << 12, | |
93 | CCR_DST_AMODE_CONSTANT = 0 << 14, | |
94 | CCR_DST_AMODE_POSTINC = 1 << 14, | |
95 | CCR_DST_AMODE_SGLIDX = 2 << 14, | |
96 | CCR_DST_AMODE_DBLIDX = 3 << 14, | |
97 | CCR_CONSTANT_FILL = BIT(16), | |
98 | CCR_TRANSPARENT_COPY = BIT(17), | |
99 | CCR_BS = BIT(18), | |
100 | CCR_SUPERVISOR = BIT(22), | |
101 | CCR_PREFETCH = BIT(23), | |
102 | CCR_TRIGGER_SRC = BIT(24), | |
103 | CCR_BUFFERING_DISABLE = BIT(25), | |
104 | CCR_WRITE_PRIORITY = BIT(26), | |
105 | CCR_SYNC_ELEMENT = 0, | |
106 | CCR_SYNC_FRAME = CCR_FS, | |
107 | CCR_SYNC_BLOCK = CCR_BS, | |
108 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, | |
109 | ||
110 | CSDP_DATA_TYPE_8 = 0, | |
111 | CSDP_DATA_TYPE_16 = 1, | |
112 | CSDP_DATA_TYPE_32 = 2, | |
113 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ | |
114 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ | |
115 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ | |
116 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ | |
117 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ | |
118 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ | |
119 | CSDP_SRC_PACKED = BIT(6), | |
120 | CSDP_SRC_BURST_1 = 0 << 7, | |
121 | CSDP_SRC_BURST_16 = 1 << 7, | |
122 | CSDP_SRC_BURST_32 = 2 << 7, | |
123 | CSDP_SRC_BURST_64 = 3 << 7, | |
124 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ | |
125 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ | |
126 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ | |
127 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ | |
128 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ | |
129 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ | |
130 | CSDP_DST_PACKED = BIT(13), | |
131 | CSDP_DST_BURST_1 = 0 << 14, | |
132 | CSDP_DST_BURST_16 = 1 << 14, | |
133 | CSDP_DST_BURST_32 = 2 << 14, | |
134 | CSDP_DST_BURST_64 = 3 << 14, | |
135 | ||
136 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ | |
137 | CICR_DROP_IE = BIT(1), | |
138 | CICR_HALF_IE = BIT(2), | |
139 | CICR_FRAME_IE = BIT(3), | |
140 | CICR_LAST_IE = BIT(4), | |
141 | CICR_BLOCK_IE = BIT(5), | |
142 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ | |
143 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ | |
144 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ | |
145 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ | |
146 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ | |
147 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ | |
148 | ||
149 | CLNK_CTRL_ENABLE_LNK = BIT(15), | |
150 | }; | |
151 | ||
7bedaa55 | 152 | static const unsigned es_bytes[] = { |
9043826d RK |
153 | [CSDP_DATA_TYPE_8] = 1, |
154 | [CSDP_DATA_TYPE_16] = 2, | |
155 | [CSDP_DATA_TYPE_32] = 4, | |
7bedaa55 RK |
156 | }; |
157 | ||
8d30662a JH |
158 | static struct of_dma_filter_info omap_dma_info = { |
159 | .filter_fn = omap_dma_filter_fn, | |
160 | }; | |
161 | ||
7bedaa55 RK |
162 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
163 | { | |
164 | return container_of(d, struct omap_dmadev, ddev); | |
165 | } | |
166 | ||
167 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) | |
168 | { | |
169 | return container_of(c, struct omap_chan, vc.chan); | |
170 | } | |
171 | ||
172 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) | |
173 | { | |
174 | return container_of(t, struct omap_desc, vd.tx); | |
175 | } | |
176 | ||
177 | static void omap_dma_desc_free(struct virt_dma_desc *vd) | |
178 | { | |
179 | kfree(container_of(vd, struct omap_desc, vd)); | |
180 | } | |
181 | ||
596c471b RK |
182 | static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) |
183 | { | |
184 | switch (type) { | |
185 | case OMAP_DMA_REG_16BIT: | |
186 | writew_relaxed(val, addr); | |
187 | break; | |
188 | case OMAP_DMA_REG_2X16BIT: | |
189 | writew_relaxed(val, addr); | |
190 | writew_relaxed(val >> 16, addr + 2); | |
191 | break; | |
192 | case OMAP_DMA_REG_32BIT: | |
193 | writel_relaxed(val, addr); | |
194 | break; | |
195 | default: | |
196 | WARN_ON(1); | |
197 | } | |
198 | } | |
199 | ||
200 | static unsigned omap_dma_read(unsigned type, void __iomem *addr) | |
201 | { | |
202 | unsigned val; | |
203 | ||
204 | switch (type) { | |
205 | case OMAP_DMA_REG_16BIT: | |
206 | val = readw_relaxed(addr); | |
207 | break; | |
208 | case OMAP_DMA_REG_2X16BIT: | |
209 | val = readw_relaxed(addr); | |
210 | val |= readw_relaxed(addr + 2) << 16; | |
211 | break; | |
212 | case OMAP_DMA_REG_32BIT: | |
213 | val = readl_relaxed(addr); | |
214 | break; | |
215 | default: | |
216 | WARN_ON(1); | |
217 | val = 0; | |
218 | } | |
219 | ||
220 | return val; | |
221 | } | |
222 | ||
c5ed98b6 RK |
223 | static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) |
224 | { | |
596c471b RK |
225 | const struct omap_dma_reg *r = od->reg_map + reg; |
226 | ||
227 | WARN_ON(r->stride); | |
228 | ||
229 | omap_dma_write(val, r->type, od->base + r->offset); | |
c5ed98b6 RK |
230 | } |
231 | ||
232 | static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) | |
233 | { | |
596c471b RK |
234 | const struct omap_dma_reg *r = od->reg_map + reg; |
235 | ||
236 | WARN_ON(r->stride); | |
237 | ||
238 | return omap_dma_read(r->type, od->base + r->offset); | |
c5ed98b6 RK |
239 | } |
240 | ||
241 | static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) | |
242 | { | |
596c471b RK |
243 | const struct omap_dma_reg *r = c->reg_map + reg; |
244 | ||
245 | omap_dma_write(val, r->type, c->channel_base + r->offset); | |
c5ed98b6 RK |
246 | } |
247 | ||
248 | static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) | |
249 | { | |
596c471b RK |
250 | const struct omap_dma_reg *r = c->reg_map + reg; |
251 | ||
252 | return omap_dma_read(r->type, c->channel_base + r->offset); | |
c5ed98b6 RK |
253 | } |
254 | ||
470b23f7 RK |
255 | static void omap_dma_clear_csr(struct omap_chan *c) |
256 | { | |
257 | if (dma_omap1()) | |
c5ed98b6 | 258 | omap_dma_chan_read(c, CSR); |
470b23f7 | 259 | else |
c5ed98b6 | 260 | omap_dma_chan_write(c, CSR, ~0); |
470b23f7 RK |
261 | } |
262 | ||
6ddeb6d8 RK |
263 | static unsigned omap_dma_get_csr(struct omap_chan *c) |
264 | { | |
265 | unsigned val = omap_dma_chan_read(c, CSR); | |
266 | ||
267 | if (!dma_omap1()) | |
268 | omap_dma_chan_write(c, CSR, val); | |
269 | ||
270 | return val; | |
271 | } | |
272 | ||
596c471b RK |
273 | static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c, |
274 | unsigned lch) | |
275 | { | |
276 | c->channel_base = od->base + od->plat->channel_stride * lch; | |
6ddeb6d8 RK |
277 | |
278 | od->lch_map[lch] = c; | |
596c471b RK |
279 | } |
280 | ||
fa3ad86a RK |
281 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
282 | { | |
283 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
fa3ad86a RK |
284 | |
285 | if (__dma_omap15xx(od->plat->dma_attr)) | |
c5ed98b6 | 286 | omap_dma_chan_write(c, CPC, 0); |
fa3ad86a | 287 | else |
c5ed98b6 | 288 | omap_dma_chan_write(c, CDAC, 0); |
fa3ad86a | 289 | |
470b23f7 | 290 | omap_dma_clear_csr(c); |
fa3ad86a RK |
291 | |
292 | /* Enable interrupts */ | |
c5ed98b6 | 293 | omap_dma_chan_write(c, CICR, d->cicr); |
fa3ad86a | 294 | |
45da7b04 | 295 | /* Enable channel */ |
c5ed98b6 | 296 | omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); |
fa3ad86a RK |
297 | } |
298 | ||
299 | static void omap_dma_stop(struct omap_chan *c) | |
300 | { | |
301 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
302 | uint32_t val; | |
303 | ||
304 | /* disable irq */ | |
c5ed98b6 | 305 | omap_dma_chan_write(c, CICR, 0); |
fa3ad86a | 306 | |
470b23f7 | 307 | omap_dma_clear_csr(c); |
fa3ad86a | 308 | |
c5ed98b6 | 309 | val = omap_dma_chan_read(c, CCR); |
9043826d | 310 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
fa3ad86a RK |
311 | uint32_t sysconfig; |
312 | unsigned i; | |
313 | ||
c5ed98b6 | 314 | sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); |
fa3ad86a RK |
315 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
316 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
c5ed98b6 | 317 | omap_dma_glbl_write(od, OCP_SYSCONFIG, val); |
fa3ad86a | 318 | |
c5ed98b6 | 319 | val = omap_dma_chan_read(c, CCR); |
9043826d | 320 | val &= ~CCR_ENABLE; |
c5ed98b6 | 321 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
322 | |
323 | /* Wait for sDMA FIFO to drain */ | |
324 | for (i = 0; ; i++) { | |
c5ed98b6 | 325 | val = omap_dma_chan_read(c, CCR); |
9043826d | 326 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
fa3ad86a RK |
327 | break; |
328 | ||
329 | if (i > 100) | |
330 | break; | |
331 | ||
332 | udelay(5); | |
333 | } | |
334 | ||
9043826d | 335 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
fa3ad86a RK |
336 | dev_err(c->vc.chan.device->dev, |
337 | "DMA drain did not complete on lch %d\n", | |
338 | c->dma_ch); | |
339 | ||
c5ed98b6 | 340 | omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig); |
fa3ad86a | 341 | } else { |
9043826d | 342 | val &= ~CCR_ENABLE; |
c5ed98b6 | 343 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
344 | } |
345 | ||
346 | mb(); | |
347 | ||
348 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { | |
c5ed98b6 | 349 | val = omap_dma_chan_read(c, CLNK_CTRL); |
fa3ad86a RK |
350 | |
351 | if (dma_omap1()) | |
352 | val |= 1 << 14; /* set the STOP_LNK bit */ | |
353 | else | |
9043826d | 354 | val &= ~CLNK_CTRL_ENABLE_LNK; |
fa3ad86a | 355 | |
c5ed98b6 | 356 | omap_dma_chan_write(c, CLNK_CTRL, val); |
fa3ad86a RK |
357 | } |
358 | } | |
359 | ||
7bedaa55 RK |
360 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
361 | unsigned idx) | |
362 | { | |
363 | struct omap_sg *sg = d->sg + idx; | |
893e63e3 | 364 | unsigned cxsa, cxei, cxfi; |
913a2d0c | 365 | |
4ce98c0a | 366 | if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) { |
893e63e3 RK |
367 | cxsa = CDSA; |
368 | cxei = CDEI; | |
369 | cxfi = CDFI; | |
913a2d0c | 370 | } else { |
893e63e3 RK |
371 | cxsa = CSSA; |
372 | cxei = CSEI; | |
373 | cxfi = CSFI; | |
913a2d0c RK |
374 | } |
375 | ||
c5ed98b6 RK |
376 | omap_dma_chan_write(c, cxsa, sg->addr); |
377 | omap_dma_chan_write(c, cxei, 0); | |
378 | omap_dma_chan_write(c, cxfi, 0); | |
379 | omap_dma_chan_write(c, CEN, sg->en); | |
380 | omap_dma_chan_write(c, CFN, sg->fn); | |
913a2d0c | 381 | |
fa3ad86a | 382 | omap_dma_start(c, d); |
913a2d0c RK |
383 | } |
384 | ||
385 | static void omap_dma_start_desc(struct omap_chan *c) | |
386 | { | |
387 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
388 | struct omap_desc *d; | |
893e63e3 | 389 | unsigned cxsa, cxei, cxfi; |
b9e97822 | 390 | |
913a2d0c RK |
391 | if (!vd) { |
392 | c->desc = NULL; | |
393 | return; | |
394 | } | |
395 | ||
396 | list_del(&vd->node); | |
397 | ||
398 | c->desc = d = to_omap_dma_desc(&vd->tx); | |
399 | c->sgidx = 0; | |
400 | ||
59871902 RK |
401 | /* |
402 | * This provides the necessary barrier to ensure data held in | |
403 | * DMA coherent memory is visible to the DMA engine prior to | |
404 | * the transfer starting. | |
405 | */ | |
406 | mb(); | |
407 | ||
c5ed98b6 | 408 | omap_dma_chan_write(c, CCR, d->ccr); |
3ed4d18f | 409 | if (dma_omap1()) |
c5ed98b6 | 410 | omap_dma_chan_write(c, CCR2, d->ccr >> 16); |
b9e97822 | 411 | |
4ce98c0a | 412 | if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) { |
893e63e3 RK |
413 | cxsa = CSSA; |
414 | cxei = CSEI; | |
415 | cxfi = CSFI; | |
b9e97822 | 416 | } else { |
893e63e3 RK |
417 | cxsa = CDSA; |
418 | cxei = CDEI; | |
419 | cxfi = CDFI; | |
b9e97822 RK |
420 | } |
421 | ||
c5ed98b6 RK |
422 | omap_dma_chan_write(c, cxsa, d->dev_addr); |
423 | omap_dma_chan_write(c, cxei, 0); | |
424 | omap_dma_chan_write(c, cxfi, d->fi); | |
425 | omap_dma_chan_write(c, CSDP, d->csdp); | |
426 | omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl); | |
b9e97822 | 427 | |
7bedaa55 RK |
428 | omap_dma_start_sg(c, d, 0); |
429 | } | |
430 | ||
431 | static void omap_dma_callback(int ch, u16 status, void *data) | |
432 | { | |
433 | struct omap_chan *c = data; | |
434 | struct omap_desc *d; | |
435 | unsigned long flags; | |
436 | ||
437 | spin_lock_irqsave(&c->vc.lock, flags); | |
438 | d = c->desc; | |
439 | if (d) { | |
3a774ea9 RK |
440 | if (!c->cyclic) { |
441 | if (++c->sgidx < d->sglen) { | |
442 | omap_dma_start_sg(c, d, c->sgidx); | |
443 | } else { | |
444 | omap_dma_start_desc(c); | |
445 | vchan_cookie_complete(&d->vd); | |
446 | } | |
7bedaa55 | 447 | } else { |
3a774ea9 | 448 | vchan_cyclic_callback(&d->vd); |
7bedaa55 RK |
449 | } |
450 | } | |
451 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
452 | } | |
453 | ||
6ddeb6d8 RK |
454 | static irqreturn_t omap_dma_irq(int irq, void *devid) |
455 | { | |
456 | struct omap_dmadev *od = devid; | |
457 | unsigned status, channel; | |
458 | ||
459 | spin_lock(&od->irq_lock); | |
460 | ||
461 | status = omap_dma_glbl_read(od, IRQSTATUS_L1); | |
462 | status &= od->irq_enable_mask; | |
463 | if (status == 0) { | |
464 | spin_unlock(&od->irq_lock); | |
465 | return IRQ_NONE; | |
466 | } | |
467 | ||
468 | while ((channel = ffs(status)) != 0) { | |
469 | unsigned mask, csr; | |
470 | struct omap_chan *c; | |
471 | ||
472 | channel -= 1; | |
473 | mask = BIT(channel); | |
474 | status &= ~mask; | |
475 | ||
476 | c = od->lch_map[channel]; | |
477 | if (c == NULL) { | |
478 | /* This should never happen */ | |
479 | dev_err(od->ddev.dev, "invalid channel %u\n", channel); | |
480 | continue; | |
481 | } | |
482 | ||
483 | csr = omap_dma_get_csr(c); | |
484 | omap_dma_glbl_write(od, IRQSTATUS_L1, mask); | |
485 | ||
486 | omap_dma_callback(channel, csr, c); | |
487 | } | |
488 | ||
489 | spin_unlock(&od->irq_lock); | |
490 | ||
491 | return IRQ_HANDLED; | |
492 | } | |
493 | ||
7bedaa55 RK |
494 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
495 | { | |
596c471b | 496 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 | 497 | struct omap_chan *c = to_omap_dma_chan(chan); |
596c471b RK |
498 | int ret; |
499 | ||
6ddeb6d8 RK |
500 | if (od->legacy) { |
501 | ret = omap_request_dma(c->dma_sig, "DMA engine", | |
502 | omap_dma_callback, c, &c->dma_ch); | |
503 | } else { | |
504 | ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL, | |
505 | &c->dma_ch); | |
506 | } | |
7bedaa55 | 507 | |
6ddeb6d8 RK |
508 | dev_dbg(od->ddev.dev, "allocating channel %u for %u\n", |
509 | c->dma_ch, c->dma_sig); | |
7bedaa55 | 510 | |
6ddeb6d8 | 511 | if (ret >= 0) { |
596c471b RK |
512 | omap_dma_assign(od, c, c->dma_ch); |
513 | ||
6ddeb6d8 RK |
514 | if (!od->legacy) { |
515 | unsigned val; | |
516 | ||
517 | spin_lock_irq(&od->irq_lock); | |
518 | val = BIT(c->dma_ch); | |
519 | omap_dma_glbl_write(od, IRQSTATUS_L1, val); | |
520 | od->irq_enable_mask |= val; | |
521 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); | |
522 | ||
523 | val = omap_dma_glbl_read(od, IRQENABLE_L0); | |
524 | val &= ~BIT(c->dma_ch); | |
525 | omap_dma_glbl_write(od, IRQENABLE_L0, val); | |
526 | spin_unlock_irq(&od->irq_lock); | |
527 | } | |
528 | } | |
529 | ||
aa4c5b96 RK |
530 | if (dma_omap1()) { |
531 | if (__dma_omap16xx(od->plat->dma_attr)) { | |
532 | c->ccr = CCR_OMAP31_DISABLE; | |
533 | /* Duplicate what plat-omap/dma.c does */ | |
534 | c->ccr |= c->dma_ch + 1; | |
535 | } else { | |
536 | c->ccr = c->dma_sig & 0x1f; | |
537 | } | |
538 | } else { | |
539 | c->ccr = c->dma_sig & 0x1f; | |
540 | c->ccr |= (c->dma_sig & ~0x1f) << 14; | |
541 | } | |
542 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) | |
543 | c->ccr |= CCR_BUFFERING_DISABLE; | |
544 | ||
596c471b | 545 | return ret; |
7bedaa55 RK |
546 | } |
547 | ||
548 | static void omap_dma_free_chan_resources(struct dma_chan *chan) | |
549 | { | |
6ddeb6d8 | 550 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
551 | struct omap_chan *c = to_omap_dma_chan(chan); |
552 | ||
6ddeb6d8 RK |
553 | if (!od->legacy) { |
554 | spin_lock_irq(&od->irq_lock); | |
555 | od->irq_enable_mask &= ~BIT(c->dma_ch); | |
556 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); | |
557 | spin_unlock_irq(&od->irq_lock); | |
558 | } | |
559 | ||
596c471b | 560 | c->channel_base = NULL; |
6ddeb6d8 | 561 | od->lch_map[c->dma_ch] = NULL; |
7bedaa55 RK |
562 | vchan_free_chan_resources(&c->vc); |
563 | omap_free_dma(c->dma_ch); | |
564 | ||
6ddeb6d8 | 565 | dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig); |
eea531ea | 566 | c->dma_sig = 0; |
7bedaa55 RK |
567 | } |
568 | ||
3850e22f RK |
569 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
570 | { | |
571 | return sg->en * sg->fn; | |
572 | } | |
573 | ||
574 | static size_t omap_dma_desc_size(struct omap_desc *d) | |
575 | { | |
576 | unsigned i; | |
577 | size_t size; | |
578 | ||
579 | for (size = i = 0; i < d->sglen; i++) | |
580 | size += omap_dma_sg_size(&d->sg[i]); | |
581 | ||
582 | return size * es_bytes[d->es]; | |
583 | } | |
584 | ||
585 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) | |
586 | { | |
587 | unsigned i; | |
588 | size_t size, es_size = es_bytes[d->es]; | |
589 | ||
590 | for (size = i = 0; i < d->sglen; i++) { | |
591 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; | |
592 | ||
593 | if (size) | |
594 | size += this_size; | |
595 | else if (addr >= d->sg[i].addr && | |
596 | addr < d->sg[i].addr + this_size) | |
597 | size += d->sg[i].addr + this_size - addr; | |
598 | } | |
599 | return size; | |
600 | } | |
601 | ||
b07fd625 RK |
602 | /* |
603 | * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
604 | * read before the DMA controller finished disabling the channel. | |
605 | */ | |
606 | static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) | |
607 | { | |
608 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
609 | uint32_t val; | |
610 | ||
611 | val = omap_dma_chan_read(c, reg); | |
612 | if (val == 0 && od->plat->errata & DMA_ERRATA_3_3) | |
613 | val = omap_dma_chan_read(c, reg); | |
614 | ||
615 | return val; | |
616 | } | |
617 | ||
3997cab3 RK |
618 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
619 | { | |
620 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
b07fd625 | 621 | dma_addr_t addr, cdac; |
3997cab3 | 622 | |
b07fd625 | 623 | if (__dma_omap15xx(od->plat->dma_attr)) { |
c5ed98b6 | 624 | addr = omap_dma_chan_read(c, CPC); |
b07fd625 RK |
625 | } else { |
626 | addr = omap_dma_chan_read_3_3(c, CSAC); | |
627 | cdac = omap_dma_chan_read_3_3(c, CDAC); | |
3997cab3 | 628 | |
3997cab3 RK |
629 | /* |
630 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
631 | * not been started (no data has been transferred so far). | |
632 | * Return the programmed source start address in this case. | |
633 | */ | |
b07fd625 | 634 | if (cdac == 0) |
c5ed98b6 | 635 | addr = omap_dma_chan_read(c, CSSA); |
3997cab3 RK |
636 | } |
637 | ||
638 | if (dma_omap1()) | |
c5ed98b6 | 639 | addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000; |
3997cab3 RK |
640 | |
641 | return addr; | |
642 | } | |
643 | ||
644 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) | |
645 | { | |
646 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
647 | dma_addr_t addr; | |
648 | ||
b07fd625 | 649 | if (__dma_omap15xx(od->plat->dma_attr)) { |
c5ed98b6 | 650 | addr = omap_dma_chan_read(c, CPC); |
b07fd625 RK |
651 | } else { |
652 | addr = omap_dma_chan_read_3_3(c, CDAC); | |
3997cab3 | 653 | |
3997cab3 | 654 | /* |
b07fd625 RK |
655 | * CDAC == 0 indicates that the DMA transfer on the channel |
656 | * has not been started (no data has been transferred so | |
657 | * far). Return the programmed destination start address in | |
658 | * this case. | |
3997cab3 RK |
659 | */ |
660 | if (addr == 0) | |
c5ed98b6 | 661 | addr = omap_dma_chan_read(c, CDSA); |
3997cab3 RK |
662 | } |
663 | ||
664 | if (dma_omap1()) | |
c5ed98b6 | 665 | addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000; |
3997cab3 RK |
666 | |
667 | return addr; | |
668 | } | |
669 | ||
7bedaa55 RK |
670 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
671 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
672 | { | |
3850e22f RK |
673 | struct omap_chan *c = to_omap_dma_chan(chan); |
674 | struct virt_dma_desc *vd; | |
675 | enum dma_status ret; | |
1a7cf7b2 | 676 | uint32_t ccr; |
3850e22f RK |
677 | unsigned long flags; |
678 | ||
1a7cf7b2 PU |
679 | ccr = omap_dma_chan_read(c, CCR); |
680 | /* The channel is no longer active, handle the completion right away */ | |
681 | if (!(ccr & CCR_ENABLE)) | |
682 | omap_dma_callback(c->dma_ch, 0, c); | |
683 | ||
3850e22f | 684 | ret = dma_cookie_status(chan, cookie, txstate); |
7cce5083 | 685 | if (ret == DMA_COMPLETE || !txstate) |
3850e22f RK |
686 | return ret; |
687 | ||
688 | spin_lock_irqsave(&c->vc.lock, flags); | |
689 | vd = vchan_find_desc(&c->vc, cookie); | |
690 | if (vd) { | |
691 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); | |
692 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
693 | struct omap_desc *d = c->desc; | |
694 | dma_addr_t pos; | |
695 | ||
696 | if (d->dir == DMA_MEM_TO_DEV) | |
3997cab3 | 697 | pos = omap_dma_get_src_pos(c); |
adf850bc | 698 | else if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) |
3997cab3 | 699 | pos = omap_dma_get_dst_pos(c); |
3850e22f RK |
700 | else |
701 | pos = 0; | |
702 | ||
703 | txstate->residue = omap_dma_desc_size_pos(d, pos); | |
704 | } else { | |
705 | txstate->residue = 0; | |
706 | } | |
707 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
708 | ||
709 | return ret; | |
7bedaa55 RK |
710 | } |
711 | ||
712 | static void omap_dma_issue_pending(struct dma_chan *chan) | |
713 | { | |
714 | struct omap_chan *c = to_omap_dma_chan(chan); | |
715 | unsigned long flags; | |
716 | ||
717 | spin_lock_irqsave(&c->vc.lock, flags); | |
1c1d25f9 PU |
718 | if (vchan_issue_pending(&c->vc) && !c->desc) |
719 | omap_dma_start_desc(c); | |
7bedaa55 RK |
720 | spin_unlock_irqrestore(&c->vc.lock, flags); |
721 | } | |
722 | ||
723 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( | |
724 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, | |
725 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
726 | { | |
49ae0b29 | 727 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
728 | struct omap_chan *c = to_omap_dma_chan(chan); |
729 | enum dma_slave_buswidth dev_width; | |
730 | struct scatterlist *sgent; | |
731 | struct omap_desc *d; | |
732 | dma_addr_t dev_addr; | |
e8a5e79c | 733 | unsigned i, es, en, frame_bytes; |
7bedaa55 RK |
734 | u32 burst; |
735 | ||
736 | if (dir == DMA_DEV_TO_MEM) { | |
737 | dev_addr = c->cfg.src_addr; | |
738 | dev_width = c->cfg.src_addr_width; | |
739 | burst = c->cfg.src_maxburst; | |
7bedaa55 RK |
740 | } else if (dir == DMA_MEM_TO_DEV) { |
741 | dev_addr = c->cfg.dst_addr; | |
742 | dev_width = c->cfg.dst_addr_width; | |
743 | burst = c->cfg.dst_maxburst; | |
7bedaa55 RK |
744 | } else { |
745 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
746 | return NULL; | |
747 | } | |
748 | ||
749 | /* Bus width translates to the element size (ES) */ | |
750 | switch (dev_width) { | |
751 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 752 | es = CSDP_DATA_TYPE_8; |
7bedaa55 RK |
753 | break; |
754 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 755 | es = CSDP_DATA_TYPE_16; |
7bedaa55 RK |
756 | break; |
757 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 758 | es = CSDP_DATA_TYPE_32; |
7bedaa55 RK |
759 | break; |
760 | default: /* not reached */ | |
761 | return NULL; | |
762 | } | |
763 | ||
764 | /* Now allocate and setup the descriptor. */ | |
765 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); | |
766 | if (!d) | |
767 | return NULL; | |
768 | ||
769 | d->dir = dir; | |
770 | d->dev_addr = dev_addr; | |
771 | d->es = es; | |
3ed4d18f | 772 | |
aa4c5b96 | 773 | d->ccr = c->ccr | CCR_SYNC_FRAME; |
3ed4d18f | 774 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 775 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 776 | else |
9043826d | 777 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 778 | |
9043826d | 779 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
2f0d13bd | 780 | d->csdp = es; |
fa3ad86a | 781 | |
2f0d13bd | 782 | if (dma_omap1()) { |
9043826d | 783 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
784 | |
785 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 786 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
2f0d13bd | 787 | else |
9043826d | 788 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 789 | } else { |
3ed4d18f | 790 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 791 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 792 | |
9043826d | 793 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
2f0d13bd | 794 | } |
965aeb4d RK |
795 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
796 | d->clnk_ctrl = c->dma_ch; | |
7bedaa55 RK |
797 | |
798 | /* | |
799 | * Build our scatterlist entries: each contains the address, | |
800 | * the number of elements (EN) in each frame, and the number of | |
801 | * frames (FN). Number of bytes for this entry = ES * EN * FN. | |
802 | * | |
803 | * Burst size translates to number of elements with frame sync. | |
804 | * Note: DMA engine defines burst to be the number of dev-width | |
805 | * transfers. | |
806 | */ | |
807 | en = burst; | |
808 | frame_bytes = es_bytes[es] * en; | |
809 | for_each_sg(sgl, sgent, sglen, i) { | |
e8a5e79c PU |
810 | d->sg[i].addr = sg_dma_address(sgent); |
811 | d->sg[i].en = en; | |
812 | d->sg[i].fn = sg_dma_len(sgent) / frame_bytes; | |
7bedaa55 RK |
813 | } |
814 | ||
e8a5e79c | 815 | d->sglen = sglen; |
7bedaa55 RK |
816 | |
817 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
818 | } | |
819 | ||
3a774ea9 RK |
820 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
821 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
31c1e5a1 | 822 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags) |
3a774ea9 | 823 | { |
fa3ad86a | 824 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
3a774ea9 RK |
825 | struct omap_chan *c = to_omap_dma_chan(chan); |
826 | enum dma_slave_buswidth dev_width; | |
827 | struct omap_desc *d; | |
828 | dma_addr_t dev_addr; | |
3ed4d18f | 829 | unsigned es; |
3a774ea9 RK |
830 | u32 burst; |
831 | ||
832 | if (dir == DMA_DEV_TO_MEM) { | |
833 | dev_addr = c->cfg.src_addr; | |
834 | dev_width = c->cfg.src_addr_width; | |
835 | burst = c->cfg.src_maxburst; | |
3a774ea9 RK |
836 | } else if (dir == DMA_MEM_TO_DEV) { |
837 | dev_addr = c->cfg.dst_addr; | |
838 | dev_width = c->cfg.dst_addr_width; | |
839 | burst = c->cfg.dst_maxburst; | |
3a774ea9 RK |
840 | } else { |
841 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
842 | return NULL; | |
843 | } | |
844 | ||
845 | /* Bus width translates to the element size (ES) */ | |
846 | switch (dev_width) { | |
847 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 848 | es = CSDP_DATA_TYPE_8; |
3a774ea9 RK |
849 | break; |
850 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 851 | es = CSDP_DATA_TYPE_16; |
3a774ea9 RK |
852 | break; |
853 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 854 | es = CSDP_DATA_TYPE_32; |
3a774ea9 RK |
855 | break; |
856 | default: /* not reached */ | |
857 | return NULL; | |
858 | } | |
859 | ||
860 | /* Now allocate and setup the descriptor. */ | |
861 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
862 | if (!d) | |
863 | return NULL; | |
864 | ||
865 | d->dir = dir; | |
866 | d->dev_addr = dev_addr; | |
867 | d->fi = burst; | |
868 | d->es = es; | |
3a774ea9 RK |
869 | d->sg[0].addr = buf_addr; |
870 | d->sg[0].en = period_len / es_bytes[es]; | |
871 | d->sg[0].fn = buf_len / period_len; | |
872 | d->sglen = 1; | |
3ed4d18f | 873 | |
aa4c5b96 | 874 | d->ccr = c->ccr; |
3ed4d18f | 875 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 876 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 877 | else |
9043826d | 878 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 879 | |
9043826d | 880 | d->cicr = CICR_DROP_IE; |
fa3ad86a | 881 | if (flags & DMA_PREP_INTERRUPT) |
9043826d | 882 | d->cicr |= CICR_FRAME_IE; |
fa3ad86a | 883 | |
2f0d13bd RK |
884 | d->csdp = es; |
885 | ||
886 | if (dma_omap1()) { | |
9043826d | 887 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
888 | |
889 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 890 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
2f0d13bd | 891 | else |
9043826d | 892 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 893 | } else { |
3ed4d18f | 894 | if (burst) |
9043826d RK |
895 | d->ccr |= CCR_SYNC_PACKET; |
896 | else | |
897 | d->ccr |= CCR_SYNC_ELEMENT; | |
3ed4d18f | 898 | |
47fac241 | 899 | if (dir == DMA_DEV_TO_MEM) { |
9043826d | 900 | d->ccr |= CCR_TRIGGER_SRC; |
47fac241 MLC |
901 | d->csdp |= CSDP_DST_PACKED; |
902 | } else { | |
903 | d->csdp |= CSDP_SRC_PACKED; | |
904 | } | |
3ed4d18f | 905 | |
9043826d | 906 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
3a774ea9 | 907 | |
9043826d | 908 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
2f0d13bd RK |
909 | } |
910 | ||
965aeb4d RK |
911 | if (__dma_omap15xx(od->plat->dma_attr)) |
912 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; | |
913 | else | |
914 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; | |
915 | ||
3ed4d18f | 916 | c->cyclic = true; |
3a774ea9 | 917 | |
2dde5b90 | 918 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
3a774ea9 RK |
919 | } |
920 | ||
4ce98c0a PU |
921 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_memcpy( |
922 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
923 | size_t len, unsigned long tx_flags) | |
924 | { | |
925 | struct omap_chan *c = to_omap_dma_chan(chan); | |
926 | struct omap_desc *d; | |
927 | uint8_t data_type; | |
928 | ||
929 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
930 | if (!d) | |
931 | return NULL; | |
932 | ||
933 | data_type = __ffs((src | dest | len)); | |
934 | if (data_type > CSDP_DATA_TYPE_32) | |
935 | data_type = CSDP_DATA_TYPE_32; | |
936 | ||
937 | d->dir = DMA_MEM_TO_MEM; | |
938 | d->dev_addr = src; | |
939 | d->fi = 0; | |
940 | d->es = data_type; | |
941 | d->sg[0].en = len / BIT(data_type); | |
942 | d->sg[0].fn = 1; | |
943 | d->sg[0].addr = dest; | |
944 | d->sglen = 1; | |
945 | d->ccr = c->ccr; | |
946 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC; | |
947 | ||
948 | d->cicr = CICR_DROP_IE; | |
949 | if (tx_flags & DMA_PREP_INTERRUPT) | |
950 | d->cicr |= CICR_FRAME_IE; | |
951 | ||
952 | d->csdp = data_type; | |
953 | ||
954 | if (dma_omap1()) { | |
955 | d->cicr |= CICR_TOUT_IE; | |
956 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF; | |
957 | } else { | |
958 | d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED; | |
959 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; | |
960 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; | |
961 | } | |
962 | ||
963 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
964 | } | |
965 | ||
78ea4fe7 | 966 | static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) |
7bedaa55 | 967 | { |
78ea4fe7 MR |
968 | struct omap_chan *c = to_omap_dma_chan(chan); |
969 | ||
7bedaa55 RK |
970 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
971 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
972 | return -EINVAL; | |
973 | ||
974 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
78ea4fe7 | 979 | static int omap_dma_terminate_all(struct dma_chan *chan) |
7bedaa55 | 980 | { |
78ea4fe7 | 981 | struct omap_chan *c = to_omap_dma_chan(chan); |
7bedaa55 RK |
982 | unsigned long flags; |
983 | LIST_HEAD(head); | |
984 | ||
985 | spin_lock_irqsave(&c->vc.lock, flags); | |
986 | ||
7bedaa55 RK |
987 | /* |
988 | * Stop DMA activity: we assume the callback will not be called | |
fa3ad86a | 989 | * after omap_dma_stop() returns (even if it does, it will see |
7bedaa55 RK |
990 | * c->desc is NULL and exit.) |
991 | */ | |
992 | if (c->desc) { | |
02d88b73 | 993 | omap_dma_desc_free(&c->desc->vd); |
7bedaa55 | 994 | c->desc = NULL; |
2dcdf570 PU |
995 | /* Avoid stopping the dma twice */ |
996 | if (!c->paused) | |
fa3ad86a | 997 | omap_dma_stop(c); |
7bedaa55 RK |
998 | } |
999 | ||
3a774ea9 RK |
1000 | if (c->cyclic) { |
1001 | c->cyclic = false; | |
2dcdf570 | 1002 | c->paused = false; |
3a774ea9 RK |
1003 | } |
1004 | ||
7bedaa55 RK |
1005 | vchan_get_all_descriptors(&c->vc, &head); |
1006 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
1007 | vchan_dma_desc_free_list(&c->vc, &head); | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
9bef6d82 PU |
1012 | static void omap_dma_synchronize(struct dma_chan *chan) |
1013 | { | |
1014 | struct omap_chan *c = to_omap_dma_chan(chan); | |
1015 | ||
1016 | vchan_synchronize(&c->vc); | |
1017 | } | |
1018 | ||
78ea4fe7 | 1019 | static int omap_dma_pause(struct dma_chan *chan) |
7bedaa55 | 1020 | { |
78ea4fe7 MR |
1021 | struct omap_chan *c = to_omap_dma_chan(chan); |
1022 | ||
2dcdf570 PU |
1023 | /* Pause/Resume only allowed with cyclic mode */ |
1024 | if (!c->cyclic) | |
1025 | return -EINVAL; | |
1026 | ||
1027 | if (!c->paused) { | |
fa3ad86a | 1028 | omap_dma_stop(c); |
2dcdf570 PU |
1029 | c->paused = true; |
1030 | } | |
1031 | ||
1032 | return 0; | |
7bedaa55 RK |
1033 | } |
1034 | ||
78ea4fe7 | 1035 | static int omap_dma_resume(struct dma_chan *chan) |
7bedaa55 | 1036 | { |
78ea4fe7 MR |
1037 | struct omap_chan *c = to_omap_dma_chan(chan); |
1038 | ||
2dcdf570 PU |
1039 | /* Pause/Resume only allowed with cyclic mode */ |
1040 | if (!c->cyclic) | |
1041 | return -EINVAL; | |
1042 | ||
1043 | if (c->paused) { | |
b3d09da7 PU |
1044 | mb(); |
1045 | ||
bfb60745 PU |
1046 | /* Restore channel link register */ |
1047 | omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl); | |
1048 | ||
fa3ad86a | 1049 | omap_dma_start(c, c->desc); |
2dcdf570 PU |
1050 | c->paused = false; |
1051 | } | |
1052 | ||
1053 | return 0; | |
7bedaa55 RK |
1054 | } |
1055 | ||
eea531ea | 1056 | static int omap_dma_chan_init(struct omap_dmadev *od) |
7bedaa55 RK |
1057 | { |
1058 | struct omap_chan *c; | |
1059 | ||
1060 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
1061 | if (!c) | |
1062 | return -ENOMEM; | |
1063 | ||
596c471b | 1064 | c->reg_map = od->reg_map; |
7bedaa55 RK |
1065 | c->vc.desc_free = omap_dma_desc_free; |
1066 | vchan_init(&c->vc, &od->ddev); | |
7bedaa55 | 1067 | |
7bedaa55 RK |
1068 | return 0; |
1069 | } | |
1070 | ||
1071 | static void omap_dma_free(struct omap_dmadev *od) | |
1072 | { | |
7bedaa55 RK |
1073 | while (!list_empty(&od->ddev.channels)) { |
1074 | struct omap_chan *c = list_first_entry(&od->ddev.channels, | |
1075 | struct omap_chan, vc.chan.device_node); | |
1076 | ||
1077 | list_del(&c->vc.chan.device_node); | |
1078 | tasklet_kill(&c->vc.task); | |
1079 | kfree(c); | |
1080 | } | |
7bedaa55 RK |
1081 | } |
1082 | ||
80b0e0ab PU |
1083 | #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
1084 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
1085 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
1086 | ||
7bedaa55 RK |
1087 | static int omap_dma_probe(struct platform_device *pdev) |
1088 | { | |
1089 | struct omap_dmadev *od; | |
596c471b | 1090 | struct resource *res; |
6ddeb6d8 | 1091 | int rc, i, irq; |
7bedaa55 | 1092 | |
104fce73 | 1093 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
7bedaa55 RK |
1094 | if (!od) |
1095 | return -ENOMEM; | |
1096 | ||
596c471b RK |
1097 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1098 | od->base = devm_ioremap_resource(&pdev->dev, res); | |
1099 | if (IS_ERR(od->base)) | |
1100 | return PTR_ERR(od->base); | |
1101 | ||
1b416c4b RK |
1102 | od->plat = omap_get_plat_info(); |
1103 | if (!od->plat) | |
1104 | return -EPROBE_DEFER; | |
1105 | ||
596c471b RK |
1106 | od->reg_map = od->plat->reg_map; |
1107 | ||
7bedaa55 | 1108 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
3a774ea9 | 1109 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
4ce98c0a | 1110 | dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask); |
7bedaa55 RK |
1111 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
1112 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; | |
1113 | od->ddev.device_tx_status = omap_dma_tx_status; | |
1114 | od->ddev.device_issue_pending = omap_dma_issue_pending; | |
1115 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; | |
3a774ea9 | 1116 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
4ce98c0a | 1117 | od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy; |
6c04cd4f | 1118 | od->ddev.device_config = omap_dma_slave_config; |
78ea4fe7 MR |
1119 | od->ddev.device_pause = omap_dma_pause; |
1120 | od->ddev.device_resume = omap_dma_resume; | |
1121 | od->ddev.device_terminate_all = omap_dma_terminate_all; | |
9bef6d82 | 1122 | od->ddev.device_synchronize = omap_dma_synchronize; |
7d15b87d MR |
1123 | od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS; |
1124 | od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS; | |
1125 | od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1126 | od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
7bedaa55 RK |
1127 | od->ddev.dev = &pdev->dev; |
1128 | INIT_LIST_HEAD(&od->ddev.channels); | |
7bedaa55 | 1129 | spin_lock_init(&od->lock); |
6ddeb6d8 | 1130 | spin_lock_init(&od->irq_lock); |
7bedaa55 | 1131 | |
de506089 PU |
1132 | od->dma_requests = OMAP_SDMA_REQUESTS; |
1133 | if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node, | |
1134 | "dma-requests", | |
1135 | &od->dma_requests)) { | |
1136 | dev_info(&pdev->dev, | |
1137 | "Missing dma-requests property, using %u.\n", | |
1138 | OMAP_SDMA_REQUESTS); | |
1139 | } | |
1140 | ||
8a322226 | 1141 | for (i = 0; i < OMAP_SDMA_CHANNELS; i++) { |
eea531ea | 1142 | rc = omap_dma_chan_init(od); |
7bedaa55 RK |
1143 | if (rc) { |
1144 | omap_dma_free(od); | |
1145 | return rc; | |
1146 | } | |
1147 | } | |
1148 | ||
6ddeb6d8 RK |
1149 | irq = platform_get_irq(pdev, 1); |
1150 | if (irq <= 0) { | |
1151 | dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq); | |
1152 | od->legacy = true; | |
1153 | } else { | |
1154 | /* Disable all interrupts */ | |
1155 | od->irq_enable_mask = 0; | |
1156 | omap_dma_glbl_write(od, IRQENABLE_L1, 0); | |
1157 | ||
1158 | rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq, | |
1159 | IRQF_SHARED, "omap-dma-engine", od); | |
1160 | if (rc) | |
1161 | return rc; | |
1162 | } | |
1163 | ||
020c62ae PU |
1164 | od->ddev.filter.map = od->plat->slave_map; |
1165 | od->ddev.filter.mapcnt = od->plat->slavecnt; | |
1166 | od->ddev.filter.fn = omap_dma_filter_fn; | |
1167 | ||
7bedaa55 RK |
1168 | rc = dma_async_device_register(&od->ddev); |
1169 | if (rc) { | |
1170 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", | |
1171 | rc); | |
1172 | omap_dma_free(od); | |
8d30662a JH |
1173 | return rc; |
1174 | } | |
1175 | ||
1176 | platform_set_drvdata(pdev, od); | |
1177 | ||
1178 | if (pdev->dev.of_node) { | |
1179 | omap_dma_info.dma_cap = od->ddev.cap_mask; | |
1180 | ||
1181 | /* Device-tree DMA controller registration */ | |
1182 | rc = of_dma_controller_register(pdev->dev.of_node, | |
1183 | of_dma_simple_xlate, &omap_dma_info); | |
1184 | if (rc) { | |
1185 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); | |
1186 | dma_async_device_unregister(&od->ddev); | |
1187 | omap_dma_free(od); | |
1188 | } | |
7bedaa55 RK |
1189 | } |
1190 | ||
1191 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); | |
1192 | ||
1193 | return rc; | |
1194 | } | |
1195 | ||
1196 | static int omap_dma_remove(struct platform_device *pdev) | |
1197 | { | |
1198 | struct omap_dmadev *od = platform_get_drvdata(pdev); | |
1199 | ||
8d30662a JH |
1200 | if (pdev->dev.of_node) |
1201 | of_dma_controller_free(pdev->dev.of_node); | |
1202 | ||
7bedaa55 | 1203 | dma_async_device_unregister(&od->ddev); |
6ddeb6d8 RK |
1204 | |
1205 | if (!od->legacy) { | |
1206 | /* Disable all interrupts */ | |
1207 | omap_dma_glbl_write(od, IRQENABLE_L0, 0); | |
1208 | } | |
1209 | ||
7bedaa55 RK |
1210 | omap_dma_free(od); |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
8d30662a JH |
1215 | static const struct of_device_id omap_dma_match[] = { |
1216 | { .compatible = "ti,omap2420-sdma", }, | |
1217 | { .compatible = "ti,omap2430-sdma", }, | |
1218 | { .compatible = "ti,omap3430-sdma", }, | |
1219 | { .compatible = "ti,omap3630-sdma", }, | |
1220 | { .compatible = "ti,omap4430-sdma", }, | |
1221 | {}, | |
1222 | }; | |
1223 | MODULE_DEVICE_TABLE(of, omap_dma_match); | |
1224 | ||
7bedaa55 RK |
1225 | static struct platform_driver omap_dma_driver = { |
1226 | .probe = omap_dma_probe, | |
1227 | .remove = omap_dma_remove, | |
1228 | .driver = { | |
1229 | .name = "omap-dma-engine", | |
8d30662a | 1230 | .of_match_table = of_match_ptr(omap_dma_match), |
7bedaa55 RK |
1231 | }, |
1232 | }; | |
1233 | ||
1234 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) | |
1235 | { | |
1236 | if (chan->device->dev->driver == &omap_dma_driver.driver) { | |
eea531ea | 1237 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
1238 | struct omap_chan *c = to_omap_dma_chan(chan); |
1239 | unsigned req = *(unsigned *)param; | |
1240 | ||
eea531ea PU |
1241 | if (req <= od->dma_requests) { |
1242 | c->dma_sig = req; | |
1243 | return true; | |
1244 | } | |
7bedaa55 RK |
1245 | } |
1246 | return false; | |
1247 | } | |
1248 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); | |
1249 | ||
7bedaa55 RK |
1250 | static int omap_dma_init(void) |
1251 | { | |
be1f9481 | 1252 | return platform_driver_register(&omap_dma_driver); |
7bedaa55 RK |
1253 | } |
1254 | subsys_initcall(omap_dma_init); | |
1255 | ||
1256 | static void __exit omap_dma_exit(void) | |
1257 | { | |
7bedaa55 RK |
1258 | platform_driver_unregister(&omap_dma_driver); |
1259 | } | |
1260 | module_exit(omap_dma_exit); | |
1261 | ||
1262 | MODULE_AUTHOR("Russell King"); | |
1263 | MODULE_LICENSE("GPL"); |