[linux-2.6-block.git] / drivers / dma / mv_xor.h

/*
 * Copyright (C) 2007, 2008, Marvell International Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

#ifndef MV_XOR_H
#define MV_XOR_H

#include <linux/types.h>
#include <linux/io.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>

#define MV_XOR_POOL_SIZE		PAGE_SIZE
#define MV_XOR_SLOT_SIZE		64
#define MV_XOR_THRESHOLD		1
#define MV_XOR_MAX_CHANNELS             2

#define MV_XOR_MIN_BYTE_COUNT		SZ_128
#define MV_XOR_MAX_BYTE_COUNT		(SZ_16M - 1)

/* Values for the XOR_CONFIG register */
#define XOR_OPERATION_MODE_XOR		0
#define XOR_OPERATION_MODE_MEMCPY	2
#define XOR_DESCRIPTOR_SWAP		BIT(14)

#define XOR_DESC_DMA_OWNED		BIT(31)
#define XOR_DESC_EOD_INT_EN		BIT(31)

#define XOR_CURR_DESC(chan)	(chan->mmr_high_base + 0x10 + (chan->idx * 4))
#define XOR_NEXT_DESC(chan)	(chan->mmr_high_base + 0x00 + (chan->idx * 4))
#define XOR_BYTE_COUNT(chan)	(chan->mmr_high_base + 0x20 + (chan->idx * 4))
#define XOR_DEST_POINTER(chan)	(chan->mmr_high_base + 0xB0 + (chan->idx * 4))
#define XOR_BLOCK_SIZE(chan)	(chan->mmr_high_base + 0xC0 + (chan->idx * 4))
#define XOR_INIT_VALUE_LOW(chan)	(chan->mmr_high_base + 0xE0)
#define XOR_INIT_VALUE_HIGH(chan)	(chan->mmr_high_base + 0xE4)

#define XOR_CONFIG(chan)	(chan->mmr_base + 0x10 + (chan->idx * 4))
#define XOR_ACTIVATION(chan)	(chan->mmr_base + 0x20 + (chan->idx * 4))
#define XOR_INTR_CAUSE(chan)	(chan->mmr_base + 0x30)
#define XOR_INTR_MASK(chan)	(chan->mmr_base + 0x40)
#define XOR_ERROR_CAUSE(chan)	(chan->mmr_base + 0x50)
#define XOR_ERROR_ADDR(chan)	(chan->mmr_base + 0x60)

#define XOR_INT_END_OF_DESC	BIT(0)
#define XOR_INT_END_OF_CHAIN	BIT(1)
#define XOR_INT_STOPPED		BIT(2)
#define XOR_INT_PAUSED		BIT(3)
#define XOR_INT_ERR_DECODE	BIT(4)
#define XOR_INT_ERR_RDPROT	BIT(5)
#define XOR_INT_ERR_WRPROT	BIT(6)
#define XOR_INT_ERR_OWN		BIT(7)
#define XOR_INT_ERR_PAR		BIT(8)
#define XOR_INT_ERR_MBUS	BIT(9)

#define XOR_INTR_ERRORS		(XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \
				 XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN    | \
				 XOR_INT_ERR_PAR    | XOR_INT_ERR_MBUS)

#define XOR_INTR_MASK_VALUE	(XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \
				 XOR_INT_STOPPED     | XOR_INTR_ERRORS)

#define WINDOW_BASE(w)		(0x50 + ((w) << 2))
#define WINDOW_SIZE(w)		(0x70 + ((w) << 2))
#define WINDOW_REMAP_HIGH(w)	(0x90 + ((w) << 2))
#define WINDOW_BAR_ENABLE(chan)	(0x40 + ((chan) << 2))
#define WINDOW_OVERRIDE_CTRL(chan)	(0xA0 + ((chan) << 2))

struct mv_xor_device {
	void __iomem	     *xor_base;
	void __iomem	     *xor_high_base;
	struct clk	     *clk;
	struct mv_xor_chan   *channels[MV_XOR_MAX_CHANNELS];
};

/**
 * struct mv_xor_chan - internal representation of a XOR channel
 * @pending: allows batching of hardware operations
 * @lock: serializes enqueue/dequeue operations to the descriptors pool
 * @mmr_base: memory mapped register base
 * @idx: the index of the xor channel
 * @chain: device chain view of the descriptors
 * @completed_slots: slots completed by HW but still need to be acked
 * @device: parent device
 * @common: common dmaengine channel object members
 * @last_used: place holder for allocation to continue from where it left off
 * @all_slots: complete domain of slots usable by the channel
 * @slots_allocated: records the actual size of the descriptor slot pool
 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
 */
struct mv_xor_chan {
	int			pending;
	spinlock_t		lock; /* protects the descriptor slot pool */
	void __iomem		*mmr_base;
	void __iomem		*mmr_high_base;
	unsigned int		idx;
	int                     irq;
	enum dma_transaction_type	current_type;
	struct list_head	chain;
	struct list_head	completed_slots;
	dma_addr_t		dma_desc_pool;
	void			*dma_desc_pool_virt;
	size_t                  pool_size;
	struct dma_device	dmadev;
	struct dma_chan		dmachan;
	struct mv_xor_desc_slot	*last_used;
	struct list_head	all_slots;
	int			slots_allocated;
	struct tasklet_struct	irq_tasklet;
	char			dummy_src[MV_XOR_MIN_BYTE_COUNT];
	char			dummy_dst[MV_XOR_MIN_BYTE_COUNT];
	dma_addr_t		dummy_src_addr, dummy_dst_addr;
};

/**
 * struct mv_xor_desc_slot - software descriptor
 * @slot_node: node on the mv_xor_chan.all_slots list
 * @chain_node: node on the mv_xor_chan.chain list
 * @completed_node: node on the mv_xor_chan.completed_slots list
 * @hw_desc: virtual address of the hardware descriptor chain
 * @phys: hardware address of the hardware descriptor chain
 * @slot_used: slot in use or not
 * @idx: pool index
 * @tx_list: list of slots that make up a multi-descriptor transaction
 * @async_tx: support for the async_tx api
 */
struct mv_xor_desc_slot {
	struct list_head	slot_node;
	struct list_head	chain_node;
	struct list_head	completed_node;
	enum dma_transaction_type	type;
	void			*hw_desc;
	u16			slot_used;
	u16			idx;
	struct dma_async_tx_descriptor	async_tx;
};

/*
 * This structure describes XOR descriptor size 64bytes. The
 * mv_phy_src_idx() macro must be used when indexing the values of the
 * phy_src_addr[] array. This is due to the fact that the 'descriptor
 * swap' feature, used on big endian systems, swaps descriptors data
 * within blocks of 8 bytes. So two consecutive values of the
 * phy_src_addr[] array are actually swapped in big-endian, which
 * explains the different mv_phy_src_idx() implementation.
 */
#if defined(__LITTLE_ENDIAN)
struct mv_xor_desc {
	u32 status;		/* descriptor execution status */
	u32 crc32_result;	/* result of CRC-32 calculation */
	u32 desc_command;	/* type of operation to be carried out */
	u32 phy_next_desc;	/* next descriptor address pointer */
	u32 byte_count;		/* size of src/dst blocks in bytes */
	u32 phy_dest_addr;	/* destination block address */
	u32 phy_src_addr[8];	/* source block addresses */
	u32 reserved0;
	u32 reserved1;
};
#define mv_phy_src_idx(src_idx) (src_idx)
#else
struct mv_xor_desc {
	u32 crc32_result;	/* result of CRC-32 calculation */
	u32 status;		/* descriptor execution status */
	u32 phy_next_desc;	/* next descriptor address pointer */
	u32 desc_command;	/* type of operation to be carried out */
	u32 phy_dest_addr;	/* destination block address */
	u32 byte_count;		/* size of src/dst blocks in bytes */
	u32 phy_src_addr[8];	/* source block addresses */
	u32 reserved1;
	u32 reserved0;
};
#define mv_phy_src_idx(src_idx) (src_idx ^ 1)
#endif

#define to_mv_sw_desc(addr_hw_desc)		\
	container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)

#define mv_hw_desc_slot_idx(hw_desc, idx)	\
	((void *)(((unsigned long)hw_desc) + ((idx) << 5)))

#endif
Commit	Line	Data
ff7b0479 SB	1	/*
	2	* Copyright (C) 2007, 2008, Marvell International Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	11	* for more details.
ff7b0479 SB	12	*/
	13
	14	#ifndef MV_XOR_H
	15	#define MV_XOR_H
	16
	17	#include <linux/types.h>
	18	#include <linux/io.h>
	19	#include <linux/dmaengine.h>
	20	#include <linux/interrupt.h>
	21
b503fa01	22	#define MV_XOR_POOL_SIZE PAGE_SIZE
ff7b0479 SB	23	#define MV_XOR_SLOT_SIZE 64
ff7b0479 SB	24	#define MV_XOR_THRESHOLD 1
60d151f3	25	#define MV_XOR_MAX_CHANNELS 2
ff7b0479	26
22843545 LA	27	#define MV_XOR_MIN_BYTE_COUNT SZ_128
	28	#define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1)
	29
e03bc654	30	/* Values for the XOR_CONFIG register */
ff7b0479 SB	31	#define XOR_OPERATION_MODE_XOR 0
ff7b0479 SB	32	#define XOR_OPERATION_MODE_MEMCPY 2
e03bc654	33	#define XOR_DESCRIPTOR_SWAP BIT(14)
ff7b0479	34
0e7488ed EG	35	#define XOR_DESC_DMA_OWNED BIT(31)
	36	#define XOR_DESC_EOD_INT_EN BIT(31)
	37
82a1402e EG	38	#define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
	39	#define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
	40	#define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4))
	41	#define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
	42	#define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
	43	#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0)
	44	#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4)
ff7b0479 SB	45
	46	#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
	47	#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
	48	#define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
	49	#define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
	50	#define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
	51	#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
0e7488ed EG	52
	53	#define XOR_INT_END_OF_DESC BIT(0)
	54	#define XOR_INT_END_OF_CHAIN BIT(1)
	55	#define XOR_INT_STOPPED BIT(2)
	56	#define XOR_INT_PAUSED BIT(3)
	57	#define XOR_INT_ERR_DECODE BIT(4)
	58	#define XOR_INT_ERR_RDPROT BIT(5)
	59	#define XOR_INT_ERR_WRPROT BIT(6)
	60	#define XOR_INT_ERR_OWN BIT(7)
	61	#define XOR_INT_ERR_PAR BIT(8)
	62	#define XOR_INT_ERR_MBUS BIT(9)
	63
	64	#define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE \| XOR_INT_ERR_RDPROT \| \
	65	XOR_INT_ERR_WRPROT \| XOR_INT_ERR_OWN \| \
	66	XOR_INT_ERR_PAR \| XOR_INT_ERR_MBUS)
	67
ba87d137	68	#define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC \| XOR_INT_END_OF_CHAIN \| \
0e7488ed	69	XOR_INT_STOPPED \| XOR_INTR_ERRORS)
ff7b0479	70
82a1402e EG	71	#define WINDOW_BASE(w) (0x50 + ((w) << 2))
	72	#define WINDOW_SIZE(w) (0x70 + ((w) << 2))
	73	#define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2))
	74	#define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
	75	#define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
ff7b0479	76
297eedba	77	struct mv_xor_device {
60d151f3 TP	78	void __iomem *xor_base;
	79	void __iomem *xor_high_base;
	80	struct clk *clk;
1ef48a26	81	struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
ff7b0479 SB	82	};
	83
	84	/**
	85	* struct mv_xor_chan - internal representation of a XOR channel
	86	* @pending: allows batching of hardware operations
ff7b0479 SB	87	* @lock: serializes enqueue/dequeue operations to the descriptors pool
	88	* @mmr_base: memory mapped register base
	89	* @idx: the index of the xor channel
	90	* @chain: device chain view of the descriptors
	91	* @completed_slots: slots completed by HW but still need to be acked
	92	* @device: parent device
	93	* @common: common dmaengine channel object members
	94	* @last_used: place holder for allocation to continue from where it left off
	95	* @all_slots: complete domain of slots usable by the channel
	96	* @slots_allocated: records the actual size of the descriptor slot pool
	97	* @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
	98	*/
	99	struct mv_xor_chan {
	100	int pending;
ff7b0479 SB	101	spinlock_t lock; /* protects the descriptor slot pool */
ff7b0479 SB	102	void __iomem *mmr_base;
82a1402e	103	void __iomem *mmr_high_base;
ff7b0479	104	unsigned int idx;
88eb92cb	105	int irq;
ff7b0479 SB	106	enum dma_transaction_type current_type;
	107	struct list_head chain;
	108	struct list_head completed_slots;
1ef48a26 TP	109	dma_addr_t dma_desc_pool;
	110	void *dma_desc_pool_virt;
	111	size_t pool_size;
	112	struct dma_device dmadev;
98817b99	113	struct dma_chan dmachan;
ff7b0479 SB	114	struct mv_xor_desc_slot *last_used;
	115	struct list_head all_slots;
	116	int slots_allocated;
	117	struct tasklet_struct irq_tasklet;
22843545 LA	118	char dummy_src[MV_XOR_MIN_BYTE_COUNT];
	119	char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
	120	dma_addr_t dummy_src_addr, dummy_dst_addr;
ff7b0479 SB	121	};
	122
	123	/**
	124	* struct mv_xor_desc_slot - software descriptor
	125	* @slot_node: node on the mv_xor_chan.all_slots list
	126	* @chain_node: node on the mv_xor_chan.chain list
	127	* @completed_node: node on the mv_xor_chan.completed_slots list
	128	* @hw_desc: virtual address of the hardware descriptor chain
	129	* @phys: hardware address of the hardware descriptor chain
dfc97661	130	* @slot_used: slot in use or not
ff7b0479	131	* @idx: pool index
64203b67	132	* @tx_list: list of slots that make up a multi-descriptor transaction
ff7b0479	133	* @async_tx: support for the async_tx api
ff7b0479 SB	134	*/
	135	struct mv_xor_desc_slot {
	136	struct list_head slot_node;
	137	struct list_head chain_node;
	138	struct list_head completed_node;
	139	enum dma_transaction_type type;
	140	void *hw_desc;
dfc97661	141	u16 slot_used;
ff7b0479	142	u16 idx;
ff7b0479	143	struct dma_async_tx_descriptor async_tx;
ff7b0479 SB	144	};
ff7b0479 SB	145
e03bc654 TP	146	/*
	147	* This structure describes XOR descriptor size 64bytes. The
	148	* mv_phy_src_idx() macro must be used when indexing the values of the
	149	* phy_src_addr[] array. This is due to the fact that the 'descriptor
	150	* swap' feature, used on big endian systems, swaps descriptors data
	151	* within blocks of 8 bytes. So two consecutive values of the
	152	* phy_src_addr[] array are actually swapped in big-endian, which
	153	* explains the different mv_phy_src_idx() implementation.
	154	*/
	155	#if defined(__LITTLE_ENDIAN)
ff7b0479 SB	156	struct mv_xor_desc {
	157	u32 status; /* descriptor execution status */
	158	u32 crc32_result; /* result of CRC-32 calculation */
	159	u32 desc_command; /* type of operation to be carried out */
	160	u32 phy_next_desc; /* next descriptor address pointer */
	161	u32 byte_count; /* size of src/dst blocks in bytes */
	162	u32 phy_dest_addr; /* destination block address */
	163	u32 phy_src_addr[8]; /* source block addresses */
	164	u32 reserved0;
	165	u32 reserved1;
	166	};
e03bc654 TP	167	#define mv_phy_src_idx(src_idx) (src_idx)
	168	#else
	169	struct mv_xor_desc {
	170	u32 crc32_result; /* result of CRC-32 calculation */
	171	u32 status; /* descriptor execution status */
	172	u32 phy_next_desc; /* next descriptor address pointer */
	173	u32 desc_command; /* type of operation to be carried out */
	174	u32 phy_dest_addr; /* destination block address */
	175	u32 byte_count; /* size of src/dst blocks in bytes */
	176	u32 phy_src_addr[8]; /* source block addresses */
	177	u32 reserved1;
	178	u32 reserved0;
	179	};
	180	#define mv_phy_src_idx(src_idx) (src_idx ^ 1)
	181	#endif
ff7b0479 SB	182
	183	#define to_mv_sw_desc(addr_hw_desc) \
	184	container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
	185
	186	#define mv_hw_desc_slot_idx(hw_desc, idx) \
	187	((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
	188
ff7b0479	189	#endif