Commit | Line | Data |
---|---|---|
ff7b0479 SB |
1 | /* |
2 | * offload engine driver for the Marvell XOR engine | |
3 | * Copyright (C) 2007, 2008, Marvell International Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
ff7b0479 SB |
13 | */ |
14 | ||
15 | #include <linux/init.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
ff7b0479 SB |
17 | #include <linux/delay.h> |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
6f166312 | 21 | #include <linux/of_device.h> |
ff7b0479 SB |
22 | #include <linux/platform_device.h> |
23 | #include <linux/memory.h> | |
c510182b | 24 | #include <linux/clk.h> |
f7d12ef5 TP |
25 | #include <linux/of.h> |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/irqdomain.h> | |
77757291 | 28 | #include <linux/cpumask.h> |
c02cecb9 | 29 | #include <linux/platform_data/dma-mv_xor.h> |
d2ebfb33 RKAL |
30 | |
31 | #include "dmaengine.h" | |
ff7b0479 SB |
32 | #include "mv_xor.h" |
33 | ||
dd130c65 GC |
34 | enum mv_xor_type { |
35 | XOR_ORION, | |
36 | XOR_ARMADA_38X, | |
ac5f0f3f | 37 | XOR_ARMADA_37XX, |
dd130c65 GC |
38 | }; |
39 | ||
6f166312 LA |
40 | enum mv_xor_mode { |
41 | XOR_MODE_IN_REG, | |
42 | XOR_MODE_IN_DESC, | |
43 | }; | |
44 | ||
ff7b0479 SB |
45 | static void mv_xor_issue_pending(struct dma_chan *chan); |
46 | ||
47 | #define to_mv_xor_chan(chan) \ | |
98817b99 | 48 | container_of(chan, struct mv_xor_chan, dmachan) |
ff7b0479 SB |
49 | |
50 | #define to_mv_xor_slot(tx) \ | |
51 | container_of(tx, struct mv_xor_desc_slot, async_tx) | |
52 | ||
c98c1781 | 53 | #define mv_chan_to_devp(chan) \ |
1ef48a26 | 54 | ((chan)->dmadev.dev) |
c98c1781 | 55 | |
dfc97661 | 56 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
ba87d137 LA |
57 | dma_addr_t addr, u32 byte_count, |
58 | enum dma_ctrl_flags flags) | |
ff7b0479 SB |
59 | { |
60 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
61 | ||
0e7488ed | 62 | hw_desc->status = XOR_DESC_DMA_OWNED; |
ff7b0479 | 63 | hw_desc->phy_next_desc = 0; |
ba87d137 LA |
64 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
65 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? | |
66 | XOR_DESC_EOD_INT_EN : 0; | |
dfc97661 | 67 | hw_desc->phy_dest_addr = addr; |
ff7b0479 SB |
68 | hw_desc->byte_count = byte_count; |
69 | } | |
70 | ||
6f166312 LA |
71 | static void mv_desc_set_mode(struct mv_xor_desc_slot *desc) |
72 | { | |
73 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
74 | ||
75 | switch (desc->type) { | |
76 | case DMA_XOR: | |
77 | case DMA_INTERRUPT: | |
78 | hw_desc->desc_command |= XOR_DESC_OPERATION_XOR; | |
79 | break; | |
80 | case DMA_MEMCPY: | |
81 | hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY; | |
82 | break; | |
83 | default: | |
84 | BUG(); | |
85 | return; | |
86 | } | |
87 | } | |
88 | ||
ff7b0479 SB |
89 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
90 | u32 next_desc_addr) | |
91 | { | |
92 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
93 | BUG_ON(hw_desc->phy_next_desc); | |
94 | hw_desc->phy_next_desc = next_desc_addr; | |
95 | } | |
96 | ||
ff7b0479 SB |
97 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
98 | int index, dma_addr_t addr) | |
99 | { | |
100 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
e03bc654 | 101 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
ff7b0479 SB |
102 | if (desc->type == DMA_XOR) |
103 | hw_desc->desc_command |= (1 << index); | |
104 | } | |
105 | ||
106 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) | |
107 | { | |
5733c38a | 108 | return readl_relaxed(XOR_CURR_DESC(chan)); |
ff7b0479 SB |
109 | } |
110 | ||
111 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, | |
112 | u32 next_desc_addr) | |
113 | { | |
5733c38a | 114 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
ff7b0479 SB |
115 | } |
116 | ||
ff7b0479 SB |
117 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
118 | { | |
5733c38a | 119 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
ff7b0479 | 120 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
5733c38a | 121 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
ff7b0479 SB |
122 | } |
123 | ||
124 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |
125 | { | |
5733c38a | 126 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
127 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
128 | return intr_cause; | |
129 | } | |
130 | ||
0951e728 | 131 | static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan) |
ff7b0479 | 132 | { |
ba87d137 LA |
133 | u32 val; |
134 | ||
135 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; | |
136 | val = ~(val << (chan->idx * 16)); | |
c98c1781 | 137 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
5733c38a | 138 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
139 | } |
140 | ||
0951e728 | 141 | static void mv_chan_clear_err_status(struct mv_xor_chan *chan) |
ff7b0479 SB |
142 | { |
143 | u32 val = 0xFFFF0000 >> (chan->idx * 16); | |
5733c38a | 144 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
145 | } |
146 | ||
0951e728 | 147 | static void mv_chan_set_mode(struct mv_xor_chan *chan, |
81aafb3e | 148 | u32 op_mode) |
ff7b0479 | 149 | { |
5733c38a | 150 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
ff7b0479 | 151 | |
6f166312 LA |
152 | config &= ~0x7; |
153 | config |= op_mode; | |
154 | ||
e03bc654 TP |
155 | #if defined(__BIG_ENDIAN) |
156 | config |= XOR_DESCRIPTOR_SWAP; | |
157 | #else | |
158 | config &= ~XOR_DESCRIPTOR_SWAP; | |
159 | #endif | |
160 | ||
5733c38a | 161 | writel_relaxed(config, XOR_CONFIG(chan)); |
ff7b0479 SB |
162 | } |
163 | ||
164 | static void mv_chan_activate(struct mv_xor_chan *chan) | |
165 | { | |
c98c1781 | 166 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
5a9a55bf EG |
167 | |
168 | /* writel ensures all descriptors are flushed before activation */ | |
169 | writel(BIT(0), XOR_ACTIVATION(chan)); | |
ff7b0479 SB |
170 | } |
171 | ||
172 | static char mv_chan_is_busy(struct mv_xor_chan *chan) | |
173 | { | |
5733c38a | 174 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 SB |
175 | |
176 | state = (state >> 4) & 0x3; | |
177 | ||
178 | return (state == 1) ? 1 : 0; | |
179 | } | |
180 | ||
ff7b0479 | 181 | /* |
0951e728 MR |
182 | * mv_chan_start_new_chain - program the engine to operate on new |
183 | * chain headed by sw_desc | |
ff7b0479 SB |
184 | * Caller must hold &mv_chan->lock while calling this function |
185 | */ | |
0951e728 MR |
186 | static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan, |
187 | struct mv_xor_desc_slot *sw_desc) | |
ff7b0479 | 188 | { |
c98c1781 | 189 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
ff7b0479 | 190 | __func__, __LINE__, sw_desc); |
ff7b0479 | 191 | |
48a9db46 BZ |
192 | /* set the hardware chain */ |
193 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); | |
194 | ||
dfc97661 | 195 | mv_chan->pending++; |
98817b99 | 196 | mv_xor_issue_pending(&mv_chan->dmachan); |
ff7b0479 SB |
197 | } |
198 | ||
199 | static dma_cookie_t | |
0951e728 MR |
200 | mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
201 | struct mv_xor_chan *mv_chan, | |
202 | dma_cookie_t cookie) | |
ff7b0479 SB |
203 | { |
204 | BUG_ON(desc->async_tx.cookie < 0); | |
205 | ||
206 | if (desc->async_tx.cookie > 0) { | |
207 | cookie = desc->async_tx.cookie; | |
208 | ||
8058e258 | 209 | dma_descriptor_unmap(&desc->async_tx); |
ff7b0479 SB |
210 | /* call the callback (must not sleep or submit new |
211 | * operations to this channel) | |
212 | */ | |
ee7681a4 | 213 | dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL); |
ff7b0479 SB |
214 | } |
215 | ||
216 | /* run dependent operations */ | |
07f2211e | 217 | dma_run_dependencies(&desc->async_tx); |
ff7b0479 SB |
218 | |
219 | return cookie; | |
220 | } | |
221 | ||
222 | static int | |
0951e728 | 223 | mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
224 | { |
225 | struct mv_xor_desc_slot *iter, *_iter; | |
226 | ||
c98c1781 | 227 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
ff7b0479 | 228 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
fbea28a2 | 229 | node) { |
ff7b0479 | 230 | |
c5db858b | 231 | if (async_tx_test_ack(&iter->async_tx)) { |
fbea28a2 | 232 | list_move_tail(&iter->node, &mv_chan->free_slots); |
c5db858b SR |
233 | if (!list_empty(&iter->sg_tx_list)) { |
234 | list_splice_tail_init(&iter->sg_tx_list, | |
235 | &mv_chan->free_slots); | |
236 | } | |
237 | } | |
ff7b0479 SB |
238 | } |
239 | return 0; | |
240 | } | |
241 | ||
242 | static int | |
0951e728 MR |
243 | mv_desc_clean_slot(struct mv_xor_desc_slot *desc, |
244 | struct mv_xor_chan *mv_chan) | |
ff7b0479 | 245 | { |
c98c1781 | 246 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
ff7b0479 | 247 | __func__, __LINE__, desc, desc->async_tx.flags); |
fbea28a2 | 248 | |
ff7b0479 SB |
249 | /* the client is allowed to attach dependent operations |
250 | * until 'ack' is set | |
251 | */ | |
c5db858b | 252 | if (!async_tx_test_ack(&desc->async_tx)) { |
ff7b0479 | 253 | /* move this slot to the completed_slots */ |
fbea28a2 | 254 | list_move_tail(&desc->node, &mv_chan->completed_slots); |
c5db858b SR |
255 | if (!list_empty(&desc->sg_tx_list)) { |
256 | list_splice_tail_init(&desc->sg_tx_list, | |
257 | &mv_chan->completed_slots); | |
258 | } | |
259 | } else { | |
fbea28a2 | 260 | list_move_tail(&desc->node, &mv_chan->free_slots); |
c5db858b SR |
261 | if (!list_empty(&desc->sg_tx_list)) { |
262 | list_splice_tail_init(&desc->sg_tx_list, | |
263 | &mv_chan->free_slots); | |
264 | } | |
265 | } | |
ff7b0479 | 266 | |
ff7b0479 SB |
267 | return 0; |
268 | } | |
269 | ||
fbeec99a | 270 | /* This function must be called with the mv_xor_chan spinlock held */ |
0951e728 | 271 | static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
272 | { |
273 | struct mv_xor_desc_slot *iter, *_iter; | |
274 | dma_cookie_t cookie = 0; | |
275 | int busy = mv_chan_is_busy(mv_chan); | |
276 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
9136291f LA |
277 | int current_cleaned = 0; |
278 | struct mv_xor_desc *hw_desc; | |
ff7b0479 | 279 | |
c98c1781 TP |
280 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
281 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); | |
0951e728 | 282 | mv_chan_clean_completed_slots(mv_chan); |
ff7b0479 SB |
283 | |
284 | /* free completed slots from the chain starting with | |
285 | * the oldest descriptor | |
286 | */ | |
287 | ||
288 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
fbea28a2 | 289 | node) { |
ff7b0479 | 290 | |
9136291f LA |
291 | /* clean finished descriptors */ |
292 | hw_desc = iter->hw_desc; | |
293 | if (hw_desc->status & XOR_DESC_SUCCESS) { | |
0951e728 MR |
294 | cookie = mv_desc_run_tx_complete_actions(iter, mv_chan, |
295 | cookie); | |
ff7b0479 | 296 | |
9136291f | 297 | /* done processing desc, clean slot */ |
0951e728 | 298 | mv_desc_clean_slot(iter, mv_chan); |
9136291f LA |
299 | |
300 | /* break if we did cleaned the current */ | |
301 | if (iter->async_tx.phys == current_desc) { | |
302 | current_cleaned = 1; | |
303 | break; | |
304 | } | |
305 | } else { | |
306 | if (iter->async_tx.phys == current_desc) { | |
307 | current_cleaned = 0; | |
ff7b0479 | 308 | break; |
9136291f | 309 | } |
ff7b0479 | 310 | } |
ff7b0479 SB |
311 | } |
312 | ||
313 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { | |
9136291f LA |
314 | if (current_cleaned) { |
315 | /* | |
316 | * current descriptor cleaned and removed, run | |
317 | * from list head | |
318 | */ | |
319 | iter = list_entry(mv_chan->chain.next, | |
320 | struct mv_xor_desc_slot, | |
fbea28a2 | 321 | node); |
0951e728 | 322 | mv_chan_start_new_chain(mv_chan, iter); |
9136291f | 323 | } else { |
fbea28a2 | 324 | if (!list_is_last(&iter->node, &mv_chan->chain)) { |
9136291f LA |
325 | /* |
326 | * descriptors are still waiting after | |
327 | * current, trigger them | |
328 | */ | |
fbea28a2 | 329 | iter = list_entry(iter->node.next, |
9136291f | 330 | struct mv_xor_desc_slot, |
fbea28a2 | 331 | node); |
0951e728 | 332 | mv_chan_start_new_chain(mv_chan, iter); |
9136291f LA |
333 | } else { |
334 | /* | |
335 | * some descriptors are still waiting | |
336 | * to be cleaned | |
337 | */ | |
338 | tasklet_schedule(&mv_chan->irq_tasklet); | |
339 | } | |
340 | } | |
ff7b0479 SB |
341 | } |
342 | ||
343 | if (cookie > 0) | |
98817b99 | 344 | mv_chan->dmachan.completed_cookie = cookie; |
ff7b0479 SB |
345 | } |
346 | ||
ff7b0479 SB |
347 | static void mv_xor_tasklet(unsigned long data) |
348 | { | |
349 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; | |
e43147ac | 350 | |
cbc229a4 | 351 | spin_lock(&chan->lock); |
0951e728 | 352 | mv_chan_slot_cleanup(chan); |
cbc229a4 | 353 | spin_unlock(&chan->lock); |
ff7b0479 SB |
354 | } |
355 | ||
356 | static struct mv_xor_desc_slot * | |
0951e728 | 357 | mv_chan_alloc_slot(struct mv_xor_chan *mv_chan) |
ff7b0479 | 358 | { |
fbea28a2 | 359 | struct mv_xor_desc_slot *iter; |
ff7b0479 | 360 | |
fbea28a2 LA |
361 | spin_lock_bh(&mv_chan->lock); |
362 | ||
363 | if (!list_empty(&mv_chan->free_slots)) { | |
364 | iter = list_first_entry(&mv_chan->free_slots, | |
365 | struct mv_xor_desc_slot, | |
366 | node); | |
367 | ||
368 | list_move_tail(&iter->node, &mv_chan->allocated_slots); | |
369 | ||
370 | spin_unlock_bh(&mv_chan->lock); | |
ff7b0479 | 371 | |
dfc97661 LA |
372 | /* pre-ack descriptor */ |
373 | async_tx_ack(&iter->async_tx); | |
dfc97661 | 374 | iter->async_tx.cookie = -EBUSY; |
dfc97661 LA |
375 | |
376 | return iter; | |
377 | ||
ff7b0479 | 378 | } |
fbea28a2 LA |
379 | |
380 | spin_unlock_bh(&mv_chan->lock); | |
ff7b0479 SB |
381 | |
382 | /* try to free some slots if the allocation fails */ | |
383 | tasklet_schedule(&mv_chan->irq_tasklet); | |
384 | ||
385 | return NULL; | |
386 | } | |
387 | ||
ff7b0479 SB |
388 | /************************ DMA engine API functions ****************************/ |
389 | static dma_cookie_t | |
390 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) | |
391 | { | |
392 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); | |
393 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); | |
dfc97661 | 394 | struct mv_xor_desc_slot *old_chain_tail; |
ff7b0479 SB |
395 | dma_cookie_t cookie; |
396 | int new_hw_chain = 1; | |
397 | ||
c98c1781 | 398 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
399 | "%s sw_desc %p: async_tx %p\n", |
400 | __func__, sw_desc, &sw_desc->async_tx); | |
401 | ||
ff7b0479 | 402 | spin_lock_bh(&mv_chan->lock); |
884485e1 | 403 | cookie = dma_cookie_assign(tx); |
ff7b0479 SB |
404 | |
405 | if (list_empty(&mv_chan->chain)) | |
fbea28a2 | 406 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
ff7b0479 SB |
407 | else { |
408 | new_hw_chain = 0; | |
409 | ||
410 | old_chain_tail = list_entry(mv_chan->chain.prev, | |
411 | struct mv_xor_desc_slot, | |
fbea28a2 LA |
412 | node); |
413 | list_move_tail(&sw_desc->node, &mv_chan->chain); | |
ff7b0479 | 414 | |
31fd8f5b OJ |
415 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
416 | &old_chain_tail->async_tx.phys); | |
ff7b0479 SB |
417 | |
418 | /* fix up the hardware chain */ | |
dfc97661 | 419 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
ff7b0479 SB |
420 | |
421 | /* if the channel is not busy */ | |
422 | if (!mv_chan_is_busy(mv_chan)) { | |
423 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
424 | /* | |
425 | * and the curren desc is the end of the chain before | |
426 | * the append, then we need to start the channel | |
427 | */ | |
428 | if (current_desc == old_chain_tail->async_tx.phys) | |
429 | new_hw_chain = 1; | |
430 | } | |
431 | } | |
432 | ||
433 | if (new_hw_chain) | |
0951e728 | 434 | mv_chan_start_new_chain(mv_chan, sw_desc); |
ff7b0479 | 435 | |
ff7b0479 SB |
436 | spin_unlock_bh(&mv_chan->lock); |
437 | ||
438 | return cookie; | |
439 | } | |
440 | ||
441 | /* returns the number of allocated descriptors */ | |
aa1e6f1a | 442 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
ff7b0479 | 443 | { |
31fd8f5b OJ |
444 | void *virt_desc; |
445 | dma_addr_t dma_desc; | |
ff7b0479 SB |
446 | int idx; |
447 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
448 | struct mv_xor_desc_slot *slot = NULL; | |
b503fa01 | 449 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
ff7b0479 SB |
450 | |
451 | /* Allocate descriptor slots */ | |
452 | idx = mv_chan->slots_allocated; | |
453 | while (idx < num_descs_in_pool) { | |
454 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
455 | if (!slot) { | |
b8291dde EG |
456 | dev_info(mv_chan_to_devp(mv_chan), |
457 | "channel only initialized %d descriptor slots", | |
458 | idx); | |
ff7b0479 SB |
459 | break; |
460 | } | |
31fd8f5b OJ |
461 | virt_desc = mv_chan->dma_desc_pool_virt; |
462 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
463 | |
464 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
465 | slot->async_tx.tx_submit = mv_xor_tx_submit; | |
fbea28a2 | 466 | INIT_LIST_HEAD(&slot->node); |
c5db858b | 467 | INIT_LIST_HEAD(&slot->sg_tx_list); |
31fd8f5b OJ |
468 | dma_desc = mv_chan->dma_desc_pool; |
469 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
470 | slot->idx = idx++; |
471 | ||
472 | spin_lock_bh(&mv_chan->lock); | |
473 | mv_chan->slots_allocated = idx; | |
fbea28a2 | 474 | list_add_tail(&slot->node, &mv_chan->free_slots); |
ff7b0479 SB |
475 | spin_unlock_bh(&mv_chan->lock); |
476 | } | |
477 | ||
c98c1781 | 478 | dev_dbg(mv_chan_to_devp(mv_chan), |
fbea28a2 LA |
479 | "allocated %d descriptor slots\n", |
480 | mv_chan->slots_allocated); | |
ff7b0479 SB |
481 | |
482 | return mv_chan->slots_allocated ? : -ENOMEM; | |
483 | } | |
484 | ||
77ff7a70 SR |
485 | /* |
486 | * Check if source or destination is an PCIe/IO address (non-SDRAM) and add | |
487 | * a new MBus window if necessary. Use a cache for these check so that | |
488 | * the MMIO mapped registers don't have to be accessed for this check | |
489 | * to speed up this process. | |
490 | */ | |
491 | static int mv_xor_add_io_win(struct mv_xor_chan *mv_chan, u32 addr) | |
492 | { | |
493 | struct mv_xor_device *xordev = mv_chan->xordev; | |
494 | void __iomem *base = mv_chan->mmr_high_base; | |
495 | u32 win_enable; | |
496 | u32 size; | |
497 | u8 target, attr; | |
498 | int ret; | |
499 | int i; | |
500 | ||
501 | /* Nothing needs to get done for the Armada 3700 */ | |
502 | if (xordev->xor_type == XOR_ARMADA_37XX) | |
503 | return 0; | |
504 | ||
505 | /* | |
506 | * Loop over the cached windows to check, if the requested area | |
507 | * is already mapped. If this the case, nothing needs to be done | |
508 | * and we can return. | |
509 | */ | |
510 | for (i = 0; i < WINDOW_COUNT; i++) { | |
511 | if (addr >= xordev->win_start[i] && | |
512 | addr <= xordev->win_end[i]) { | |
513 | /* Window is already mapped */ | |
514 | return 0; | |
515 | } | |
516 | } | |
517 | ||
518 | /* | |
519 | * The window is not mapped, so we need to create the new mapping | |
520 | */ | |
521 | ||
522 | /* If no IO window is found that addr has to be located in SDRAM */ | |
523 | ret = mvebu_mbus_get_io_win_info(addr, &size, &target, &attr); | |
524 | if (ret < 0) | |
525 | return 0; | |
526 | ||
527 | /* | |
528 | * Mask the base addr 'addr' according to 'size' read back from the | |
529 | * MBus window. Otherwise we might end up with an address located | |
530 | * somewhere in the middle of this area here. | |
531 | */ | |
532 | size -= 1; | |
533 | addr &= ~size; | |
534 | ||
535 | /* | |
536 | * Reading one of both enabled register is enough, as they are always | |
537 | * programmed to the identical values | |
538 | */ | |
539 | win_enable = readl(base + WINDOW_BAR_ENABLE(0)); | |
540 | ||
541 | /* Set 'i' to the first free window to write the new values to */ | |
542 | i = ffs(~win_enable) - 1; | |
543 | if (i >= WINDOW_COUNT) | |
544 | return -ENOMEM; | |
545 | ||
546 | writel((addr & 0xffff0000) | (attr << 8) | target, | |
547 | base + WINDOW_BASE(i)); | |
548 | writel(size & 0xffff0000, base + WINDOW_SIZE(i)); | |
549 | ||
550 | /* Fill the caching variables for later use */ | |
551 | xordev->win_start[i] = addr; | |
552 | xordev->win_end[i] = addr + size; | |
553 | ||
554 | win_enable |= (1 << i); | |
555 | win_enable |= 3 << (16 + (2 * i)); | |
556 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
557 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
ff7b0479 SB |
562 | static struct dma_async_tx_descriptor * |
563 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
564 | unsigned int src_cnt, size_t len, unsigned long flags) | |
565 | { | |
566 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
dfc97661 | 567 | struct mv_xor_desc_slot *sw_desc; |
77ff7a70 | 568 | int ret; |
ff7b0479 SB |
569 | |
570 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
571 | return NULL; | |
572 | ||
7912d300 | 573 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 | 574 | |
c98c1781 | 575 | dev_dbg(mv_chan_to_devp(mv_chan), |
bc822e12 | 576 | "%s src_cnt: %d len: %zu dest %pad flags: %ld\n", |
31fd8f5b | 577 | __func__, src_cnt, len, &dest, flags); |
ff7b0479 | 578 | |
77ff7a70 SR |
579 | /* Check if a new window needs to get added for 'dest' */ |
580 | ret = mv_xor_add_io_win(mv_chan, dest); | |
581 | if (ret) | |
582 | return NULL; | |
583 | ||
0951e728 | 584 | sw_desc = mv_chan_alloc_slot(mv_chan); |
ff7b0479 SB |
585 | if (sw_desc) { |
586 | sw_desc->type = DMA_XOR; | |
587 | sw_desc->async_tx.flags = flags; | |
ba87d137 | 588 | mv_desc_init(sw_desc, dest, len, flags); |
6f166312 LA |
589 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
590 | mv_desc_set_mode(sw_desc); | |
77ff7a70 SR |
591 | while (src_cnt--) { |
592 | /* Check if a new window needs to get added for 'src' */ | |
593 | ret = mv_xor_add_io_win(mv_chan, src[src_cnt]); | |
594 | if (ret) | |
595 | return NULL; | |
dfc97661 | 596 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
77ff7a70 | 597 | } |
ff7b0479 | 598 | } |
fbea28a2 | 599 | |
c98c1781 | 600 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
601 | "%s sw_desc %p async_tx %p \n", |
602 | __func__, sw_desc, &sw_desc->async_tx); | |
603 | return sw_desc ? &sw_desc->async_tx : NULL; | |
604 | } | |
605 | ||
3e4f52e2 LA |
606 | static struct dma_async_tx_descriptor * |
607 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
608 | size_t len, unsigned long flags) | |
609 | { | |
610 | /* | |
611 | * A MEMCPY operation is identical to an XOR operation with only | |
612 | * a single source address. | |
613 | */ | |
614 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
615 | } | |
616 | ||
22843545 LA |
617 | static struct dma_async_tx_descriptor * |
618 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) | |
619 | { | |
620 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
621 | dma_addr_t src, dest; | |
622 | size_t len; | |
623 | ||
624 | src = mv_chan->dummy_src_addr; | |
625 | dest = mv_chan->dummy_dst_addr; | |
626 | len = MV_XOR_MIN_BYTE_COUNT; | |
627 | ||
628 | /* | |
629 | * We implement the DMA_INTERRUPT operation as a minimum sized | |
630 | * XOR operation with a single dummy source address. | |
631 | */ | |
632 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
633 | } | |
634 | ||
ff7b0479 SB |
635 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
636 | { | |
637 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
638 | struct mv_xor_desc_slot *iter, *_iter; | |
639 | int in_use_descs = 0; | |
640 | ||
ff7b0479 | 641 | spin_lock_bh(&mv_chan->lock); |
e43147ac | 642 | |
0951e728 | 643 | mv_chan_slot_cleanup(mv_chan); |
ff7b0479 | 644 | |
ff7b0479 | 645 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
fbea28a2 | 646 | node) { |
ff7b0479 | 647 | in_use_descs++; |
fbea28a2 | 648 | list_move_tail(&iter->node, &mv_chan->free_slots); |
ff7b0479 SB |
649 | } |
650 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, | |
fbea28a2 LA |
651 | node) { |
652 | in_use_descs++; | |
653 | list_move_tail(&iter->node, &mv_chan->free_slots); | |
654 | } | |
655 | list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots, | |
656 | node) { | |
ff7b0479 | 657 | in_use_descs++; |
fbea28a2 | 658 | list_move_tail(&iter->node, &mv_chan->free_slots); |
ff7b0479 SB |
659 | } |
660 | list_for_each_entry_safe_reverse( | |
fbea28a2 LA |
661 | iter, _iter, &mv_chan->free_slots, node) { |
662 | list_del(&iter->node); | |
ff7b0479 SB |
663 | kfree(iter); |
664 | mv_chan->slots_allocated--; | |
665 | } | |
ff7b0479 | 666 | |
c98c1781 | 667 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
ff7b0479 SB |
668 | __func__, mv_chan->slots_allocated); |
669 | spin_unlock_bh(&mv_chan->lock); | |
670 | ||
671 | if (in_use_descs) | |
c98c1781 | 672 | dev_err(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
673 | "freeing %d in use descriptors!\n", in_use_descs); |
674 | } | |
675 | ||
676 | /** | |
07934481 | 677 | * mv_xor_status - poll the status of an XOR transaction |
ff7b0479 SB |
678 | * @chan: XOR channel handle |
679 | * @cookie: XOR transaction identifier | |
07934481 | 680 | * @txstate: XOR transactions state holder (or NULL) |
ff7b0479 | 681 | */ |
07934481 | 682 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
ff7b0479 | 683 | dma_cookie_t cookie, |
07934481 | 684 | struct dma_tx_state *txstate) |
ff7b0479 SB |
685 | { |
686 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
ff7b0479 SB |
687 | enum dma_status ret; |
688 | ||
96a2af41 | 689 | ret = dma_cookie_status(chan, cookie, txstate); |
890766d2 | 690 | if (ret == DMA_COMPLETE) |
ff7b0479 | 691 | return ret; |
e43147ac EG |
692 | |
693 | spin_lock_bh(&mv_chan->lock); | |
0951e728 | 694 | mv_chan_slot_cleanup(mv_chan); |
e43147ac | 695 | spin_unlock_bh(&mv_chan->lock); |
ff7b0479 | 696 | |
96a2af41 | 697 | return dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
698 | } |
699 | ||
0951e728 | 700 | static void mv_chan_dump_regs(struct mv_xor_chan *chan) |
ff7b0479 SB |
701 | { |
702 | u32 val; | |
703 | ||
5733c38a | 704 | val = readl_relaxed(XOR_CONFIG(chan)); |
1ba151cd | 705 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
ff7b0479 | 706 | |
5733c38a | 707 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
1ba151cd | 708 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
ff7b0479 | 709 | |
5733c38a | 710 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
1ba151cd | 711 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
ff7b0479 | 712 | |
5733c38a | 713 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
1ba151cd | 714 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
ff7b0479 | 715 | |
5733c38a | 716 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
1ba151cd | 717 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
ff7b0479 | 718 | |
5733c38a | 719 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
1ba151cd | 720 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
ff7b0479 SB |
721 | } |
722 | ||
0951e728 MR |
723 | static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan, |
724 | u32 intr_cause) | |
ff7b0479 | 725 | { |
0e7488ed EG |
726 | if (intr_cause & XOR_INT_ERR_DECODE) { |
727 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); | |
728 | return; | |
ff7b0479 SB |
729 | } |
730 | ||
0e7488ed | 731 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
a3fc74bc | 732 | chan->idx, intr_cause); |
ff7b0479 | 733 | |
0951e728 | 734 | mv_chan_dump_regs(chan); |
0e7488ed | 735 | WARN_ON(1); |
ff7b0479 SB |
736 | } |
737 | ||
738 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |
739 | { | |
740 | struct mv_xor_chan *chan = data; | |
741 | u32 intr_cause = mv_chan_get_intr_cause(chan); | |
742 | ||
c98c1781 | 743 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
ff7b0479 | 744 | |
0e7488ed | 745 | if (intr_cause & XOR_INTR_ERRORS) |
0951e728 | 746 | mv_chan_err_interrupt_handler(chan, intr_cause); |
ff7b0479 SB |
747 | |
748 | tasklet_schedule(&chan->irq_tasklet); | |
749 | ||
0951e728 | 750 | mv_chan_clear_eoc_cause(chan); |
ff7b0479 SB |
751 | |
752 | return IRQ_HANDLED; | |
753 | } | |
754 | ||
755 | static void mv_xor_issue_pending(struct dma_chan *chan) | |
756 | { | |
757 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
758 | ||
759 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { | |
760 | mv_chan->pending = 0; | |
761 | mv_chan_activate(mv_chan); | |
762 | } | |
763 | } | |
764 | ||
765 | /* | |
766 | * Perform a transaction to verify the HW works. | |
767 | */ | |
ff7b0479 | 768 | |
0951e728 | 769 | static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 | 770 | { |
b8c01d25 | 771 | int i, ret; |
ff7b0479 SB |
772 | void *src, *dest; |
773 | dma_addr_t src_dma, dest_dma; | |
774 | struct dma_chan *dma_chan; | |
775 | dma_cookie_t cookie; | |
776 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 777 | struct dmaengine_unmap_data *unmap; |
ff7b0479 | 778 | int err = 0; |
ff7b0479 | 779 | |
6da2ec56 | 780 | src = kmalloc(PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
781 | if (!src) |
782 | return -ENOMEM; | |
783 | ||
6396bb22 | 784 | dest = kzalloc(PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
785 | if (!dest) { |
786 | kfree(src); | |
787 | return -ENOMEM; | |
788 | } | |
789 | ||
790 | /* Fill in src buffer */ | |
d16695a7 | 791 | for (i = 0; i < PAGE_SIZE; i++) |
ff7b0479 SB |
792 | ((u8 *) src)[i] = (u8)i; |
793 | ||
275cc0c8 | 794 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 795 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
796 | err = -ENODEV; |
797 | goto out; | |
798 | } | |
799 | ||
d16695a7 EG |
800 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
801 | if (!unmap) { | |
802 | err = -ENOMEM; | |
803 | goto free_resources; | |
804 | } | |
805 | ||
51564635 | 806 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), |
b70e52ca | 807 | offset_in_page(src), PAGE_SIZE, |
51564635 | 808 | DMA_TO_DEVICE); |
d16695a7 | 809 | unmap->addr[0] = src_dma; |
ff7b0479 | 810 | |
b8c01d25 EG |
811 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
812 | if (ret) { | |
813 | err = -ENOMEM; | |
814 | goto free_resources; | |
815 | } | |
816 | unmap->to_cnt = 1; | |
817 | ||
51564635 | 818 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), |
b70e52ca | 819 | offset_in_page(dest), PAGE_SIZE, |
51564635 | 820 | DMA_FROM_DEVICE); |
d16695a7 EG |
821 | unmap->addr[1] = dest_dma; |
822 | ||
b8c01d25 EG |
823 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
824 | if (ret) { | |
825 | err = -ENOMEM; | |
826 | goto free_resources; | |
827 | } | |
828 | unmap->from_cnt = 1; | |
d16695a7 | 829 | unmap->len = PAGE_SIZE; |
ff7b0479 SB |
830 | |
831 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | |
d16695a7 | 832 | PAGE_SIZE, 0); |
b8c01d25 EG |
833 | if (!tx) { |
834 | dev_err(dma_chan->device->dev, | |
835 | "Self-test cannot prepare operation, disabling\n"); | |
836 | err = -ENODEV; | |
837 | goto free_resources; | |
838 | } | |
839 | ||
ff7b0479 | 840 | cookie = mv_xor_tx_submit(tx); |
b8c01d25 EG |
841 | if (dma_submit_error(cookie)) { |
842 | dev_err(dma_chan->device->dev, | |
843 | "Self-test submit error, disabling\n"); | |
844 | err = -ENODEV; | |
845 | goto free_resources; | |
846 | } | |
847 | ||
ff7b0479 SB |
848 | mv_xor_issue_pending(dma_chan); |
849 | async_tx_ack(tx); | |
850 | msleep(1); | |
851 | ||
07934481 | 852 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 853 | DMA_COMPLETE) { |
a3fc74bc TP |
854 | dev_err(dma_chan->device->dev, |
855 | "Self-test copy timed out, disabling\n"); | |
ff7b0479 SB |
856 | err = -ENODEV; |
857 | goto free_resources; | |
858 | } | |
859 | ||
c35064c4 | 860 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
d16695a7 EG |
861 | PAGE_SIZE, DMA_FROM_DEVICE); |
862 | if (memcmp(src, dest, PAGE_SIZE)) { | |
a3fc74bc TP |
863 | dev_err(dma_chan->device->dev, |
864 | "Self-test copy failed compare, disabling\n"); | |
ff7b0479 SB |
865 | err = -ENODEV; |
866 | goto free_resources; | |
867 | } | |
868 | ||
869 | free_resources: | |
d16695a7 | 870 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
871 | mv_xor_free_chan_resources(dma_chan); |
872 | out: | |
873 | kfree(src); | |
874 | kfree(dest); | |
875 | return err; | |
876 | } | |
877 | ||
878 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 879 | static int |
0951e728 | 880 | mv_chan_xor_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 | 881 | { |
b8c01d25 | 882 | int i, src_idx, ret; |
ff7b0479 SB |
883 | struct page *dest; |
884 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; | |
885 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; | |
886 | dma_addr_t dest_dma; | |
887 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 888 | struct dmaengine_unmap_data *unmap; |
ff7b0479 SB |
889 | struct dma_chan *dma_chan; |
890 | dma_cookie_t cookie; | |
891 | u8 cmp_byte = 0; | |
892 | u32 cmp_word; | |
893 | int err = 0; | |
d16695a7 | 894 | int src_count = MV_XOR_NUM_SRC_TEST; |
ff7b0479 | 895 | |
d16695a7 | 896 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 | 897 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
a09b09ae RK |
898 | if (!xor_srcs[src_idx]) { |
899 | while (src_idx--) | |
ff7b0479 | 900 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
901 | return -ENOMEM; |
902 | } | |
ff7b0479 SB |
903 | } |
904 | ||
905 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
906 | if (!dest) { |
907 | while (src_idx--) | |
ff7b0479 | 908 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
909 | return -ENOMEM; |
910 | } | |
ff7b0479 SB |
911 | |
912 | /* Fill in src buffers */ | |
d16695a7 | 913 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 SB |
914 | u8 *ptr = page_address(xor_srcs[src_idx]); |
915 | for (i = 0; i < PAGE_SIZE; i++) | |
916 | ptr[i] = (1 << src_idx); | |
917 | } | |
918 | ||
d16695a7 | 919 | for (src_idx = 0; src_idx < src_count; src_idx++) |
ff7b0479 SB |
920 | cmp_byte ^= (u8) (1 << src_idx); |
921 | ||
922 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
923 | (cmp_byte << 8) | cmp_byte; | |
924 | ||
925 | memset(page_address(dest), 0, PAGE_SIZE); | |
926 | ||
275cc0c8 | 927 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 928 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
929 | err = -ENODEV; |
930 | goto out; | |
931 | } | |
932 | ||
d16695a7 EG |
933 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
934 | GFP_KERNEL); | |
935 | if (!unmap) { | |
936 | err = -ENOMEM; | |
937 | goto free_resources; | |
938 | } | |
939 | ||
ff7b0479 | 940 | /* test xor */ |
d16695a7 EG |
941 | for (i = 0; i < src_count; i++) { |
942 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
943 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
944 | dma_srcs[i] = unmap->addr[i]; | |
b8c01d25 EG |
945 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
946 | if (ret) { | |
947 | err = -ENOMEM; | |
948 | goto free_resources; | |
949 | } | |
d16695a7 EG |
950 | unmap->to_cnt++; |
951 | } | |
ff7b0479 | 952 | |
d16695a7 EG |
953 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
954 | DMA_FROM_DEVICE); | |
955 | dest_dma = unmap->addr[src_count]; | |
b8c01d25 EG |
956 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
957 | if (ret) { | |
958 | err = -ENOMEM; | |
959 | goto free_resources; | |
960 | } | |
d16695a7 EG |
961 | unmap->from_cnt = 1; |
962 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
963 | |
964 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
d16695a7 | 965 | src_count, PAGE_SIZE, 0); |
b8c01d25 EG |
966 | if (!tx) { |
967 | dev_err(dma_chan->device->dev, | |
968 | "Self-test cannot prepare operation, disabling\n"); | |
969 | err = -ENODEV; | |
970 | goto free_resources; | |
971 | } | |
ff7b0479 SB |
972 | |
973 | cookie = mv_xor_tx_submit(tx); | |
b8c01d25 EG |
974 | if (dma_submit_error(cookie)) { |
975 | dev_err(dma_chan->device->dev, | |
976 | "Self-test submit error, disabling\n"); | |
977 | err = -ENODEV; | |
978 | goto free_resources; | |
979 | } | |
980 | ||
ff7b0479 SB |
981 | mv_xor_issue_pending(dma_chan); |
982 | async_tx_ack(tx); | |
983 | msleep(8); | |
984 | ||
07934481 | 985 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 986 | DMA_COMPLETE) { |
a3fc74bc TP |
987 | dev_err(dma_chan->device->dev, |
988 | "Self-test xor timed out, disabling\n"); | |
ff7b0479 SB |
989 | err = -ENODEV; |
990 | goto free_resources; | |
991 | } | |
992 | ||
c35064c4 | 993 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
994 | PAGE_SIZE, DMA_FROM_DEVICE); |
995 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
996 | u32 *ptr = page_address(dest); | |
997 | if (ptr[i] != cmp_word) { | |
a3fc74bc | 998 | dev_err(dma_chan->device->dev, |
1ba151cd JP |
999 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
1000 | i, ptr[i], cmp_word); | |
ff7b0479 SB |
1001 | err = -ENODEV; |
1002 | goto free_resources; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | free_resources: | |
d16695a7 | 1007 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
1008 | mv_xor_free_chan_resources(dma_chan); |
1009 | out: | |
d16695a7 | 1010 | src_idx = src_count; |
ff7b0479 SB |
1011 | while (src_idx--) |
1012 | __free_page(xor_srcs[src_idx]); | |
1013 | __free_page(dest); | |
1014 | return err; | |
1015 | } | |
1016 | ||
1ef48a26 | 1017 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
ff7b0479 | 1018 | { |
ff7b0479 | 1019 | struct dma_chan *chan, *_chan; |
1ef48a26 | 1020 | struct device *dev = mv_chan->dmadev.dev; |
ff7b0479 | 1021 | |
1ef48a26 | 1022 | dma_async_device_unregister(&mv_chan->dmadev); |
ff7b0479 | 1023 | |
b503fa01 | 1024 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1025 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
22843545 LA |
1026 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
1027 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); | |
1028 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, | |
1029 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); | |
ff7b0479 | 1030 | |
1ef48a26 | 1031 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
a6b4a9d2 | 1032 | device_node) { |
ff7b0479 SB |
1033 | list_del(&chan->device_node); |
1034 | } | |
1035 | ||
88eb92cb TP |
1036 | free_irq(mv_chan->irq, mv_chan); |
1037 | ||
ff7b0479 SB |
1038 | return 0; |
1039 | } | |
1040 | ||
1ef48a26 | 1041 | static struct mv_xor_chan * |
297eedba | 1042 | mv_xor_channel_add(struct mv_xor_device *xordev, |
a6b4a9d2 | 1043 | struct platform_device *pdev, |
dd130c65 | 1044 | int idx, dma_cap_mask_t cap_mask, int irq) |
ff7b0479 SB |
1045 | { |
1046 | int ret = 0; | |
ff7b0479 SB |
1047 | struct mv_xor_chan *mv_chan; |
1048 | struct dma_device *dma_dev; | |
ff7b0479 | 1049 | |
1ef48a26 | 1050 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
a577659f SK |
1051 | if (!mv_chan) |
1052 | return ERR_PTR(-ENOMEM); | |
ff7b0479 | 1053 | |
9aedbdba | 1054 | mv_chan->idx = idx; |
88eb92cb | 1055 | mv_chan->irq = irq; |
dd130c65 GC |
1056 | if (xordev->xor_type == XOR_ORION) |
1057 | mv_chan->op_in_desc = XOR_MODE_IN_REG; | |
1058 | else | |
1059 | mv_chan->op_in_desc = XOR_MODE_IN_DESC; | |
ff7b0479 | 1060 | |
1ef48a26 | 1061 | dma_dev = &mv_chan->dmadev; |
77ff7a70 | 1062 | mv_chan->xordev = xordev; |
ff7b0479 | 1063 | |
22843545 LA |
1064 | /* |
1065 | * These source and destination dummy buffers are used to implement | |
1066 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. | |
1067 | * Hence, we only need to map the buffers at initialization-time. | |
1068 | */ | |
1069 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, | |
1070 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); | |
1071 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, | |
1072 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); | |
1073 | ||
ff7b0479 SB |
1074 | /* allocate coherent memory for hardware descriptors |
1075 | * note: writecombine gives slightly better performance, but | |
1076 | * requires that we explicitly flush the writes | |
1077 | */ | |
1ef48a26 | 1078 | mv_chan->dma_desc_pool_virt = |
f6e45661 LR |
1079 | dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool, |
1080 | GFP_KERNEL); | |
1ef48a26 | 1081 | if (!mv_chan->dma_desc_pool_virt) |
a6b4a9d2 | 1082 | return ERR_PTR(-ENOMEM); |
ff7b0479 SB |
1083 | |
1084 | /* discover transaction capabilites from the platform data */ | |
a6b4a9d2 | 1085 | dma_dev->cap_mask = cap_mask; |
ff7b0479 SB |
1086 | |
1087 | INIT_LIST_HEAD(&dma_dev->channels); | |
1088 | ||
1089 | /* set base routines */ | |
1090 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; | |
1091 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; | |
07934481 | 1092 | dma_dev->device_tx_status = mv_xor_status; |
ff7b0479 SB |
1093 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
1094 | dma_dev->dev = &pdev->dev; | |
1095 | ||
1096 | /* set prep routines based on capability */ | |
22843545 LA |
1097 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
1098 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; | |
ff7b0479 SB |
1099 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
1100 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; | |
ff7b0479 | 1101 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
c019894e | 1102 | dma_dev->max_xor = 8; |
ff7b0479 SB |
1103 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
1104 | } | |
1105 | ||
297eedba | 1106 | mv_chan->mmr_base = xordev->xor_base; |
82a1402e | 1107 | mv_chan->mmr_high_base = xordev->xor_high_base; |
ff7b0479 SB |
1108 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
1109 | mv_chan); | |
1110 | ||
1111 | /* clear errors before enabling interrupts */ | |
0951e728 | 1112 | mv_chan_clear_err_status(mv_chan); |
ff7b0479 | 1113 | |
2d0a0745 TP |
1114 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
1115 | 0, dev_name(&pdev->dev), mv_chan); | |
ff7b0479 SB |
1116 | if (ret) |
1117 | goto err_free_dma; | |
1118 | ||
1119 | mv_chan_unmask_interrupts(mv_chan); | |
1120 | ||
6f166312 | 1121 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
81aafb3e | 1122 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC); |
6f166312 | 1123 | else |
81aafb3e | 1124 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR); |
ff7b0479 SB |
1125 | |
1126 | spin_lock_init(&mv_chan->lock); | |
1127 | INIT_LIST_HEAD(&mv_chan->chain); | |
1128 | INIT_LIST_HEAD(&mv_chan->completed_slots); | |
fbea28a2 LA |
1129 | INIT_LIST_HEAD(&mv_chan->free_slots); |
1130 | INIT_LIST_HEAD(&mv_chan->allocated_slots); | |
98817b99 TP |
1131 | mv_chan->dmachan.device = dma_dev; |
1132 | dma_cookie_init(&mv_chan->dmachan); | |
ff7b0479 | 1133 | |
98817b99 | 1134 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
ff7b0479 SB |
1135 | |
1136 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
0951e728 | 1137 | ret = mv_chan_memcpy_self_test(mv_chan); |
ff7b0479 SB |
1138 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
1139 | if (ret) | |
2d0a0745 | 1140 | goto err_free_irq; |
ff7b0479 SB |
1141 | } |
1142 | ||
1143 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
0951e728 | 1144 | ret = mv_chan_xor_self_test(mv_chan); |
ff7b0479 SB |
1145 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1146 | if (ret) | |
2d0a0745 | 1147 | goto err_free_irq; |
ff7b0479 SB |
1148 | } |
1149 | ||
c678fa66 | 1150 | dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n", |
6f166312 | 1151 | mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode", |
1ba151cd | 1152 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
1ba151cd JP |
1153 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1154 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
ff7b0479 SB |
1155 | |
1156 | dma_async_device_register(dma_dev); | |
1ef48a26 | 1157 | return mv_chan; |
ff7b0479 | 1158 | |
2d0a0745 TP |
1159 | err_free_irq: |
1160 | free_irq(mv_chan->irq, mv_chan); | |
a4a1e53d | 1161 | err_free_dma: |
b503fa01 | 1162 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1163 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
a6b4a9d2 | 1164 | return ERR_PTR(ret); |
ff7b0479 SB |
1165 | } |
1166 | ||
1167 | static void | |
297eedba | 1168 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
63a9332b | 1169 | const struct mbus_dram_target_info *dram) |
ff7b0479 | 1170 | { |
82a1402e | 1171 | void __iomem *base = xordev->xor_high_base; |
ff7b0479 SB |
1172 | u32 win_enable = 0; |
1173 | int i; | |
1174 | ||
1175 | for (i = 0; i < 8; i++) { | |
1176 | writel(0, base + WINDOW_BASE(i)); | |
1177 | writel(0, base + WINDOW_SIZE(i)); | |
1178 | if (i < 4) | |
1179 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1180 | } | |
1181 | ||
1182 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 1183 | const struct mbus_dram_window *cs = dram->cs + i; |
ff7b0479 SB |
1184 | |
1185 | writel((cs->base & 0xffff0000) | | |
1186 | (cs->mbus_attr << 8) | | |
1187 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1188 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1189 | ||
77ff7a70 SR |
1190 | /* Fill the caching variables for later use */ |
1191 | xordev->win_start[i] = cs->base; | |
1192 | xordev->win_end[i] = cs->base + cs->size - 1; | |
1193 | ||
ff7b0479 SB |
1194 | win_enable |= (1 << i); |
1195 | win_enable |= 3 << (16 + (2 * i)); | |
1196 | } | |
1197 | ||
1198 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1199 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
c4b4b732 TP |
1200 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
1201 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
ff7b0479 SB |
1202 | } |
1203 | ||
ac5f0f3f MW |
1204 | static void |
1205 | mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev) | |
1206 | { | |
1207 | void __iomem *base = xordev->xor_high_base; | |
1208 | u32 win_enable = 0; | |
1209 | int i; | |
1210 | ||
1211 | for (i = 0; i < 8; i++) { | |
1212 | writel(0, base + WINDOW_BASE(i)); | |
1213 | writel(0, base + WINDOW_SIZE(i)); | |
1214 | if (i < 4) | |
1215 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1216 | } | |
1217 | /* | |
1218 | * For Armada3700 open default 4GB Mbus window. The dram | |
1219 | * related configuration are done at AXIS level. | |
1220 | */ | |
1221 | writel(0xffff0000, base + WINDOW_SIZE(0)); | |
1222 | win_enable |= 1; | |
1223 | win_enable |= 3 << 16; | |
1224 | ||
1225 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1226 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
1227 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); | |
1228 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
1229 | } | |
1230 | ||
8b648436 TP |
1231 | /* |
1232 | * Since this XOR driver is basically used only for RAID5, we don't | |
1233 | * need to care about synchronizing ->suspend with DMA activity, | |
1234 | * because the DMA engine will naturally be quiet due to the block | |
1235 | * devices being suspended. | |
1236 | */ | |
1237 | static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state) | |
1238 | { | |
1239 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); | |
1240 | int i; | |
1241 | ||
1242 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
1243 | struct mv_xor_chan *mv_chan = xordev->channels[i]; | |
1244 | ||
1245 | if (!mv_chan) | |
1246 | continue; | |
1247 | ||
1248 | mv_chan->saved_config_reg = | |
1249 | readl_relaxed(XOR_CONFIG(mv_chan)); | |
1250 | mv_chan->saved_int_mask_reg = | |
1251 | readl_relaxed(XOR_INTR_MASK(mv_chan)); | |
1252 | } | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | static int mv_xor_resume(struct platform_device *dev) | |
1258 | { | |
1259 | struct mv_xor_device *xordev = platform_get_drvdata(dev); | |
1260 | const struct mbus_dram_target_info *dram; | |
1261 | int i; | |
1262 | ||
1263 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
1264 | struct mv_xor_chan *mv_chan = xordev->channels[i]; | |
1265 | ||
1266 | if (!mv_chan) | |
1267 | continue; | |
1268 | ||
1269 | writel_relaxed(mv_chan->saved_config_reg, | |
1270 | XOR_CONFIG(mv_chan)); | |
1271 | writel_relaxed(mv_chan->saved_int_mask_reg, | |
1272 | XOR_INTR_MASK(mv_chan)); | |
1273 | } | |
1274 | ||
ac5f0f3f MW |
1275 | if (xordev->xor_type == XOR_ARMADA_37XX) { |
1276 | mv_xor_conf_mbus_windows_a3700(xordev); | |
1277 | return 0; | |
1278 | } | |
1279 | ||
8b648436 TP |
1280 | dram = mv_mbus_dram_info(); |
1281 | if (dram) | |
1282 | mv_xor_conf_mbus_windows(xordev, dram); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
6f166312 | 1287 | static const struct of_device_id mv_xor_dt_ids[] = { |
dd130c65 GC |
1288 | { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION }, |
1289 | { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X }, | |
ac5f0f3f | 1290 | { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX }, |
6f166312 LA |
1291 | {}, |
1292 | }; | |
6f166312 | 1293 | |
77757291 | 1294 | static unsigned int mv_xor_engine_count; |
6f166312 | 1295 | |
c2714334 | 1296 | static int mv_xor_probe(struct platform_device *pdev) |
ff7b0479 | 1297 | { |
63a9332b | 1298 | const struct mbus_dram_target_info *dram; |
297eedba | 1299 | struct mv_xor_device *xordev; |
d4adcc01 | 1300 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ff7b0479 | 1301 | struct resource *res; |
77757291 | 1302 | unsigned int max_engines, max_channels; |
60d151f3 | 1303 | int i, ret; |
ff7b0479 | 1304 | |
1ba151cd | 1305 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
ff7b0479 | 1306 | |
297eedba TP |
1307 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
1308 | if (!xordev) | |
ff7b0479 SB |
1309 | return -ENOMEM; |
1310 | ||
1311 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1312 | if (!res) | |
1313 | return -ENODEV; | |
1314 | ||
297eedba TP |
1315 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
1316 | resource_size(res)); | |
1317 | if (!xordev->xor_base) | |
ff7b0479 SB |
1318 | return -EBUSY; |
1319 | ||
1320 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1321 | if (!res) | |
1322 | return -ENODEV; | |
1323 | ||
297eedba TP |
1324 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
1325 | resource_size(res)); | |
1326 | if (!xordev->xor_high_base) | |
ff7b0479 SB |
1327 | return -EBUSY; |
1328 | ||
297eedba | 1329 | platform_set_drvdata(pdev, xordev); |
ff7b0479 | 1330 | |
dd130c65 GC |
1331 | |
1332 | /* | |
1333 | * We need to know which type of XOR device we use before | |
1334 | * setting up. In non-dt case it can only be the legacy one. | |
1335 | */ | |
1336 | xordev->xor_type = XOR_ORION; | |
1337 | if (pdev->dev.of_node) { | |
1338 | const struct of_device_id *of_id = | |
1339 | of_match_device(mv_xor_dt_ids, | |
1340 | &pdev->dev); | |
1341 | ||
1342 | xordev->xor_type = (uintptr_t)of_id->data; | |
1343 | } | |
1344 | ||
ff7b0479 SB |
1345 | /* |
1346 | * (Re-)program MBUS remapping windows if we are asked to. | |
1347 | */ | |
ac5f0f3f MW |
1348 | if (xordev->xor_type == XOR_ARMADA_37XX) { |
1349 | mv_xor_conf_mbus_windows_a3700(xordev); | |
1350 | } else { | |
1351 | dram = mv_mbus_dram_info(); | |
1352 | if (dram) | |
1353 | mv_xor_conf_mbus_windows(xordev, dram); | |
1354 | } | |
ff7b0479 | 1355 | |
c510182b AL |
1356 | /* Not all platforms can gate the clock, so it is not |
1357 | * an error if the clock does not exists. | |
1358 | */ | |
297eedba TP |
1359 | xordev->clk = clk_get(&pdev->dev, NULL); |
1360 | if (!IS_ERR(xordev->clk)) | |
1361 | clk_prepare_enable(xordev->clk); | |
c510182b | 1362 | |
77757291 TP |
1363 | /* |
1364 | * We don't want to have more than one channel per CPU in | |
1365 | * order for async_tx to perform well. So we limit the number | |
1366 | * of engines and channels so that we take into account this | |
1367 | * constraint. Note that we also want to use channels from | |
ac5f0f3f MW |
1368 | * separate engines when possible. For dual-CPU Armada 3700 |
1369 | * SoC with single XOR engine allow using its both channels. | |
77757291 TP |
1370 | */ |
1371 | max_engines = num_present_cpus(); | |
ac5f0f3f MW |
1372 | if (xordev->xor_type == XOR_ARMADA_37XX) |
1373 | max_channels = num_present_cpus(); | |
1374 | else | |
1375 | max_channels = min_t(unsigned int, | |
1376 | MV_XOR_MAX_CHANNELS, | |
1377 | DIV_ROUND_UP(num_present_cpus(), 2)); | |
77757291 TP |
1378 | |
1379 | if (mv_xor_engine_count >= max_engines) | |
1380 | return 0; | |
1381 | ||
f7d12ef5 TP |
1382 | if (pdev->dev.of_node) { |
1383 | struct device_node *np; | |
1384 | int i = 0; | |
1385 | ||
1386 | for_each_child_of_node(pdev->dev.of_node, np) { | |
0be8253f | 1387 | struct mv_xor_chan *chan; |
f7d12ef5 TP |
1388 | dma_cap_mask_t cap_mask; |
1389 | int irq; | |
1390 | ||
77757291 TP |
1391 | if (i >= max_channels) |
1392 | continue; | |
1393 | ||
f7d12ef5 | 1394 | dma_cap_zero(cap_mask); |
6d8f7abd TP |
1395 | dma_cap_set(DMA_MEMCPY, cap_mask); |
1396 | dma_cap_set(DMA_XOR, cap_mask); | |
1397 | dma_cap_set(DMA_INTERRUPT, cap_mask); | |
f7d12ef5 TP |
1398 | |
1399 | irq = irq_of_parse_and_map(np, 0); | |
f8eb9e7d TP |
1400 | if (!irq) { |
1401 | ret = -ENODEV; | |
f7d12ef5 TP |
1402 | goto err_channel_add; |
1403 | } | |
1404 | ||
0be8253f | 1405 | chan = mv_xor_channel_add(xordev, pdev, i, |
dd130c65 | 1406 | cap_mask, irq); |
0be8253f RK |
1407 | if (IS_ERR(chan)) { |
1408 | ret = PTR_ERR(chan); | |
f7d12ef5 TP |
1409 | irq_dispose_mapping(irq); |
1410 | goto err_channel_add; | |
1411 | } | |
1412 | ||
0be8253f | 1413 | xordev->channels[i] = chan; |
f7d12ef5 TP |
1414 | i++; |
1415 | } | |
1416 | } else if (pdata && pdata->channels) { | |
77757291 | 1417 | for (i = 0; i < max_channels; i++) { |
e39f6ec1 | 1418 | struct mv_xor_channel_data *cd; |
0be8253f | 1419 | struct mv_xor_chan *chan; |
60d151f3 TP |
1420 | int irq; |
1421 | ||
1422 | cd = &pdata->channels[i]; | |
60d151f3 TP |
1423 | irq = platform_get_irq(pdev, i); |
1424 | if (irq < 0) { | |
1425 | ret = irq; | |
1426 | goto err_channel_add; | |
1427 | } | |
1428 | ||
0be8253f | 1429 | chan = mv_xor_channel_add(xordev, pdev, i, |
dd130c65 | 1430 | cd->cap_mask, irq); |
0be8253f RK |
1431 | if (IS_ERR(chan)) { |
1432 | ret = PTR_ERR(chan); | |
60d151f3 TP |
1433 | goto err_channel_add; |
1434 | } | |
0be8253f RK |
1435 | |
1436 | xordev->channels[i] = chan; | |
60d151f3 TP |
1437 | } |
1438 | } | |
c510182b | 1439 | |
ff7b0479 | 1440 | return 0; |
60d151f3 TP |
1441 | |
1442 | err_channel_add: | |
1443 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) | |
f7d12ef5 | 1444 | if (xordev->channels[i]) { |
ab6e439f | 1445 | mv_xor_channel_remove(xordev->channels[i]); |
f7d12ef5 TP |
1446 | if (pdev->dev.of_node) |
1447 | irq_dispose_mapping(xordev->channels[i]->irq); | |
f7d12ef5 | 1448 | } |
60d151f3 | 1449 | |
dab92064 TP |
1450 | if (!IS_ERR(xordev->clk)) { |
1451 | clk_disable_unprepare(xordev->clk); | |
1452 | clk_put(xordev->clk); | |
1453 | } | |
1454 | ||
60d151f3 | 1455 | return ret; |
ff7b0479 SB |
1456 | } |
1457 | ||
61971656 TP |
1458 | static struct platform_driver mv_xor_driver = { |
1459 | .probe = mv_xor_probe, | |
8b648436 TP |
1460 | .suspend = mv_xor_suspend, |
1461 | .resume = mv_xor_resume, | |
ff7b0479 | 1462 | .driver = { |
f7d12ef5 TP |
1463 | .name = MV_XOR_NAME, |
1464 | .of_match_table = of_match_ptr(mv_xor_dt_ids), | |
ff7b0479 SB |
1465 | }, |
1466 | }; | |
1467 | ||
812608d1 | 1468 | builtin_platform_driver(mv_xor_driver); |
ff7b0479 | 1469 | |
25cf68da | 1470 | /* |
ff7b0479 SB |
1471 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
1472 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); | |
1473 | MODULE_LICENSE("GPL"); | |
25cf68da | 1474 | */ |