Commit | Line | Data |
---|---|---|
ff7b0479 SB |
1 | /* |
2 | * offload engine driver for the Marvell XOR engine | |
3 | * Copyright (C) 2007, 2008, Marvell International Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
ff7b0479 SB |
22 | #include <linux/delay.h> |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/memory.h> | |
c510182b | 28 | #include <linux/clk.h> |
f7d12ef5 TP |
29 | #include <linux/of.h> |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/irqdomain.h> | |
c02cecb9 | 32 | #include <linux/platform_data/dma-mv_xor.h> |
d2ebfb33 RKAL |
33 | |
34 | #include "dmaengine.h" | |
ff7b0479 SB |
35 | #include "mv_xor.h" |
36 | ||
37 | static void mv_xor_issue_pending(struct dma_chan *chan); | |
38 | ||
39 | #define to_mv_xor_chan(chan) \ | |
98817b99 | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
ff7b0479 SB |
41 | |
42 | #define to_mv_xor_slot(tx) \ | |
43 | container_of(tx, struct mv_xor_desc_slot, async_tx) | |
44 | ||
c98c1781 | 45 | #define mv_chan_to_devp(chan) \ |
1ef48a26 | 46 | ((chan)->dmadev.dev) |
c98c1781 | 47 | |
ff7b0479 SB |
48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags) |
49 | { | |
50 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
51 | ||
52 | hw_desc->status = (1 << 31); | |
53 | hw_desc->phy_next_desc = 0; | |
54 | hw_desc->desc_command = (1 << 31); | |
55 | } | |
56 | ||
ff7b0479 SB |
57 | static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc, |
58 | u32 byte_count) | |
59 | { | |
60 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
61 | hw_desc->byte_count = byte_count; | |
62 | } | |
63 | ||
64 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, | |
65 | u32 next_desc_addr) | |
66 | { | |
67 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
68 | BUG_ON(hw_desc->phy_next_desc); | |
69 | hw_desc->phy_next_desc = next_desc_addr; | |
70 | } | |
71 | ||
72 | static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc) | |
73 | { | |
74 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
75 | hw_desc->phy_next_desc = 0; | |
76 | } | |
77 | ||
ff7b0479 SB |
78 | static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc, |
79 | dma_addr_t addr) | |
80 | { | |
81 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
82 | hw_desc->phy_dest_addr = addr; | |
83 | } | |
84 | ||
85 | static int mv_chan_memset_slot_count(size_t len) | |
86 | { | |
87 | return 1; | |
88 | } | |
89 | ||
90 | #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c) | |
91 | ||
92 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, | |
93 | int index, dma_addr_t addr) | |
94 | { | |
95 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
e03bc654 | 96 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
ff7b0479 SB |
97 | if (desc->type == DMA_XOR) |
98 | hw_desc->desc_command |= (1 << index); | |
99 | } | |
100 | ||
101 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) | |
102 | { | |
5733c38a | 103 | return readl_relaxed(XOR_CURR_DESC(chan)); |
ff7b0479 SB |
104 | } |
105 | ||
106 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, | |
107 | u32 next_desc_addr) | |
108 | { | |
5733c38a | 109 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
ff7b0479 SB |
110 | } |
111 | ||
ff7b0479 SB |
112 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
113 | { | |
5733c38a | 114 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
ff7b0479 | 115 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
5733c38a | 116 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
ff7b0479 SB |
117 | } |
118 | ||
119 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |
120 | { | |
5733c38a | 121 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
122 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
123 | return intr_cause; | |
124 | } | |
125 | ||
126 | static int mv_is_err_intr(u32 intr_cause) | |
127 | { | |
128 | if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9))) | |
129 | return 1; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) | |
135 | { | |
86363682 | 136 | u32 val = ~(1 << (chan->idx * 16)); |
c98c1781 | 137 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
5733c38a | 138 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
139 | } |
140 | ||
141 | static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan) | |
142 | { | |
143 | u32 val = 0xFFFF0000 >> (chan->idx * 16); | |
5733c38a | 144 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
145 | } |
146 | ||
147 | static int mv_can_chain(struct mv_xor_desc_slot *desc) | |
148 | { | |
149 | struct mv_xor_desc_slot *chain_old_tail = list_entry( | |
150 | desc->chain_node.prev, struct mv_xor_desc_slot, chain_node); | |
151 | ||
152 | if (chain_old_tail->type != desc->type) | |
153 | return 0; | |
ff7b0479 SB |
154 | |
155 | return 1; | |
156 | } | |
157 | ||
158 | static void mv_set_mode(struct mv_xor_chan *chan, | |
159 | enum dma_transaction_type type) | |
160 | { | |
161 | u32 op_mode; | |
5733c38a | 162 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
ff7b0479 SB |
163 | |
164 | switch (type) { | |
165 | case DMA_XOR: | |
166 | op_mode = XOR_OPERATION_MODE_XOR; | |
167 | break; | |
168 | case DMA_MEMCPY: | |
169 | op_mode = XOR_OPERATION_MODE_MEMCPY; | |
170 | break; | |
ff7b0479 | 171 | default: |
c98c1781 | 172 | dev_err(mv_chan_to_devp(chan), |
1ba151cd | 173 | "error: unsupported operation %d\n", |
a3fc74bc | 174 | type); |
ff7b0479 SB |
175 | BUG(); |
176 | return; | |
177 | } | |
178 | ||
179 | config &= ~0x7; | |
180 | config |= op_mode; | |
e03bc654 TP |
181 | |
182 | #if defined(__BIG_ENDIAN) | |
183 | config |= XOR_DESCRIPTOR_SWAP; | |
184 | #else | |
185 | config &= ~XOR_DESCRIPTOR_SWAP; | |
186 | #endif | |
187 | ||
5733c38a | 188 | writel_relaxed(config, XOR_CONFIG(chan)); |
ff7b0479 SB |
189 | chan->current_type = type; |
190 | } | |
191 | ||
192 | static void mv_chan_activate(struct mv_xor_chan *chan) | |
193 | { | |
194 | u32 activation; | |
195 | ||
c98c1781 | 196 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
5733c38a | 197 | activation = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 | 198 | activation |= 0x1; |
5733c38a | 199 | writel_relaxed(activation, XOR_ACTIVATION(chan)); |
ff7b0479 SB |
200 | } |
201 | ||
202 | static char mv_chan_is_busy(struct mv_xor_chan *chan) | |
203 | { | |
5733c38a | 204 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 SB |
205 | |
206 | state = (state >> 4) & 0x3; | |
207 | ||
208 | return (state == 1) ? 1 : 0; | |
209 | } | |
210 | ||
211 | static int mv_chan_xor_slot_count(size_t len, int src_cnt) | |
212 | { | |
213 | return 1; | |
214 | } | |
215 | ||
216 | /** | |
217 | * mv_xor_free_slots - flags descriptor slots for reuse | |
218 | * @slot: Slot to free | |
219 | * Caller must hold &mv_chan->lock while calling this function | |
220 | */ | |
221 | static void mv_xor_free_slots(struct mv_xor_chan *mv_chan, | |
222 | struct mv_xor_desc_slot *slot) | |
223 | { | |
c98c1781 | 224 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", |
ff7b0479 SB |
225 | __func__, __LINE__, slot); |
226 | ||
227 | slot->slots_per_op = 0; | |
228 | ||
229 | } | |
230 | ||
231 | /* | |
232 | * mv_xor_start_new_chain - program the engine to operate on new chain headed by | |
233 | * sw_desc | |
234 | * Caller must hold &mv_chan->lock while calling this function | |
235 | */ | |
236 | static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan, | |
237 | struct mv_xor_desc_slot *sw_desc) | |
238 | { | |
c98c1781 | 239 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
ff7b0479 SB |
240 | __func__, __LINE__, sw_desc); |
241 | if (sw_desc->type != mv_chan->current_type) | |
242 | mv_set_mode(mv_chan, sw_desc->type); | |
243 | ||
48a9db46 BZ |
244 | /* set the hardware chain */ |
245 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); | |
246 | ||
ff7b0479 | 247 | mv_chan->pending += sw_desc->slot_cnt; |
98817b99 | 248 | mv_xor_issue_pending(&mv_chan->dmachan); |
ff7b0479 SB |
249 | } |
250 | ||
251 | static dma_cookie_t | |
252 | mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, | |
253 | struct mv_xor_chan *mv_chan, dma_cookie_t cookie) | |
254 | { | |
255 | BUG_ON(desc->async_tx.cookie < 0); | |
256 | ||
257 | if (desc->async_tx.cookie > 0) { | |
258 | cookie = desc->async_tx.cookie; | |
259 | ||
260 | /* call the callback (must not sleep or submit new | |
261 | * operations to this channel) | |
262 | */ | |
263 | if (desc->async_tx.callback) | |
264 | desc->async_tx.callback( | |
265 | desc->async_tx.callback_param); | |
266 | ||
d38a8c62 | 267 | dma_descriptor_unmap(&desc->async_tx); |
54f8d501 | 268 | if (desc->group_head) |
ff7b0479 | 269 | desc->group_head = NULL; |
ff7b0479 SB |
270 | } |
271 | ||
272 | /* run dependent operations */ | |
07f2211e | 273 | dma_run_dependencies(&desc->async_tx); |
ff7b0479 SB |
274 | |
275 | return cookie; | |
276 | } | |
277 | ||
278 | static int | |
279 | mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan) | |
280 | { | |
281 | struct mv_xor_desc_slot *iter, *_iter; | |
282 | ||
c98c1781 | 283 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
ff7b0479 SB |
284 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
285 | completed_node) { | |
286 | ||
287 | if (async_tx_test_ack(&iter->async_tx)) { | |
288 | list_del(&iter->completed_node); | |
289 | mv_xor_free_slots(mv_chan, iter); | |
290 | } | |
291 | } | |
292 | return 0; | |
293 | } | |
294 | ||
295 | static int | |
296 | mv_xor_clean_slot(struct mv_xor_desc_slot *desc, | |
297 | struct mv_xor_chan *mv_chan) | |
298 | { | |
c98c1781 | 299 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
ff7b0479 SB |
300 | __func__, __LINE__, desc, desc->async_tx.flags); |
301 | list_del(&desc->chain_node); | |
302 | /* the client is allowed to attach dependent operations | |
303 | * until 'ack' is set | |
304 | */ | |
305 | if (!async_tx_test_ack(&desc->async_tx)) { | |
306 | /* move this slot to the completed_slots */ | |
307 | list_add_tail(&desc->completed_node, &mv_chan->completed_slots); | |
308 | return 0; | |
309 | } | |
310 | ||
311 | mv_xor_free_slots(mv_chan, desc); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
316 | { | |
317 | struct mv_xor_desc_slot *iter, *_iter; | |
318 | dma_cookie_t cookie = 0; | |
319 | int busy = mv_chan_is_busy(mv_chan); | |
320 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
321 | int seen_current = 0; | |
322 | ||
c98c1781 TP |
323 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
324 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); | |
ff7b0479 SB |
325 | mv_xor_clean_completed_slots(mv_chan); |
326 | ||
327 | /* free completed slots from the chain starting with | |
328 | * the oldest descriptor | |
329 | */ | |
330 | ||
331 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
332 | chain_node) { | |
333 | prefetch(_iter); | |
334 | prefetch(&_iter->async_tx); | |
335 | ||
336 | /* do not advance past the current descriptor loaded into the | |
337 | * hardware channel, subsequent descriptors are either in | |
338 | * process or have not been submitted | |
339 | */ | |
340 | if (seen_current) | |
341 | break; | |
342 | ||
343 | /* stop the search if we reach the current descriptor and the | |
344 | * channel is busy | |
345 | */ | |
346 | if (iter->async_tx.phys == current_desc) { | |
347 | seen_current = 1; | |
348 | if (busy) | |
349 | break; | |
350 | } | |
351 | ||
352 | cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie); | |
353 | ||
354 | if (mv_xor_clean_slot(iter, mv_chan)) | |
355 | break; | |
356 | } | |
357 | ||
358 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { | |
359 | struct mv_xor_desc_slot *chain_head; | |
360 | chain_head = list_entry(mv_chan->chain.next, | |
361 | struct mv_xor_desc_slot, | |
362 | chain_node); | |
363 | ||
364 | mv_xor_start_new_chain(mv_chan, chain_head); | |
365 | } | |
366 | ||
367 | if (cookie > 0) | |
98817b99 | 368 | mv_chan->dmachan.completed_cookie = cookie; |
ff7b0479 SB |
369 | } |
370 | ||
371 | static void | |
372 | mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
373 | { | |
374 | spin_lock_bh(&mv_chan->lock); | |
375 | __mv_xor_slot_cleanup(mv_chan); | |
376 | spin_unlock_bh(&mv_chan->lock); | |
377 | } | |
378 | ||
379 | static void mv_xor_tasklet(unsigned long data) | |
380 | { | |
381 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; | |
8333f65e | 382 | mv_xor_slot_cleanup(chan); |
ff7b0479 SB |
383 | } |
384 | ||
385 | static struct mv_xor_desc_slot * | |
386 | mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots, | |
387 | int slots_per_op) | |
388 | { | |
389 | struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL; | |
390 | LIST_HEAD(chain); | |
391 | int slots_found, retry = 0; | |
392 | ||
393 | /* start search from the last allocated descrtiptor | |
394 | * if a contiguous allocation can not be found start searching | |
395 | * from the beginning of the list | |
396 | */ | |
397 | retry: | |
398 | slots_found = 0; | |
399 | if (retry == 0) | |
400 | iter = mv_chan->last_used; | |
401 | else | |
402 | iter = list_entry(&mv_chan->all_slots, | |
403 | struct mv_xor_desc_slot, | |
404 | slot_node); | |
405 | ||
406 | list_for_each_entry_safe_continue( | |
407 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
408 | prefetch(_iter); | |
409 | prefetch(&_iter->async_tx); | |
410 | if (iter->slots_per_op) { | |
411 | /* give up after finding the first busy slot | |
412 | * on the second pass through the list | |
413 | */ | |
414 | if (retry) | |
415 | break; | |
416 | ||
417 | slots_found = 0; | |
418 | continue; | |
419 | } | |
420 | ||
421 | /* start the allocation if the slot is correctly aligned */ | |
422 | if (!slots_found++) | |
423 | alloc_start = iter; | |
424 | ||
425 | if (slots_found == num_slots) { | |
426 | struct mv_xor_desc_slot *alloc_tail = NULL; | |
427 | struct mv_xor_desc_slot *last_used = NULL; | |
428 | iter = alloc_start; | |
429 | while (num_slots) { | |
430 | int i; | |
431 | ||
432 | /* pre-ack all but the last descriptor */ | |
433 | async_tx_ack(&iter->async_tx); | |
434 | ||
435 | list_add_tail(&iter->chain_node, &chain); | |
436 | alloc_tail = iter; | |
437 | iter->async_tx.cookie = 0; | |
438 | iter->slot_cnt = num_slots; | |
439 | iter->xor_check_result = NULL; | |
440 | for (i = 0; i < slots_per_op; i++) { | |
441 | iter->slots_per_op = slots_per_op - i; | |
442 | last_used = iter; | |
443 | iter = list_entry(iter->slot_node.next, | |
444 | struct mv_xor_desc_slot, | |
445 | slot_node); | |
446 | } | |
447 | num_slots -= slots_per_op; | |
448 | } | |
449 | alloc_tail->group_head = alloc_start; | |
450 | alloc_tail->async_tx.cookie = -EBUSY; | |
64203b67 | 451 | list_splice(&chain, &alloc_tail->tx_list); |
ff7b0479 SB |
452 | mv_chan->last_used = last_used; |
453 | mv_desc_clear_next_desc(alloc_start); | |
454 | mv_desc_clear_next_desc(alloc_tail); | |
455 | return alloc_tail; | |
456 | } | |
457 | } | |
458 | if (!retry++) | |
459 | goto retry; | |
460 | ||
461 | /* try to free some slots if the allocation fails */ | |
462 | tasklet_schedule(&mv_chan->irq_tasklet); | |
463 | ||
464 | return NULL; | |
465 | } | |
466 | ||
ff7b0479 SB |
467 | /************************ DMA engine API functions ****************************/ |
468 | static dma_cookie_t | |
469 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) | |
470 | { | |
471 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); | |
472 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); | |
473 | struct mv_xor_desc_slot *grp_start, *old_chain_tail; | |
474 | dma_cookie_t cookie; | |
475 | int new_hw_chain = 1; | |
476 | ||
c98c1781 | 477 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
478 | "%s sw_desc %p: async_tx %p\n", |
479 | __func__, sw_desc, &sw_desc->async_tx); | |
480 | ||
481 | grp_start = sw_desc->group_head; | |
482 | ||
483 | spin_lock_bh(&mv_chan->lock); | |
884485e1 | 484 | cookie = dma_cookie_assign(tx); |
ff7b0479 SB |
485 | |
486 | if (list_empty(&mv_chan->chain)) | |
64203b67 | 487 | list_splice_init(&sw_desc->tx_list, &mv_chan->chain); |
ff7b0479 SB |
488 | else { |
489 | new_hw_chain = 0; | |
490 | ||
491 | old_chain_tail = list_entry(mv_chan->chain.prev, | |
492 | struct mv_xor_desc_slot, | |
493 | chain_node); | |
64203b67 | 494 | list_splice_init(&grp_start->tx_list, |
ff7b0479 SB |
495 | &old_chain_tail->chain_node); |
496 | ||
497 | if (!mv_can_chain(grp_start)) | |
498 | goto submit_done; | |
499 | ||
31fd8f5b OJ |
500 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
501 | &old_chain_tail->async_tx.phys); | |
ff7b0479 SB |
502 | |
503 | /* fix up the hardware chain */ | |
504 | mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys); | |
505 | ||
506 | /* if the channel is not busy */ | |
507 | if (!mv_chan_is_busy(mv_chan)) { | |
508 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
509 | /* | |
510 | * and the curren desc is the end of the chain before | |
511 | * the append, then we need to start the channel | |
512 | */ | |
513 | if (current_desc == old_chain_tail->async_tx.phys) | |
514 | new_hw_chain = 1; | |
515 | } | |
516 | } | |
517 | ||
518 | if (new_hw_chain) | |
519 | mv_xor_start_new_chain(mv_chan, grp_start); | |
520 | ||
521 | submit_done: | |
522 | spin_unlock_bh(&mv_chan->lock); | |
523 | ||
524 | return cookie; | |
525 | } | |
526 | ||
527 | /* returns the number of allocated descriptors */ | |
aa1e6f1a | 528 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
ff7b0479 | 529 | { |
31fd8f5b OJ |
530 | void *virt_desc; |
531 | dma_addr_t dma_desc; | |
ff7b0479 SB |
532 | int idx; |
533 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
534 | struct mv_xor_desc_slot *slot = NULL; | |
b503fa01 | 535 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
ff7b0479 SB |
536 | |
537 | /* Allocate descriptor slots */ | |
538 | idx = mv_chan->slots_allocated; | |
539 | while (idx < num_descs_in_pool) { | |
540 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
541 | if (!slot) { | |
542 | printk(KERN_INFO "MV XOR Channel only initialized" | |
543 | " %d descriptor slots", idx); | |
544 | break; | |
545 | } | |
31fd8f5b OJ |
546 | virt_desc = mv_chan->dma_desc_pool_virt; |
547 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
548 | |
549 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
550 | slot->async_tx.tx_submit = mv_xor_tx_submit; | |
551 | INIT_LIST_HEAD(&slot->chain_node); | |
552 | INIT_LIST_HEAD(&slot->slot_node); | |
64203b67 | 553 | INIT_LIST_HEAD(&slot->tx_list); |
31fd8f5b OJ |
554 | dma_desc = mv_chan->dma_desc_pool; |
555 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
556 | slot->idx = idx++; |
557 | ||
558 | spin_lock_bh(&mv_chan->lock); | |
559 | mv_chan->slots_allocated = idx; | |
560 | list_add_tail(&slot->slot_node, &mv_chan->all_slots); | |
561 | spin_unlock_bh(&mv_chan->lock); | |
562 | } | |
563 | ||
564 | if (mv_chan->slots_allocated && !mv_chan->last_used) | |
565 | mv_chan->last_used = list_entry(mv_chan->all_slots.next, | |
566 | struct mv_xor_desc_slot, | |
567 | slot_node); | |
568 | ||
c98c1781 | 569 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
570 | "allocated %d descriptor slots last_used: %p\n", |
571 | mv_chan->slots_allocated, mv_chan->last_used); | |
572 | ||
573 | return mv_chan->slots_allocated ? : -ENOMEM; | |
574 | } | |
575 | ||
576 | static struct dma_async_tx_descriptor * | |
577 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
578 | size_t len, unsigned long flags) | |
579 | { | |
580 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
581 | struct mv_xor_desc_slot *sw_desc, *grp_start; | |
582 | int slot_cnt; | |
583 | ||
c98c1781 | 584 | dev_dbg(mv_chan_to_devp(mv_chan), |
31fd8f5b OJ |
585 | "%s dest: %pad src %pad len: %u flags: %ld\n", |
586 | __func__, &dest, &src, len, flags); | |
ff7b0479 SB |
587 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
588 | return NULL; | |
589 | ||
7912d300 | 590 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 SB |
591 | |
592 | spin_lock_bh(&mv_chan->lock); | |
593 | slot_cnt = mv_chan_memcpy_slot_count(len); | |
594 | sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); | |
595 | if (sw_desc) { | |
596 | sw_desc->type = DMA_MEMCPY; | |
597 | sw_desc->async_tx.flags = flags; | |
598 | grp_start = sw_desc->group_head; | |
599 | mv_desc_init(grp_start, flags); | |
600 | mv_desc_set_byte_count(grp_start, len); | |
601 | mv_desc_set_dest_addr(sw_desc->group_head, dest); | |
602 | mv_desc_set_src_addr(grp_start, 0, src); | |
603 | sw_desc->unmap_src_cnt = 1; | |
604 | sw_desc->unmap_len = len; | |
605 | } | |
606 | spin_unlock_bh(&mv_chan->lock); | |
607 | ||
c98c1781 | 608 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 | 609 | "%s sw_desc %p async_tx %p\n", |
4c143725 | 610 | __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL); |
ff7b0479 SB |
611 | |
612 | return sw_desc ? &sw_desc->async_tx : NULL; | |
613 | } | |
614 | ||
ff7b0479 SB |
615 | static struct dma_async_tx_descriptor * |
616 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
617 | unsigned int src_cnt, size_t len, unsigned long flags) | |
618 | { | |
619 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
620 | struct mv_xor_desc_slot *sw_desc, *grp_start; | |
621 | int slot_cnt; | |
622 | ||
623 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
624 | return NULL; | |
625 | ||
7912d300 | 626 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 | 627 | |
c98c1781 | 628 | dev_dbg(mv_chan_to_devp(mv_chan), |
31fd8f5b OJ |
629 | "%s src_cnt: %d len: %u dest %pad flags: %ld\n", |
630 | __func__, src_cnt, len, &dest, flags); | |
ff7b0479 SB |
631 | |
632 | spin_lock_bh(&mv_chan->lock); | |
633 | slot_cnt = mv_chan_xor_slot_count(len, src_cnt); | |
634 | sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); | |
635 | if (sw_desc) { | |
636 | sw_desc->type = DMA_XOR; | |
637 | sw_desc->async_tx.flags = flags; | |
638 | grp_start = sw_desc->group_head; | |
639 | mv_desc_init(grp_start, flags); | |
640 | /* the byte count field is the same as in memcpy desc*/ | |
641 | mv_desc_set_byte_count(grp_start, len); | |
642 | mv_desc_set_dest_addr(sw_desc->group_head, dest); | |
643 | sw_desc->unmap_src_cnt = src_cnt; | |
644 | sw_desc->unmap_len = len; | |
645 | while (src_cnt--) | |
646 | mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]); | |
647 | } | |
648 | spin_unlock_bh(&mv_chan->lock); | |
c98c1781 | 649 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
650 | "%s sw_desc %p async_tx %p \n", |
651 | __func__, sw_desc, &sw_desc->async_tx); | |
652 | return sw_desc ? &sw_desc->async_tx : NULL; | |
653 | } | |
654 | ||
655 | static void mv_xor_free_chan_resources(struct dma_chan *chan) | |
656 | { | |
657 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
658 | struct mv_xor_desc_slot *iter, *_iter; | |
659 | int in_use_descs = 0; | |
660 | ||
661 | mv_xor_slot_cleanup(mv_chan); | |
662 | ||
663 | spin_lock_bh(&mv_chan->lock); | |
664 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
665 | chain_node) { | |
666 | in_use_descs++; | |
667 | list_del(&iter->chain_node); | |
668 | } | |
669 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, | |
670 | completed_node) { | |
671 | in_use_descs++; | |
672 | list_del(&iter->completed_node); | |
673 | } | |
674 | list_for_each_entry_safe_reverse( | |
675 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
676 | list_del(&iter->slot_node); | |
677 | kfree(iter); | |
678 | mv_chan->slots_allocated--; | |
679 | } | |
680 | mv_chan->last_used = NULL; | |
681 | ||
c98c1781 | 682 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
ff7b0479 SB |
683 | __func__, mv_chan->slots_allocated); |
684 | spin_unlock_bh(&mv_chan->lock); | |
685 | ||
686 | if (in_use_descs) | |
c98c1781 | 687 | dev_err(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
688 | "freeing %d in use descriptors!\n", in_use_descs); |
689 | } | |
690 | ||
691 | /** | |
07934481 | 692 | * mv_xor_status - poll the status of an XOR transaction |
ff7b0479 SB |
693 | * @chan: XOR channel handle |
694 | * @cookie: XOR transaction identifier | |
07934481 | 695 | * @txstate: XOR transactions state holder (or NULL) |
ff7b0479 | 696 | */ |
07934481 | 697 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
ff7b0479 | 698 | dma_cookie_t cookie, |
07934481 | 699 | struct dma_tx_state *txstate) |
ff7b0479 SB |
700 | { |
701 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
ff7b0479 SB |
702 | enum dma_status ret; |
703 | ||
96a2af41 | 704 | ret = dma_cookie_status(chan, cookie, txstate); |
b3efb8fc | 705 | if (ret == DMA_COMPLETE) { |
ff7b0479 SB |
706 | mv_xor_clean_completed_slots(mv_chan); |
707 | return ret; | |
708 | } | |
709 | mv_xor_slot_cleanup(mv_chan); | |
710 | ||
96a2af41 | 711 | return dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
712 | } |
713 | ||
714 | static void mv_dump_xor_regs(struct mv_xor_chan *chan) | |
715 | { | |
716 | u32 val; | |
717 | ||
5733c38a | 718 | val = readl_relaxed(XOR_CONFIG(chan)); |
1ba151cd | 719 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
ff7b0479 | 720 | |
5733c38a | 721 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
1ba151cd | 722 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
ff7b0479 | 723 | |
5733c38a | 724 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
1ba151cd | 725 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
ff7b0479 | 726 | |
5733c38a | 727 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
1ba151cd | 728 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
ff7b0479 | 729 | |
5733c38a | 730 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
1ba151cd | 731 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
ff7b0479 | 732 | |
5733c38a | 733 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
1ba151cd | 734 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
ff7b0479 SB |
735 | } |
736 | ||
737 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, | |
738 | u32 intr_cause) | |
739 | { | |
740 | if (intr_cause & (1 << 4)) { | |
c98c1781 | 741 | dev_dbg(mv_chan_to_devp(chan), |
ff7b0479 SB |
742 | "ignore this error\n"); |
743 | return; | |
744 | } | |
745 | ||
c98c1781 | 746 | dev_err(mv_chan_to_devp(chan), |
1ba151cd | 747 | "error on chan %d. intr cause 0x%08x\n", |
a3fc74bc | 748 | chan->idx, intr_cause); |
ff7b0479 SB |
749 | |
750 | mv_dump_xor_regs(chan); | |
751 | BUG(); | |
752 | } | |
753 | ||
754 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |
755 | { | |
756 | struct mv_xor_chan *chan = data; | |
757 | u32 intr_cause = mv_chan_get_intr_cause(chan); | |
758 | ||
c98c1781 | 759 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
ff7b0479 SB |
760 | |
761 | if (mv_is_err_intr(intr_cause)) | |
762 | mv_xor_err_interrupt_handler(chan, intr_cause); | |
763 | ||
764 | tasklet_schedule(&chan->irq_tasklet); | |
765 | ||
766 | mv_xor_device_clear_eoc_cause(chan); | |
767 | ||
768 | return IRQ_HANDLED; | |
769 | } | |
770 | ||
771 | static void mv_xor_issue_pending(struct dma_chan *chan) | |
772 | { | |
773 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
774 | ||
775 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { | |
776 | mv_chan->pending = 0; | |
777 | mv_chan_activate(mv_chan); | |
778 | } | |
779 | } | |
780 | ||
781 | /* | |
782 | * Perform a transaction to verify the HW works. | |
783 | */ | |
ff7b0479 | 784 | |
c2714334 | 785 | static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
786 | { |
787 | int i; | |
788 | void *src, *dest; | |
789 | dma_addr_t src_dma, dest_dma; | |
790 | struct dma_chan *dma_chan; | |
791 | dma_cookie_t cookie; | |
792 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 793 | struct dmaengine_unmap_data *unmap; |
ff7b0479 | 794 | int err = 0; |
ff7b0479 | 795 | |
d16695a7 | 796 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
797 | if (!src) |
798 | return -ENOMEM; | |
799 | ||
d16695a7 | 800 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
801 | if (!dest) { |
802 | kfree(src); | |
803 | return -ENOMEM; | |
804 | } | |
805 | ||
806 | /* Fill in src buffer */ | |
d16695a7 | 807 | for (i = 0; i < PAGE_SIZE; i++) |
ff7b0479 SB |
808 | ((u8 *) src)[i] = (u8)i; |
809 | ||
275cc0c8 | 810 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 811 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
812 | err = -ENODEV; |
813 | goto out; | |
814 | } | |
815 | ||
d16695a7 EG |
816 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
817 | if (!unmap) { | |
818 | err = -ENOMEM; | |
819 | goto free_resources; | |
820 | } | |
821 | ||
822 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, | |
823 | PAGE_SIZE, DMA_TO_DEVICE); | |
824 | unmap->to_cnt = 1; | |
825 | unmap->addr[0] = src_dma; | |
ff7b0479 | 826 | |
d16695a7 EG |
827 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
828 | PAGE_SIZE, DMA_FROM_DEVICE); | |
829 | unmap->from_cnt = 1; | |
830 | unmap->addr[1] = dest_dma; | |
831 | ||
832 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
833 | |
834 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | |
d16695a7 | 835 | PAGE_SIZE, 0); |
ff7b0479 SB |
836 | cookie = mv_xor_tx_submit(tx); |
837 | mv_xor_issue_pending(dma_chan); | |
838 | async_tx_ack(tx); | |
839 | msleep(1); | |
840 | ||
07934481 | 841 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 842 | DMA_COMPLETE) { |
a3fc74bc TP |
843 | dev_err(dma_chan->device->dev, |
844 | "Self-test copy timed out, disabling\n"); | |
ff7b0479 SB |
845 | err = -ENODEV; |
846 | goto free_resources; | |
847 | } | |
848 | ||
c35064c4 | 849 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
d16695a7 EG |
850 | PAGE_SIZE, DMA_FROM_DEVICE); |
851 | if (memcmp(src, dest, PAGE_SIZE)) { | |
a3fc74bc TP |
852 | dev_err(dma_chan->device->dev, |
853 | "Self-test copy failed compare, disabling\n"); | |
ff7b0479 SB |
854 | err = -ENODEV; |
855 | goto free_resources; | |
856 | } | |
857 | ||
858 | free_resources: | |
d16695a7 | 859 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
860 | mv_xor_free_chan_resources(dma_chan); |
861 | out: | |
862 | kfree(src); | |
863 | kfree(dest); | |
864 | return err; | |
865 | } | |
866 | ||
867 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 868 | static int |
275cc0c8 | 869 | mv_xor_xor_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
870 | { |
871 | int i, src_idx; | |
872 | struct page *dest; | |
873 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; | |
874 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; | |
875 | dma_addr_t dest_dma; | |
876 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 877 | struct dmaengine_unmap_data *unmap; |
ff7b0479 SB |
878 | struct dma_chan *dma_chan; |
879 | dma_cookie_t cookie; | |
880 | u8 cmp_byte = 0; | |
881 | u32 cmp_word; | |
882 | int err = 0; | |
d16695a7 | 883 | int src_count = MV_XOR_NUM_SRC_TEST; |
ff7b0479 | 884 | |
d16695a7 | 885 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 | 886 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
a09b09ae RK |
887 | if (!xor_srcs[src_idx]) { |
888 | while (src_idx--) | |
ff7b0479 | 889 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
890 | return -ENOMEM; |
891 | } | |
ff7b0479 SB |
892 | } |
893 | ||
894 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
895 | if (!dest) { |
896 | while (src_idx--) | |
ff7b0479 | 897 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
898 | return -ENOMEM; |
899 | } | |
ff7b0479 SB |
900 | |
901 | /* Fill in src buffers */ | |
d16695a7 | 902 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 SB |
903 | u8 *ptr = page_address(xor_srcs[src_idx]); |
904 | for (i = 0; i < PAGE_SIZE; i++) | |
905 | ptr[i] = (1 << src_idx); | |
906 | } | |
907 | ||
d16695a7 | 908 | for (src_idx = 0; src_idx < src_count; src_idx++) |
ff7b0479 SB |
909 | cmp_byte ^= (u8) (1 << src_idx); |
910 | ||
911 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
912 | (cmp_byte << 8) | cmp_byte; | |
913 | ||
914 | memset(page_address(dest), 0, PAGE_SIZE); | |
915 | ||
275cc0c8 | 916 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 917 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
918 | err = -ENODEV; |
919 | goto out; | |
920 | } | |
921 | ||
d16695a7 EG |
922 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
923 | GFP_KERNEL); | |
924 | if (!unmap) { | |
925 | err = -ENOMEM; | |
926 | goto free_resources; | |
927 | } | |
928 | ||
ff7b0479 | 929 | /* test xor */ |
d16695a7 EG |
930 | for (i = 0; i < src_count; i++) { |
931 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
932 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
933 | dma_srcs[i] = unmap->addr[i]; | |
934 | unmap->to_cnt++; | |
935 | } | |
ff7b0479 | 936 | |
d16695a7 EG |
937 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
938 | DMA_FROM_DEVICE); | |
939 | dest_dma = unmap->addr[src_count]; | |
940 | unmap->from_cnt = 1; | |
941 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
942 | |
943 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
d16695a7 | 944 | src_count, PAGE_SIZE, 0); |
ff7b0479 SB |
945 | |
946 | cookie = mv_xor_tx_submit(tx); | |
947 | mv_xor_issue_pending(dma_chan); | |
948 | async_tx_ack(tx); | |
949 | msleep(8); | |
950 | ||
07934481 | 951 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 952 | DMA_COMPLETE) { |
a3fc74bc TP |
953 | dev_err(dma_chan->device->dev, |
954 | "Self-test xor timed out, disabling\n"); | |
ff7b0479 SB |
955 | err = -ENODEV; |
956 | goto free_resources; | |
957 | } | |
958 | ||
c35064c4 | 959 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
960 | PAGE_SIZE, DMA_FROM_DEVICE); |
961 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
962 | u32 *ptr = page_address(dest); | |
963 | if (ptr[i] != cmp_word) { | |
a3fc74bc | 964 | dev_err(dma_chan->device->dev, |
1ba151cd JP |
965 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
966 | i, ptr[i], cmp_word); | |
ff7b0479 SB |
967 | err = -ENODEV; |
968 | goto free_resources; | |
969 | } | |
970 | } | |
971 | ||
972 | free_resources: | |
d16695a7 | 973 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
974 | mv_xor_free_chan_resources(dma_chan); |
975 | out: | |
d16695a7 | 976 | src_idx = src_count; |
ff7b0479 SB |
977 | while (src_idx--) |
978 | __free_page(xor_srcs[src_idx]); | |
979 | __free_page(dest); | |
980 | return err; | |
981 | } | |
982 | ||
34c93c86 AL |
983 | /* This driver does not implement any of the optional DMA operations. */ |
984 | static int | |
985 | mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
986 | unsigned long arg) | |
987 | { | |
988 | return -ENOSYS; | |
989 | } | |
990 | ||
1ef48a26 | 991 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
ff7b0479 | 992 | { |
ff7b0479 | 993 | struct dma_chan *chan, *_chan; |
1ef48a26 | 994 | struct device *dev = mv_chan->dmadev.dev; |
ff7b0479 | 995 | |
1ef48a26 | 996 | dma_async_device_unregister(&mv_chan->dmadev); |
ff7b0479 | 997 | |
b503fa01 | 998 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 999 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
ff7b0479 | 1000 | |
1ef48a26 | 1001 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
a6b4a9d2 | 1002 | device_node) { |
ff7b0479 SB |
1003 | list_del(&chan->device_node); |
1004 | } | |
1005 | ||
88eb92cb TP |
1006 | free_irq(mv_chan->irq, mv_chan); |
1007 | ||
ff7b0479 SB |
1008 | return 0; |
1009 | } | |
1010 | ||
1ef48a26 | 1011 | static struct mv_xor_chan * |
297eedba | 1012 | mv_xor_channel_add(struct mv_xor_device *xordev, |
a6b4a9d2 | 1013 | struct platform_device *pdev, |
b503fa01 | 1014 | int idx, dma_cap_mask_t cap_mask, int irq) |
ff7b0479 SB |
1015 | { |
1016 | int ret = 0; | |
ff7b0479 SB |
1017 | struct mv_xor_chan *mv_chan; |
1018 | struct dma_device *dma_dev; | |
ff7b0479 | 1019 | |
1ef48a26 | 1020 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
a577659f SK |
1021 | if (!mv_chan) |
1022 | return ERR_PTR(-ENOMEM); | |
ff7b0479 | 1023 | |
9aedbdba | 1024 | mv_chan->idx = idx; |
88eb92cb | 1025 | mv_chan->irq = irq; |
ff7b0479 | 1026 | |
1ef48a26 | 1027 | dma_dev = &mv_chan->dmadev; |
ff7b0479 SB |
1028 | |
1029 | /* allocate coherent memory for hardware descriptors | |
1030 | * note: writecombine gives slightly better performance, but | |
1031 | * requires that we explicitly flush the writes | |
1032 | */ | |
1ef48a26 | 1033 | mv_chan->dma_desc_pool_virt = |
b503fa01 | 1034 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 TP |
1035 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
1036 | if (!mv_chan->dma_desc_pool_virt) | |
a6b4a9d2 | 1037 | return ERR_PTR(-ENOMEM); |
ff7b0479 SB |
1038 | |
1039 | /* discover transaction capabilites from the platform data */ | |
a6b4a9d2 | 1040 | dma_dev->cap_mask = cap_mask; |
ff7b0479 SB |
1041 | |
1042 | INIT_LIST_HEAD(&dma_dev->channels); | |
1043 | ||
1044 | /* set base routines */ | |
1045 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; | |
1046 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; | |
07934481 | 1047 | dma_dev->device_tx_status = mv_xor_status; |
ff7b0479 | 1048 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
34c93c86 | 1049 | dma_dev->device_control = mv_xor_control; |
ff7b0479 SB |
1050 | dma_dev->dev = &pdev->dev; |
1051 | ||
1052 | /* set prep routines based on capability */ | |
1053 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) | |
1054 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; | |
ff7b0479 | 1055 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
c019894e | 1056 | dma_dev->max_xor = 8; |
ff7b0479 SB |
1057 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
1058 | } | |
1059 | ||
297eedba | 1060 | mv_chan->mmr_base = xordev->xor_base; |
82a1402e | 1061 | mv_chan->mmr_high_base = xordev->xor_high_base; |
ff7b0479 SB |
1062 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
1063 | mv_chan); | |
1064 | ||
1065 | /* clear errors before enabling interrupts */ | |
1066 | mv_xor_device_clear_err_status(mv_chan); | |
1067 | ||
2d0a0745 TP |
1068 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
1069 | 0, dev_name(&pdev->dev), mv_chan); | |
ff7b0479 SB |
1070 | if (ret) |
1071 | goto err_free_dma; | |
1072 | ||
1073 | mv_chan_unmask_interrupts(mv_chan); | |
1074 | ||
1075 | mv_set_mode(mv_chan, DMA_MEMCPY); | |
1076 | ||
1077 | spin_lock_init(&mv_chan->lock); | |
1078 | INIT_LIST_HEAD(&mv_chan->chain); | |
1079 | INIT_LIST_HEAD(&mv_chan->completed_slots); | |
1080 | INIT_LIST_HEAD(&mv_chan->all_slots); | |
98817b99 TP |
1081 | mv_chan->dmachan.device = dma_dev; |
1082 | dma_cookie_init(&mv_chan->dmachan); | |
ff7b0479 | 1083 | |
98817b99 | 1084 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
ff7b0479 SB |
1085 | |
1086 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
275cc0c8 | 1087 | ret = mv_xor_memcpy_self_test(mv_chan); |
ff7b0479 SB |
1088 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
1089 | if (ret) | |
2d0a0745 | 1090 | goto err_free_irq; |
ff7b0479 SB |
1091 | } |
1092 | ||
1093 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
275cc0c8 | 1094 | ret = mv_xor_xor_self_test(mv_chan); |
ff7b0479 SB |
1095 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1096 | if (ret) | |
2d0a0745 | 1097 | goto err_free_irq; |
ff7b0479 SB |
1098 | } |
1099 | ||
48a9db46 | 1100 | dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", |
1ba151cd | 1101 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
1ba151cd JP |
1102 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1103 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
ff7b0479 SB |
1104 | |
1105 | dma_async_device_register(dma_dev); | |
1ef48a26 | 1106 | return mv_chan; |
ff7b0479 | 1107 | |
2d0a0745 TP |
1108 | err_free_irq: |
1109 | free_irq(mv_chan->irq, mv_chan); | |
ff7b0479 | 1110 | err_free_dma: |
b503fa01 | 1111 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1112 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
a6b4a9d2 | 1113 | return ERR_PTR(ret); |
ff7b0479 SB |
1114 | } |
1115 | ||
1116 | static void | |
297eedba | 1117 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
63a9332b | 1118 | const struct mbus_dram_target_info *dram) |
ff7b0479 | 1119 | { |
82a1402e | 1120 | void __iomem *base = xordev->xor_high_base; |
ff7b0479 SB |
1121 | u32 win_enable = 0; |
1122 | int i; | |
1123 | ||
1124 | for (i = 0; i < 8; i++) { | |
1125 | writel(0, base + WINDOW_BASE(i)); | |
1126 | writel(0, base + WINDOW_SIZE(i)); | |
1127 | if (i < 4) | |
1128 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1129 | } | |
1130 | ||
1131 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 1132 | const struct mbus_dram_window *cs = dram->cs + i; |
ff7b0479 SB |
1133 | |
1134 | writel((cs->base & 0xffff0000) | | |
1135 | (cs->mbus_attr << 8) | | |
1136 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1137 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1138 | ||
1139 | win_enable |= (1 << i); | |
1140 | win_enable |= 3 << (16 + (2 * i)); | |
1141 | } | |
1142 | ||
1143 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1144 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
c4b4b732 TP |
1145 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
1146 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
ff7b0479 SB |
1147 | } |
1148 | ||
c2714334 | 1149 | static int mv_xor_probe(struct platform_device *pdev) |
ff7b0479 | 1150 | { |
63a9332b | 1151 | const struct mbus_dram_target_info *dram; |
297eedba | 1152 | struct mv_xor_device *xordev; |
d4adcc01 | 1153 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ff7b0479 | 1154 | struct resource *res; |
60d151f3 | 1155 | int i, ret; |
ff7b0479 | 1156 | |
1ba151cd | 1157 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
ff7b0479 | 1158 | |
297eedba TP |
1159 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
1160 | if (!xordev) | |
ff7b0479 SB |
1161 | return -ENOMEM; |
1162 | ||
1163 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1164 | if (!res) | |
1165 | return -ENODEV; | |
1166 | ||
297eedba TP |
1167 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
1168 | resource_size(res)); | |
1169 | if (!xordev->xor_base) | |
ff7b0479 SB |
1170 | return -EBUSY; |
1171 | ||
1172 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1173 | if (!res) | |
1174 | return -ENODEV; | |
1175 | ||
297eedba TP |
1176 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
1177 | resource_size(res)); | |
1178 | if (!xordev->xor_high_base) | |
ff7b0479 SB |
1179 | return -EBUSY; |
1180 | ||
297eedba | 1181 | platform_set_drvdata(pdev, xordev); |
ff7b0479 SB |
1182 | |
1183 | /* | |
1184 | * (Re-)program MBUS remapping windows if we are asked to. | |
1185 | */ | |
63a9332b AL |
1186 | dram = mv_mbus_dram_info(); |
1187 | if (dram) | |
297eedba | 1188 | mv_xor_conf_mbus_windows(xordev, dram); |
ff7b0479 | 1189 | |
c510182b AL |
1190 | /* Not all platforms can gate the clock, so it is not |
1191 | * an error if the clock does not exists. | |
1192 | */ | |
297eedba TP |
1193 | xordev->clk = clk_get(&pdev->dev, NULL); |
1194 | if (!IS_ERR(xordev->clk)) | |
1195 | clk_prepare_enable(xordev->clk); | |
c510182b | 1196 | |
f7d12ef5 TP |
1197 | if (pdev->dev.of_node) { |
1198 | struct device_node *np; | |
1199 | int i = 0; | |
1200 | ||
1201 | for_each_child_of_node(pdev->dev.of_node, np) { | |
0be8253f | 1202 | struct mv_xor_chan *chan; |
f7d12ef5 TP |
1203 | dma_cap_mask_t cap_mask; |
1204 | int irq; | |
1205 | ||
1206 | dma_cap_zero(cap_mask); | |
1207 | if (of_property_read_bool(np, "dmacap,memcpy")) | |
1208 | dma_cap_set(DMA_MEMCPY, cap_mask); | |
1209 | if (of_property_read_bool(np, "dmacap,xor")) | |
1210 | dma_cap_set(DMA_XOR, cap_mask); | |
f7d12ef5 TP |
1211 | if (of_property_read_bool(np, "dmacap,interrupt")) |
1212 | dma_cap_set(DMA_INTERRUPT, cap_mask); | |
1213 | ||
1214 | irq = irq_of_parse_and_map(np, 0); | |
f8eb9e7d TP |
1215 | if (!irq) { |
1216 | ret = -ENODEV; | |
f7d12ef5 TP |
1217 | goto err_channel_add; |
1218 | } | |
1219 | ||
0be8253f RK |
1220 | chan = mv_xor_channel_add(xordev, pdev, i, |
1221 | cap_mask, irq); | |
1222 | if (IS_ERR(chan)) { | |
1223 | ret = PTR_ERR(chan); | |
f7d12ef5 TP |
1224 | irq_dispose_mapping(irq); |
1225 | goto err_channel_add; | |
1226 | } | |
1227 | ||
0be8253f | 1228 | xordev->channels[i] = chan; |
f7d12ef5 TP |
1229 | i++; |
1230 | } | |
1231 | } else if (pdata && pdata->channels) { | |
60d151f3 | 1232 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
e39f6ec1 | 1233 | struct mv_xor_channel_data *cd; |
0be8253f | 1234 | struct mv_xor_chan *chan; |
60d151f3 TP |
1235 | int irq; |
1236 | ||
1237 | cd = &pdata->channels[i]; | |
1238 | if (!cd) { | |
1239 | ret = -ENODEV; | |
1240 | goto err_channel_add; | |
1241 | } | |
1242 | ||
1243 | irq = platform_get_irq(pdev, i); | |
1244 | if (irq < 0) { | |
1245 | ret = irq; | |
1246 | goto err_channel_add; | |
1247 | } | |
1248 | ||
0be8253f RK |
1249 | chan = mv_xor_channel_add(xordev, pdev, i, |
1250 | cd->cap_mask, irq); | |
1251 | if (IS_ERR(chan)) { | |
1252 | ret = PTR_ERR(chan); | |
60d151f3 TP |
1253 | goto err_channel_add; |
1254 | } | |
0be8253f RK |
1255 | |
1256 | xordev->channels[i] = chan; | |
60d151f3 TP |
1257 | } |
1258 | } | |
c510182b | 1259 | |
ff7b0479 | 1260 | return 0; |
60d151f3 TP |
1261 | |
1262 | err_channel_add: | |
1263 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) | |
f7d12ef5 | 1264 | if (xordev->channels[i]) { |
ab6e439f | 1265 | mv_xor_channel_remove(xordev->channels[i]); |
f7d12ef5 TP |
1266 | if (pdev->dev.of_node) |
1267 | irq_dispose_mapping(xordev->channels[i]->irq); | |
f7d12ef5 | 1268 | } |
60d151f3 | 1269 | |
dab92064 TP |
1270 | if (!IS_ERR(xordev->clk)) { |
1271 | clk_disable_unprepare(xordev->clk); | |
1272 | clk_put(xordev->clk); | |
1273 | } | |
1274 | ||
60d151f3 | 1275 | return ret; |
ff7b0479 SB |
1276 | } |
1277 | ||
c2714334 | 1278 | static int mv_xor_remove(struct platform_device *pdev) |
ff7b0479 | 1279 | { |
297eedba | 1280 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
60d151f3 TP |
1281 | int i; |
1282 | ||
1283 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
297eedba TP |
1284 | if (xordev->channels[i]) |
1285 | mv_xor_channel_remove(xordev->channels[i]); | |
60d151f3 | 1286 | } |
c510182b | 1287 | |
297eedba TP |
1288 | if (!IS_ERR(xordev->clk)) { |
1289 | clk_disable_unprepare(xordev->clk); | |
1290 | clk_put(xordev->clk); | |
c510182b AL |
1291 | } |
1292 | ||
ff7b0479 SB |
1293 | return 0; |
1294 | } | |
1295 | ||
f7d12ef5 | 1296 | #ifdef CONFIG_OF |
c2714334 | 1297 | static struct of_device_id mv_xor_dt_ids[] = { |
f7d12ef5 TP |
1298 | { .compatible = "marvell,orion-xor", }, |
1299 | {}, | |
1300 | }; | |
1301 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); | |
1302 | #endif | |
1303 | ||
61971656 TP |
1304 | static struct platform_driver mv_xor_driver = { |
1305 | .probe = mv_xor_probe, | |
c2714334 | 1306 | .remove = mv_xor_remove, |
ff7b0479 | 1307 | .driver = { |
f7d12ef5 TP |
1308 | .owner = THIS_MODULE, |
1309 | .name = MV_XOR_NAME, | |
1310 | .of_match_table = of_match_ptr(mv_xor_dt_ids), | |
ff7b0479 SB |
1311 | }, |
1312 | }; | |
1313 | ||
1314 | ||
1315 | static int __init mv_xor_init(void) | |
1316 | { | |
61971656 | 1317 | return platform_driver_register(&mv_xor_driver); |
ff7b0479 SB |
1318 | } |
1319 | module_init(mv_xor_init); | |
1320 | ||
1321 | /* it's currently unsafe to unload this module */ | |
1322 | #if 0 | |
1323 | static void __exit mv_xor_exit(void) | |
1324 | { | |
1325 | platform_driver_unregister(&mv_xor_driver); | |
ff7b0479 SB |
1326 | return; |
1327 | } | |
1328 | ||
1329 | module_exit(mv_xor_exit); | |
1330 | #endif | |
1331 | ||
1332 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); | |
1333 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); | |
1334 | MODULE_LICENSE("GPL"); |