Commit | Line | Data |
---|---|---|
2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ff7b0479 SB |
2 | /* |
3 | * offload engine driver for the Marvell XOR engine | |
4 | * Copyright (C) 2007, 2008, Marvell International Ltd. | |
ff7b0479 SB |
5 | */ |
6 | ||
7 | #include <linux/init.h> | |
5a0e3ad6 | 8 | #include <linux/slab.h> |
ff7b0479 SB |
9 | #include <linux/delay.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/spinlock.h> | |
12 | #include <linux/interrupt.h> | |
6f166312 | 13 | #include <linux/of_device.h> |
ff7b0479 SB |
14 | #include <linux/platform_device.h> |
15 | #include <linux/memory.h> | |
c510182b | 16 | #include <linux/clk.h> |
f7d12ef5 TP |
17 | #include <linux/of.h> |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/irqdomain.h> | |
77757291 | 20 | #include <linux/cpumask.h> |
c02cecb9 | 21 | #include <linux/platform_data/dma-mv_xor.h> |
d2ebfb33 RKAL |
22 | |
23 | #include "dmaengine.h" | |
ff7b0479 SB |
24 | #include "mv_xor.h" |
25 | ||
dd130c65 GC |
26 | enum mv_xor_type { |
27 | XOR_ORION, | |
28 | XOR_ARMADA_38X, | |
ac5f0f3f | 29 | XOR_ARMADA_37XX, |
dd130c65 GC |
30 | }; |
31 | ||
6f166312 LA |
32 | enum mv_xor_mode { |
33 | XOR_MODE_IN_REG, | |
34 | XOR_MODE_IN_DESC, | |
35 | }; | |
36 | ||
ff7b0479 SB |
37 | static void mv_xor_issue_pending(struct dma_chan *chan); |
38 | ||
39 | #define to_mv_xor_chan(chan) \ | |
98817b99 | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
ff7b0479 SB |
41 | |
42 | #define to_mv_xor_slot(tx) \ | |
43 | container_of(tx, struct mv_xor_desc_slot, async_tx) | |
44 | ||
c98c1781 | 45 | #define mv_chan_to_devp(chan) \ |
1ef48a26 | 46 | ((chan)->dmadev.dev) |
c98c1781 | 47 | |
dfc97661 | 48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
ba87d137 LA |
49 | dma_addr_t addr, u32 byte_count, |
50 | enum dma_ctrl_flags flags) | |
ff7b0479 SB |
51 | { |
52 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
53 | ||
0e7488ed | 54 | hw_desc->status = XOR_DESC_DMA_OWNED; |
ff7b0479 | 55 | hw_desc->phy_next_desc = 0; |
ba87d137 LA |
56 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
57 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? | |
58 | XOR_DESC_EOD_INT_EN : 0; | |
dfc97661 | 59 | hw_desc->phy_dest_addr = addr; |
ff7b0479 SB |
60 | hw_desc->byte_count = byte_count; |
61 | } | |
62 | ||
6f166312 LA |
63 | static void mv_desc_set_mode(struct mv_xor_desc_slot *desc) |
64 | { | |
65 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
66 | ||
67 | switch (desc->type) { | |
68 | case DMA_XOR: | |
69 | case DMA_INTERRUPT: | |
70 | hw_desc->desc_command |= XOR_DESC_OPERATION_XOR; | |
71 | break; | |
72 | case DMA_MEMCPY: | |
73 | hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY; | |
74 | break; | |
75 | default: | |
76 | BUG(); | |
77 | return; | |
78 | } | |
79 | } | |
80 | ||
ff7b0479 SB |
81 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
82 | u32 next_desc_addr) | |
83 | { | |
84 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
85 | BUG_ON(hw_desc->phy_next_desc); | |
86 | hw_desc->phy_next_desc = next_desc_addr; | |
87 | } | |
88 | ||
ff7b0479 SB |
89 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
90 | int index, dma_addr_t addr) | |
91 | { | |
92 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
e03bc654 | 93 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
ff7b0479 SB |
94 | if (desc->type == DMA_XOR) |
95 | hw_desc->desc_command |= (1 << index); | |
96 | } | |
97 | ||
98 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) | |
99 | { | |
5733c38a | 100 | return readl_relaxed(XOR_CURR_DESC(chan)); |
ff7b0479 SB |
101 | } |
102 | ||
103 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, | |
104 | u32 next_desc_addr) | |
105 | { | |
5733c38a | 106 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
ff7b0479 SB |
107 | } |
108 | ||
ff7b0479 SB |
109 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
110 | { | |
5733c38a | 111 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
ff7b0479 | 112 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
5733c38a | 113 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
ff7b0479 SB |
114 | } |
115 | ||
116 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |
117 | { | |
5733c38a | 118 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
119 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
120 | return intr_cause; | |
121 | } | |
122 | ||
0951e728 | 123 | static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan) |
ff7b0479 | 124 | { |
ba87d137 LA |
125 | u32 val; |
126 | ||
127 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; | |
128 | val = ~(val << (chan->idx * 16)); | |
c98c1781 | 129 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
5733c38a | 130 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
131 | } |
132 | ||
0951e728 | 133 | static void mv_chan_clear_err_status(struct mv_xor_chan *chan) |
ff7b0479 SB |
134 | { |
135 | u32 val = 0xFFFF0000 >> (chan->idx * 16); | |
5733c38a | 136 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
137 | } |
138 | ||
0951e728 | 139 | static void mv_chan_set_mode(struct mv_xor_chan *chan, |
81aafb3e | 140 | u32 op_mode) |
ff7b0479 | 141 | { |
5733c38a | 142 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
ff7b0479 | 143 | |
6f166312 LA |
144 | config &= ~0x7; |
145 | config |= op_mode; | |
146 | ||
e03bc654 TP |
147 | #if defined(__BIG_ENDIAN) |
148 | config |= XOR_DESCRIPTOR_SWAP; | |
149 | #else | |
150 | config &= ~XOR_DESCRIPTOR_SWAP; | |
151 | #endif | |
152 | ||
5733c38a | 153 | writel_relaxed(config, XOR_CONFIG(chan)); |
ff7b0479 SB |
154 | } |
155 | ||
156 | static void mv_chan_activate(struct mv_xor_chan *chan) | |
157 | { | |
c98c1781 | 158 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
5a9a55bf EG |
159 | |
160 | /* writel ensures all descriptors are flushed before activation */ | |
161 | writel(BIT(0), XOR_ACTIVATION(chan)); | |
ff7b0479 SB |
162 | } |
163 | ||
164 | static char mv_chan_is_busy(struct mv_xor_chan *chan) | |
165 | { | |
5733c38a | 166 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 SB |
167 | |
168 | state = (state >> 4) & 0x3; | |
169 | ||
170 | return (state == 1) ? 1 : 0; | |
171 | } | |
172 | ||
ff7b0479 | 173 | /* |
0951e728 MR |
174 | * mv_chan_start_new_chain - program the engine to operate on new |
175 | * chain headed by sw_desc | |
ff7b0479 SB |
176 | * Caller must hold &mv_chan->lock while calling this function |
177 | */ | |
0951e728 MR |
178 | static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan, |
179 | struct mv_xor_desc_slot *sw_desc) | |
ff7b0479 | 180 | { |
c98c1781 | 181 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
ff7b0479 | 182 | __func__, __LINE__, sw_desc); |
ff7b0479 | 183 | |
48a9db46 BZ |
184 | /* set the hardware chain */ |
185 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); | |
186 | ||
dfc97661 | 187 | mv_chan->pending++; |
98817b99 | 188 | mv_xor_issue_pending(&mv_chan->dmachan); |
ff7b0479 SB |
189 | } |
190 | ||
191 | static dma_cookie_t | |
0951e728 MR |
192 | mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
193 | struct mv_xor_chan *mv_chan, | |
194 | dma_cookie_t cookie) | |
ff7b0479 SB |
195 | { |
196 | BUG_ON(desc->async_tx.cookie < 0); | |
197 | ||
198 | if (desc->async_tx.cookie > 0) { | |
199 | cookie = desc->async_tx.cookie; | |
200 | ||
8058e258 | 201 | dma_descriptor_unmap(&desc->async_tx); |
ff7b0479 SB |
202 | /* call the callback (must not sleep or submit new |
203 | * operations to this channel) | |
204 | */ | |
ee7681a4 | 205 | dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL); |
ff7b0479 SB |
206 | } |
207 | ||
208 | /* run dependent operations */ | |
07f2211e | 209 | dma_run_dependencies(&desc->async_tx); |
ff7b0479 SB |
210 | |
211 | return cookie; | |
212 | } | |
213 | ||
214 | static int | |
0951e728 | 215 | mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
216 | { |
217 | struct mv_xor_desc_slot *iter, *_iter; | |
218 | ||
c98c1781 | 219 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
ff7b0479 | 220 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
fbea28a2 | 221 | node) { |
ff7b0479 | 222 | |
c5db858b | 223 | if (async_tx_test_ack(&iter->async_tx)) { |
fbea28a2 | 224 | list_move_tail(&iter->node, &mv_chan->free_slots); |
c5db858b SR |
225 | if (!list_empty(&iter->sg_tx_list)) { |
226 | list_splice_tail_init(&iter->sg_tx_list, | |
227 | &mv_chan->free_slots); | |
228 | } | |
229 | } | |
ff7b0479 SB |
230 | } |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int | |
0951e728 MR |
235 | mv_desc_clean_slot(struct mv_xor_desc_slot *desc, |
236 | struct mv_xor_chan *mv_chan) | |
ff7b0479 | 237 | { |
c98c1781 | 238 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
ff7b0479 | 239 | __func__, __LINE__, desc, desc->async_tx.flags); |
fbea28a2 | 240 | |
ff7b0479 SB |
241 | /* the client is allowed to attach dependent operations |
242 | * until 'ack' is set | |
243 | */ | |
c5db858b | 244 | if (!async_tx_test_ack(&desc->async_tx)) { |
ff7b0479 | 245 | /* move this slot to the completed_slots */ |
fbea28a2 | 246 | list_move_tail(&desc->node, &mv_chan->completed_slots); |
c5db858b SR |
247 | if (!list_empty(&desc->sg_tx_list)) { |
248 | list_splice_tail_init(&desc->sg_tx_list, | |
249 | &mv_chan->completed_slots); | |
250 | } | |
251 | } else { | |
fbea28a2 | 252 | list_move_tail(&desc->node, &mv_chan->free_slots); |
c5db858b SR |
253 | if (!list_empty(&desc->sg_tx_list)) { |
254 | list_splice_tail_init(&desc->sg_tx_list, | |
255 | &mv_chan->free_slots); | |
256 | } | |
257 | } | |
ff7b0479 | 258 | |
ff7b0479 SB |
259 | return 0; |
260 | } | |
261 | ||
fbeec99a | 262 | /* This function must be called with the mv_xor_chan spinlock held */ |
0951e728 | 263 | static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
264 | { |
265 | struct mv_xor_desc_slot *iter, *_iter; | |
266 | dma_cookie_t cookie = 0; | |
267 | int busy = mv_chan_is_busy(mv_chan); | |
268 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
9136291f LA |
269 | int current_cleaned = 0; |
270 | struct mv_xor_desc *hw_desc; | |
ff7b0479 | 271 | |
c98c1781 TP |
272 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
273 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); | |
0951e728 | 274 | mv_chan_clean_completed_slots(mv_chan); |
ff7b0479 SB |
275 | |
276 | /* free completed slots from the chain starting with | |
277 | * the oldest descriptor | |
278 | */ | |
279 | ||
280 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
fbea28a2 | 281 | node) { |
ff7b0479 | 282 | |
9136291f LA |
283 | /* clean finished descriptors */ |
284 | hw_desc = iter->hw_desc; | |
285 | if (hw_desc->status & XOR_DESC_SUCCESS) { | |
0951e728 MR |
286 | cookie = mv_desc_run_tx_complete_actions(iter, mv_chan, |
287 | cookie); | |
ff7b0479 | 288 | |
9136291f | 289 | /* done processing desc, clean slot */ |
0951e728 | 290 | mv_desc_clean_slot(iter, mv_chan); |
9136291f LA |
291 | |
292 | /* break if we did cleaned the current */ | |
293 | if (iter->async_tx.phys == current_desc) { | |
294 | current_cleaned = 1; | |
295 | break; | |
296 | } | |
297 | } else { | |
298 | if (iter->async_tx.phys == current_desc) { | |
299 | current_cleaned = 0; | |
ff7b0479 | 300 | break; |
9136291f | 301 | } |
ff7b0479 | 302 | } |
ff7b0479 SB |
303 | } |
304 | ||
305 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { | |
9136291f LA |
306 | if (current_cleaned) { |
307 | /* | |
308 | * current descriptor cleaned and removed, run | |
309 | * from list head | |
310 | */ | |
311 | iter = list_entry(mv_chan->chain.next, | |
312 | struct mv_xor_desc_slot, | |
fbea28a2 | 313 | node); |
0951e728 | 314 | mv_chan_start_new_chain(mv_chan, iter); |
9136291f | 315 | } else { |
fbea28a2 | 316 | if (!list_is_last(&iter->node, &mv_chan->chain)) { |
9136291f LA |
317 | /* |
318 | * descriptors are still waiting after | |
319 | * current, trigger them | |
320 | */ | |
fbea28a2 | 321 | iter = list_entry(iter->node.next, |
9136291f | 322 | struct mv_xor_desc_slot, |
fbea28a2 | 323 | node); |
0951e728 | 324 | mv_chan_start_new_chain(mv_chan, iter); |
9136291f LA |
325 | } else { |
326 | /* | |
327 | * some descriptors are still waiting | |
328 | * to be cleaned | |
329 | */ | |
330 | tasklet_schedule(&mv_chan->irq_tasklet); | |
331 | } | |
332 | } | |
ff7b0479 SB |
333 | } |
334 | ||
335 | if (cookie > 0) | |
98817b99 | 336 | mv_chan->dmachan.completed_cookie = cookie; |
ff7b0479 SB |
337 | } |
338 | ||
34ca9a53 | 339 | static void mv_xor_tasklet(struct tasklet_struct *t) |
ff7b0479 | 340 | { |
34ca9a53 | 341 | struct mv_xor_chan *chan = from_tasklet(chan, t, irq_tasklet); |
e43147ac | 342 | |
cbc229a4 | 343 | spin_lock(&chan->lock); |
0951e728 | 344 | mv_chan_slot_cleanup(chan); |
cbc229a4 | 345 | spin_unlock(&chan->lock); |
ff7b0479 SB |
346 | } |
347 | ||
348 | static struct mv_xor_desc_slot * | |
0951e728 | 349 | mv_chan_alloc_slot(struct mv_xor_chan *mv_chan) |
ff7b0479 | 350 | { |
fbea28a2 | 351 | struct mv_xor_desc_slot *iter; |
ff7b0479 | 352 | |
fbea28a2 LA |
353 | spin_lock_bh(&mv_chan->lock); |
354 | ||
355 | if (!list_empty(&mv_chan->free_slots)) { | |
356 | iter = list_first_entry(&mv_chan->free_slots, | |
357 | struct mv_xor_desc_slot, | |
358 | node); | |
359 | ||
360 | list_move_tail(&iter->node, &mv_chan->allocated_slots); | |
361 | ||
362 | spin_unlock_bh(&mv_chan->lock); | |
ff7b0479 | 363 | |
dfc97661 LA |
364 | /* pre-ack descriptor */ |
365 | async_tx_ack(&iter->async_tx); | |
dfc97661 | 366 | iter->async_tx.cookie = -EBUSY; |
dfc97661 LA |
367 | |
368 | return iter; | |
369 | ||
ff7b0479 | 370 | } |
fbea28a2 LA |
371 | |
372 | spin_unlock_bh(&mv_chan->lock); | |
ff7b0479 SB |
373 | |
374 | /* try to free some slots if the allocation fails */ | |
375 | tasklet_schedule(&mv_chan->irq_tasklet); | |
376 | ||
377 | return NULL; | |
378 | } | |
379 | ||
ff7b0479 SB |
380 | /************************ DMA engine API functions ****************************/ |
381 | static dma_cookie_t | |
382 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) | |
383 | { | |
384 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); | |
385 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); | |
dfc97661 | 386 | struct mv_xor_desc_slot *old_chain_tail; |
ff7b0479 SB |
387 | dma_cookie_t cookie; |
388 | int new_hw_chain = 1; | |
389 | ||
c98c1781 | 390 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
391 | "%s sw_desc %p: async_tx %p\n", |
392 | __func__, sw_desc, &sw_desc->async_tx); | |
393 | ||
ff7b0479 | 394 | spin_lock_bh(&mv_chan->lock); |
884485e1 | 395 | cookie = dma_cookie_assign(tx); |
ff7b0479 SB |
396 | |
397 | if (list_empty(&mv_chan->chain)) | |
fbea28a2 | 398 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
ff7b0479 SB |
399 | else { |
400 | new_hw_chain = 0; | |
401 | ||
402 | old_chain_tail = list_entry(mv_chan->chain.prev, | |
403 | struct mv_xor_desc_slot, | |
fbea28a2 LA |
404 | node); |
405 | list_move_tail(&sw_desc->node, &mv_chan->chain); | |
ff7b0479 | 406 | |
31fd8f5b OJ |
407 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
408 | &old_chain_tail->async_tx.phys); | |
ff7b0479 SB |
409 | |
410 | /* fix up the hardware chain */ | |
dfc97661 | 411 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
ff7b0479 SB |
412 | |
413 | /* if the channel is not busy */ | |
414 | if (!mv_chan_is_busy(mv_chan)) { | |
415 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
416 | /* | |
417 | * and the curren desc is the end of the chain before | |
418 | * the append, then we need to start the channel | |
419 | */ | |
420 | if (current_desc == old_chain_tail->async_tx.phys) | |
421 | new_hw_chain = 1; | |
422 | } | |
423 | } | |
424 | ||
425 | if (new_hw_chain) | |
0951e728 | 426 | mv_chan_start_new_chain(mv_chan, sw_desc); |
ff7b0479 | 427 | |
ff7b0479 SB |
428 | spin_unlock_bh(&mv_chan->lock); |
429 | ||
430 | return cookie; | |
431 | } | |
432 | ||
433 | /* returns the number of allocated descriptors */ | |
aa1e6f1a | 434 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
ff7b0479 | 435 | { |
31fd8f5b OJ |
436 | void *virt_desc; |
437 | dma_addr_t dma_desc; | |
ff7b0479 SB |
438 | int idx; |
439 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
440 | struct mv_xor_desc_slot *slot = NULL; | |
b503fa01 | 441 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
ff7b0479 SB |
442 | |
443 | /* Allocate descriptor slots */ | |
444 | idx = mv_chan->slots_allocated; | |
445 | while (idx < num_descs_in_pool) { | |
446 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
447 | if (!slot) { | |
b8291dde EG |
448 | dev_info(mv_chan_to_devp(mv_chan), |
449 | "channel only initialized %d descriptor slots", | |
450 | idx); | |
ff7b0479 SB |
451 | break; |
452 | } | |
31fd8f5b OJ |
453 | virt_desc = mv_chan->dma_desc_pool_virt; |
454 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
455 | |
456 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
457 | slot->async_tx.tx_submit = mv_xor_tx_submit; | |
fbea28a2 | 458 | INIT_LIST_HEAD(&slot->node); |
c5db858b | 459 | INIT_LIST_HEAD(&slot->sg_tx_list); |
31fd8f5b OJ |
460 | dma_desc = mv_chan->dma_desc_pool; |
461 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
462 | slot->idx = idx++; |
463 | ||
464 | spin_lock_bh(&mv_chan->lock); | |
465 | mv_chan->slots_allocated = idx; | |
fbea28a2 | 466 | list_add_tail(&slot->node, &mv_chan->free_slots); |
ff7b0479 SB |
467 | spin_unlock_bh(&mv_chan->lock); |
468 | } | |
469 | ||
c98c1781 | 470 | dev_dbg(mv_chan_to_devp(mv_chan), |
fbea28a2 LA |
471 | "allocated %d descriptor slots\n", |
472 | mv_chan->slots_allocated); | |
ff7b0479 SB |
473 | |
474 | return mv_chan->slots_allocated ? : -ENOMEM; | |
475 | } | |
476 | ||
77ff7a70 SR |
477 | /* |
478 | * Check if source or destination is an PCIe/IO address (non-SDRAM) and add | |
479 | * a new MBus window if necessary. Use a cache for these check so that | |
480 | * the MMIO mapped registers don't have to be accessed for this check | |
481 | * to speed up this process. | |
482 | */ | |
483 | static int mv_xor_add_io_win(struct mv_xor_chan *mv_chan, u32 addr) | |
484 | { | |
485 | struct mv_xor_device *xordev = mv_chan->xordev; | |
486 | void __iomem *base = mv_chan->mmr_high_base; | |
487 | u32 win_enable; | |
488 | u32 size; | |
489 | u8 target, attr; | |
490 | int ret; | |
491 | int i; | |
492 | ||
493 | /* Nothing needs to get done for the Armada 3700 */ | |
494 | if (xordev->xor_type == XOR_ARMADA_37XX) | |
495 | return 0; | |
496 | ||
497 | /* | |
498 | * Loop over the cached windows to check, if the requested area | |
499 | * is already mapped. If this the case, nothing needs to be done | |
500 | * and we can return. | |
501 | */ | |
502 | for (i = 0; i < WINDOW_COUNT; i++) { | |
503 | if (addr >= xordev->win_start[i] && | |
504 | addr <= xordev->win_end[i]) { | |
505 | /* Window is already mapped */ | |
506 | return 0; | |
507 | } | |
508 | } | |
509 | ||
510 | /* | |
511 | * The window is not mapped, so we need to create the new mapping | |
512 | */ | |
513 | ||
514 | /* If no IO window is found that addr has to be located in SDRAM */ | |
515 | ret = mvebu_mbus_get_io_win_info(addr, &size, &target, &attr); | |
516 | if (ret < 0) | |
517 | return 0; | |
518 | ||
519 | /* | |
520 | * Mask the base addr 'addr' according to 'size' read back from the | |
521 | * MBus window. Otherwise we might end up with an address located | |
522 | * somewhere in the middle of this area here. | |
523 | */ | |
524 | size -= 1; | |
525 | addr &= ~size; | |
526 | ||
527 | /* | |
528 | * Reading one of both enabled register is enough, as they are always | |
529 | * programmed to the identical values | |
530 | */ | |
531 | win_enable = readl(base + WINDOW_BAR_ENABLE(0)); | |
532 | ||
533 | /* Set 'i' to the first free window to write the new values to */ | |
534 | i = ffs(~win_enable) - 1; | |
535 | if (i >= WINDOW_COUNT) | |
536 | return -ENOMEM; | |
537 | ||
538 | writel((addr & 0xffff0000) | (attr << 8) | target, | |
539 | base + WINDOW_BASE(i)); | |
540 | writel(size & 0xffff0000, base + WINDOW_SIZE(i)); | |
541 | ||
542 | /* Fill the caching variables for later use */ | |
543 | xordev->win_start[i] = addr; | |
544 | xordev->win_end[i] = addr + size; | |
545 | ||
546 | win_enable |= (1 << i); | |
547 | win_enable |= 3 << (16 + (2 * i)); | |
548 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
549 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
ff7b0479 SB |
554 | static struct dma_async_tx_descriptor * |
555 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
556 | unsigned int src_cnt, size_t len, unsigned long flags) | |
557 | { | |
558 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
dfc97661 | 559 | struct mv_xor_desc_slot *sw_desc; |
77ff7a70 | 560 | int ret; |
ff7b0479 SB |
561 | |
562 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
563 | return NULL; | |
564 | ||
7912d300 | 565 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 | 566 | |
c98c1781 | 567 | dev_dbg(mv_chan_to_devp(mv_chan), |
bc822e12 | 568 | "%s src_cnt: %d len: %zu dest %pad flags: %ld\n", |
31fd8f5b | 569 | __func__, src_cnt, len, &dest, flags); |
ff7b0479 | 570 | |
77ff7a70 SR |
571 | /* Check if a new window needs to get added for 'dest' */ |
572 | ret = mv_xor_add_io_win(mv_chan, dest); | |
573 | if (ret) | |
574 | return NULL; | |
575 | ||
0951e728 | 576 | sw_desc = mv_chan_alloc_slot(mv_chan); |
ff7b0479 SB |
577 | if (sw_desc) { |
578 | sw_desc->type = DMA_XOR; | |
579 | sw_desc->async_tx.flags = flags; | |
ba87d137 | 580 | mv_desc_init(sw_desc, dest, len, flags); |
6f166312 LA |
581 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
582 | mv_desc_set_mode(sw_desc); | |
77ff7a70 SR |
583 | while (src_cnt--) { |
584 | /* Check if a new window needs to get added for 'src' */ | |
585 | ret = mv_xor_add_io_win(mv_chan, src[src_cnt]); | |
586 | if (ret) | |
587 | return NULL; | |
dfc97661 | 588 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
77ff7a70 | 589 | } |
ff7b0479 | 590 | } |
fbea28a2 | 591 | |
c98c1781 | 592 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
593 | "%s sw_desc %p async_tx %p \n", |
594 | __func__, sw_desc, &sw_desc->async_tx); | |
595 | return sw_desc ? &sw_desc->async_tx : NULL; | |
596 | } | |
597 | ||
3e4f52e2 LA |
598 | static struct dma_async_tx_descriptor * |
599 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
600 | size_t len, unsigned long flags) | |
601 | { | |
602 | /* | |
603 | * A MEMCPY operation is identical to an XOR operation with only | |
604 | * a single source address. | |
605 | */ | |
606 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
607 | } | |
608 | ||
22843545 LA |
609 | static struct dma_async_tx_descriptor * |
610 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) | |
611 | { | |
612 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
613 | dma_addr_t src, dest; | |
614 | size_t len; | |
615 | ||
616 | src = mv_chan->dummy_src_addr; | |
617 | dest = mv_chan->dummy_dst_addr; | |
618 | len = MV_XOR_MIN_BYTE_COUNT; | |
619 | ||
620 | /* | |
621 | * We implement the DMA_INTERRUPT operation as a minimum sized | |
622 | * XOR operation with a single dummy source address. | |
623 | */ | |
624 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
625 | } | |
626 | ||
ff7b0479 SB |
627 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
628 | { | |
629 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
630 | struct mv_xor_desc_slot *iter, *_iter; | |
631 | int in_use_descs = 0; | |
632 | ||
ff7b0479 | 633 | spin_lock_bh(&mv_chan->lock); |
e43147ac | 634 | |
0951e728 | 635 | mv_chan_slot_cleanup(mv_chan); |
ff7b0479 | 636 | |
ff7b0479 | 637 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
fbea28a2 | 638 | node) { |
ff7b0479 | 639 | in_use_descs++; |
fbea28a2 | 640 | list_move_tail(&iter->node, &mv_chan->free_slots); |
ff7b0479 SB |
641 | } |
642 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, | |
fbea28a2 LA |
643 | node) { |
644 | in_use_descs++; | |
645 | list_move_tail(&iter->node, &mv_chan->free_slots); | |
646 | } | |
647 | list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots, | |
648 | node) { | |
ff7b0479 | 649 | in_use_descs++; |
fbea28a2 | 650 | list_move_tail(&iter->node, &mv_chan->free_slots); |
ff7b0479 SB |
651 | } |
652 | list_for_each_entry_safe_reverse( | |
fbea28a2 LA |
653 | iter, _iter, &mv_chan->free_slots, node) { |
654 | list_del(&iter->node); | |
ff7b0479 SB |
655 | kfree(iter); |
656 | mv_chan->slots_allocated--; | |
657 | } | |
ff7b0479 | 658 | |
c98c1781 | 659 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
ff7b0479 SB |
660 | __func__, mv_chan->slots_allocated); |
661 | spin_unlock_bh(&mv_chan->lock); | |
662 | ||
663 | if (in_use_descs) | |
c98c1781 | 664 | dev_err(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
665 | "freeing %d in use descriptors!\n", in_use_descs); |
666 | } | |
667 | ||
668 | /** | |
07934481 | 669 | * mv_xor_status - poll the status of an XOR transaction |
ff7b0479 SB |
670 | * @chan: XOR channel handle |
671 | * @cookie: XOR transaction identifier | |
07934481 | 672 | * @txstate: XOR transactions state holder (or NULL) |
ff7b0479 | 673 | */ |
07934481 | 674 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
ff7b0479 | 675 | dma_cookie_t cookie, |
07934481 | 676 | struct dma_tx_state *txstate) |
ff7b0479 SB |
677 | { |
678 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
ff7b0479 SB |
679 | enum dma_status ret; |
680 | ||
96a2af41 | 681 | ret = dma_cookie_status(chan, cookie, txstate); |
890766d2 | 682 | if (ret == DMA_COMPLETE) |
ff7b0479 | 683 | return ret; |
e43147ac EG |
684 | |
685 | spin_lock_bh(&mv_chan->lock); | |
0951e728 | 686 | mv_chan_slot_cleanup(mv_chan); |
e43147ac | 687 | spin_unlock_bh(&mv_chan->lock); |
ff7b0479 | 688 | |
96a2af41 | 689 | return dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
690 | } |
691 | ||
0951e728 | 692 | static void mv_chan_dump_regs(struct mv_xor_chan *chan) |
ff7b0479 SB |
693 | { |
694 | u32 val; | |
695 | ||
5733c38a | 696 | val = readl_relaxed(XOR_CONFIG(chan)); |
1ba151cd | 697 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
ff7b0479 | 698 | |
5733c38a | 699 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
1ba151cd | 700 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
ff7b0479 | 701 | |
5733c38a | 702 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
1ba151cd | 703 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
ff7b0479 | 704 | |
5733c38a | 705 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
1ba151cd | 706 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
ff7b0479 | 707 | |
5733c38a | 708 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
1ba151cd | 709 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
ff7b0479 | 710 | |
5733c38a | 711 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
1ba151cd | 712 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
ff7b0479 SB |
713 | } |
714 | ||
0951e728 MR |
715 | static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan, |
716 | u32 intr_cause) | |
ff7b0479 | 717 | { |
0e7488ed EG |
718 | if (intr_cause & XOR_INT_ERR_DECODE) { |
719 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); | |
720 | return; | |
ff7b0479 SB |
721 | } |
722 | ||
0e7488ed | 723 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
a3fc74bc | 724 | chan->idx, intr_cause); |
ff7b0479 | 725 | |
0951e728 | 726 | mv_chan_dump_regs(chan); |
0e7488ed | 727 | WARN_ON(1); |
ff7b0479 SB |
728 | } |
729 | ||
730 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |
731 | { | |
732 | struct mv_xor_chan *chan = data; | |
733 | u32 intr_cause = mv_chan_get_intr_cause(chan); | |
734 | ||
c98c1781 | 735 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
ff7b0479 | 736 | |
0e7488ed | 737 | if (intr_cause & XOR_INTR_ERRORS) |
0951e728 | 738 | mv_chan_err_interrupt_handler(chan, intr_cause); |
ff7b0479 SB |
739 | |
740 | tasklet_schedule(&chan->irq_tasklet); | |
741 | ||
0951e728 | 742 | mv_chan_clear_eoc_cause(chan); |
ff7b0479 SB |
743 | |
744 | return IRQ_HANDLED; | |
745 | } | |
746 | ||
747 | static void mv_xor_issue_pending(struct dma_chan *chan) | |
748 | { | |
749 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
750 | ||
751 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { | |
752 | mv_chan->pending = 0; | |
753 | mv_chan_activate(mv_chan); | |
754 | } | |
755 | } | |
756 | ||
757 | /* | |
758 | * Perform a transaction to verify the HW works. | |
759 | */ | |
ff7b0479 | 760 | |
0951e728 | 761 | static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 | 762 | { |
b8c01d25 | 763 | int i, ret; |
ff7b0479 SB |
764 | void *src, *dest; |
765 | dma_addr_t src_dma, dest_dma; | |
766 | struct dma_chan *dma_chan; | |
767 | dma_cookie_t cookie; | |
768 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 769 | struct dmaengine_unmap_data *unmap; |
ff7b0479 | 770 | int err = 0; |
ff7b0479 | 771 | |
6da2ec56 | 772 | src = kmalloc(PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
773 | if (!src) |
774 | return -ENOMEM; | |
775 | ||
6396bb22 | 776 | dest = kzalloc(PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
777 | if (!dest) { |
778 | kfree(src); | |
779 | return -ENOMEM; | |
780 | } | |
781 | ||
782 | /* Fill in src buffer */ | |
d16695a7 | 783 | for (i = 0; i < PAGE_SIZE; i++) |
ff7b0479 SB |
784 | ((u8 *) src)[i] = (u8)i; |
785 | ||
275cc0c8 | 786 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 787 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
788 | err = -ENODEV; |
789 | goto out; | |
790 | } | |
791 | ||
d16695a7 EG |
792 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
793 | if (!unmap) { | |
794 | err = -ENOMEM; | |
795 | goto free_resources; | |
796 | } | |
797 | ||
51564635 | 798 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), |
b70e52ca | 799 | offset_in_page(src), PAGE_SIZE, |
51564635 | 800 | DMA_TO_DEVICE); |
d16695a7 | 801 | unmap->addr[0] = src_dma; |
ff7b0479 | 802 | |
b8c01d25 EG |
803 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
804 | if (ret) { | |
805 | err = -ENOMEM; | |
806 | goto free_resources; | |
807 | } | |
808 | unmap->to_cnt = 1; | |
809 | ||
51564635 | 810 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), |
b70e52ca | 811 | offset_in_page(dest), PAGE_SIZE, |
51564635 | 812 | DMA_FROM_DEVICE); |
d16695a7 EG |
813 | unmap->addr[1] = dest_dma; |
814 | ||
b8c01d25 EG |
815 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
816 | if (ret) { | |
817 | err = -ENOMEM; | |
818 | goto free_resources; | |
819 | } | |
820 | unmap->from_cnt = 1; | |
d16695a7 | 821 | unmap->len = PAGE_SIZE; |
ff7b0479 SB |
822 | |
823 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | |
d16695a7 | 824 | PAGE_SIZE, 0); |
b8c01d25 EG |
825 | if (!tx) { |
826 | dev_err(dma_chan->device->dev, | |
827 | "Self-test cannot prepare operation, disabling\n"); | |
828 | err = -ENODEV; | |
829 | goto free_resources; | |
830 | } | |
831 | ||
ff7b0479 | 832 | cookie = mv_xor_tx_submit(tx); |
b8c01d25 EG |
833 | if (dma_submit_error(cookie)) { |
834 | dev_err(dma_chan->device->dev, | |
835 | "Self-test submit error, disabling\n"); | |
836 | err = -ENODEV; | |
837 | goto free_resources; | |
838 | } | |
839 | ||
ff7b0479 SB |
840 | mv_xor_issue_pending(dma_chan); |
841 | async_tx_ack(tx); | |
842 | msleep(1); | |
843 | ||
07934481 | 844 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 845 | DMA_COMPLETE) { |
a3fc74bc TP |
846 | dev_err(dma_chan->device->dev, |
847 | "Self-test copy timed out, disabling\n"); | |
ff7b0479 SB |
848 | err = -ENODEV; |
849 | goto free_resources; | |
850 | } | |
851 | ||
c35064c4 | 852 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
d16695a7 EG |
853 | PAGE_SIZE, DMA_FROM_DEVICE); |
854 | if (memcmp(src, dest, PAGE_SIZE)) { | |
a3fc74bc TP |
855 | dev_err(dma_chan->device->dev, |
856 | "Self-test copy failed compare, disabling\n"); | |
ff7b0479 SB |
857 | err = -ENODEV; |
858 | goto free_resources; | |
859 | } | |
860 | ||
861 | free_resources: | |
d16695a7 | 862 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
863 | mv_xor_free_chan_resources(dma_chan); |
864 | out: | |
865 | kfree(src); | |
866 | kfree(dest); | |
867 | return err; | |
868 | } | |
869 | ||
870 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 871 | static int |
0951e728 | 872 | mv_chan_xor_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 | 873 | { |
b8c01d25 | 874 | int i, src_idx, ret; |
ff7b0479 SB |
875 | struct page *dest; |
876 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; | |
877 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; | |
878 | dma_addr_t dest_dma; | |
879 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 880 | struct dmaengine_unmap_data *unmap; |
ff7b0479 SB |
881 | struct dma_chan *dma_chan; |
882 | dma_cookie_t cookie; | |
883 | u8 cmp_byte = 0; | |
884 | u32 cmp_word; | |
885 | int err = 0; | |
d16695a7 | 886 | int src_count = MV_XOR_NUM_SRC_TEST; |
ff7b0479 | 887 | |
d16695a7 | 888 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 | 889 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
a09b09ae RK |
890 | if (!xor_srcs[src_idx]) { |
891 | while (src_idx--) | |
ff7b0479 | 892 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
893 | return -ENOMEM; |
894 | } | |
ff7b0479 SB |
895 | } |
896 | ||
897 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
898 | if (!dest) { |
899 | while (src_idx--) | |
ff7b0479 | 900 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
901 | return -ENOMEM; |
902 | } | |
ff7b0479 SB |
903 | |
904 | /* Fill in src buffers */ | |
d16695a7 | 905 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 SB |
906 | u8 *ptr = page_address(xor_srcs[src_idx]); |
907 | for (i = 0; i < PAGE_SIZE; i++) | |
908 | ptr[i] = (1 << src_idx); | |
909 | } | |
910 | ||
d16695a7 | 911 | for (src_idx = 0; src_idx < src_count; src_idx++) |
ff7b0479 SB |
912 | cmp_byte ^= (u8) (1 << src_idx); |
913 | ||
914 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
915 | (cmp_byte << 8) | cmp_byte; | |
916 | ||
917 | memset(page_address(dest), 0, PAGE_SIZE); | |
918 | ||
275cc0c8 | 919 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 920 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
921 | err = -ENODEV; |
922 | goto out; | |
923 | } | |
924 | ||
d16695a7 EG |
925 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
926 | GFP_KERNEL); | |
927 | if (!unmap) { | |
928 | err = -ENOMEM; | |
929 | goto free_resources; | |
930 | } | |
931 | ||
ff7b0479 | 932 | /* test xor */ |
d16695a7 EG |
933 | for (i = 0; i < src_count; i++) { |
934 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
935 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
936 | dma_srcs[i] = unmap->addr[i]; | |
b8c01d25 EG |
937 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
938 | if (ret) { | |
939 | err = -ENOMEM; | |
940 | goto free_resources; | |
941 | } | |
d16695a7 EG |
942 | unmap->to_cnt++; |
943 | } | |
ff7b0479 | 944 | |
d16695a7 EG |
945 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
946 | DMA_FROM_DEVICE); | |
947 | dest_dma = unmap->addr[src_count]; | |
b8c01d25 EG |
948 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
949 | if (ret) { | |
950 | err = -ENOMEM; | |
951 | goto free_resources; | |
952 | } | |
d16695a7 EG |
953 | unmap->from_cnt = 1; |
954 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
955 | |
956 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
d16695a7 | 957 | src_count, PAGE_SIZE, 0); |
b8c01d25 EG |
958 | if (!tx) { |
959 | dev_err(dma_chan->device->dev, | |
960 | "Self-test cannot prepare operation, disabling\n"); | |
961 | err = -ENODEV; | |
962 | goto free_resources; | |
963 | } | |
ff7b0479 SB |
964 | |
965 | cookie = mv_xor_tx_submit(tx); | |
b8c01d25 EG |
966 | if (dma_submit_error(cookie)) { |
967 | dev_err(dma_chan->device->dev, | |
968 | "Self-test submit error, disabling\n"); | |
969 | err = -ENODEV; | |
970 | goto free_resources; | |
971 | } | |
972 | ||
ff7b0479 SB |
973 | mv_xor_issue_pending(dma_chan); |
974 | async_tx_ack(tx); | |
975 | msleep(8); | |
976 | ||
07934481 | 977 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 978 | DMA_COMPLETE) { |
a3fc74bc TP |
979 | dev_err(dma_chan->device->dev, |
980 | "Self-test xor timed out, disabling\n"); | |
ff7b0479 SB |
981 | err = -ENODEV; |
982 | goto free_resources; | |
983 | } | |
984 | ||
c35064c4 | 985 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
986 | PAGE_SIZE, DMA_FROM_DEVICE); |
987 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
988 | u32 *ptr = page_address(dest); | |
989 | if (ptr[i] != cmp_word) { | |
a3fc74bc | 990 | dev_err(dma_chan->device->dev, |
1ba151cd JP |
991 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
992 | i, ptr[i], cmp_word); | |
ff7b0479 SB |
993 | err = -ENODEV; |
994 | goto free_resources; | |
995 | } | |
996 | } | |
997 | ||
998 | free_resources: | |
d16695a7 | 999 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
1000 | mv_xor_free_chan_resources(dma_chan); |
1001 | out: | |
d16695a7 | 1002 | src_idx = src_count; |
ff7b0479 SB |
1003 | while (src_idx--) |
1004 | __free_page(xor_srcs[src_idx]); | |
1005 | __free_page(dest); | |
1006 | return err; | |
1007 | } | |
1008 | ||
1ef48a26 | 1009 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
ff7b0479 | 1010 | { |
ff7b0479 | 1011 | struct dma_chan *chan, *_chan; |
1ef48a26 | 1012 | struct device *dev = mv_chan->dmadev.dev; |
ff7b0479 | 1013 | |
1ef48a26 | 1014 | dma_async_device_unregister(&mv_chan->dmadev); |
ff7b0479 | 1015 | |
b503fa01 | 1016 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1017 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
22843545 LA |
1018 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
1019 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); | |
1020 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, | |
1021 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); | |
ff7b0479 | 1022 | |
1ef48a26 | 1023 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
a6b4a9d2 | 1024 | device_node) { |
ff7b0479 SB |
1025 | list_del(&chan->device_node); |
1026 | } | |
1027 | ||
88eb92cb TP |
1028 | free_irq(mv_chan->irq, mv_chan); |
1029 | ||
ff7b0479 SB |
1030 | return 0; |
1031 | } | |
1032 | ||
1ef48a26 | 1033 | static struct mv_xor_chan * |
297eedba | 1034 | mv_xor_channel_add(struct mv_xor_device *xordev, |
a6b4a9d2 | 1035 | struct platform_device *pdev, |
dd130c65 | 1036 | int idx, dma_cap_mask_t cap_mask, int irq) |
ff7b0479 SB |
1037 | { |
1038 | int ret = 0; | |
ff7b0479 SB |
1039 | struct mv_xor_chan *mv_chan; |
1040 | struct dma_device *dma_dev; | |
ff7b0479 | 1041 | |
1ef48a26 | 1042 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
a577659f SK |
1043 | if (!mv_chan) |
1044 | return ERR_PTR(-ENOMEM); | |
ff7b0479 | 1045 | |
9aedbdba | 1046 | mv_chan->idx = idx; |
88eb92cb | 1047 | mv_chan->irq = irq; |
dd130c65 GC |
1048 | if (xordev->xor_type == XOR_ORION) |
1049 | mv_chan->op_in_desc = XOR_MODE_IN_REG; | |
1050 | else | |
1051 | mv_chan->op_in_desc = XOR_MODE_IN_DESC; | |
ff7b0479 | 1052 | |
1ef48a26 | 1053 | dma_dev = &mv_chan->dmadev; |
3e5daee5 | 1054 | dma_dev->dev = &pdev->dev; |
77ff7a70 | 1055 | mv_chan->xordev = xordev; |
ff7b0479 | 1056 | |
22843545 LA |
1057 | /* |
1058 | * These source and destination dummy buffers are used to implement | |
1059 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. | |
1060 | * Hence, we only need to map the buffers at initialization-time. | |
1061 | */ | |
1062 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, | |
1063 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); | |
1064 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, | |
1065 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); | |
1066 | ||
ff7b0479 SB |
1067 | /* allocate coherent memory for hardware descriptors |
1068 | * note: writecombine gives slightly better performance, but | |
1069 | * requires that we explicitly flush the writes | |
1070 | */ | |
1ef48a26 | 1071 | mv_chan->dma_desc_pool_virt = |
f6e45661 LR |
1072 | dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool, |
1073 | GFP_KERNEL); | |
1ef48a26 | 1074 | if (!mv_chan->dma_desc_pool_virt) |
a6b4a9d2 | 1075 | return ERR_PTR(-ENOMEM); |
ff7b0479 SB |
1076 | |
1077 | /* discover transaction capabilites from the platform data */ | |
a6b4a9d2 | 1078 | dma_dev->cap_mask = cap_mask; |
ff7b0479 SB |
1079 | |
1080 | INIT_LIST_HEAD(&dma_dev->channels); | |
1081 | ||
1082 | /* set base routines */ | |
1083 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; | |
1084 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; | |
07934481 | 1085 | dma_dev->device_tx_status = mv_xor_status; |
ff7b0479 | 1086 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
ff7b0479 SB |
1087 | |
1088 | /* set prep routines based on capability */ | |
22843545 LA |
1089 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
1090 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; | |
ff7b0479 SB |
1091 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
1092 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; | |
ff7b0479 | 1093 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
c019894e | 1094 | dma_dev->max_xor = 8; |
ff7b0479 SB |
1095 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
1096 | } | |
1097 | ||
297eedba | 1098 | mv_chan->mmr_base = xordev->xor_base; |
82a1402e | 1099 | mv_chan->mmr_high_base = xordev->xor_high_base; |
34ca9a53 | 1100 | tasklet_setup(&mv_chan->irq_tasklet, mv_xor_tasklet); |
ff7b0479 SB |
1101 | |
1102 | /* clear errors before enabling interrupts */ | |
0951e728 | 1103 | mv_chan_clear_err_status(mv_chan); |
ff7b0479 | 1104 | |
2d0a0745 TP |
1105 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
1106 | 0, dev_name(&pdev->dev), mv_chan); | |
ff7b0479 SB |
1107 | if (ret) |
1108 | goto err_free_dma; | |
1109 | ||
1110 | mv_chan_unmask_interrupts(mv_chan); | |
1111 | ||
6f166312 | 1112 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
81aafb3e | 1113 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC); |
6f166312 | 1114 | else |
81aafb3e | 1115 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR); |
ff7b0479 SB |
1116 | |
1117 | spin_lock_init(&mv_chan->lock); | |
1118 | INIT_LIST_HEAD(&mv_chan->chain); | |
1119 | INIT_LIST_HEAD(&mv_chan->completed_slots); | |
fbea28a2 LA |
1120 | INIT_LIST_HEAD(&mv_chan->free_slots); |
1121 | INIT_LIST_HEAD(&mv_chan->allocated_slots); | |
98817b99 TP |
1122 | mv_chan->dmachan.device = dma_dev; |
1123 | dma_cookie_init(&mv_chan->dmachan); | |
ff7b0479 | 1124 | |
98817b99 | 1125 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
ff7b0479 SB |
1126 | |
1127 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
0951e728 | 1128 | ret = mv_chan_memcpy_self_test(mv_chan); |
ff7b0479 SB |
1129 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
1130 | if (ret) | |
2d0a0745 | 1131 | goto err_free_irq; |
ff7b0479 SB |
1132 | } |
1133 | ||
1134 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
0951e728 | 1135 | ret = mv_chan_xor_self_test(mv_chan); |
ff7b0479 SB |
1136 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1137 | if (ret) | |
2d0a0745 | 1138 | goto err_free_irq; |
ff7b0479 SB |
1139 | } |
1140 | ||
c678fa66 | 1141 | dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n", |
6f166312 | 1142 | mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode", |
1ba151cd | 1143 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
1ba151cd JP |
1144 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1145 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
ff7b0479 | 1146 | |
7c97381e AP |
1147 | ret = dma_async_device_register(dma_dev); |
1148 | if (ret) | |
1149 | goto err_free_irq; | |
1150 | ||
1ef48a26 | 1151 | return mv_chan; |
ff7b0479 | 1152 | |
2d0a0745 TP |
1153 | err_free_irq: |
1154 | free_irq(mv_chan->irq, mv_chan); | |
a4a1e53d | 1155 | err_free_dma: |
b503fa01 | 1156 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1157 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
a6b4a9d2 | 1158 | return ERR_PTR(ret); |
ff7b0479 SB |
1159 | } |
1160 | ||
1161 | static void | |
297eedba | 1162 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
63a9332b | 1163 | const struct mbus_dram_target_info *dram) |
ff7b0479 | 1164 | { |
82a1402e | 1165 | void __iomem *base = xordev->xor_high_base; |
ff7b0479 SB |
1166 | u32 win_enable = 0; |
1167 | int i; | |
1168 | ||
1169 | for (i = 0; i < 8; i++) { | |
1170 | writel(0, base + WINDOW_BASE(i)); | |
1171 | writel(0, base + WINDOW_SIZE(i)); | |
1172 | if (i < 4) | |
1173 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1174 | } | |
1175 | ||
1176 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 1177 | const struct mbus_dram_window *cs = dram->cs + i; |
ff7b0479 SB |
1178 | |
1179 | writel((cs->base & 0xffff0000) | | |
1180 | (cs->mbus_attr << 8) | | |
1181 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1182 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1183 | ||
77ff7a70 SR |
1184 | /* Fill the caching variables for later use */ |
1185 | xordev->win_start[i] = cs->base; | |
1186 | xordev->win_end[i] = cs->base + cs->size - 1; | |
1187 | ||
ff7b0479 SB |
1188 | win_enable |= (1 << i); |
1189 | win_enable |= 3 << (16 + (2 * i)); | |
1190 | } | |
1191 | ||
1192 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1193 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
c4b4b732 TP |
1194 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
1195 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
ff7b0479 SB |
1196 | } |
1197 | ||
ac5f0f3f MW |
1198 | static void |
1199 | mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev) | |
1200 | { | |
1201 | void __iomem *base = xordev->xor_high_base; | |
1202 | u32 win_enable = 0; | |
1203 | int i; | |
1204 | ||
1205 | for (i = 0; i < 8; i++) { | |
1206 | writel(0, base + WINDOW_BASE(i)); | |
1207 | writel(0, base + WINDOW_SIZE(i)); | |
1208 | if (i < 4) | |
1209 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1210 | } | |
1211 | /* | |
1212 | * For Armada3700 open default 4GB Mbus window. The dram | |
1213 | * related configuration are done at AXIS level. | |
1214 | */ | |
1215 | writel(0xffff0000, base + WINDOW_SIZE(0)); | |
1216 | win_enable |= 1; | |
1217 | win_enable |= 3 << 16; | |
1218 | ||
1219 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1220 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
1221 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); | |
1222 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
1223 | } | |
1224 | ||
8b648436 TP |
1225 | /* |
1226 | * Since this XOR driver is basically used only for RAID5, we don't | |
1227 | * need to care about synchronizing ->suspend with DMA activity, | |
1228 | * because the DMA engine will naturally be quiet due to the block | |
1229 | * devices being suspended. | |
1230 | */ | |
1231 | static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state) | |
1232 | { | |
1233 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); | |
1234 | int i; | |
1235 | ||
1236 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
1237 | struct mv_xor_chan *mv_chan = xordev->channels[i]; | |
1238 | ||
1239 | if (!mv_chan) | |
1240 | continue; | |
1241 | ||
1242 | mv_chan->saved_config_reg = | |
1243 | readl_relaxed(XOR_CONFIG(mv_chan)); | |
1244 | mv_chan->saved_int_mask_reg = | |
1245 | readl_relaxed(XOR_INTR_MASK(mv_chan)); | |
1246 | } | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | static int mv_xor_resume(struct platform_device *dev) | |
1252 | { | |
1253 | struct mv_xor_device *xordev = platform_get_drvdata(dev); | |
1254 | const struct mbus_dram_target_info *dram; | |
1255 | int i; | |
1256 | ||
1257 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
1258 | struct mv_xor_chan *mv_chan = xordev->channels[i]; | |
1259 | ||
1260 | if (!mv_chan) | |
1261 | continue; | |
1262 | ||
1263 | writel_relaxed(mv_chan->saved_config_reg, | |
1264 | XOR_CONFIG(mv_chan)); | |
1265 | writel_relaxed(mv_chan->saved_int_mask_reg, | |
1266 | XOR_INTR_MASK(mv_chan)); | |
1267 | } | |
1268 | ||
ac5f0f3f MW |
1269 | if (xordev->xor_type == XOR_ARMADA_37XX) { |
1270 | mv_xor_conf_mbus_windows_a3700(xordev); | |
1271 | return 0; | |
1272 | } | |
1273 | ||
8b648436 TP |
1274 | dram = mv_mbus_dram_info(); |
1275 | if (dram) | |
1276 | mv_xor_conf_mbus_windows(xordev, dram); | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
6f166312 | 1281 | static const struct of_device_id mv_xor_dt_ids[] = { |
dd130c65 GC |
1282 | { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION }, |
1283 | { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X }, | |
ac5f0f3f | 1284 | { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX }, |
6f166312 LA |
1285 | {}, |
1286 | }; | |
6f166312 | 1287 | |
77757291 | 1288 | static unsigned int mv_xor_engine_count; |
6f166312 | 1289 | |
c2714334 | 1290 | static int mv_xor_probe(struct platform_device *pdev) |
ff7b0479 | 1291 | { |
63a9332b | 1292 | const struct mbus_dram_target_info *dram; |
297eedba | 1293 | struct mv_xor_device *xordev; |
d4adcc01 | 1294 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ff7b0479 | 1295 | struct resource *res; |
77757291 | 1296 | unsigned int max_engines, max_channels; |
60d151f3 | 1297 | int i, ret; |
ff7b0479 | 1298 | |
1ba151cd | 1299 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
ff7b0479 | 1300 | |
297eedba TP |
1301 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
1302 | if (!xordev) | |
ff7b0479 SB |
1303 | return -ENOMEM; |
1304 | ||
1305 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1306 | if (!res) | |
1307 | return -ENODEV; | |
1308 | ||
297eedba TP |
1309 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
1310 | resource_size(res)); | |
1311 | if (!xordev->xor_base) | |
ff7b0479 SB |
1312 | return -EBUSY; |
1313 | ||
1314 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1315 | if (!res) | |
1316 | return -ENODEV; | |
1317 | ||
297eedba TP |
1318 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
1319 | resource_size(res)); | |
1320 | if (!xordev->xor_high_base) | |
ff7b0479 SB |
1321 | return -EBUSY; |
1322 | ||
297eedba | 1323 | platform_set_drvdata(pdev, xordev); |
ff7b0479 | 1324 | |
dd130c65 GC |
1325 | |
1326 | /* | |
1327 | * We need to know which type of XOR device we use before | |
1328 | * setting up. In non-dt case it can only be the legacy one. | |
1329 | */ | |
1330 | xordev->xor_type = XOR_ORION; | |
1331 | if (pdev->dev.of_node) { | |
1332 | const struct of_device_id *of_id = | |
1333 | of_match_device(mv_xor_dt_ids, | |
1334 | &pdev->dev); | |
1335 | ||
1336 | xordev->xor_type = (uintptr_t)of_id->data; | |
1337 | } | |
1338 | ||
ff7b0479 SB |
1339 | /* |
1340 | * (Re-)program MBUS remapping windows if we are asked to. | |
1341 | */ | |
ac5f0f3f MW |
1342 | if (xordev->xor_type == XOR_ARMADA_37XX) { |
1343 | mv_xor_conf_mbus_windows_a3700(xordev); | |
1344 | } else { | |
1345 | dram = mv_mbus_dram_info(); | |
1346 | if (dram) | |
1347 | mv_xor_conf_mbus_windows(xordev, dram); | |
1348 | } | |
ff7b0479 | 1349 | |
c510182b AL |
1350 | /* Not all platforms can gate the clock, so it is not |
1351 | * an error if the clock does not exists. | |
1352 | */ | |
297eedba TP |
1353 | xordev->clk = clk_get(&pdev->dev, NULL); |
1354 | if (!IS_ERR(xordev->clk)) | |
1355 | clk_prepare_enable(xordev->clk); | |
c510182b | 1356 | |
77757291 TP |
1357 | /* |
1358 | * We don't want to have more than one channel per CPU in | |
1359 | * order for async_tx to perform well. So we limit the number | |
1360 | * of engines and channels so that we take into account this | |
1361 | * constraint. Note that we also want to use channels from | |
ac5f0f3f MW |
1362 | * separate engines when possible. For dual-CPU Armada 3700 |
1363 | * SoC with single XOR engine allow using its both channels. | |
77757291 TP |
1364 | */ |
1365 | max_engines = num_present_cpus(); | |
ac5f0f3f MW |
1366 | if (xordev->xor_type == XOR_ARMADA_37XX) |
1367 | max_channels = num_present_cpus(); | |
1368 | else | |
1369 | max_channels = min_t(unsigned int, | |
1370 | MV_XOR_MAX_CHANNELS, | |
1371 | DIV_ROUND_UP(num_present_cpus(), 2)); | |
77757291 TP |
1372 | |
1373 | if (mv_xor_engine_count >= max_engines) | |
1374 | return 0; | |
1375 | ||
f7d12ef5 TP |
1376 | if (pdev->dev.of_node) { |
1377 | struct device_node *np; | |
1378 | int i = 0; | |
1379 | ||
1380 | for_each_child_of_node(pdev->dev.of_node, np) { | |
0be8253f | 1381 | struct mv_xor_chan *chan; |
f7d12ef5 TP |
1382 | dma_cap_mask_t cap_mask; |
1383 | int irq; | |
1384 | ||
77757291 TP |
1385 | if (i >= max_channels) |
1386 | continue; | |
1387 | ||
f7d12ef5 | 1388 | dma_cap_zero(cap_mask); |
6d8f7abd TP |
1389 | dma_cap_set(DMA_MEMCPY, cap_mask); |
1390 | dma_cap_set(DMA_XOR, cap_mask); | |
1391 | dma_cap_set(DMA_INTERRUPT, cap_mask); | |
f7d12ef5 TP |
1392 | |
1393 | irq = irq_of_parse_and_map(np, 0); | |
f8eb9e7d TP |
1394 | if (!irq) { |
1395 | ret = -ENODEV; | |
f7d12ef5 TP |
1396 | goto err_channel_add; |
1397 | } | |
1398 | ||
0be8253f | 1399 | chan = mv_xor_channel_add(xordev, pdev, i, |
dd130c65 | 1400 | cap_mask, irq); |
0be8253f RK |
1401 | if (IS_ERR(chan)) { |
1402 | ret = PTR_ERR(chan); | |
f7d12ef5 TP |
1403 | irq_dispose_mapping(irq); |
1404 | goto err_channel_add; | |
1405 | } | |
1406 | ||
0be8253f | 1407 | xordev->channels[i] = chan; |
f7d12ef5 TP |
1408 | i++; |
1409 | } | |
1410 | } else if (pdata && pdata->channels) { | |
77757291 | 1411 | for (i = 0; i < max_channels; i++) { |
e39f6ec1 | 1412 | struct mv_xor_channel_data *cd; |
0be8253f | 1413 | struct mv_xor_chan *chan; |
60d151f3 TP |
1414 | int irq; |
1415 | ||
1416 | cd = &pdata->channels[i]; | |
60d151f3 TP |
1417 | irq = platform_get_irq(pdev, i); |
1418 | if (irq < 0) { | |
1419 | ret = irq; | |
1420 | goto err_channel_add; | |
1421 | } | |
1422 | ||
0be8253f | 1423 | chan = mv_xor_channel_add(xordev, pdev, i, |
dd130c65 | 1424 | cd->cap_mask, irq); |
0be8253f RK |
1425 | if (IS_ERR(chan)) { |
1426 | ret = PTR_ERR(chan); | |
60d151f3 TP |
1427 | goto err_channel_add; |
1428 | } | |
0be8253f RK |
1429 | |
1430 | xordev->channels[i] = chan; | |
60d151f3 TP |
1431 | } |
1432 | } | |
c510182b | 1433 | |
ff7b0479 | 1434 | return 0; |
60d151f3 TP |
1435 | |
1436 | err_channel_add: | |
1437 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) | |
f7d12ef5 | 1438 | if (xordev->channels[i]) { |
ab6e439f | 1439 | mv_xor_channel_remove(xordev->channels[i]); |
f7d12ef5 TP |
1440 | if (pdev->dev.of_node) |
1441 | irq_dispose_mapping(xordev->channels[i]->irq); | |
f7d12ef5 | 1442 | } |
60d151f3 | 1443 | |
dab92064 TP |
1444 | if (!IS_ERR(xordev->clk)) { |
1445 | clk_disable_unprepare(xordev->clk); | |
1446 | clk_put(xordev->clk); | |
1447 | } | |
1448 | ||
60d151f3 | 1449 | return ret; |
ff7b0479 SB |
1450 | } |
1451 | ||
61971656 TP |
1452 | static struct platform_driver mv_xor_driver = { |
1453 | .probe = mv_xor_probe, | |
8b648436 TP |
1454 | .suspend = mv_xor_suspend, |
1455 | .resume = mv_xor_resume, | |
ff7b0479 | 1456 | .driver = { |
f7d12ef5 | 1457 | .name = MV_XOR_NAME, |
890bcd49 | 1458 | .of_match_table = mv_xor_dt_ids, |
ff7b0479 SB |
1459 | }, |
1460 | }; | |
1461 | ||
812608d1 | 1462 | builtin_platform_driver(mv_xor_driver); |
ff7b0479 | 1463 | |
25cf68da | 1464 | /* |
ff7b0479 SB |
1465 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
1466 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); | |
1467 | MODULE_LICENSE("GPL"); | |
25cf68da | 1468 | */ |