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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c2110923 DW |
2 | /* |
3 | * offload engine driver for the Intel Xscale series of i/o processors | |
4 | * Copyright © 2006, Intel Corporation. | |
c2110923 DW |
5 | */ |
6 | ||
7 | /* | |
8 | * This driver supports the asynchrounous DMA copy and RAID engines available | |
9 | * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x) | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
c2110923 DW |
14 | #include <linux/delay.h> |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
7f8bf11a | 19 | #include <linux/prefetch.h> |
c2110923 DW |
20 | #include <linux/memory.h> |
21 | #include <linux/ioport.h> | |
f6dbf651 | 22 | #include <linux/raid/pq.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
c2110923 | 24 | |
aad7ad2a | 25 | #include "iop-adma.h" |
d2ebfb33 RKAL |
26 | #include "dmaengine.h" |
27 | ||
c2110923 DW |
28 | #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) |
29 | #define to_iop_adma_device(dev) \ | |
30 | container_of(dev, struct iop_adma_device, common) | |
31 | #define tx_to_iop_adma_slot(tx) \ | |
32 | container_of(tx, struct iop_adma_desc_slot, async_tx) | |
33 | ||
34 | /** | |
35 | * iop_adma_free_slots - flags descriptor slots for reuse | |
36 | * @slot: Slot to free | |
37 | * Caller must hold &iop_chan->lock while calling this function | |
38 | */ | |
39 | static void iop_adma_free_slots(struct iop_adma_desc_slot *slot) | |
40 | { | |
41 | int stride = slot->slots_per_op; | |
42 | ||
43 | while (stride--) { | |
44 | slot->slots_per_op = 0; | |
45 | slot = list_entry(slot->slot_node.next, | |
46 | struct iop_adma_desc_slot, | |
47 | slot_node); | |
48 | } | |
49 | } | |
50 | ||
51 | static dma_cookie_t | |
52 | iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, | |
53 | struct iop_adma_chan *iop_chan, dma_cookie_t cookie) | |
54 | { | |
507fbec4 DW |
55 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
56 | ||
57 | BUG_ON(tx->cookie < 0); | |
58 | if (tx->cookie > 0) { | |
59 | cookie = tx->cookie; | |
60 | tx->cookie = 0; | |
c2110923 DW |
61 | |
62 | /* call the callback (must not sleep or submit new | |
63 | * operations to this channel) | |
64 | */ | |
db89e3c8 | 65 | dmaengine_desc_get_callback_invoke(tx, NULL); |
c2110923 | 66 | |
d38a8c62 | 67 | dma_descriptor_unmap(tx); |
54f8d501 BZ |
68 | if (desc->group_head) |
69 | desc->group_head = NULL; | |
c2110923 DW |
70 | } |
71 | ||
72 | /* run dependent operations */ | |
507fbec4 | 73 | dma_run_dependencies(tx); |
c2110923 DW |
74 | |
75 | return cookie; | |
76 | } | |
77 | ||
78 | static int | |
79 | iop_adma_clean_slot(struct iop_adma_desc_slot *desc, | |
80 | struct iop_adma_chan *iop_chan) | |
81 | { | |
82 | /* the client is allowed to attach dependent operations | |
83 | * until 'ack' is set | |
84 | */ | |
636bdeaa | 85 | if (!async_tx_test_ack(&desc->async_tx)) |
c2110923 DW |
86 | return 0; |
87 | ||
88 | /* leave the last descriptor in the chain | |
89 | * so we can append to it | |
90 | */ | |
91 | if (desc->chain_node.next == &iop_chan->chain) | |
92 | return 1; | |
93 | ||
94 | dev_dbg(iop_chan->device->common.dev, | |
95 | "\tfree slot: %d slots_per_op: %d\n", | |
96 | desc->idx, desc->slots_per_op); | |
97 | ||
98 | list_del(&desc->chain_node); | |
99 | iop_adma_free_slots(desc); | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
104 | static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |
105 | { | |
106 | struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL; | |
107 | dma_cookie_t cookie = 0; | |
108 | u32 current_desc = iop_chan_get_current_descriptor(iop_chan); | |
109 | int busy = iop_chan_is_busy(iop_chan); | |
110 | int seen_current = 0, slot_cnt = 0, slots_per_op = 0; | |
111 | ||
3d9b525b | 112 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
113 | /* free completed slots from the chain starting with |
114 | * the oldest descriptor | |
115 | */ | |
116 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, | |
117 | chain_node) { | |
118 | pr_debug("\tcookie: %d slot: %d busy: %d " | |
04cbfba6 | 119 | "this_desc: %pad next_desc: %#llx ack: %d\n", |
c2110923 | 120 | iter->async_tx.cookie, iter->idx, busy, |
04cbfba6 | 121 | &iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter), |
636bdeaa | 122 | async_tx_test_ack(&iter->async_tx)); |
c2110923 DW |
123 | prefetch(_iter); |
124 | prefetch(&_iter->async_tx); | |
125 | ||
126 | /* do not advance past the current descriptor loaded into the | |
127 | * hardware channel, subsequent descriptors are either in | |
128 | * process or have not been submitted | |
129 | */ | |
130 | if (seen_current) | |
131 | break; | |
132 | ||
133 | /* stop the search if we reach the current descriptor and the | |
134 | * channel is busy, or if it appears that the current descriptor | |
135 | * needs to be re-read (i.e. has been appended to) | |
136 | */ | |
137 | if (iter->async_tx.phys == current_desc) { | |
138 | BUG_ON(seen_current++); | |
139 | if (busy || iop_desc_get_next_desc(iter)) | |
140 | break; | |
141 | } | |
142 | ||
143 | /* detect the start of a group transaction */ | |
144 | if (!slot_cnt && !slots_per_op) { | |
145 | slot_cnt = iter->slot_cnt; | |
146 | slots_per_op = iter->slots_per_op; | |
147 | if (slot_cnt <= slots_per_op) { | |
148 | slot_cnt = 0; | |
149 | slots_per_op = 0; | |
150 | } | |
151 | } | |
152 | ||
153 | if (slot_cnt) { | |
154 | pr_debug("\tgroup++\n"); | |
155 | if (!grp_start) | |
156 | grp_start = iter; | |
157 | slot_cnt -= slots_per_op; | |
158 | } | |
159 | ||
160 | /* all the members of a group are complete */ | |
161 | if (slots_per_op != 0 && slot_cnt == 0) { | |
162 | struct iop_adma_desc_slot *grp_iter, *_grp_iter; | |
163 | int end_of_chain = 0; | |
164 | pr_debug("\tgroup end\n"); | |
165 | ||
166 | /* collect the total results */ | |
167 | if (grp_start->xor_check_result) { | |
168 | u32 zero_sum_result = 0; | |
169 | slot_cnt = grp_start->slot_cnt; | |
170 | grp_iter = grp_start; | |
171 | ||
172 | list_for_each_entry_from(grp_iter, | |
173 | &iop_chan->chain, chain_node) { | |
174 | zero_sum_result |= | |
175 | iop_desc_get_zero_result(grp_iter); | |
051f5175 | 176 | pr_debug("\titer%d result: %d\n", |
c2110923 DW |
177 | grp_iter->idx, zero_sum_result); |
178 | slot_cnt -= slots_per_op; | |
179 | if (slot_cnt == 0) | |
180 | break; | |
181 | } | |
182 | pr_debug("\tgrp_start->xor_check_result: %p\n", | |
183 | grp_start->xor_check_result); | |
184 | *grp_start->xor_check_result = zero_sum_result; | |
185 | } | |
186 | ||
187 | /* clean up the group */ | |
188 | slot_cnt = grp_start->slot_cnt; | |
189 | grp_iter = grp_start; | |
190 | list_for_each_entry_safe_from(grp_iter, _grp_iter, | |
191 | &iop_chan->chain, chain_node) { | |
192 | cookie = iop_adma_run_tx_complete_actions( | |
193 | grp_iter, iop_chan, cookie); | |
194 | ||
195 | slot_cnt -= slots_per_op; | |
196 | end_of_chain = iop_adma_clean_slot(grp_iter, | |
197 | iop_chan); | |
198 | ||
199 | if (slot_cnt == 0 || end_of_chain) | |
200 | break; | |
201 | } | |
202 | ||
203 | /* the group should be complete at this point */ | |
204 | BUG_ON(slot_cnt); | |
205 | ||
206 | slots_per_op = 0; | |
207 | grp_start = NULL; | |
208 | if (end_of_chain) | |
209 | break; | |
210 | else | |
211 | continue; | |
212 | } else if (slots_per_op) /* wait for group completion */ | |
213 | continue; | |
214 | ||
215 | /* write back zero sum results (single descriptor case) */ | |
216 | if (iter->xor_check_result && iter->async_tx.cookie) | |
217 | *iter->xor_check_result = | |
218 | iop_desc_get_zero_result(iter); | |
219 | ||
220 | cookie = iop_adma_run_tx_complete_actions( | |
221 | iter, iop_chan, cookie); | |
222 | ||
223 | if (iop_adma_clean_slot(iter, iop_chan)) | |
224 | break; | |
225 | } | |
226 | ||
c2110923 | 227 | if (cookie > 0) { |
4d4e58de | 228 | iop_chan->common.completed_cookie = cookie; |
c2110923 DW |
229 | pr_debug("\tcompleted cookie %d\n", cookie); |
230 | } | |
231 | } | |
232 | ||
233 | static void | |
234 | iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |
235 | { | |
236 | spin_lock_bh(&iop_chan->lock); | |
237 | __iop_adma_slot_cleanup(iop_chan); | |
238 | spin_unlock_bh(&iop_chan->lock); | |
239 | } | |
240 | ||
5bbb671f | 241 | static void iop_adma_tasklet(struct tasklet_struct *t) |
c2110923 | 242 | { |
5bbb671f AP |
243 | struct iop_adma_chan *iop_chan = from_tasklet(iop_chan, t, |
244 | irq_tasklet); | |
19242d72 | 245 | |
72be12f0 DW |
246 | /* lockdep will flag depedency submissions as potentially |
247 | * recursive locking, this is not the case as a dependency | |
248 | * submission will never recurse a channels submit routine. | |
249 | * There are checks in async_tx.c to prevent this. | |
250 | */ | |
251 | spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING); | |
19242d72 DW |
252 | __iop_adma_slot_cleanup(iop_chan); |
253 | spin_unlock(&iop_chan->lock); | |
c2110923 DW |
254 | } |
255 | ||
256 | static struct iop_adma_desc_slot * | |
257 | iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots, | |
258 | int slots_per_op) | |
259 | { | |
260 | struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL; | |
e73ef9ac | 261 | LIST_HEAD(chain); |
c2110923 DW |
262 | int slots_found, retry = 0; |
263 | ||
264 | /* start search from the last allocated descrtiptor | |
265 | * if a contiguous allocation can not be found start searching | |
266 | * from the beginning of the list | |
267 | */ | |
268 | retry: | |
269 | slots_found = 0; | |
270 | if (retry == 0) | |
271 | iter = iop_chan->last_used; | |
272 | else | |
273 | iter = list_entry(&iop_chan->all_slots, | |
274 | struct iop_adma_desc_slot, | |
275 | slot_node); | |
276 | ||
277 | list_for_each_entry_safe_continue( | |
278 | iter, _iter, &iop_chan->all_slots, slot_node) { | |
279 | prefetch(_iter); | |
280 | prefetch(&_iter->async_tx); | |
281 | if (iter->slots_per_op) { | |
282 | /* give up after finding the first busy slot | |
283 | * on the second pass through the list | |
284 | */ | |
285 | if (retry) | |
286 | break; | |
287 | ||
288 | slots_found = 0; | |
289 | continue; | |
290 | } | |
291 | ||
292 | /* start the allocation if the slot is correctly aligned */ | |
293 | if (!slots_found++) { | |
294 | if (iop_desc_is_aligned(iter, slots_per_op)) | |
295 | alloc_start = iter; | |
296 | else { | |
297 | slots_found = 0; | |
298 | continue; | |
299 | } | |
300 | } | |
301 | ||
302 | if (slots_found == num_slots) { | |
303 | struct iop_adma_desc_slot *alloc_tail = NULL; | |
304 | struct iop_adma_desc_slot *last_used = NULL; | |
305 | iter = alloc_start; | |
306 | while (num_slots) { | |
307 | int i; | |
308 | dev_dbg(iop_chan->device->common.dev, | |
309 | "allocated slot: %d " | |
00c97555 | 310 | "(desc %p phys: %#llx) slots_per_op %d\n", |
c2110923 | 311 | iter->idx, iter->hw_desc, |
00c97555 | 312 | (u64)iter->async_tx.phys, slots_per_op); |
c2110923 DW |
313 | |
314 | /* pre-ack all but the last descriptor */ | |
315 | if (num_slots != slots_per_op) | |
636bdeaa | 316 | async_tx_ack(&iter->async_tx); |
c2110923 DW |
317 | |
318 | list_add_tail(&iter->chain_node, &chain); | |
319 | alloc_tail = iter; | |
320 | iter->async_tx.cookie = 0; | |
321 | iter->slot_cnt = num_slots; | |
322 | iter->xor_check_result = NULL; | |
323 | for (i = 0; i < slots_per_op; i++) { | |
324 | iter->slots_per_op = slots_per_op - i; | |
325 | last_used = iter; | |
326 | iter = list_entry(iter->slot_node.next, | |
327 | struct iop_adma_desc_slot, | |
328 | slot_node); | |
329 | } | |
330 | num_slots -= slots_per_op; | |
331 | } | |
332 | alloc_tail->group_head = alloc_start; | |
333 | alloc_tail->async_tx.cookie = -EBUSY; | |
308136d1 | 334 | list_splice(&chain, &alloc_tail->tx_list); |
c2110923 DW |
335 | iop_chan->last_used = last_used; |
336 | iop_desc_clear_next_desc(alloc_start); | |
337 | iop_desc_clear_next_desc(alloc_tail); | |
338 | return alloc_tail; | |
339 | } | |
340 | } | |
341 | if (!retry++) | |
342 | goto retry; | |
343 | ||
c7141d00 DW |
344 | /* perform direct reclaim if the allocation fails */ |
345 | __iop_adma_slot_cleanup(iop_chan); | |
c2110923 DW |
346 | |
347 | return NULL; | |
348 | } | |
349 | ||
c2110923 DW |
350 | static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan) |
351 | { | |
352 | dev_dbg(iop_chan->device->common.dev, "pending: %d\n", | |
353 | iop_chan->pending); | |
354 | ||
355 | if (iop_chan->pending >= IOP_ADMA_THRESHOLD) { | |
356 | iop_chan->pending = 0; | |
357 | iop_chan_append(iop_chan); | |
358 | } | |
359 | } | |
360 | ||
361 | static dma_cookie_t | |
362 | iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) | |
363 | { | |
364 | struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx); | |
365 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan); | |
366 | struct iop_adma_desc_slot *grp_start, *old_chain_tail; | |
367 | int slot_cnt; | |
c2110923 | 368 | dma_cookie_t cookie; |
137cb55c | 369 | dma_addr_t next_dma; |
c2110923 DW |
370 | |
371 | grp_start = sw_desc->group_head; | |
372 | slot_cnt = grp_start->slot_cnt; | |
c2110923 DW |
373 | |
374 | spin_lock_bh(&iop_chan->lock); | |
884485e1 | 375 | cookie = dma_cookie_assign(tx); |
c2110923 DW |
376 | |
377 | old_chain_tail = list_entry(iop_chan->chain.prev, | |
378 | struct iop_adma_desc_slot, chain_node); | |
308136d1 | 379 | list_splice_init(&sw_desc->tx_list, |
c2110923 DW |
380 | &old_chain_tail->chain_node); |
381 | ||
382 | /* fix up the hardware chain */ | |
137cb55c DW |
383 | next_dma = grp_start->async_tx.phys; |
384 | iop_desc_set_next_desc(old_chain_tail, next_dma); | |
385 | BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */ | |
c2110923 | 386 | |
137cb55c | 387 | /* check for pre-chained descriptors */ |
65e50381 | 388 | iop_paranoia(iop_desc_get_next_desc(sw_desc)); |
c2110923 DW |
389 | |
390 | /* increment the pending count by the number of slots | |
391 | * memcpy operations have a 1:1 (slot:operation) relation | |
392 | * other operations are heavier and will pop the threshold | |
393 | * more often. | |
394 | */ | |
395 | iop_chan->pending += slot_cnt; | |
396 | iop_adma_check_threshold(iop_chan); | |
397 | spin_unlock_bh(&iop_chan->lock); | |
398 | ||
399 | dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n", | |
3d9b525b | 400 | __func__, sw_desc->async_tx.cookie, sw_desc->idx); |
c2110923 DW |
401 | |
402 | return cookie; | |
403 | } | |
404 | ||
c2110923 DW |
405 | static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan); |
406 | static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan); | |
407 | ||
5eb907aa DW |
408 | /** |
409 | * iop_adma_alloc_chan_resources - returns the number of allocated descriptors | |
1c5933c5 | 410 | * @chan: allocate descriptor resources for this channel |
5eb907aa DW |
411 | * |
412 | * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To | |
413 | * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be | |
414 | * greater than 2x the number slots needed to satisfy a device->max_xor | |
415 | * request. | |
416 | * */ | |
aa1e6f1a | 417 | static int iop_adma_alloc_chan_resources(struct dma_chan *chan) |
c2110923 DW |
418 | { |
419 | char *hw_desc; | |
985d5137 | 420 | dma_addr_t dma_desc; |
c2110923 DW |
421 | int idx; |
422 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
423 | struct iop_adma_desc_slot *slot = NULL; | |
424 | int init = iop_chan->slots_allocated ? 0 : 1; | |
425 | struct iop_adma_platform_data *plat_data = | |
d4adcc01 | 426 | dev_get_platdata(&iop_chan->device->pdev->dev); |
c2110923 DW |
427 | int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE; |
428 | ||
429 | /* Allocate descriptor slots */ | |
430 | do { | |
431 | idx = iop_chan->slots_allocated; | |
432 | if (idx == num_descs_in_pool) | |
433 | break; | |
434 | ||
435 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
436 | if (!slot) { | |
437 | printk(KERN_INFO "IOP ADMA Channel only initialized" | |
438 | " %d descriptor slots", idx); | |
439 | break; | |
440 | } | |
441 | hw_desc = (char *) iop_chan->device->dma_desc_pool_virt; | |
442 | slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; | |
443 | ||
444 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
445 | slot->async_tx.tx_submit = iop_adma_tx_submit; | |
308136d1 | 446 | INIT_LIST_HEAD(&slot->tx_list); |
c2110923 DW |
447 | INIT_LIST_HEAD(&slot->chain_node); |
448 | INIT_LIST_HEAD(&slot->slot_node); | |
985d5137 Y |
449 | dma_desc = iop_chan->device->dma_desc_pool; |
450 | slot->async_tx.phys = dma_desc + idx * IOP_ADMA_SLOT_SIZE; | |
c2110923 DW |
451 | slot->idx = idx; |
452 | ||
453 | spin_lock_bh(&iop_chan->lock); | |
454 | iop_chan->slots_allocated++; | |
455 | list_add_tail(&slot->slot_node, &iop_chan->all_slots); | |
456 | spin_unlock_bh(&iop_chan->lock); | |
457 | } while (iop_chan->slots_allocated < num_descs_in_pool); | |
458 | ||
459 | if (idx && !iop_chan->last_used) | |
460 | iop_chan->last_used = list_entry(iop_chan->all_slots.next, | |
461 | struct iop_adma_desc_slot, | |
462 | slot_node); | |
463 | ||
464 | dev_dbg(iop_chan->device->common.dev, | |
465 | "allocated %d descriptor slots last_used: %p\n", | |
466 | iop_chan->slots_allocated, iop_chan->last_used); | |
467 | ||
468 | /* initialize the channel and the chain with a null operation */ | |
469 | if (init) { | |
470 | if (dma_has_cap(DMA_MEMCPY, | |
471 | iop_chan->device->common.cap_mask)) | |
472 | iop_chan_start_null_memcpy(iop_chan); | |
473 | else if (dma_has_cap(DMA_XOR, | |
474 | iop_chan->device->common.cap_mask)) | |
475 | iop_chan_start_null_xor(iop_chan); | |
476 | else | |
477 | BUG(); | |
478 | } | |
479 | ||
480 | return (idx > 0) ? idx : -ENOMEM; | |
481 | } | |
482 | ||
483 | static struct dma_async_tx_descriptor * | |
636bdeaa | 484 | iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
c2110923 DW |
485 | { |
486 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
487 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
488 | int slot_cnt, slots_per_op; | |
489 | ||
3d9b525b | 490 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
491 | |
492 | spin_lock_bh(&iop_chan->lock); | |
493 | slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan); | |
494 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
495 | if (sw_desc) { | |
496 | grp_start = sw_desc->group_head; | |
497 | iop_desc_init_interrupt(grp_start, iop_chan); | |
636bdeaa | 498 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
499 | } |
500 | spin_unlock_bh(&iop_chan->lock); | |
501 | ||
502 | return sw_desc ? &sw_desc->async_tx : NULL; | |
503 | } | |
504 | ||
c2110923 | 505 | static struct dma_async_tx_descriptor * |
0036731c | 506 | iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, |
d4c56f97 | 507 | dma_addr_t dma_src, size_t len, unsigned long flags) |
c2110923 DW |
508 | { |
509 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
510 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
511 | int slot_cnt, slots_per_op; | |
512 | ||
513 | if (unlikely(!len)) | |
514 | return NULL; | |
e2ec771a | 515 | BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT); |
c2110923 | 516 | |
00c97555 | 517 | dev_dbg(iop_chan->device->common.dev, "%s len: %zu\n", |
3d9b525b | 518 | __func__, len); |
c2110923 DW |
519 | |
520 | spin_lock_bh(&iop_chan->lock); | |
521 | slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op); | |
522 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
523 | if (sw_desc) { | |
524 | grp_start = sw_desc->group_head; | |
d4c56f97 | 525 | iop_desc_init_memcpy(grp_start, flags); |
c2110923 | 526 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c DW |
527 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
528 | iop_desc_set_memcpy_src_addr(grp_start, dma_src); | |
636bdeaa | 529 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
530 | } |
531 | spin_unlock_bh(&iop_chan->lock); | |
532 | ||
533 | return sw_desc ? &sw_desc->async_tx : NULL; | |
534 | } | |
535 | ||
c2110923 | 536 | static struct dma_async_tx_descriptor * |
0036731c DW |
537 | iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, |
538 | dma_addr_t *dma_src, unsigned int src_cnt, size_t len, | |
d4c56f97 | 539 | unsigned long flags) |
c2110923 DW |
540 | { |
541 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
542 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
543 | int slot_cnt, slots_per_op; | |
544 | ||
545 | if (unlikely(!len)) | |
546 | return NULL; | |
e2ec771a | 547 | BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); |
c2110923 DW |
548 | |
549 | dev_dbg(iop_chan->device->common.dev, | |
00c97555 | 550 | "%s src_cnt: %d len: %zu flags: %lx\n", |
3d9b525b | 551 | __func__, src_cnt, len, flags); |
c2110923 DW |
552 | |
553 | spin_lock_bh(&iop_chan->lock); | |
554 | slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op); | |
555 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
556 | if (sw_desc) { | |
557 | grp_start = sw_desc->group_head; | |
d4c56f97 | 558 | iop_desc_init_xor(grp_start, src_cnt, flags); |
c2110923 | 559 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c | 560 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
636bdeaa | 561 | sw_desc->async_tx.flags = flags; |
0036731c DW |
562 | while (src_cnt--) |
563 | iop_desc_set_xor_src_addr(grp_start, src_cnt, | |
564 | dma_src[src_cnt]); | |
c2110923 DW |
565 | } |
566 | spin_unlock_bh(&iop_chan->lock); | |
567 | ||
568 | return sw_desc ? &sw_desc->async_tx : NULL; | |
569 | } | |
570 | ||
c2110923 | 571 | static struct dma_async_tx_descriptor * |
099f53cb DW |
572 | iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, |
573 | unsigned int src_cnt, size_t len, u32 *result, | |
574 | unsigned long flags) | |
c2110923 DW |
575 | { |
576 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
577 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
578 | int slot_cnt, slots_per_op; | |
579 | ||
580 | if (unlikely(!len)) | |
581 | return NULL; | |
582 | ||
00c97555 | 583 | dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n", |
3d9b525b | 584 | __func__, src_cnt, len); |
c2110923 DW |
585 | |
586 | spin_lock_bh(&iop_chan->lock); | |
587 | slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op); | |
588 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
589 | if (sw_desc) { | |
590 | grp_start = sw_desc->group_head; | |
d4c56f97 | 591 | iop_desc_init_zero_sum(grp_start, src_cnt, flags); |
c2110923 DW |
592 | iop_desc_set_zero_sum_byte_count(grp_start, len); |
593 | grp_start->xor_check_result = result; | |
594 | pr_debug("\t%s: grp_start->xor_check_result: %p\n", | |
3d9b525b | 595 | __func__, grp_start->xor_check_result); |
636bdeaa | 596 | sw_desc->async_tx.flags = flags; |
0036731c DW |
597 | while (src_cnt--) |
598 | iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, | |
599 | dma_src[src_cnt]); | |
c2110923 DW |
600 | } |
601 | spin_unlock_bh(&iop_chan->lock); | |
602 | ||
603 | return sw_desc ? &sw_desc->async_tx : NULL; | |
604 | } | |
605 | ||
7bf649ae DW |
606 | static struct dma_async_tx_descriptor * |
607 | iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
608 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
609 | unsigned long flags) | |
610 | { | |
611 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
612 | struct iop_adma_desc_slot *sw_desc, *g; | |
613 | int slot_cnt, slots_per_op; | |
614 | int continue_srcs; | |
615 | ||
616 | if (unlikely(!len)) | |
617 | return NULL; | |
618 | BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); | |
619 | ||
620 | dev_dbg(iop_chan->device->common.dev, | |
00c97555 | 621 | "%s src_cnt: %d len: %zu flags: %lx\n", |
7bf649ae DW |
622 | __func__, src_cnt, len, flags); |
623 | ||
624 | if (dmaf_p_disabled_continue(flags)) | |
625 | continue_srcs = 1+src_cnt; | |
626 | else if (dmaf_continue(flags)) | |
627 | continue_srcs = 3+src_cnt; | |
628 | else | |
629 | continue_srcs = 0+src_cnt; | |
630 | ||
631 | spin_lock_bh(&iop_chan->lock); | |
632 | slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op); | |
633 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
634 | if (sw_desc) { | |
635 | int i; | |
636 | ||
637 | g = sw_desc->group_head; | |
638 | iop_desc_set_byte_count(g, iop_chan, len); | |
639 | ||
640 | /* even if P is disabled its destination address (bits | |
641 | * [3:0]) must match Q. It is ok if P points to an | |
642 | * invalid address, it won't be written. | |
643 | */ | |
644 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
645 | dst[0] = dst[1] & 0x7; | |
646 | ||
647 | iop_desc_set_pq_addr(g, dst); | |
7bf649ae DW |
648 | sw_desc->async_tx.flags = flags; |
649 | for (i = 0; i < src_cnt; i++) | |
650 | iop_desc_set_pq_src_addr(g, i, src[i], scf[i]); | |
651 | ||
652 | /* if we are continuing a previous operation factor in | |
653 | * the old p and q values, see the comment for dma_maxpq | |
654 | * in include/linux/dmaengine.h | |
655 | */ | |
656 | if (dmaf_p_disabled_continue(flags)) | |
657 | iop_desc_set_pq_src_addr(g, i++, dst[1], 1); | |
658 | else if (dmaf_continue(flags)) { | |
659 | iop_desc_set_pq_src_addr(g, i++, dst[0], 0); | |
660 | iop_desc_set_pq_src_addr(g, i++, dst[1], 1); | |
661 | iop_desc_set_pq_src_addr(g, i++, dst[1], 0); | |
662 | } | |
663 | iop_desc_init_pq(g, i, flags); | |
664 | } | |
665 | spin_unlock_bh(&iop_chan->lock); | |
666 | ||
667 | return sw_desc ? &sw_desc->async_tx : NULL; | |
668 | } | |
669 | ||
670 | static struct dma_async_tx_descriptor * | |
671 | iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
672 | unsigned int src_cnt, const unsigned char *scf, | |
673 | size_t len, enum sum_check_flags *pqres, | |
674 | unsigned long flags) | |
675 | { | |
676 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
677 | struct iop_adma_desc_slot *sw_desc, *g; | |
678 | int slot_cnt, slots_per_op; | |
679 | ||
680 | if (unlikely(!len)) | |
681 | return NULL; | |
682 | BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); | |
683 | ||
00c97555 | 684 | dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n", |
7bf649ae DW |
685 | __func__, src_cnt, len); |
686 | ||
687 | spin_lock_bh(&iop_chan->lock); | |
688 | slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op); | |
689 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
690 | if (sw_desc) { | |
691 | /* for validate operations p and q are tagged onto the | |
692 | * end of the source list | |
693 | */ | |
694 | int pq_idx = src_cnt; | |
695 | ||
696 | g = sw_desc->group_head; | |
697 | iop_desc_init_pq_zero_sum(g, src_cnt+2, flags); | |
698 | iop_desc_set_pq_zero_sum_byte_count(g, len); | |
699 | g->pq_check_result = pqres; | |
700 | pr_debug("\t%s: g->pq_check_result: %p\n", | |
701 | __func__, g->pq_check_result); | |
7bf649ae DW |
702 | sw_desc->async_tx.flags = flags; |
703 | while (src_cnt--) | |
704 | iop_desc_set_pq_zero_sum_src_addr(g, src_cnt, | |
705 | src[src_cnt], | |
706 | scf[src_cnt]); | |
707 | iop_desc_set_pq_zero_sum_addr(g, pq_idx, src); | |
708 | } | |
709 | spin_unlock_bh(&iop_chan->lock); | |
710 | ||
711 | return sw_desc ? &sw_desc->async_tx : NULL; | |
712 | } | |
713 | ||
c2110923 DW |
714 | static void iop_adma_free_chan_resources(struct dma_chan *chan) |
715 | { | |
716 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
717 | struct iop_adma_desc_slot *iter, *_iter; | |
718 | int in_use_descs = 0; | |
719 | ||
720 | iop_adma_slot_cleanup(iop_chan); | |
721 | ||
722 | spin_lock_bh(&iop_chan->lock); | |
723 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, | |
724 | chain_node) { | |
725 | in_use_descs++; | |
726 | list_del(&iter->chain_node); | |
727 | } | |
728 | list_for_each_entry_safe_reverse( | |
729 | iter, _iter, &iop_chan->all_slots, slot_node) { | |
730 | list_del(&iter->slot_node); | |
731 | kfree(iter); | |
732 | iop_chan->slots_allocated--; | |
733 | } | |
734 | iop_chan->last_used = NULL; | |
735 | ||
736 | dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n", | |
3d9b525b | 737 | __func__, iop_chan->slots_allocated); |
c2110923 DW |
738 | spin_unlock_bh(&iop_chan->lock); |
739 | ||
740 | /* one is ok since we left it on there on purpose */ | |
741 | if (in_use_descs > 1) | |
742 | printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n", | |
743 | in_use_descs - 1); | |
744 | } | |
745 | ||
746 | /** | |
07934481 | 747 | * iop_adma_status - poll the status of an ADMA transaction |
c2110923 DW |
748 | * @chan: ADMA channel handle |
749 | * @cookie: ADMA transaction identifier | |
07934481 | 750 | * @txstate: a holder for the current state of the channel or NULL |
c2110923 | 751 | */ |
07934481 | 752 | static enum dma_status iop_adma_status(struct dma_chan *chan, |
c2110923 | 753 | dma_cookie_t cookie, |
07934481 | 754 | struct dma_tx_state *txstate) |
c2110923 DW |
755 | { |
756 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
949ff5b8 | 757 | int ret; |
96a2af41 RKAL |
758 | |
759 | ret = dma_cookie_status(chan, cookie, txstate); | |
9f571502 | 760 | if (ret == DMA_COMPLETE) |
c2110923 DW |
761 | return ret; |
762 | ||
763 | iop_adma_slot_cleanup(iop_chan); | |
764 | ||
96a2af41 | 765 | return dma_cookie_status(chan, cookie, txstate); |
c2110923 DW |
766 | } |
767 | ||
768 | static irqreturn_t iop_adma_eot_handler(int irq, void *data) | |
769 | { | |
770 | struct iop_adma_chan *chan = data; | |
771 | ||
3d9b525b | 772 | dev_dbg(chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
773 | |
774 | tasklet_schedule(&chan->irq_tasklet); | |
775 | ||
776 | iop_adma_device_clear_eot_status(chan); | |
777 | ||
778 | return IRQ_HANDLED; | |
779 | } | |
780 | ||
781 | static irqreturn_t iop_adma_eoc_handler(int irq, void *data) | |
782 | { | |
783 | struct iop_adma_chan *chan = data; | |
784 | ||
3d9b525b | 785 | dev_dbg(chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
786 | |
787 | tasklet_schedule(&chan->irq_tasklet); | |
788 | ||
789 | iop_adma_device_clear_eoc_status(chan); | |
790 | ||
791 | return IRQ_HANDLED; | |
792 | } | |
793 | ||
794 | static irqreturn_t iop_adma_err_handler(int irq, void *data) | |
795 | { | |
796 | struct iop_adma_chan *chan = data; | |
797 | unsigned long status = iop_chan_get_status(chan); | |
798 | ||
1ba151cd | 799 | dev_err(chan->device->common.dev, |
c2110923 DW |
800 | "error ( %s%s%s%s%s%s%s)\n", |
801 | iop_is_err_int_parity(status, chan) ? "int_parity " : "", | |
802 | iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "", | |
803 | iop_is_err_int_tabort(status, chan) ? "int_tabort " : "", | |
804 | iop_is_err_int_mabort(status, chan) ? "int_mabort " : "", | |
805 | iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "", | |
806 | iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "", | |
807 | iop_is_err_split_tx(status, chan) ? "split_tx " : ""); | |
808 | ||
809 | iop_adma_device_clear_err_status(chan); | |
810 | ||
811 | BUG(); | |
812 | ||
813 | return IRQ_HANDLED; | |
814 | } | |
815 | ||
816 | static void iop_adma_issue_pending(struct dma_chan *chan) | |
817 | { | |
818 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
819 | ||
820 | if (iop_chan->pending) { | |
821 | iop_chan->pending = 0; | |
822 | iop_chan_append(iop_chan); | |
823 | } | |
824 | } | |
825 | ||
826 | /* | |
827 | * Perform a transaction to verify the HW works. | |
828 | */ | |
829 | #define IOP_ADMA_TEST_SIZE 2000 | |
830 | ||
463a1f8b | 831 | static int iop_adma_memcpy_self_test(struct iop_adma_device *device) |
c2110923 DW |
832 | { |
833 | int i; | |
834 | void *src, *dest; | |
835 | dma_addr_t src_dma, dest_dma; | |
836 | struct dma_chan *dma_chan; | |
837 | dma_cookie_t cookie; | |
838 | struct dma_async_tx_descriptor *tx; | |
839 | int err = 0; | |
840 | struct iop_adma_chan *iop_chan; | |
841 | ||
3d9b525b | 842 | dev_dbg(device->common.dev, "%s\n", __func__); |
c2110923 | 843 | |
eccf2144 | 844 | src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c2110923 DW |
845 | if (!src) |
846 | return -ENOMEM; | |
eccf2144 | 847 | dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c2110923 DW |
848 | if (!dest) { |
849 | kfree(src); | |
850 | return -ENOMEM; | |
851 | } | |
852 | ||
853 | /* Fill in src buffer */ | |
854 | for (i = 0; i < IOP_ADMA_TEST_SIZE; i++) | |
855 | ((u8 *) src)[i] = (u8)i; | |
856 | ||
c2110923 DW |
857 | /* Start copy, using first DMA channel */ |
858 | dma_chan = container_of(device->common.channels.next, | |
859 | struct dma_chan, | |
860 | device_node); | |
aa1e6f1a | 861 | if (iop_adma_alloc_chan_resources(dma_chan) < 1) { |
c2110923 DW |
862 | err = -ENODEV; |
863 | goto out; | |
864 | } | |
865 | ||
c2110923 DW |
866 | dest_dma = dma_map_single(dma_chan->device->dev, dest, |
867 | IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); | |
c2110923 DW |
868 | src_dma = dma_map_single(dma_chan->device->dev, src, |
869 | IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); | |
0036731c | 870 | tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
636bdeaa DW |
871 | IOP_ADMA_TEST_SIZE, |
872 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
873 | |
874 | cookie = iop_adma_tx_submit(tx); | |
875 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
876 | msleep(1); |
877 | ||
07934481 | 878 | if (iop_adma_status(dma_chan, cookie, NULL) != |
9f571502 | 879 | DMA_COMPLETE) { |
1ba151cd | 880 | dev_err(dma_chan->device->dev, |
c2110923 DW |
881 | "Self-test copy timed out, disabling\n"); |
882 | err = -ENODEV; | |
883 | goto free_resources; | |
884 | } | |
885 | ||
886 | iop_chan = to_iop_adma_chan(dma_chan); | |
887 | dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, | |
888 | IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); | |
889 | if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) { | |
1ba151cd | 890 | dev_err(dma_chan->device->dev, |
c2110923 DW |
891 | "Self-test copy failed compare, disabling\n"); |
892 | err = -ENODEV; | |
893 | goto free_resources; | |
894 | } | |
895 | ||
896 | free_resources: | |
897 | iop_adma_free_chan_resources(dma_chan); | |
898 | out: | |
899 | kfree(src); | |
900 | kfree(dest); | |
901 | return err; | |
902 | } | |
903 | ||
904 | #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 905 | static int |
099f53cb | 906 | iop_adma_xor_val_self_test(struct iop_adma_device *device) |
c2110923 DW |
907 | { |
908 | int i, src_idx; | |
909 | struct page *dest; | |
910 | struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST]; | |
911 | struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; | |
0036731c | 912 | dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; |
f9f0a7d0 | 913 | dma_addr_t dest_dma; |
c2110923 DW |
914 | struct dma_async_tx_descriptor *tx; |
915 | struct dma_chan *dma_chan; | |
916 | dma_cookie_t cookie; | |
917 | u8 cmp_byte = 0; | |
918 | u32 cmp_word; | |
919 | u32 zero_sum_result; | |
920 | int err = 0; | |
921 | struct iop_adma_chan *iop_chan; | |
922 | ||
3d9b525b | 923 | dev_dbg(device->common.dev, "%s\n", __func__); |
c2110923 DW |
924 | |
925 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | |
926 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
927 | if (!xor_srcs[src_idx]) { |
928 | while (src_idx--) | |
c2110923 | 929 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
930 | return -ENOMEM; |
931 | } | |
c2110923 DW |
932 | } |
933 | ||
934 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
935 | if (!dest) { |
936 | while (src_idx--) | |
c2110923 | 937 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
938 | return -ENOMEM; |
939 | } | |
c2110923 DW |
940 | |
941 | /* Fill in src buffers */ | |
942 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | |
943 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
944 | for (i = 0; i < PAGE_SIZE; i++) | |
945 | ptr[i] = (1 << src_idx); | |
946 | } | |
947 | ||
948 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) | |
949 | cmp_byte ^= (u8) (1 << src_idx); | |
950 | ||
951 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
952 | (cmp_byte << 8) | cmp_byte; | |
953 | ||
954 | memset(page_address(dest), 0, PAGE_SIZE); | |
955 | ||
956 | dma_chan = container_of(device->common.channels.next, | |
957 | struct dma_chan, | |
958 | device_node); | |
aa1e6f1a | 959 | if (iop_adma_alloc_chan_resources(dma_chan) < 1) { |
c2110923 DW |
960 | err = -ENODEV; |
961 | goto out; | |
962 | } | |
963 | ||
964 | /* test xor */ | |
c2110923 DW |
965 | dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, |
966 | PAGE_SIZE, DMA_FROM_DEVICE); | |
0036731c DW |
967 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) |
968 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
969 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
970 | tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
636bdeaa DW |
971 | IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, |
972 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
973 | |
974 | cookie = iop_adma_tx_submit(tx); | |
975 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
976 | msleep(8); |
977 | ||
07934481 | 978 | if (iop_adma_status(dma_chan, cookie, NULL) != |
9f571502 | 979 | DMA_COMPLETE) { |
1ba151cd | 980 | dev_err(dma_chan->device->dev, |
c2110923 DW |
981 | "Self-test xor timed out, disabling\n"); |
982 | err = -ENODEV; | |
983 | goto free_resources; | |
984 | } | |
985 | ||
986 | iop_chan = to_iop_adma_chan(dma_chan); | |
987 | dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, | |
988 | PAGE_SIZE, DMA_FROM_DEVICE); | |
989 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
990 | u32 *ptr = page_address(dest); | |
991 | if (ptr[i] != cmp_word) { | |
1ba151cd | 992 | dev_err(dma_chan->device->dev, |
c2110923 DW |
993 | "Self-test xor failed compare, disabling\n"); |
994 | err = -ENODEV; | |
995 | goto free_resources; | |
996 | } | |
997 | } | |
998 | dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma, | |
999 | PAGE_SIZE, DMA_TO_DEVICE); | |
1000 | ||
1001 | /* skip zero sum if the capability is not present */ | |
099f53cb | 1002 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) |
c2110923 DW |
1003 | goto free_resources; |
1004 | ||
1005 | /* zero sum the sources with the destintation page */ | |
1006 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) | |
1007 | zero_sum_srcs[i] = xor_srcs[i]; | |
1008 | zero_sum_srcs[i] = dest; | |
1009 | ||
1010 | zero_sum_result = 1; | |
1011 | ||
0036731c DW |
1012 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) |
1013 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, | |
1014 | zero_sum_srcs[i], 0, PAGE_SIZE, | |
1015 | DMA_TO_DEVICE); | |
099f53cb DW |
1016 | tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, |
1017 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1018 | &zero_sum_result, | |
1019 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1020 | |
1021 | cookie = iop_adma_tx_submit(tx); | |
1022 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1023 | msleep(8); |
1024 | ||
9f571502 | 1025 | if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { |
1ba151cd | 1026 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1027 | "Self-test zero sum timed out, disabling\n"); |
1028 | err = -ENODEV; | |
1029 | goto free_resources; | |
1030 | } | |
1031 | ||
1032 | if (zero_sum_result != 0) { | |
1ba151cd | 1033 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1034 | "Self-test zero sum failed compare, disabling\n"); |
1035 | err = -ENODEV; | |
1036 | goto free_resources; | |
1037 | } | |
1038 | ||
c2110923 DW |
1039 | /* test for non-zero parity sum */ |
1040 | zero_sum_result = 0; | |
0036731c DW |
1041 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) |
1042 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, | |
1043 | zero_sum_srcs[i], 0, PAGE_SIZE, | |
1044 | DMA_TO_DEVICE); | |
099f53cb DW |
1045 | tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, |
1046 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1047 | &zero_sum_result, | |
1048 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1049 | |
1050 | cookie = iop_adma_tx_submit(tx); | |
1051 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1052 | msleep(8); |
1053 | ||
9f571502 | 1054 | if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { |
1ba151cd | 1055 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1056 | "Self-test non-zero sum timed out, disabling\n"); |
1057 | err = -ENODEV; | |
1058 | goto free_resources; | |
1059 | } | |
1060 | ||
1061 | if (zero_sum_result != 1) { | |
1ba151cd | 1062 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1063 | "Self-test non-zero sum failed compare, disabling\n"); |
1064 | err = -ENODEV; | |
1065 | goto free_resources; | |
1066 | } | |
1067 | ||
1068 | free_resources: | |
1069 | iop_adma_free_chan_resources(dma_chan); | |
1070 | out: | |
1071 | src_idx = IOP_ADMA_NUM_SRC_TEST; | |
1072 | while (src_idx--) | |
1073 | __free_page(xor_srcs[src_idx]); | |
1074 | __free_page(dest); | |
1075 | return err; | |
1076 | } | |
1077 | ||
0261f741 | 1078 | #ifdef CONFIG_RAID6_PQ |
463a1f8b | 1079 | static int |
f6dbf651 DW |
1080 | iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device) |
1081 | { | |
1082 | /* combined sources, software pq results, and extra hw pq results */ | |
1083 | struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2]; | |
1084 | /* ptr to the extra hw pq buffers defined above */ | |
1085 | struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2]; | |
1086 | /* address conversion buffers (dma_map / page_address) */ | |
1087 | void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2]; | |
3d9ea9e3 DM |
1088 | dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2]; |
1089 | dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST]; | |
f6dbf651 DW |
1090 | |
1091 | int i; | |
1092 | struct dma_async_tx_descriptor *tx; | |
1093 | struct dma_chan *dma_chan; | |
1094 | dma_cookie_t cookie; | |
1095 | u32 zero_sum_result; | |
1096 | int err = 0; | |
1097 | struct device *dev; | |
1098 | ||
1099 | dev_dbg(device->common.dev, "%s\n", __func__); | |
1100 | ||
1101 | for (i = 0; i < ARRAY_SIZE(pq); i++) { | |
1102 | pq[i] = alloc_page(GFP_KERNEL); | |
1103 | if (!pq[i]) { | |
1104 | while (i--) | |
1105 | __free_page(pq[i]); | |
1106 | return -ENOMEM; | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | /* Fill in src buffers */ | |
1111 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) { | |
1112 | pq_sw[i] = page_address(pq[i]); | |
1113 | memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE); | |
1114 | } | |
1115 | pq_sw[i] = page_address(pq[i]); | |
1116 | pq_sw[i+1] = page_address(pq[i+1]); | |
1117 | ||
1118 | dma_chan = container_of(device->common.channels.next, | |
1119 | struct dma_chan, | |
1120 | device_node); | |
1121 | if (iop_adma_alloc_chan_resources(dma_chan) < 1) { | |
1122 | err = -ENODEV; | |
1123 | goto out; | |
1124 | } | |
1125 | ||
1126 | dev = dma_chan->device->dev; | |
1127 | ||
1128 | /* initialize the dests */ | |
1129 | memset(page_address(pq_hw[0]), 0 , PAGE_SIZE); | |
1130 | memset(page_address(pq_hw[1]), 0 , PAGE_SIZE); | |
1131 | ||
1132 | /* test pq */ | |
1133 | pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
1134 | pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
1135 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) | |
1136 | pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, | |
1137 | DMA_TO_DEVICE); | |
1138 | ||
1139 | tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src, | |
1140 | IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp, | |
1141 | PAGE_SIZE, | |
1142 | DMA_PREP_INTERRUPT | | |
1143 | DMA_CTRL_ACK); | |
1144 | ||
1145 | cookie = iop_adma_tx_submit(tx); | |
1146 | iop_adma_issue_pending(dma_chan); | |
1147 | msleep(8); | |
1148 | ||
07934481 | 1149 | if (iop_adma_status(dma_chan, cookie, NULL) != |
9f571502 | 1150 | DMA_COMPLETE) { |
f6dbf651 DW |
1151 | dev_err(dev, "Self-test pq timed out, disabling\n"); |
1152 | err = -ENODEV; | |
1153 | goto free_resources; | |
1154 | } | |
1155 | ||
1156 | raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw); | |
1157 | ||
1158 | if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST], | |
1159 | page_address(pq_hw[0]), PAGE_SIZE) != 0) { | |
1160 | dev_err(dev, "Self-test p failed compare, disabling\n"); | |
1161 | err = -ENODEV; | |
1162 | goto free_resources; | |
1163 | } | |
1164 | if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1], | |
1165 | page_address(pq_hw[1]), PAGE_SIZE) != 0) { | |
1166 | dev_err(dev, "Self-test q failed compare, disabling\n"); | |
1167 | err = -ENODEV; | |
1168 | goto free_resources; | |
1169 | } | |
1170 | ||
1171 | /* test correct zero sum using the software generated pq values */ | |
1172 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) | |
1173 | pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, | |
1174 | DMA_TO_DEVICE); | |
1175 | ||
1176 | zero_sum_result = ~0; | |
1177 | tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], | |
1178 | pq_src, IOP_ADMA_NUM_SRC_TEST, | |
1179 | raid6_gfexp, PAGE_SIZE, &zero_sum_result, | |
1180 | DMA_PREP_INTERRUPT|DMA_CTRL_ACK); | |
1181 | ||
1182 | cookie = iop_adma_tx_submit(tx); | |
1183 | iop_adma_issue_pending(dma_chan); | |
1184 | msleep(8); | |
1185 | ||
07934481 | 1186 | if (iop_adma_status(dma_chan, cookie, NULL) != |
9f571502 | 1187 | DMA_COMPLETE) { |
f6dbf651 DW |
1188 | dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n"); |
1189 | err = -ENODEV; | |
1190 | goto free_resources; | |
1191 | } | |
1192 | ||
1193 | if (zero_sum_result != 0) { | |
1194 | dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n", | |
1195 | zero_sum_result); | |
1196 | err = -ENODEV; | |
1197 | goto free_resources; | |
1198 | } | |
1199 | ||
1200 | /* test incorrect zero sum */ | |
1201 | i = IOP_ADMA_NUM_SRC_TEST; | |
1202 | memset(pq_sw[i] + 100, 0, 100); | |
1203 | memset(pq_sw[i+1] + 200, 0, 200); | |
1204 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) | |
1205 | pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, | |
1206 | DMA_TO_DEVICE); | |
1207 | ||
1208 | zero_sum_result = 0; | |
1209 | tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], | |
1210 | pq_src, IOP_ADMA_NUM_SRC_TEST, | |
1211 | raid6_gfexp, PAGE_SIZE, &zero_sum_result, | |
1212 | DMA_PREP_INTERRUPT|DMA_CTRL_ACK); | |
1213 | ||
1214 | cookie = iop_adma_tx_submit(tx); | |
1215 | iop_adma_issue_pending(dma_chan); | |
1216 | msleep(8); | |
1217 | ||
07934481 | 1218 | if (iop_adma_status(dma_chan, cookie, NULL) != |
9f571502 | 1219 | DMA_COMPLETE) { |
f6dbf651 DW |
1220 | dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n"); |
1221 | err = -ENODEV; | |
1222 | goto free_resources; | |
1223 | } | |
1224 | ||
1225 | if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) { | |
1226 | dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n", | |
1227 | zero_sum_result); | |
1228 | err = -ENODEV; | |
1229 | goto free_resources; | |
1230 | } | |
1231 | ||
1232 | free_resources: | |
1233 | iop_adma_free_chan_resources(dma_chan); | |
1234 | out: | |
1235 | i = ARRAY_SIZE(pq); | |
1236 | while (i--) | |
1237 | __free_page(pq[i]); | |
1238 | return err; | |
1239 | } | |
1240 | #endif | |
1241 | ||
4bf27b8b | 1242 | static int iop_adma_remove(struct platform_device *dev) |
c2110923 DW |
1243 | { |
1244 | struct iop_adma_device *device = platform_get_drvdata(dev); | |
1245 | struct dma_chan *chan, *_chan; | |
1246 | struct iop_adma_chan *iop_chan; | |
d4adcc01 | 1247 | struct iop_adma_platform_data *plat_data = dev_get_platdata(&dev->dev); |
c2110923 DW |
1248 | |
1249 | dma_async_device_unregister(&device->common); | |
1250 | ||
c2110923 DW |
1251 | dma_free_coherent(&dev->dev, plat_data->pool_size, |
1252 | device->dma_desc_pool_virt, device->dma_desc_pool); | |
1253 | ||
c2110923 DW |
1254 | list_for_each_entry_safe(chan, _chan, &device->common.channels, |
1255 | device_node) { | |
1256 | iop_chan = to_iop_adma_chan(chan); | |
1257 | list_del(&chan->device_node); | |
1258 | kfree(iop_chan); | |
1259 | } | |
1260 | kfree(device); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
463a1f8b | 1265 | static int iop_adma_probe(struct platform_device *pdev) |
c2110923 DW |
1266 | { |
1267 | struct resource *res; | |
1268 | int ret = 0, i; | |
1269 | struct iop_adma_device *adev; | |
1270 | struct iop_adma_chan *iop_chan; | |
1271 | struct dma_device *dma_dev; | |
d4adcc01 | 1272 | struct iop_adma_platform_data *plat_data = dev_get_platdata(&pdev->dev); |
c2110923 DW |
1273 | |
1274 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1275 | if (!res) | |
1276 | return -ENODEV; | |
1277 | ||
1278 | if (!devm_request_mem_region(&pdev->dev, res->start, | |
2e032b62 | 1279 | resource_size(res), pdev->name)) |
c2110923 DW |
1280 | return -EBUSY; |
1281 | ||
1282 | adev = kzalloc(sizeof(*adev), GFP_KERNEL); | |
1283 | if (!adev) | |
1284 | return -ENOMEM; | |
1285 | dma_dev = &adev->common; | |
1286 | ||
1287 | /* allocate coherent memory for hardware descriptors | |
1288 | * note: writecombine gives slightly better performance, but | |
1289 | * requires that we explicitly flush the writes | |
1290 | */ | |
f6e45661 LR |
1291 | adev->dma_desc_pool_virt = dma_alloc_wc(&pdev->dev, |
1292 | plat_data->pool_size, | |
1293 | &adev->dma_desc_pool, | |
1294 | GFP_KERNEL); | |
39c33704 | 1295 | if (!adev->dma_desc_pool_virt) { |
c2110923 DW |
1296 | ret = -ENOMEM; |
1297 | goto err_free_adev; | |
1298 | } | |
1299 | ||
985d5137 Y |
1300 | dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %pad\n", |
1301 | __func__, adev->dma_desc_pool_virt, &adev->dma_desc_pool); | |
c2110923 DW |
1302 | |
1303 | adev->id = plat_data->hw_id; | |
1304 | ||
1305 | /* discover transaction capabilites from the platform data */ | |
1306 | dma_dev->cap_mask = plat_data->cap_mask; | |
1307 | ||
1308 | adev->pdev = pdev; | |
1309 | platform_set_drvdata(pdev, adev); | |
1310 | ||
1311 | INIT_LIST_HEAD(&dma_dev->channels); | |
1312 | ||
1313 | /* set base routines */ | |
1314 | dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources; | |
1315 | dma_dev->device_free_chan_resources = iop_adma_free_chan_resources; | |
07934481 | 1316 | dma_dev->device_tx_status = iop_adma_status; |
c2110923 | 1317 | dma_dev->device_issue_pending = iop_adma_issue_pending; |
c2110923 DW |
1318 | dma_dev->dev = &pdev->dev; |
1319 | ||
1320 | /* set prep routines based on capability */ | |
1321 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) | |
1322 | dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy; | |
c2110923 DW |
1323 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
1324 | dma_dev->max_xor = iop_adma_get_max_xor(); | |
1325 | dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor; | |
1326 | } | |
099f53cb DW |
1327 | if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask)) |
1328 | dma_dev->device_prep_dma_xor_val = | |
1329 | iop_adma_prep_dma_xor_val; | |
7bf649ae DW |
1330 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { |
1331 | dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0); | |
1332 | dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq; | |
1333 | } | |
1334 | if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) | |
1335 | dma_dev->device_prep_dma_pq_val = | |
1336 | iop_adma_prep_dma_pq_val; | |
c2110923 DW |
1337 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
1338 | dma_dev->device_prep_dma_interrupt = | |
1339 | iop_adma_prep_dma_interrupt; | |
1340 | ||
1341 | iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL); | |
1342 | if (!iop_chan) { | |
1343 | ret = -ENOMEM; | |
1344 | goto err_free_dma; | |
1345 | } | |
1346 | iop_chan->device = adev; | |
1347 | ||
1348 | iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start, | |
2e032b62 | 1349 | resource_size(res)); |
c2110923 DW |
1350 | if (!iop_chan->mmr_base) { |
1351 | ret = -ENOMEM; | |
1352 | goto err_free_iop_chan; | |
1353 | } | |
5bbb671f | 1354 | tasklet_setup(&iop_chan->irq_tasklet, iop_adma_tasklet); |
c2110923 DW |
1355 | |
1356 | /* clear errors before enabling interrupts */ | |
1357 | iop_adma_device_clear_err_status(iop_chan); | |
1358 | ||
1359 | for (i = 0; i < 3; i++) { | |
bc3ecbe0 CIK |
1360 | static const irq_handler_t handler[] = { |
1361 | iop_adma_eot_handler, | |
1362 | iop_adma_eoc_handler, | |
1363 | iop_adma_err_handler | |
1364 | }; | |
c2110923 DW |
1365 | int irq = platform_get_irq(pdev, i); |
1366 | if (irq < 0) { | |
1367 | ret = -ENXIO; | |
1368 | goto err_free_iop_chan; | |
1369 | } else { | |
1370 | ret = devm_request_irq(&pdev->dev, irq, | |
1371 | handler[i], 0, pdev->name, iop_chan); | |
1372 | if (ret) | |
1373 | goto err_free_iop_chan; | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | spin_lock_init(&iop_chan->lock); | |
c2110923 DW |
1378 | INIT_LIST_HEAD(&iop_chan->chain); |
1379 | INIT_LIST_HEAD(&iop_chan->all_slots); | |
c2110923 | 1380 | iop_chan->common.device = dma_dev; |
8ac69546 | 1381 | dma_cookie_init(&iop_chan->common); |
c2110923 DW |
1382 | list_add_tail(&iop_chan->common.device_node, &dma_dev->channels); |
1383 | ||
1384 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
1385 | ret = iop_adma_memcpy_self_test(adev); | |
1386 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); | |
1387 | if (ret) | |
1388 | goto err_free_iop_chan; | |
1389 | } | |
1390 | ||
48a9db46 | 1391 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
099f53cb | 1392 | ret = iop_adma_xor_val_self_test(adev); |
c2110923 DW |
1393 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1394 | if (ret) | |
1395 | goto err_free_iop_chan; | |
1396 | } | |
1397 | ||
f6dbf651 DW |
1398 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) && |
1399 | dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) { | |
0261f741 | 1400 | #ifdef CONFIG_RAID6_PQ |
f6dbf651 DW |
1401 | ret = iop_adma_pq_zero_sum_self_test(adev); |
1402 | dev_dbg(&pdev->dev, "pq self test returned %d\n", ret); | |
1403 | #else | |
1404 | /* can not test raid6, so do not publish capability */ | |
1405 | dma_cap_clear(DMA_PQ, dma_dev->cap_mask); | |
1406 | dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask); | |
1407 | ret = 0; | |
1408 | #endif | |
1409 | if (ret) | |
1410 | goto err_free_iop_chan; | |
1411 | } | |
1412 | ||
f9f0a7d0 | 1413 | dev_info(&pdev->dev, "Intel(R) IOP: ( %s%s%s%s%s%s)\n", |
1ba151cd JP |
1414 | dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", |
1415 | dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", | |
1416 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", | |
1417 | dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "", | |
1ba151cd JP |
1418 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1419 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
c2110923 DW |
1420 | |
1421 | dma_async_device_register(dma_dev); | |
1422 | goto out; | |
1423 | ||
1424 | err_free_iop_chan: | |
1425 | kfree(iop_chan); | |
1426 | err_free_dma: | |
1427 | dma_free_coherent(&adev->pdev->dev, plat_data->pool_size, | |
1428 | adev->dma_desc_pool_virt, adev->dma_desc_pool); | |
1429 | err_free_adev: | |
1430 | kfree(adev); | |
1431 | out: | |
1432 | return ret; | |
1433 | } | |
1434 | ||
1435 | static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) | |
1436 | { | |
1437 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
1438 | dma_cookie_t cookie; | |
1439 | int slot_cnt, slots_per_op; | |
1440 | ||
3d9b525b | 1441 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
1442 | |
1443 | spin_lock_bh(&iop_chan->lock); | |
1444 | slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op); | |
1445 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
1446 | if (sw_desc) { | |
1447 | grp_start = sw_desc->group_head; | |
1448 | ||
308136d1 | 1449 | list_splice_init(&sw_desc->tx_list, &iop_chan->chain); |
636bdeaa | 1450 | async_tx_ack(&sw_desc->async_tx); |
c2110923 DW |
1451 | iop_desc_init_memcpy(grp_start, 0); |
1452 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | |
1453 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | |
1454 | iop_desc_set_memcpy_src_addr(grp_start, 0); | |
1455 | ||
2a926e46 | 1456 | cookie = dma_cookie_assign(&sw_desc->async_tx); |
c2110923 DW |
1457 | |
1458 | /* initialize the completed cookie to be less than | |
1459 | * the most recently used cookie | |
1460 | */ | |
4d4e58de | 1461 | iop_chan->common.completed_cookie = cookie - 1; |
c2110923 DW |
1462 | |
1463 | /* channel should not be busy */ | |
1464 | BUG_ON(iop_chan_is_busy(iop_chan)); | |
1465 | ||
1466 | /* clear any prior error-status bits */ | |
1467 | iop_adma_device_clear_err_status(iop_chan); | |
1468 | ||
1469 | /* disable operation */ | |
1470 | iop_chan_disable(iop_chan); | |
1471 | ||
1472 | /* set the descriptor address */ | |
1473 | iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); | |
1474 | ||
1475 | /* 1/ don't add pre-chained descriptors | |
1476 | * 2/ dummy read to flush next_desc write | |
1477 | */ | |
1478 | BUG_ON(iop_desc_get_next_desc(sw_desc)); | |
1479 | ||
1480 | /* run the descriptor */ | |
1481 | iop_chan_enable(iop_chan); | |
1482 | } else | |
1ba151cd JP |
1483 | dev_err(iop_chan->device->common.dev, |
1484 | "failed to allocate null descriptor\n"); | |
c2110923 DW |
1485 | spin_unlock_bh(&iop_chan->lock); |
1486 | } | |
1487 | ||
1488 | static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) | |
1489 | { | |
1490 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
1491 | dma_cookie_t cookie; | |
1492 | int slot_cnt, slots_per_op; | |
1493 | ||
3d9b525b | 1494 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
1495 | |
1496 | spin_lock_bh(&iop_chan->lock); | |
1497 | slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op); | |
1498 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
1499 | if (sw_desc) { | |
1500 | grp_start = sw_desc->group_head; | |
308136d1 | 1501 | list_splice_init(&sw_desc->tx_list, &iop_chan->chain); |
636bdeaa | 1502 | async_tx_ack(&sw_desc->async_tx); |
c2110923 DW |
1503 | iop_desc_init_null_xor(grp_start, 2, 0); |
1504 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | |
1505 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | |
1506 | iop_desc_set_xor_src_addr(grp_start, 0, 0); | |
1507 | iop_desc_set_xor_src_addr(grp_start, 1, 0); | |
1508 | ||
2a926e46 | 1509 | cookie = dma_cookie_assign(&sw_desc->async_tx); |
c2110923 DW |
1510 | |
1511 | /* initialize the completed cookie to be less than | |
1512 | * the most recently used cookie | |
1513 | */ | |
4d4e58de | 1514 | iop_chan->common.completed_cookie = cookie - 1; |
c2110923 DW |
1515 | |
1516 | /* channel should not be busy */ | |
1517 | BUG_ON(iop_chan_is_busy(iop_chan)); | |
1518 | ||
1519 | /* clear any prior error-status bits */ | |
1520 | iop_adma_device_clear_err_status(iop_chan); | |
1521 | ||
1522 | /* disable operation */ | |
1523 | iop_chan_disable(iop_chan); | |
1524 | ||
1525 | /* set the descriptor address */ | |
1526 | iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); | |
1527 | ||
1528 | /* 1/ don't add pre-chained descriptors | |
1529 | * 2/ dummy read to flush next_desc write | |
1530 | */ | |
1531 | BUG_ON(iop_desc_get_next_desc(sw_desc)); | |
1532 | ||
1533 | /* run the descriptor */ | |
1534 | iop_chan_enable(iop_chan); | |
1535 | } else | |
1ba151cd | 1536 | dev_err(iop_chan->device->common.dev, |
c2110923 DW |
1537 | "failed to allocate null descriptor\n"); |
1538 | spin_unlock_bh(&iop_chan->lock); | |
1539 | } | |
1540 | ||
1541 | static struct platform_driver iop_adma_driver = { | |
1542 | .probe = iop_adma_probe, | |
a7d6e3ec | 1543 | .remove = iop_adma_remove, |
c2110923 | 1544 | .driver = { |
c2110923 DW |
1545 | .name = "iop-adma", |
1546 | }, | |
1547 | }; | |
1548 | ||
c94e9105 | 1549 | module_platform_driver(iop_adma_driver); |
c2110923 DW |
1550 | |
1551 | MODULE_AUTHOR("Intel Corporation"); | |
1552 | MODULE_DESCRIPTION("IOP ADMA Engine Driver"); | |
1553 | MODULE_LICENSE("GPL"); | |
c94e9105 | 1554 | MODULE_ALIAS("platform:iop-adma"); |