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0bbd5f4e CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef IOATDMA_H | |
22 | #define IOATDMA_H | |
23 | ||
24 | #include <linux/dmaengine.h> | |
25 | #include "ioatdma_hw.h" | |
26 | #include <linux/init.h> | |
27 | #include <linux/dmapool.h> | |
28 | #include <linux/cache.h> | |
57c651f7 | 29 | #include <linux/pci_ids.h> |
0bbd5f4e | 30 | |
3e037454 SN |
31 | enum ioat_interrupt { |
32 | none = 0, | |
33 | msix_multi_vector = 1, | |
34 | msix_single_vector = 2, | |
35 | msi = 3, | |
36 | intx = 4, | |
37 | }; | |
38 | ||
0bbd5f4e CL |
39 | #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 |
40 | ||
0bbd5f4e | 41 | /** |
8ab89567 | 42 | * struct ioatdma_device - internal representation of a IOAT device |
0bbd5f4e CL |
43 | * @pdev: PCI-Express device |
44 | * @reg_base: MMIO register space base address | |
45 | * @dma_pool: for allocating DMA descriptors | |
46 | * @common: embedded struct dma_device | |
8ab89567 | 47 | * @version: version of ioatdma device |
0bbd5f4e CL |
48 | */ |
49 | ||
8ab89567 | 50 | struct ioatdma_device { |
0bbd5f4e | 51 | struct pci_dev *pdev; |
47b16539 | 52 | void __iomem *reg_base; |
0bbd5f4e CL |
53 | struct pci_pool *dma_pool; |
54 | struct pci_pool *completion_pool; | |
0bbd5f4e | 55 | struct dma_device common; |
8ab89567 | 56 | u8 version; |
3e037454 SN |
57 | enum ioat_interrupt irq_mode; |
58 | struct msix_entry msix_entries[4]; | |
59 | struct ioat_dma_chan *idx[4]; | |
0bbd5f4e CL |
60 | }; |
61 | ||
62 | /** | |
63 | * struct ioat_dma_chan - internal representation of a DMA channel | |
64 | * @device: | |
65 | * @reg_base: | |
66 | * @sw_in_use: | |
67 | * @completion: | |
68 | * @completion_low: | |
69 | * @completion_high: | |
70 | * @completed_cookie: last cookie seen completed on cleanup | |
71 | * @cookie: value of last cookie given to client | |
72 | * @last_completion: | |
73 | * @xfercap: | |
74 | * @desc_lock: | |
75 | * @free_desc: | |
76 | * @used_desc: | |
77 | * @resource: | |
78 | * @device_node: | |
79 | */ | |
80 | ||
81 | struct ioat_dma_chan { | |
82 | ||
47b16539 | 83 | void __iomem *reg_base; |
0bbd5f4e CL |
84 | |
85 | dma_cookie_t completed_cookie; | |
86 | unsigned long last_completion; | |
87 | ||
88 | u32 xfercap; /* XFERCAP register value expanded out */ | |
89 | ||
90 | spinlock_t cleanup_lock; | |
91 | spinlock_t desc_lock; | |
92 | struct list_head free_desc; | |
93 | struct list_head used_desc; | |
94 | ||
95 | int pending; | |
96 | ||
8ab89567 | 97 | struct ioatdma_device *device; |
0bbd5f4e CL |
98 | struct dma_chan common; |
99 | ||
100 | dma_addr_t completion_addr; | |
101 | union { | |
102 | u64 full; /* HW completion writeback */ | |
103 | struct { | |
104 | u32 low; | |
105 | u32 high; | |
106 | }; | |
107 | } *completion_virt; | |
3e037454 | 108 | struct tasklet_struct cleanup_task; |
0bbd5f4e CL |
109 | }; |
110 | ||
111 | /* wrapper around hardware descriptor format + additional software fields */ | |
112 | ||
113 | /** | |
114 | * struct ioat_desc_sw - wrapper around hardware descriptor | |
115 | * @hw: hardware DMA descriptor | |
7405f74b DW |
116 | * @node: this descriptor will either be on the free list, |
117 | * or attached to a transaction list (async_tx.tx_list) | |
118 | * @tx_cnt: number of descriptors required to complete the transaction | |
119 | * @async_tx: the generic software descriptor for all engines | |
0bbd5f4e | 120 | */ |
0bbd5f4e CL |
121 | struct ioat_desc_sw { |
122 | struct ioat_dma_descriptor *hw; | |
123 | struct list_head node; | |
7405f74b | 124 | int tx_cnt; |
54a09feb | 125 | DECLARE_PCI_UNMAP_LEN(len) |
0bbd5f4e | 126 | DECLARE_PCI_UNMAP_ADDR(src) |
0bbd5f4e | 127 | DECLARE_PCI_UNMAP_ADDR(dst) |
7405f74b | 128 | struct dma_async_tx_descriptor async_tx; |
0bbd5f4e CL |
129 | }; |
130 | ||
8ab89567 SN |
131 | #if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE) |
132 | struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, | |
133 | void __iomem *iobase); | |
134 | void ioat_dma_remove(struct ioatdma_device *device); | |
2ed6dc34 SN |
135 | struct dca_provider *ioat_dca_init(struct pci_dev *pdev, |
136 | void __iomem *iobase); | |
8ab89567 SN |
137 | #else |
138 | #define ioat_dma_probe(pdev, iobase) NULL | |
139 | #define ioat_dma_remove(device) do { } while (0) | |
2ed6dc34 | 140 | #define ioat_dca_init(pdev, iobase) NULL |
8ab89567 SN |
141 | #endif |
142 | ||
0bbd5f4e | 143 | #endif /* IOATDMA_H */ |