Commit | Line | Data |
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0bbd5f4e | 1 | /* |
7bb67c14 | 2 | * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved. |
0bbd5f4e CL |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef IOATDMA_H | |
22 | #define IOATDMA_H | |
23 | ||
24 | #include <linux/dmaengine.h> | |
25 | #include "ioatdma_hw.h" | |
26 | #include <linux/init.h> | |
27 | #include <linux/dmapool.h> | |
28 | #include <linux/cache.h> | |
57c651f7 | 29 | #include <linux/pci_ids.h> |
0bbd5f4e | 30 | |
7bb67c14 | 31 | #define IOAT_DMA_VERSION "2.04" |
5149fd01 | 32 | |
3e037454 SN |
33 | enum ioat_interrupt { |
34 | none = 0, | |
35 | msix_multi_vector = 1, | |
36 | msix_single_vector = 2, | |
37 | msi = 3, | |
38 | intx = 4, | |
39 | }; | |
40 | ||
0bbd5f4e | 41 | #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 |
7bb67c14 SN |
42 | #define IOAT_DMA_DCA_ANY_CPU ~0 |
43 | ||
0bbd5f4e | 44 | |
0bbd5f4e | 45 | /** |
8ab89567 | 46 | * struct ioatdma_device - internal representation of a IOAT device |
0bbd5f4e CL |
47 | * @pdev: PCI-Express device |
48 | * @reg_base: MMIO register space base address | |
49 | * @dma_pool: for allocating DMA descriptors | |
50 | * @common: embedded struct dma_device | |
8ab89567 | 51 | * @version: version of ioatdma device |
7bb67c14 SN |
52 | * @irq_mode: which style irq to use |
53 | * @msix_entries: irq handlers | |
54 | * @idx: per channel data | |
0bbd5f4e CL |
55 | */ |
56 | ||
8ab89567 | 57 | struct ioatdma_device { |
0bbd5f4e | 58 | struct pci_dev *pdev; |
47b16539 | 59 | void __iomem *reg_base; |
0bbd5f4e CL |
60 | struct pci_pool *dma_pool; |
61 | struct pci_pool *completion_pool; | |
0bbd5f4e | 62 | struct dma_device common; |
8ab89567 | 63 | u8 version; |
3e037454 SN |
64 | enum ioat_interrupt irq_mode; |
65 | struct msix_entry msix_entries[4]; | |
66 | struct ioat_dma_chan *idx[4]; | |
0bbd5f4e CL |
67 | }; |
68 | ||
69 | /** | |
70 | * struct ioat_dma_chan - internal representation of a DMA channel | |
0bbd5f4e | 71 | */ |
0bbd5f4e CL |
72 | struct ioat_dma_chan { |
73 | ||
47b16539 | 74 | void __iomem *reg_base; |
0bbd5f4e CL |
75 | |
76 | dma_cookie_t completed_cookie; | |
77 | unsigned long last_completion; | |
78 | ||
79 | u32 xfercap; /* XFERCAP register value expanded out */ | |
80 | ||
81 | spinlock_t cleanup_lock; | |
82 | spinlock_t desc_lock; | |
83 | struct list_head free_desc; | |
84 | struct list_head used_desc; | |
85 | ||
86 | int pending; | |
7bb67c14 SN |
87 | int dmacount; |
88 | int desccount; | |
0bbd5f4e | 89 | |
8ab89567 | 90 | struct ioatdma_device *device; |
0bbd5f4e CL |
91 | struct dma_chan common; |
92 | ||
93 | dma_addr_t completion_addr; | |
94 | union { | |
95 | u64 full; /* HW completion writeback */ | |
96 | struct { | |
97 | u32 low; | |
98 | u32 high; | |
99 | }; | |
100 | } *completion_virt; | |
3e037454 | 101 | struct tasklet_struct cleanup_task; |
0bbd5f4e CL |
102 | }; |
103 | ||
104 | /* wrapper around hardware descriptor format + additional software fields */ | |
105 | ||
106 | /** | |
107 | * struct ioat_desc_sw - wrapper around hardware descriptor | |
108 | * @hw: hardware DMA descriptor | |
7405f74b DW |
109 | * @node: this descriptor will either be on the free list, |
110 | * or attached to a transaction list (async_tx.tx_list) | |
111 | * @tx_cnt: number of descriptors required to complete the transaction | |
112 | * @async_tx: the generic software descriptor for all engines | |
0bbd5f4e | 113 | */ |
0bbd5f4e CL |
114 | struct ioat_desc_sw { |
115 | struct ioat_dma_descriptor *hw; | |
116 | struct list_head node; | |
7405f74b | 117 | int tx_cnt; |
7f2b291f SN |
118 | size_t len; |
119 | dma_addr_t src; | |
120 | dma_addr_t dst; | |
7405f74b | 121 | struct dma_async_tx_descriptor async_tx; |
0bbd5f4e CL |
122 | }; |
123 | ||
8ab89567 SN |
124 | #if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE) |
125 | struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, | |
126 | void __iomem *iobase); | |
127 | void ioat_dma_remove(struct ioatdma_device *device); | |
7bb67c14 SN |
128 | struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); |
129 | struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); | |
8ab89567 SN |
130 | #else |
131 | #define ioat_dma_probe(pdev, iobase) NULL | |
132 | #define ioat_dma_remove(device) do { } while (0) | |
2ed6dc34 | 133 | #define ioat_dca_init(pdev, iobase) NULL |
7bb67c14 | 134 | #define ioat2_dca_init(pdev, iobase) NULL |
8ab89567 SN |
135 | #endif |
136 | ||
0bbd5f4e | 137 | #endif /* IOATDMA_H */ |