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dmaengine: ioatdma: Add Snow Ridge ioatdma device id
[linux-2.6-block.git] / drivers / dma / ioat / init.c
CommitLineData
c0f28ce6
DJ		 1/*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/dmaengine.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/workqueue.h>
28#include <linux/prefetch.h>
29#include <linux/dca.h>
4222a907 30#include <linux/aer.h>
dd4645eb 31#include <linux/sizes.h>
c0f28ce6
DJ		 32#include "dma.h"
33#include "registers.h"
34#include "hw.h"
35
36#include "../dmaengine.h"
37
38MODULE_VERSION(IOAT_DMA_VERSION);
39MODULE_LICENSE("Dual BSD/GPL");
40MODULE_AUTHOR("Intel Corporation");
41
01fa2fae 42static const struct pci_device_id ioat_pci_tbl[] = {
c0f28ce6
DJ		 43 /* I/OAT v3 platforms */
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
52
53 /* I/OAT v3.2 platforms */
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
64
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
75
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
86
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
97
ab98193d
DJ		 98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) },
99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) },
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) },
101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) },
103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) },
104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) },
106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) },
107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) },
108
1594c18f
DJ		 109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) },
110
c0f28ce6
DJ		 111 /* I/OAT v3.3 platforms */
112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
116
117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
120 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
121
4d75873f
DJ		 122 /* I/OAT v3.4 platforms */
123 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_ICX) },
124
c0f28ce6
DJ		 125 { 0, }
126};
127MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
128
129static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
130static void ioat_remove(struct pci_dev *pdev);
599d49de
DJ		 131static void
132ioat_init_channel(struct ioatdma_device *ioat_dma,
133 struct ioatdma_chan *ioat_chan, int idx);
ef97bd0f 134static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
f4d34aa8 135static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
ef97bd0f 136static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
c0f28ce6
DJ		 137
138static int ioat_dca_enabled = 1;
139module_param(ioat_dca_enabled, int, 0644);
140MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
141int ioat_pending_level = 4;
142module_param(ioat_pending_level, int, 0644);
143MODULE_PARM_DESC(ioat_pending_level,
144 "high-water mark for pushing ioat descriptors (default: 4)");
c0f28ce6
DJ		 145static char ioat_interrupt_style[32] = "msix";
146module_param_string(ioat_interrupt_style, ioat_interrupt_style,
147 sizeof(ioat_interrupt_style), 0644);
148MODULE_PARM_DESC(ioat_interrupt_style,
149 "set ioat interrupt style: msix (default), msi, intx");
150
151struct kmem_cache *ioat_cache;
152struct kmem_cache *ioat_sed_cache;
153
154static bool is_jf_ioat(struct pci_dev *pdev)
155{
156 switch (pdev->device) {
157 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
158 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
159 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
160 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
161 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
162 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
163 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
164 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
165 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
166 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
167 return true;
168 default:
169 return false;
170 }
171}
172
173static bool is_snb_ioat(struct pci_dev *pdev)
174{
175 switch (pdev->device) {
176 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
177 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
178 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
179 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
180 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
181 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
182 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
183 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
184 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
185 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
186 return true;
187 default:
188 return false;
189 }
190}
191
192static bool is_ivb_ioat(struct pci_dev *pdev)
193{
194 switch (pdev->device) {
195 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
196 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
197 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
198 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
199 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
200 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
201 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
202 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
203 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
204 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
205 return true;
206 default:
207 return false;
208 }
209
210}
211
212static bool is_hsw_ioat(struct pci_dev *pdev)
213{
214 switch (pdev->device) {
215 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
216 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
217 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
218 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
219 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
220 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
221 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
222 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
223 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
224 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
225 return true;
226 default:
227 return false;
228 }
229
230}
231
ab98193d
DJ		 232static bool is_bdx_ioat(struct pci_dev *pdev)
233{
234 switch (pdev->device) {
235 case PCI_DEVICE_ID_INTEL_IOAT_BDX0:
236 case PCI_DEVICE_ID_INTEL_IOAT_BDX1:
237 case PCI_DEVICE_ID_INTEL_IOAT_BDX2:
238 case PCI_DEVICE_ID_INTEL_IOAT_BDX3:
239 case PCI_DEVICE_ID_INTEL_IOAT_BDX4:
240 case PCI_DEVICE_ID_INTEL_IOAT_BDX5:
241 case PCI_DEVICE_ID_INTEL_IOAT_BDX6:
242 case PCI_DEVICE_ID_INTEL_IOAT_BDX7:
243 case PCI_DEVICE_ID_INTEL_IOAT_BDX8:
244 case PCI_DEVICE_ID_INTEL_IOAT_BDX9:
245 return true;
246 default:
247 return false;
248 }
249}
250
1594c18f
DJ		 251static inline bool is_skx_ioat(struct pci_dev *pdev)
252{
253 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false;
254}
255
c0f28ce6
DJ		 256static bool is_xeon_cb32(struct pci_dev *pdev)
257{
258 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
1594c18f 259 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev);
c0f28ce6
DJ		 260}
261
262bool is_bwd_ioat(struct pci_dev *pdev)
263{
264 switch (pdev->device) {
265 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
266 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
267 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
268 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
269 /* even though not Atom, BDX-DE has same DMA silicon */
270 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
271 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
272 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
273 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
274 return true;
275 default:
276 return false;
277 }
278}
279
280static bool is_bwd_noraid(struct pci_dev *pdev)
281{
282 switch (pdev->device) {
283 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
284 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
285 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
286 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
287 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
288 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
289 return true;
290 default:
291 return false;
292 }
293
294}
295
296/*
297 * Perform a IOAT transaction to verify the HW works.
298 */
299#define IOAT_TEST_SIZE 2000
300
301static void ioat_dma_test_callback(void *dma_async_param)
302{
303 struct completion *cmp = dma_async_param;
304
305 complete(cmp);
306}
307
308/**
309 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
310 * @ioat_dma: dma device to be tested
311 */
599d49de 312static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
c0f28ce6
DJ		 313{
314 int i;
315 u8 *src;
316 u8 *dest;
317 struct dma_device *dma = &ioat_dma->dma_dev;
318 struct device *dev = &ioat_dma->pdev->dev;
319 struct dma_chan *dma_chan;
320 struct dma_async_tx_descriptor *tx;
321 dma_addr_t dma_dest, dma_src;
322 dma_cookie_t cookie;
323 int err = 0;
324 struct completion cmp;
325 unsigned long tmo;
326 unsigned long flags;
327
6396bb22 328 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL);
c0f28ce6
DJ		 329 if (!src)
330 return -ENOMEM;
6396bb22 331 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL);
c0f28ce6
DJ		 332 if (!dest) {
333 kfree(src);
334 return -ENOMEM;
335 }
336
337 /* Fill in src buffer */
338 for (i = 0; i < IOAT_TEST_SIZE; i++)
339 src[i] = (u8)i;
340
341 /* Start copy, using first DMA channel */
342 dma_chan = container_of(dma->channels.next, struct dma_chan,
343 device_node);
344 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
345 dev_err(dev, "selftest cannot allocate chan resource\n");
346 err = -ENODEV;
347 goto out;
348 }
349
350 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
351 if (dma_mapping_error(dev, dma_src)) {
352 dev_err(dev, "mapping src buffer failed\n");
b424d2a0 353 err = -ENOMEM;
c0f28ce6
DJ		 354 goto free_resources;
355 }
356 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
357 if (dma_mapping_error(dev, dma_dest)) {
358 dev_err(dev, "mapping dest buffer failed\n");
b424d2a0 359 err = -ENOMEM;
c0f28ce6
DJ		 360 goto unmap_src;
361 }
362 flags = DMA_PREP_INTERRUPT;
363 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
364 dma_src, IOAT_TEST_SIZE,
365 flags);
366 if (!tx) {
367 dev_err(dev, "Self-test prep failed, disabling\n");
368 err = -ENODEV;
369 goto unmap_dma;
370 }
371
372 async_tx_ack(tx);
373 init_completion(&cmp);
374 tx->callback = ioat_dma_test_callback;
375 tx->callback_param = &cmp;
376 cookie = tx->tx_submit(tx);
377 if (cookie < 0) {
378 dev_err(dev, "Self-test setup failed, disabling\n");
379 err = -ENODEV;
380 goto unmap_dma;
381 }
382 dma->device_issue_pending(dma_chan);
383
384 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
385
386 if (tmo == 0 ||
387 dma->device_tx_status(dma_chan, cookie, NULL)
388 != DMA_COMPLETE) {
389 dev_err(dev, "Self-test copy timed out, disabling\n");
390 err = -ENODEV;
391 goto unmap_dma;
392 }
393 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
394 dev_err(dev, "Self-test copy failed compare, disabling\n");
395 err = -ENODEV;
5c9afbda 396 goto unmap_dma;
c0f28ce6
DJ		 397 }
398
399unmap_dma:
400 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
401unmap_src:
402 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
403free_resources:
404 dma->device_free_chan_resources(dma_chan);
405out:
406 kfree(src);
407 kfree(dest);
408 return err;
409}
410
411/**
412 * ioat_dma_setup_interrupts - setup interrupt handler
413 * @ioat_dma: ioat dma device
414 */
415int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
416{
417 struct ioatdma_chan *ioat_chan;
418 struct pci_dev *pdev = ioat_dma->pdev;
419 struct device *dev = &pdev->dev;
420 struct msix_entry *msix;
421 int i, j, msixcnt;
422 int err = -EINVAL;
423 u8 intrctrl = 0;
424
425 if (!strcmp(ioat_interrupt_style, "msix"))
426 goto msix;
427 if (!strcmp(ioat_interrupt_style, "msi"))
428 goto msi;
429 if (!strcmp(ioat_interrupt_style, "intx"))
430 goto intx;
431 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
432 goto err_no_irq;
433
434msix:
435 /* The number of MSI-X vectors should equal the number of channels */
436 msixcnt = ioat_dma->dma_dev.chancnt;
437 for (i = 0; i < msixcnt; i++)
438 ioat_dma->msix_entries[i].entry = i;
439
440 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
441 if (err)
442 goto msi;
443
444 for (i = 0; i < msixcnt; i++) {
445 msix = &ioat_dma->msix_entries[i];
446 ioat_chan = ioat_chan_by_index(ioat_dma, i);
447 err = devm_request_irq(dev, msix->vector,
448 ioat_dma_do_interrupt_msix, 0,
449 "ioat-msix", ioat_chan);
450 if (err) {
451 for (j = 0; j < i; j++) {
452 msix = &ioat_dma->msix_entries[j];
453 ioat_chan = ioat_chan_by_index(ioat_dma, j);
454 devm_free_irq(dev, msix->vector, ioat_chan);
455 }
456 goto msi;
457 }
458 }
459 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
460 ioat_dma->irq_mode = IOAT_MSIX;
461 goto done;
462
463msi:
464 err = pci_enable_msi(pdev);
465 if (err)
466 goto intx;
467
468 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
469 "ioat-msi", ioat_dma);
470 if (err) {
471 pci_disable_msi(pdev);
472 goto intx;
473 }
474 ioat_dma->irq_mode = IOAT_MSI;
475 goto done;
476
477intx:
478 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
479 IRQF_SHARED, "ioat-intx", ioat_dma);
480 if (err)
481 goto err_no_irq;
482
483 ioat_dma->irq_mode = IOAT_INTX;
484done:
ef97bd0f
DJ		 485 if (is_bwd_ioat(pdev))
486 ioat_intr_quirk(ioat_dma);
c0f28ce6
DJ		 487 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
488 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
489 return 0;
490
491err_no_irq:
492 /* Disable all interrupt generation */
493 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
494 ioat_dma->irq_mode = IOAT_NOIRQ;
495 dev_err(dev, "no usable interrupts\n");
496 return err;
497}
c0f28ce6
DJ		 498
499static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
500{
501 /* Disable all interrupt generation */
502 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
503}
504
599d49de 505static int ioat_probe(struct ioatdma_device *ioat_dma)
c0f28ce6
DJ		 506{
507 int err = -ENODEV;
508 struct dma_device *dma = &ioat_dma->dma_dev;
509 struct pci_dev *pdev = ioat_dma->pdev;
510 struct device *dev = &pdev->dev;
511
679cfbf7 512 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev,
c0f28ce6
DJ		 513 sizeof(u64),
514 SMP_CACHE_BYTES,
515 SMP_CACHE_BYTES);
516
517 if (!ioat_dma->completion_pool) {
518 err = -ENOMEM;
dd4645eb 519 goto err_out;
c0f28ce6
DJ		 520 }
521
ef97bd0f 522 ioat_enumerate_channels(ioat_dma);
c0f28ce6
DJ		 523
524 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
525 dma->dev = &pdev->dev;
526
527 if (!dma->chancnt) {
528 dev_err(dev, "channel enumeration error\n");
529 goto err_setup_interrupts;
530 }
531
532 err = ioat_dma_setup_interrupts(ioat_dma);
533 if (err)
534 goto err_setup_interrupts;
535
ef97bd0f 536 err = ioat3_dma_self_test(ioat_dma);
c0f28ce6
DJ		 537 if (err)
538 goto err_self_test;
539
540 return 0;
541
542err_self_test:
543 ioat_disable_interrupts(ioat_dma);
544err_setup_interrupts:
679cfbf7 545 dma_pool_destroy(ioat_dma->completion_pool);
dd4645eb 546err_out:
c0f28ce6
DJ		 547 return err;
548}
549
599d49de 550static int ioat_register(struct ioatdma_device *ioat_dma)
c0f28ce6
DJ		 551{
552 int err = dma_async_device_register(&ioat_dma->dma_dev);
553
554 if (err) {
555 ioat_disable_interrupts(ioat_dma);
679cfbf7 556 dma_pool_destroy(ioat_dma->completion_pool);
c0f28ce6
DJ		 557 }
558
559 return err;
560}
561
599d49de 562static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
c0f28ce6
DJ		 563{
564 struct dma_device *dma = &ioat_dma->dma_dev;
565
566 ioat_disable_interrupts(ioat_dma);
567
568 ioat_kobject_del(ioat_dma);
569
570 dma_async_device_unregister(dma);
571
679cfbf7 572 dma_pool_destroy(ioat_dma->completion_pool);
c0f28ce6
DJ		 573
574 INIT_LIST_HEAD(&dma->channels);
575}
576
577/**
578 * ioat_enumerate_channels - find and initialize the device's channels
579 * @ioat_dma: the ioat dma device to be enumerated
580 */
f4d34aa8 581static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
c0f28ce6
DJ		 582{
583 struct ioatdma_chan *ioat_chan;
584 struct device *dev = &ioat_dma->pdev->dev;
585 struct dma_device *dma = &ioat_dma->dma_dev;
586 u8 xfercap_log;
587 int i;
588
589 INIT_LIST_HEAD(&dma->channels);
590 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
591 dma->chancnt &= 0x1f; /* bits [4:0] valid */
592 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) {
593 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
594 dma->chancnt, ARRAY_SIZE(ioat_dma->idx));
595 dma->chancnt = ARRAY_SIZE(ioat_dma->idx);
596 }
597 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
598 xfercap_log &= 0x1f; /* bits [4:0] valid */
599 if (xfercap_log == 0)
f4d34aa8 600 return;
c0f28ce6
DJ		 601 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
602
603 for (i = 0; i < dma->chancnt; i++) {
604 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL);
605 if (!ioat_chan)
606 break;
607
608 ioat_init_channel(ioat_dma, ioat_chan, i);
609 ioat_chan->xfercap_log = xfercap_log;
610 spin_lock_init(&ioat_chan->prep_lock);
ef97bd0f 611 if (ioat_reset_hw(ioat_chan)) {
c0f28ce6
DJ		 612 i = 0;
613 break;
614 }
615 }
616 dma->chancnt = i;
c0f28ce6
DJ		 617}
618
619/**
620 * ioat_free_chan_resources - release all the descriptors
621 * @chan: the channel to be cleaned
622 */
599d49de 623static void ioat_free_chan_resources(struct dma_chan *c)
c0f28ce6
DJ		 624{
625 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
626 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
627 struct ioat_ring_ent *desc;
628 const int total_descs = 1 << ioat_chan->alloc_order;
629 int descs;
630 int i;
631
632 /* Before freeing channel resources first check
633 * if they have been previously allocated for this channel.
634 */
635 if (!ioat_chan->ring)
636 return;
637
638 ioat_stop(ioat_chan);
ef97bd0f 639 ioat_reset_hw(ioat_chan);
c0f28ce6
DJ		 640
641 spin_lock_bh(&ioat_chan->cleanup_lock);
642 spin_lock_bh(&ioat_chan->prep_lock);
643 descs = ioat_ring_space(ioat_chan);
644 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
645 for (i = 0; i < descs; i++) {
646 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
647 ioat_free_ring_ent(desc, c);
648 }
649
650 if (descs < total_descs)
651 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
652 total_descs - descs);
653
654 for (i = 0; i < total_descs - descs; i++) {
655 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
656 dump_desc_dbg(ioat_chan, desc);
657 ioat_free_ring_ent(desc, c);
658 }
659
dd4645eb
DJ		 660 for (i = 0; i < ioat_chan->desc_chunks; i++) {
661 dma_free_coherent(to_dev(ioat_chan), SZ_2M,
662 ioat_chan->descs[i].virt,
663 ioat_chan->descs[i].hw);
664 ioat_chan->descs[i].virt = NULL;
665 ioat_chan->descs[i].hw = 0;
666 }
667 ioat_chan->desc_chunks = 0;
668
c0f28ce6
DJ		 669 kfree(ioat_chan->ring);
670 ioat_chan->ring = NULL;
671 ioat_chan->alloc_order = 0;
679cfbf7 672 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
c0f28ce6
DJ		 673 ioat_chan->completion_dma);
674 spin_unlock_bh(&ioat_chan->prep_lock);
675 spin_unlock_bh(&ioat_chan->cleanup_lock);
676
677 ioat_chan->last_completion = 0;
678 ioat_chan->completion_dma = 0;
679 ioat_chan->dmacount = 0;
680}
681
682/* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
683 * @chan: channel to be initialized
684 */
599d49de 685static int ioat_alloc_chan_resources(struct dma_chan *c)
c0f28ce6
DJ		 686{
687 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
688 struct ioat_ring_ent **ring;
689 u64 status;
690 int order;
691 int i = 0;
692 u32 chanerr;
693
694 /* have we already been set up? */
695 if (ioat_chan->ring)
696 return 1 << ioat_chan->alloc_order;
697
698 /* Setup register to interrupt and write completion status on error */
699 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
700
701 /* allocate a completion writeback area */
702 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
703 ioat_chan->completion =
305697fa 704 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool,
21d25f6a 705 GFP_NOWAIT, &ioat_chan->completion_dma);
c0f28ce6
DJ		 706 if (!ioat_chan->completion)
707 return -ENOMEM;
708
c0f28ce6
DJ		 709 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
710 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
711 writel(((u64)ioat_chan->completion_dma) >> 32,
712 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
713
cd60cd96 714 order = IOAT_MAX_ORDER;
21d25f6a 715 ring = ioat_alloc_ring(c, order, GFP_NOWAIT);
c0f28ce6
DJ		 716 if (!ring)
717 return -ENOMEM;
718
719 spin_lock_bh(&ioat_chan->cleanup_lock);
720 spin_lock_bh(&ioat_chan->prep_lock);
721 ioat_chan->ring = ring;
722 ioat_chan->head = 0;
723 ioat_chan->issued = 0;
724 ioat_chan->tail = 0;
725 ioat_chan->alloc_order = order;
726 set_bit(IOAT_RUN, &ioat_chan->state);
727 spin_unlock_bh(&ioat_chan->prep_lock);
728 spin_unlock_bh(&ioat_chan->cleanup_lock);
729
730 ioat_start_null_desc(ioat_chan);
731
732 /* check that we got off the ground */
733 do {
734 udelay(1);
735 status = ioat_chansts(ioat_chan);
736 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
737
738 if (is_ioat_active(status) || is_ioat_idle(status))
739 return 1 << ioat_chan->alloc_order;
740
741 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
742
743 dev_WARN(to_dev(ioat_chan),
744 "failed to start channel chanerr: %#x\n", chanerr);
745 ioat_free_chan_resources(c);
746 return -EFAULT;
747}
748
749/* common channel initialization */
599d49de 750static void
c0f28ce6
DJ		 751ioat_init_channel(struct ioatdma_device *ioat_dma,
752 struct ioatdma_chan *ioat_chan, int idx)
753{
754 struct dma_device *dma = &ioat_dma->dma_dev;
755 struct dma_chan *c = &ioat_chan->dma_chan;
756 unsigned long data = (unsigned long) c;
757
758 ioat_chan->ioat_dma = ioat_dma;
759 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
760 spin_lock_init(&ioat_chan->cleanup_lock);
761 ioat_chan->dma_chan.device = dma;
762 dma_cookie_init(&ioat_chan->dma_chan);
763 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
764 ioat_dma->idx[idx] = ioat_chan;
bcdc4bd3 765 timer_setup(&ioat_chan->timer, ioat_timer_event, 0);
ef97bd0f 766 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data);
c0f28ce6
DJ		 767}
768
c0f28ce6
DJ		 769#define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
770static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
771{
772 int i, src_idx;
773 struct page *dest;
774 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
775 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
776 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
777 dma_addr_t dest_dma;
778 struct dma_async_tx_descriptor *tx;
779 struct dma_chan *dma_chan;
780 dma_cookie_t cookie;
781 u8 cmp_byte = 0;
782 u32 cmp_word;
783 u32 xor_val_result;
784 int err = 0;
785 struct completion cmp;
786 unsigned long tmo;
787 struct device *dev = &ioat_dma->pdev->dev;
788 struct dma_device *dma = &ioat_dma->dma_dev;
789 u8 op = 0;
790
791 dev_dbg(dev, "%s\n", __func__);
792
793 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
794 return 0;
795
796 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
797 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
798 if (!xor_srcs[src_idx]) {
799 while (src_idx--)
800 __free_page(xor_srcs[src_idx]);
801 return -ENOMEM;
802 }
803 }
804
805 dest = alloc_page(GFP_KERNEL);
806 if (!dest) {
807 while (src_idx--)
808 __free_page(xor_srcs[src_idx]);
809 return -ENOMEM;
810 }
811
812 /* Fill in src buffers */
813 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
814 u8 *ptr = page_address(xor_srcs[src_idx]);
815
816 for (i = 0; i < PAGE_SIZE; i++)
817 ptr[i] = (1 << src_idx);
818 }
819
820 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
821 cmp_byte ^= (u8) (1 << src_idx);
822
823 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
824 (cmp_byte << 8) | cmp_byte;
825
826 memset(page_address(dest), 0, PAGE_SIZE);
827
828 dma_chan = container_of(dma->channels.next, struct dma_chan,
829 device_node);
830 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
831 err = -ENODEV;
832 goto out;
833 }
834
835 /* test xor */
836 op = IOAT_OP_XOR;
837
838 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7393fca9
PB		 839 if (dma_mapping_error(dev, dest_dma)) {
840 err = -ENOMEM;
2eab9b1a 841 goto free_resources;
7393fca9 842 }
c0f28ce6 843
c0f28ce6
DJ		 844 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
845 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
846 DMA_TO_DEVICE);
7393fca9
PB		 847 if (dma_mapping_error(dev, dma_srcs[i])) {
848 err = -ENOMEM;
c0f28ce6 849 goto dma_unmap;
7393fca9 850 }
c0f28ce6
DJ		 851 }
852 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
853 IOAT_NUM_SRC_TEST, PAGE_SIZE,
854 DMA_PREP_INTERRUPT);
855
856 if (!tx) {
857 dev_err(dev, "Self-test xor prep failed\n");
858 err = -ENODEV;
859 goto dma_unmap;
860 }
861
862 async_tx_ack(tx);
863 init_completion(&cmp);
3372de58 864 tx->callback = ioat_dma_test_callback;
c0f28ce6
DJ		 865 tx->callback_param = &cmp;
866 cookie = tx->tx_submit(tx);
867 if (cookie < 0) {
868 dev_err(dev, "Self-test xor setup failed\n");
869 err = -ENODEV;
870 goto dma_unmap;
871 }
872 dma->device_issue_pending(dma_chan);
873
874 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
875
876 if (tmo == 0 ||
877 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
878 dev_err(dev, "Self-test xor timed out\n");
879 err = -ENODEV;
880 goto dma_unmap;
881 }
882
883 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
884 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
885
886 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
887 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
888 u32 *ptr = page_address(dest);
889
890 if (ptr[i] != cmp_word) {
891 dev_err(dev, "Self-test xor failed compare\n");
892 err = -ENODEV;
893 goto free_resources;
894 }
895 }
896 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
897
898 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
899
900 /* skip validate if the capability is not present */
901 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
902 goto free_resources;
903
904 op = IOAT_OP_XOR_VAL;
905
906 /* validate the sources with the destintation page */
907 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
908 xor_val_srcs[i] = xor_srcs[i];
909 xor_val_srcs[i] = dest;
910
911 xor_val_result = 1;
912
c0f28ce6
DJ		 913 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
914 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
915 DMA_TO_DEVICE);
7393fca9
PB		 916 if (dma_mapping_error(dev, dma_srcs[i])) {
917 err = -ENOMEM;
c0f28ce6 918 goto dma_unmap;
7393fca9 919 }
c0f28ce6
DJ		 920 }
921 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
922 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
923 &xor_val_result, DMA_PREP_INTERRUPT);
924 if (!tx) {
925 dev_err(dev, "Self-test zero prep failed\n");
926 err = -ENODEV;
927 goto dma_unmap;
928 }
929
930 async_tx_ack(tx);
931 init_completion(&cmp);
3372de58 932 tx->callback = ioat_dma_test_callback;
c0f28ce6
DJ		 933 tx->callback_param = &cmp;
934 cookie = tx->tx_submit(tx);
935 if (cookie < 0) {
936 dev_err(dev, "Self-test zero setup failed\n");
937 err = -ENODEV;
938 goto dma_unmap;
939 }
940 dma->device_issue_pending(dma_chan);
941
942 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
943
944 if (tmo == 0 ||
945 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
946 dev_err(dev, "Self-test validate timed out\n");
947 err = -ENODEV;
948 goto dma_unmap;
949 }
950
951 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
952 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
953
954 if (xor_val_result != 0) {
955 dev_err(dev, "Self-test validate failed compare\n");
956 err = -ENODEV;
957 goto free_resources;
958 }
959
960 memset(page_address(dest), 0, PAGE_SIZE);
961
962 /* test for non-zero parity sum */
963 op = IOAT_OP_XOR_VAL;
964
965 xor_val_result = 0;
c0f28ce6
DJ		 966 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
967 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
968 DMA_TO_DEVICE);
7393fca9
PB		 969 if (dma_mapping_error(dev, dma_srcs[i])) {
970 err = -ENOMEM;
c0f28ce6 971 goto dma_unmap;
7393fca9 972 }
c0f28ce6
DJ		 973 }
974 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
975 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
976 &xor_val_result, DMA_PREP_INTERRUPT);
977 if (!tx) {
978 dev_err(dev, "Self-test 2nd zero prep failed\n");
979 err = -ENODEV;
980 goto dma_unmap;
981 }
982
983 async_tx_ack(tx);
984 init_completion(&cmp);
3372de58 985 tx->callback = ioat_dma_test_callback;
c0f28ce6
DJ		 986 tx->callback_param = &cmp;
987 cookie = tx->tx_submit(tx);
988 if (cookie < 0) {
989 dev_err(dev, "Self-test 2nd zero setup failed\n");
990 err = -ENODEV;
991 goto dma_unmap;
992 }
993 dma->device_issue_pending(dma_chan);
994
995 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
996
997 if (tmo == 0 ||
998 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
999 dev_err(dev, "Self-test 2nd validate timed out\n");
1000 err = -ENODEV;
1001 goto dma_unmap;
1002 }
1003
1004 if (xor_val_result != SUM_CHECK_P_RESULT) {
1005 dev_err(dev, "Self-test validate failed compare\n");
1006 err = -ENODEV;
1007 goto dma_unmap;
1008 }
1009
1010 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1011 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1012
1013 goto free_resources;
1014dma_unmap:
1015 if (op == IOAT_OP_XOR) {
e4734b3f
CH		 1016 while (--i >= 0)
1017 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1018 DMA_TO_DEVICE);
1019 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
c0f28ce6 1020 } else if (op == IOAT_OP_XOR_VAL) {
e4734b3f
CH		 1021 while (--i >= 0)
1022 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1023 DMA_TO_DEVICE);
c0f28ce6
DJ		 1024 }
1025free_resources:
1026 dma->device_free_chan_resources(dma_chan);
1027out:
1028 src_idx = IOAT_NUM_SRC_TEST;
1029 while (src_idx--)
1030 __free_page(xor_srcs[src_idx]);
1031 __free_page(dest);
1032 return err;
1033}
1034
1035static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1036{
64f1d0ff 1037 int rc;
c0f28ce6 1038
64f1d0ff 1039 rc = ioat_dma_self_test(ioat_dma);
c0f28ce6
DJ		 1040 if (rc)
1041 return rc;
1042
1043 rc = ioat_xor_val_self_test(ioat_dma);
c0f28ce6 1044
64f1d0ff 1045 return rc;
c0f28ce6
DJ		 1046}
1047
3372de58 1048static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
c0f28ce6
DJ		 1049{
1050 struct dma_device *dma;
1051 struct dma_chan *c;
1052 struct ioatdma_chan *ioat_chan;
1053 u32 errmask;
1054
1055 dma = &ioat_dma->dma_dev;
1056
1057 /*
1058 * if we have descriptor write back error status, we mask the
1059 * error interrupts
1060 */
1061 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1062 list_for_each_entry(c, &dma->channels, device_node) {
1063 ioat_chan = to_ioat_chan(c);
1064 errmask = readl(ioat_chan->reg_base +
1065 IOAT_CHANERR_MASK_OFFSET);
1066 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1067 IOAT_CHANERR_XOR_Q_ERR;
1068 writel(errmask, ioat_chan->reg_base +
1069 IOAT_CHANERR_MASK_OFFSET);
1070 }
1071 }
1072}
1073
599d49de 1074static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
c0f28ce6
DJ		 1075{
1076 struct pci_dev *pdev = ioat_dma->pdev;
1077 int dca_en = system_has_dca_enabled(pdev);
1078 struct dma_device *dma;
1079 struct dma_chan *c;
1080 struct ioatdma_chan *ioat_chan;
c0f28ce6 1081 int err;
511deae0 1082 u16 val16;
c0f28ce6 1083
c0f28ce6
DJ		 1084 dma = &ioat_dma->dma_dev;
1085 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1086 dma->device_issue_pending = ioat_issue_pending;
1087 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1088 dma->device_free_chan_resources = ioat_free_chan_resources;
1089
1090 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1091 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1092
1093 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1094
1095 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1096 ioat_dma->cap &=
1097 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1098
1099 /* dca is incompatible with raid operations */
1100 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1101 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1102
1103 if (ioat_dma->cap & IOAT_CAP_XOR) {
c0f28ce6
DJ		 1104 dma->max_xor = 8;
1105
1106 dma_cap_set(DMA_XOR, dma->cap_mask);
1107 dma->device_prep_dma_xor = ioat_prep_xor;
1108
1109 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1110 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1111 }
1112
1113 if (ioat_dma->cap & IOAT_CAP_PQ) {
c0f28ce6
DJ		 1114
1115 dma->device_prep_dma_pq = ioat_prep_pq;
1116 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1117 dma_cap_set(DMA_PQ, dma->cap_mask);
1118 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1119
1120 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1121 dma_set_maxpq(dma, 16, 0);
1122 else
1123 dma_set_maxpq(dma, 8, 0);
1124
1125 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1126 dma->device_prep_dma_xor = ioat_prep_pqxor;
1127 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1128 dma_cap_set(DMA_XOR, dma->cap_mask);
1129 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1130
1131 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1132 dma->max_xor = 16;
1133 else
1134 dma->max_xor = 8;
1135 }
1136 }
1137
1138 dma->device_tx_status = ioat_tx_status;
c0f28ce6
DJ		 1139
1140 /* starting with CB3.3 super extended descriptors are supported */
1141 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1142 char pool_name[14];
1143 int i;
1144
1145 for (i = 0; i < MAX_SED_POOLS; i++) {
1146 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1147
1148 /* allocate SED DMA pool */
1149 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1150 &pdev->dev,
1151 SED_SIZE * (i + 1), 64, 0);
1152 if (!ioat_dma->sed_hw_pool[i])
1153 return -ENOMEM;
1154
1155 }
1156 }
1157
1158 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1159 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1160
1161 err = ioat_probe(ioat_dma);
1162 if (err)
1163 return err;
1164
1165 list_for_each_entry(c, &dma->channels, device_node) {
1166 ioat_chan = to_ioat_chan(c);
1167 writel(IOAT_DMA_DCA_ANY_CPU,
1168 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1169 }
1170
1171 err = ioat_register(ioat_dma);
1172 if (err)
1173 return err;
1174
1175 ioat_kobject_add(ioat_dma, &ioat_ktype);
1176
1177 if (dca)
3372de58 1178 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
c0f28ce6 1179
511deae0
DJ		 1180 /* disable relaxed ordering */
1181 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
1182 if (err)
1183 return err;
1184
1185 /* clear relaxed ordering enable */
1186 val16 &= ~IOAT_DEVCTRL_ROE;
1187 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
1188 if (err)
1189 return err;
1190
c0f28ce6
DJ		 1191 return 0;
1192}
1193
ad4a7b50
DJ		 1194static void ioat_shutdown(struct pci_dev *pdev)
1195{
1196 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1197 struct ioatdma_chan *ioat_chan;
1198 int i;
1199
1200 if (!ioat_dma)
1201 return;
1202
1203 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1204 ioat_chan = ioat_dma->idx[i];
1205 if (!ioat_chan)
1206 continue;
1207
1208 spin_lock_bh(&ioat_chan->prep_lock);
1209 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
ad4a7b50 1210 spin_unlock_bh(&ioat_chan->prep_lock);
cfb03be6
WL		 1211 /*
1212 * Synchronization rule for del_timer_sync():
1213 * - The caller must not hold locks which would prevent
1214 * completion of the timer's handler.
1215 * So prep_lock cannot be held before calling it.
1216 */
1217 del_timer_sync(&ioat_chan->timer);
1218
ad4a7b50
DJ		 1219 /* this should quiesce then reset */
1220 ioat_reset_hw(ioat_chan);
1221 }
1222
1223 ioat_disable_interrupts(ioat_dma);
1224}
1225
184ff2aa 1226static void ioat_resume(struct ioatdma_device *ioat_dma)
4222a907
DJ		 1227{
1228 struct ioatdma_chan *ioat_chan;
1229 u32 chanerr;
1230 int i;
1231
1232 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1233 ioat_chan = ioat_dma->idx[i];
1234 if (!ioat_chan)
1235 continue;
1236
1237 spin_lock_bh(&ioat_chan->prep_lock);
1238 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1239 spin_unlock_bh(&ioat_chan->prep_lock);
1240
1241 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1242 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1243
1244 /* no need to reset as shutdown already did that */
1245 }
1246}
1247
c0f28ce6
DJ		 1248#define DRV_NAME "ioatdma"
1249
4222a907
DJ		 1250static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev,
1251 enum pci_channel_state error)
1252{
1253 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error);
1254
1255 /* quiesce and block I/O */
1256 ioat_shutdown(pdev);
1257
1258 return PCI_ERS_RESULT_NEED_RESET;
1259}
1260
1261static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev)
1262{
1263 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
4222a907
DJ		 1264
1265 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME);
1266
1267 if (pci_enable_device_mem(pdev) < 0) {
1268 dev_err(&pdev->dev,
1269 "Failed to enable PCIe device after reset.\n");
1270 result = PCI_ERS_RESULT_DISCONNECT;
1271 } else {
1272 pci_set_master(pdev);
1273 pci_restore_state(pdev);
1274 pci_save_state(pdev);
1275 pci_wake_from_d3(pdev, false);
1276 }
1277
4222a907
DJ		 1278 return result;
1279}
1280
1281static void ioat_pcie_error_resume(struct pci_dev *pdev)
1282{
1283 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1284
1285 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME);
1286
1287 /* initialize and bring everything back */
1288 ioat_resume(ioat_dma);
1289}
1290
1291static const struct pci_error_handlers ioat_err_handler = {
1292 .error_detected = ioat_pcie_error_detected,
1293 .slot_reset = ioat_pcie_error_slot_reset,
1294 .resume = ioat_pcie_error_resume,
1295};
1296
c0f28ce6
DJ		 1297static struct pci_driver ioat_pci_driver = {
1298 .name = DRV_NAME,
1299 .id_table = ioat_pci_tbl,
1300 .probe = ioat_pci_probe,
1301 .remove = ioat_remove,
ad4a7b50 1302 .shutdown = ioat_shutdown,
4222a907 1303 .err_handler = &ioat_err_handler,
c0f28ce6
DJ		 1304};
1305
1306static struct ioatdma_device *
1307alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1308{
1309 struct device *dev = &pdev->dev;
1310 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1311
1312 if (!d)
1313 return NULL;
1314 d->pdev = pdev;
1315 d->reg_base = iobase;
1316 return d;
1317}
1318
1319static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1320{
1321 void __iomem * const *iomap;
1322 struct device *dev = &pdev->dev;
1323 struct ioatdma_device *device;
1324 int err;
1325
1326 err = pcim_enable_device(pdev);
1327 if (err)
1328 return err;
1329
1330 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1331 if (err)
1332 return err;
1333 iomap = pcim_iomap_table(pdev);
1334 if (!iomap)
1335 return -ENOMEM;
1336
1337 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1338 if (err)
1339 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1340 if (err)
1341 return err;
1342
1343 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1344 if (err)
1345 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1346 if (err)
1347 return err;
1348
1349 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1350 if (!device)
1351 return -ENOMEM;
1352 pci_set_master(pdev);
1353 pci_set_drvdata(pdev, device);
1354
1355 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
4222a907 1356 if (device->version >= IOAT_VER_3_0) {
34a31f0a
DJ		 1357 if (is_skx_ioat(pdev))
1358 device->version = IOAT_VER_3_2;
c0f28ce6 1359 err = ioat3_dma_probe(device, ioat_dca_enabled);
4222a907
DJ		 1360
1361 if (device->version >= IOAT_VER_3_3)
1362 pci_enable_pcie_error_reporting(pdev);
1363 } else
c0f28ce6
DJ		 1364 return -ENODEV;
1365
1366 if (err) {
1367 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
4222a907 1368 pci_disable_pcie_error_reporting(pdev);
c0f28ce6
DJ		 1369 return -ENODEV;
1370 }
1371
1372 return 0;
1373}
1374
1375static void ioat_remove(struct pci_dev *pdev)
1376{
1377 struct ioatdma_device *device = pci_get_drvdata(pdev);
1378
1379 if (!device)
1380 return;
1381
1382 dev_err(&pdev->dev, "Removing dma and dca services\n");
1383 if (device->dca) {
1384 unregister_dca_provider(device->dca, &pdev->dev);
1385 free_dca_provider(device->dca);
1386 device->dca = NULL;
1387 }
4222a907
DJ		 1388
1389 pci_disable_pcie_error_reporting(pdev);
c0f28ce6
DJ		 1390 ioat_dma_remove(device);
1391}
1392
1393static int __init ioat_init_module(void)
1394{
1395 int err = -ENOMEM;
1396
1397 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1398 DRV_NAME, IOAT_DMA_VERSION);
1399
1400 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1401 0, SLAB_HWCACHE_ALIGN, NULL);
1402 if (!ioat_cache)
1403 return -ENOMEM;
1404
1405 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1406 if (!ioat_sed_cache)
1407 goto err_ioat_cache;
1408
1409 err = pci_register_driver(&ioat_pci_driver);
1410 if (err)
1411 goto err_ioat3_cache;
1412
1413 return 0;
1414
1415 err_ioat3_cache:
1416 kmem_cache_destroy(ioat_sed_cache);
1417
1418 err_ioat_cache:
1419 kmem_cache_destroy(ioat_cache);
1420
1421 return err;
1422}
1423module_init(ioat_init_module);
1424
1425static void __exit ioat_exit_module(void)
1426{
1427 pci_unregister_driver(&ioat_pci_driver);
1428 kmem_cache_destroy(ioat_cache);
1429}
1430module_exit(ioat_exit_module);
Linux 6.x block layer and io_uring tree(s)