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0bbd5f4e | 1 | /* |
211a22ce | 2 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
0bbd5f4e CL |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef _IOAT_HW_H_ | |
22 | #define _IOAT_HW_H_ | |
23 | ||
24 | /* PCI Configuration Space Values */ | |
7bb67c14 | 25 | #define IOAT_PCI_VID 0x8086 |
e6c0b69a | 26 | #define IOAT_MMIO_BAR 0 |
7bb67c14 SN |
27 | |
28 | /* CB device ID's */ | |
29 | #define IOAT_PCI_DID_5000 0x1A38 | |
30 | #define IOAT_PCI_DID_CNB 0x360B | |
31 | #define IOAT_PCI_DID_SCNB 0x65FF | |
32 | #define IOAT_PCI_DID_SNB 0x402F | |
33 | ||
34 | #define IOAT_PCI_RID 0x00 | |
35 | #define IOAT_PCI_SVID 0x8086 | |
36 | #define IOAT_PCI_SID 0x8086 | |
37 | #define IOAT_VER_1_2 0x12 /* Version 1.2 */ | |
38 | #define IOAT_VER_2_0 0x20 /* Version 2.0 */ | |
7f1b358a | 39 | #define IOAT_VER_3_0 0x30 /* Version 3.0 */ |
2aec048c | 40 | #define IOAT_VER_3_2 0x32 /* Version 3.2 */ |
0bbd5f4e | 41 | |
228c4f5c DW |
42 | int system_has_dca_enabled(struct pci_dev *pdev); |
43 | ||
0bbd5f4e CL |
44 | struct ioat_dma_descriptor { |
45 | uint32_t size; | |
c7984f4e DW |
46 | union { |
47 | uint32_t ctl; | |
48 | struct { | |
49 | unsigned int int_en:1; | |
50 | unsigned int src_snoop_dis:1; | |
51 | unsigned int dest_snoop_dis:1; | |
52 | unsigned int compl_write:1; | |
53 | unsigned int fence:1; | |
54 | unsigned int null:1; | |
55 | unsigned int src_brk:1; | |
56 | unsigned int dest_brk:1; | |
57 | unsigned int bundle:1; | |
58 | unsigned int dest_dca:1; | |
59 | unsigned int hint:1; | |
60 | unsigned int rsvd2:13; | |
2aec048c | 61 | #define IOAT_OP_COPY 0x00 |
c7984f4e DW |
62 | unsigned int op:8; |
63 | } ctl_f; | |
64 | }; | |
0bbd5f4e CL |
65 | uint64_t src_addr; |
66 | uint64_t dst_addr; | |
67 | uint64_t next; | |
68 | uint64_t rsv1; | |
69 | uint64_t rsv2; | |
ad643f54 DW |
70 | /* store some driver data in an unused portion of the descriptor */ |
71 | union { | |
72 | uint64_t user1; | |
73 | uint64_t tx_cnt; | |
74 | }; | |
0bbd5f4e CL |
75 | uint64_t user2; |
76 | }; | |
2aec048c DW |
77 | |
78 | struct ioat_fill_descriptor { | |
79 | uint32_t size; | |
80 | union { | |
81 | uint32_t ctl; | |
82 | struct { | |
83 | unsigned int int_en:1; | |
84 | unsigned int rsvd:1; | |
85 | unsigned int dest_snoop_dis:1; | |
86 | unsigned int compl_write:1; | |
87 | unsigned int fence:1; | |
88 | unsigned int rsvd2:2; | |
89 | unsigned int dest_brk:1; | |
90 | unsigned int bundle:1; | |
91 | unsigned int rsvd4:15; | |
92 | #define IOAT_OP_FILL 0x01 | |
93 | unsigned int op:8; | |
94 | } ctl_f; | |
95 | }; | |
96 | uint64_t src_data; | |
97 | uint64_t dst_addr; | |
98 | uint64_t next; | |
99 | uint64_t rsv1; | |
100 | uint64_t next_dst_addr; | |
101 | uint64_t user1; | |
102 | uint64_t user2; | |
103 | }; | |
104 | ||
105 | struct ioat_xor_descriptor { | |
106 | uint32_t size; | |
107 | union { | |
108 | uint32_t ctl; | |
109 | struct { | |
110 | unsigned int int_en:1; | |
111 | unsigned int src_snoop_dis:1; | |
112 | unsigned int dest_snoop_dis:1; | |
113 | unsigned int compl_write:1; | |
114 | unsigned int fence:1; | |
115 | unsigned int src_cnt:3; | |
116 | unsigned int bundle:1; | |
117 | unsigned int dest_dca:1; | |
118 | unsigned int hint:1; | |
119 | unsigned int rsvd:13; | |
120 | #define IOAT_OP_XOR 0x87 | |
121 | #define IOAT_OP_XOR_VAL 0x88 | |
122 | unsigned int op:8; | |
123 | } ctl_f; | |
124 | }; | |
125 | uint64_t src_addr; | |
126 | uint64_t dst_addr; | |
127 | uint64_t next; | |
128 | uint64_t src_addr2; | |
129 | uint64_t src_addr3; | |
130 | uint64_t src_addr4; | |
131 | uint64_t src_addr5; | |
132 | }; | |
133 | ||
134 | struct ioat_xor_ext_descriptor { | |
135 | uint64_t src_addr6; | |
136 | uint64_t src_addr7; | |
137 | uint64_t src_addr8; | |
138 | uint64_t next; | |
139 | uint64_t rsvd[4]; | |
140 | }; | |
141 | ||
142 | struct ioat_pq_descriptor { | |
143 | uint32_t size; | |
144 | union { | |
145 | uint32_t ctl; | |
146 | struct { | |
147 | unsigned int int_en:1; | |
148 | unsigned int src_snoop_dis:1; | |
149 | unsigned int dest_snoop_dis:1; | |
150 | unsigned int compl_write:1; | |
151 | unsigned int fence:1; | |
152 | unsigned int src_cnt:3; | |
153 | unsigned int bundle:1; | |
154 | unsigned int dest_dca:1; | |
155 | unsigned int hint:1; | |
156 | unsigned int p_disable:1; | |
157 | unsigned int q_disable:1; | |
158 | unsigned int rsvd:11; | |
159 | #define IOAT_OP_PQ 0x89 | |
160 | #define IOAT_OP_PQ_VAL 0x8a | |
161 | unsigned int op:8; | |
162 | } ctl_f; | |
163 | }; | |
164 | uint64_t src_addr; | |
165 | uint64_t p_addr; | |
166 | uint64_t next; | |
167 | uint64_t src_addr2; | |
168 | uint64_t src_addr3; | |
169 | uint8_t coef[8]; | |
170 | uint64_t q_addr; | |
171 | }; | |
172 | ||
173 | struct ioat_pq_ext_descriptor { | |
174 | uint64_t src_addr4; | |
175 | uint64_t src_addr5; | |
176 | uint64_t src_addr6; | |
177 | uint64_t next; | |
178 | uint64_t src_addr7; | |
179 | uint64_t src_addr8; | |
180 | uint64_t rsvd[2]; | |
181 | }; | |
182 | ||
183 | struct ioat_pq_update_descriptor { | |
184 | uint32_t size; | |
185 | union { | |
186 | uint32_t ctl; | |
187 | struct { | |
188 | unsigned int int_en:1; | |
189 | unsigned int src_snoop_dis:1; | |
190 | unsigned int dest_snoop_dis:1; | |
191 | unsigned int compl_write:1; | |
192 | unsigned int fence:1; | |
193 | unsigned int src_cnt:3; | |
194 | unsigned int bundle:1; | |
195 | unsigned int dest_dca:1; | |
196 | unsigned int hint:1; | |
197 | unsigned int p_disable:1; | |
198 | unsigned int q_disable:1; | |
199 | unsigned int rsvd:3; | |
200 | unsigned int coef:8; | |
201 | #define IOAT_OP_PQ_UP 0x8b | |
202 | unsigned int op:8; | |
203 | } ctl_f; | |
204 | }; | |
205 | uint64_t src_addr; | |
206 | uint64_t p_addr; | |
207 | uint64_t next; | |
208 | uint64_t src_addr2; | |
209 | uint64_t p_src; | |
210 | uint64_t q_src; | |
211 | uint64_t q_addr; | |
212 | }; | |
213 | ||
214 | struct ioat_raw_descriptor { | |
215 | uint64_t field[8]; | |
216 | }; | |
0bbd5f4e | 217 | #endif |