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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
58 | ||
59 | #include <linux/pci.h> | |
60 | #include <linux/dmaengine.h> | |
61 | #include <linux/dma-mapping.h> | |
62 | #include "registers.h" | |
63 | #include "hw.h" | |
64 | #include "dma.h" | |
65 | #include "dma_v2.h" | |
66 | ||
b094ad3b DW |
67 | /* ioat hardware assumes at least two sources for raid operations */ |
68 | #define src_cnt_to_sw(x) ((x) + 2) | |
69 | #define src_cnt_to_hw(x) ((x) - 2) | |
70 | ||
71 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 72 | * extended descriptor of an xor or pq descriptor |
b094ad3b DW |
73 | */ |
74 | static const u8 xor_idx_to_desc __read_mostly = 0xd0; | |
75 | static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 }; | |
d69d235b DW |
76 | static const u8 pq_idx_to_desc __read_mostly = 0xf8; |
77 | static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 }; | |
b094ad3b DW |
78 | |
79 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) | |
80 | { | |
81 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
82 | ||
83 | return raw->field[xor_idx_to_field[idx]]; | |
84 | } | |
85 | ||
86 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], | |
87 | dma_addr_t addr, u32 offset, int idx) | |
88 | { | |
89 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
90 | ||
91 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
92 | } | |
93 | ||
d69d235b DW |
94 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
95 | { | |
96 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
97 | ||
98 | return raw->field[pq_idx_to_field[idx]]; | |
99 | } | |
100 | ||
101 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], | |
102 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
103 | { | |
104 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
105 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
106 | ||
107 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
108 | pq->coef[idx] = coef; | |
109 | } | |
110 | ||
bf40a686 | 111 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
b094ad3b | 112 | struct ioat_ring_ent *desc, int idx) |
bf40a686 DW |
113 | { |
114 | struct ioat_chan_common *chan = &ioat->base; | |
115 | struct pci_dev *pdev = chan->device->pdev; | |
116 | size_t len = desc->len; | |
117 | size_t offset = len - desc->hw->size; | |
118 | struct dma_async_tx_descriptor *tx = &desc->txd; | |
119 | enum dma_ctrl_flags flags = tx->flags; | |
120 | ||
121 | switch (desc->hw->ctl_f.op) { | |
122 | case IOAT_OP_COPY: | |
58c8649e DW |
123 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
124 | ioat_dma_unmap(chan, flags, len, desc->hw); | |
bf40a686 DW |
125 | break; |
126 | case IOAT_OP_FILL: { | |
127 | struct ioat_fill_descriptor *hw = desc->fill; | |
128 | ||
129 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
130 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
131 | PCI_DMA_FROMDEVICE, flags, 1); | |
132 | break; | |
133 | } | |
b094ad3b DW |
134 | case IOAT_OP_XOR_VAL: |
135 | case IOAT_OP_XOR: { | |
136 | struct ioat_xor_descriptor *xor = desc->xor; | |
137 | struct ioat_ring_ent *ext; | |
138 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
139 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); | |
140 | struct ioat_raw_descriptor *descs[2]; | |
141 | int i; | |
142 | ||
143 | if (src_cnt > 5) { | |
144 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
145 | xor_ex = ext->xor_ex; | |
146 | } | |
147 | ||
148 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
149 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
150 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
151 | for (i = 0; i < src_cnt; i++) { | |
152 | dma_addr_t src = xor_get_src(descs, i); | |
153 | ||
154 | ioat_unmap(pdev, src - offset, len, | |
155 | PCI_DMA_TODEVICE, flags, 0); | |
156 | } | |
157 | ||
158 | /* dest is a source in xor validate operations */ | |
159 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { | |
160 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
161 | PCI_DMA_TODEVICE, flags, 1); | |
162 | break; | |
163 | } | |
164 | } | |
165 | ||
166 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
167 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
168 | PCI_DMA_FROMDEVICE, flags, 1); | |
169 | break; | |
170 | } | |
d69d235b DW |
171 | case IOAT_OP_PQ_VAL: |
172 | case IOAT_OP_PQ: { | |
173 | struct ioat_pq_descriptor *pq = desc->pq; | |
174 | struct ioat_ring_ent *ext; | |
175 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
176 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
177 | struct ioat_raw_descriptor *descs[2]; | |
178 | int i; | |
179 | ||
180 | if (src_cnt > 3) { | |
181 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
182 | pq_ex = ext->pq_ex; | |
183 | } | |
184 | ||
185 | /* in the 'continue' case don't unmap the dests as sources */ | |
186 | if (dmaf_p_disabled_continue(flags)) | |
187 | src_cnt--; | |
188 | else if (dmaf_continue(flags)) | |
189 | src_cnt -= 3; | |
190 | ||
191 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
192 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
193 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
194 | for (i = 0; i < src_cnt; i++) { | |
195 | dma_addr_t src = pq_get_src(descs, i); | |
196 | ||
197 | ioat_unmap(pdev, src - offset, len, | |
198 | PCI_DMA_TODEVICE, flags, 0); | |
199 | } | |
200 | ||
201 | /* the dests are sources in pq validate operations */ | |
202 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
203 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
204 | ioat_unmap(pdev, pq->p_addr - offset, | |
205 | len, PCI_DMA_TODEVICE, flags, 0); | |
206 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
207 | ioat_unmap(pdev, pq->q_addr - offset, | |
208 | len, PCI_DMA_TODEVICE, flags, 0); | |
209 | break; | |
210 | } | |
211 | } | |
212 | ||
213 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
214 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
215 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
216 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
217 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
218 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
219 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
220 | } | |
221 | break; | |
222 | } | |
bf40a686 DW |
223 | default: |
224 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", | |
225 | __func__, desc->hw->ctl_f.op); | |
226 | } | |
227 | } | |
228 | ||
b094ad3b DW |
229 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
230 | { | |
231 | struct ioat_dma_descriptor *hw = desc->hw; | |
232 | ||
233 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
234 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
235 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 236 | |
b094ad3b DW |
237 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
238 | return true; | |
d69d235b DW |
239 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
240 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
241 | struct ioat_pq_descriptor *pq = desc->pq; | |
242 | ||
243 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
244 | return true; | |
b094ad3b DW |
245 | } |
246 | ||
247 | return false; | |
248 | } | |
249 | ||
250 | /** | |
251 | * __cleanup - reclaim used descriptors | |
252 | * @ioat: channel (ring) to clean | |
253 | * | |
254 | * The difference from the dma_v2.c __cleanup() is that this routine | |
255 | * handles extended descriptors and dma-unmapping raid operations. | |
256 | */ | |
bf40a686 DW |
257 | static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) |
258 | { | |
259 | struct ioat_chan_common *chan = &ioat->base; | |
260 | struct ioat_ring_ent *desc; | |
261 | bool seen_current = false; | |
262 | u16 active; | |
263 | int i; | |
264 | ||
265 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
266 | __func__, ioat->head, ioat->tail, ioat->issued); | |
267 | ||
268 | active = ioat2_ring_active(ioat); | |
269 | for (i = 0; i < active && !seen_current; i++) { | |
270 | struct dma_async_tx_descriptor *tx; | |
271 | ||
272 | prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); | |
273 | desc = ioat2_get_ring_ent(ioat, ioat->tail + i); | |
274 | dump_desc_dbg(ioat, desc); | |
275 | tx = &desc->txd; | |
276 | if (tx->cookie) { | |
277 | chan->completed_cookie = tx->cookie; | |
b094ad3b | 278 | ioat3_dma_unmap(ioat, desc, ioat->tail + i); |
bf40a686 DW |
279 | tx->cookie = 0; |
280 | if (tx->callback) { | |
281 | tx->callback(tx->callback_param); | |
282 | tx->callback = NULL; | |
283 | } | |
284 | } | |
285 | ||
286 | if (tx->phys == phys_complete) | |
287 | seen_current = true; | |
b094ad3b DW |
288 | |
289 | /* skip extended descriptors */ | |
290 | if (desc_has_ext(desc)) { | |
291 | BUG_ON(i + 1 >= active); | |
292 | i++; | |
293 | } | |
bf40a686 DW |
294 | } |
295 | ioat->tail += i; | |
296 | BUG_ON(!seen_current); /* no active descs have written a completion? */ | |
297 | chan->last_completion = phys_complete; | |
298 | if (ioat->head == ioat->tail) { | |
299 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", | |
300 | __func__); | |
301 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
302 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
303 | } | |
304 | } | |
305 | ||
306 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) | |
307 | { | |
308 | struct ioat_chan_common *chan = &ioat->base; | |
309 | unsigned long phys_complete; | |
310 | ||
311 | prefetch(chan->completion); | |
312 | ||
313 | if (!spin_trylock_bh(&chan->cleanup_lock)) | |
314 | return; | |
315 | ||
316 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { | |
317 | spin_unlock_bh(&chan->cleanup_lock); | |
318 | return; | |
319 | } | |
320 | ||
321 | if (!spin_trylock_bh(&ioat->ring_lock)) { | |
322 | spin_unlock_bh(&chan->cleanup_lock); | |
323 | return; | |
324 | } | |
325 | ||
326 | __cleanup(ioat, phys_complete); | |
327 | ||
328 | spin_unlock_bh(&ioat->ring_lock); | |
329 | spin_unlock_bh(&chan->cleanup_lock); | |
330 | } | |
331 | ||
332 | static void ioat3_cleanup_tasklet(unsigned long data) | |
333 | { | |
334 | struct ioat2_dma_chan *ioat = (void *) data; | |
335 | ||
336 | ioat3_cleanup(ioat); | |
773d9e2d | 337 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
bf40a686 DW |
338 | } |
339 | ||
340 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
341 | { | |
342 | struct ioat_chan_common *chan = &ioat->base; | |
343 | unsigned long phys_complete; | |
bf40a686 | 344 | |
b372ec2d | 345 | ioat2_quiesce(chan, 0); |
bf40a686 DW |
346 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
347 | __cleanup(ioat, phys_complete); | |
348 | ||
349 | __ioat2_restart_chan(ioat); | |
350 | } | |
351 | ||
352 | static void ioat3_timer_event(unsigned long data) | |
353 | { | |
354 | struct ioat2_dma_chan *ioat = (void *) data; | |
355 | struct ioat_chan_common *chan = &ioat->base; | |
356 | ||
357 | spin_lock_bh(&chan->cleanup_lock); | |
358 | if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { | |
359 | unsigned long phys_complete; | |
360 | u64 status; | |
361 | ||
362 | spin_lock_bh(&ioat->ring_lock); | |
363 | status = ioat_chansts(chan); | |
364 | ||
365 | /* when halted due to errors check for channel | |
366 | * programming errors before advancing the completion state | |
367 | */ | |
368 | if (is_ioat_halted(status)) { | |
369 | u32 chanerr; | |
370 | ||
371 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
b57014de DW |
372 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", |
373 | __func__, chanerr); | |
bf40a686 DW |
374 | BUG_ON(is_ioat_bug(chanerr)); |
375 | } | |
376 | ||
377 | /* if we haven't made progress and we have already | |
378 | * acknowledged a pending completion once, then be more | |
379 | * forceful with a restart | |
380 | */ | |
381 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
382 | __cleanup(ioat, phys_complete); | |
383 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) | |
384 | ioat3_restart_channel(ioat); | |
385 | else { | |
386 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
387 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
388 | } | |
389 | spin_unlock_bh(&ioat->ring_lock); | |
390 | } else { | |
391 | u16 active; | |
392 | ||
393 | /* if the ring is idle, empty, and oversized try to step | |
394 | * down the size | |
395 | */ | |
396 | spin_lock_bh(&ioat->ring_lock); | |
397 | active = ioat2_ring_active(ioat); | |
398 | if (active == 0 && ioat->alloc_order > ioat_get_alloc_order()) | |
399 | reshape_ring(ioat, ioat->alloc_order-1); | |
400 | spin_unlock_bh(&ioat->ring_lock); | |
401 | ||
402 | /* keep shrinking until we get back to our minimum | |
403 | * default size | |
404 | */ | |
405 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
406 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
407 | } | |
408 | spin_unlock_bh(&chan->cleanup_lock); | |
409 | } | |
410 | ||
411 | static enum dma_status | |
412 | ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie, | |
413 | dma_cookie_t *done, dma_cookie_t *used) | |
414 | { | |
415 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
416 | ||
417 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) | |
418 | return DMA_SUCCESS; | |
419 | ||
420 | ioat3_cleanup(ioat); | |
421 | ||
422 | return ioat_is_complete(c, cookie, done, used); | |
423 | } | |
424 | ||
425 | static struct dma_async_tx_descriptor * | |
426 | ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, | |
427 | size_t len, unsigned long flags) | |
428 | { | |
429 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
430 | struct ioat_ring_ent *desc; | |
431 | size_t total_len = len; | |
432 | struct ioat_fill_descriptor *fill; | |
433 | int num_descs; | |
434 | u64 src_data = (0x0101010101010101ULL) * (value & 0xff); | |
435 | u16 idx; | |
436 | int i; | |
437 | ||
438 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
439 | if (likely(num_descs) && | |
440 | ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0) | |
441 | /* pass */; | |
442 | else | |
443 | return NULL; | |
cdef57db DW |
444 | i = 0; |
445 | do { | |
bf40a686 DW |
446 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
447 | ||
448 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
449 | fill = desc->fill; | |
450 | ||
451 | fill->size = xfer_size; | |
452 | fill->src_data = src_data; | |
453 | fill->dst_addr = dest; | |
454 | fill->ctl = 0; | |
455 | fill->ctl_f.op = IOAT_OP_FILL; | |
456 | ||
457 | len -= xfer_size; | |
458 | dest += xfer_size; | |
459 | dump_desc_dbg(ioat, desc); | |
cdef57db | 460 | } while (++i < num_descs); |
bf40a686 DW |
461 | |
462 | desc->txd.flags = flags; | |
463 | desc->len = total_len; | |
464 | fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
465 | fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
466 | fill->ctl_f.compl_write = 1; | |
467 | dump_desc_dbg(ioat, desc); | |
468 | ||
469 | /* we leave the channel locked to ensure in order submission */ | |
470 | return &desc->txd; | |
471 | } | |
472 | ||
b094ad3b DW |
473 | static struct dma_async_tx_descriptor * |
474 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
475 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
476 | size_t len, unsigned long flags) | |
477 | { | |
478 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
479 | struct ioat_ring_ent *compl_desc; | |
480 | struct ioat_ring_ent *desc; | |
481 | struct ioat_ring_ent *ext; | |
482 | size_t total_len = len; | |
483 | struct ioat_xor_descriptor *xor; | |
484 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
485 | struct ioat_dma_descriptor *hw; | |
486 | u32 offset = 0; | |
487 | int num_descs; | |
488 | int with_ext; | |
489 | int i; | |
490 | u16 idx; | |
491 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; | |
492 | ||
493 | BUG_ON(src_cnt < 2); | |
494 | ||
495 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
496 | /* we need 2x the number of descriptors to cover greater than 5 | |
497 | * sources | |
498 | */ | |
499 | if (src_cnt > 5) { | |
500 | with_ext = 1; | |
501 | num_descs *= 2; | |
502 | } else | |
503 | with_ext = 0; | |
504 | ||
505 | /* completion writes from the raid engine may pass completion | |
506 | * writes from the legacy engine, so we need one extra null | |
507 | * (legacy) descriptor to ensure all completion writes arrive in | |
508 | * order. | |
509 | */ | |
510 | if (likely(num_descs) && | |
511 | ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) | |
512 | /* pass */; | |
513 | else | |
514 | return NULL; | |
cdef57db DW |
515 | i = 0; |
516 | do { | |
b094ad3b DW |
517 | struct ioat_raw_descriptor *descs[2]; |
518 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
519 | int s; | |
520 | ||
521 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
522 | xor = desc->xor; | |
523 | ||
524 | /* save a branch by unconditionally retrieving the | |
525 | * extended descriptor xor_set_src() knows to not write | |
526 | * to it in the single descriptor case | |
527 | */ | |
528 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
529 | xor_ex = ext->xor_ex; | |
530 | ||
531 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
532 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
533 | for (s = 0; s < src_cnt; s++) | |
534 | xor_set_src(descs, src[s], offset, s); | |
535 | xor->size = xfer_size; | |
536 | xor->dst_addr = dest + offset; | |
537 | xor->ctl = 0; | |
538 | xor->ctl_f.op = op; | |
539 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
540 | ||
541 | len -= xfer_size; | |
542 | offset += xfer_size; | |
543 | dump_desc_dbg(ioat, desc); | |
cdef57db | 544 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
545 | |
546 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
547 | desc->txd.flags = flags; | |
548 | desc->len = total_len; | |
549 | if (result) | |
550 | desc->result = result; | |
551 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
552 | ||
553 | /* completion descriptor carries interrupt bit */ | |
554 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
555 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
556 | hw = compl_desc->hw; | |
557 | hw->ctl = 0; | |
558 | hw->ctl_f.null = 1; | |
559 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
560 | hw->ctl_f.compl_write = 1; | |
561 | hw->size = NULL_DESC_BUFFER_SIZE; | |
562 | dump_desc_dbg(ioat, compl_desc); | |
563 | ||
564 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 565 | return &compl_desc->txd; |
b094ad3b DW |
566 | } |
567 | ||
568 | static struct dma_async_tx_descriptor * | |
569 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
570 | unsigned int src_cnt, size_t len, unsigned long flags) | |
571 | { | |
572 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
573 | } | |
574 | ||
575 | struct dma_async_tx_descriptor * | |
576 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
577 | unsigned int src_cnt, size_t len, | |
578 | enum sum_check_flags *result, unsigned long flags) | |
579 | { | |
580 | /* the cleanup routine only sets bits on validate failure, it | |
581 | * does not clear bits on validate success... so clear it here | |
582 | */ | |
583 | *result = 0; | |
584 | ||
585 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
586 | src_cnt - 1, len, flags); | |
587 | } | |
588 | ||
d69d235b DW |
589 | static void |
590 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
591 | { | |
592 | struct device *dev = to_dev(&ioat->base); | |
593 | struct ioat_pq_descriptor *pq = desc->pq; | |
594 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
595 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
596 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
597 | int i; | |
598 | ||
599 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
600 | " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n", | |
601 | desc_id(desc), (unsigned long long) desc->txd.phys, | |
602 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
603 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
604 | pq->ctl_f.compl_write, | |
605 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
606 | pq->ctl_f.src_cnt); | |
607 | for (i = 0; i < src_cnt; i++) | |
608 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
609 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
610 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
611 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
612 | } | |
613 | ||
614 | static struct dma_async_tx_descriptor * | |
615 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
616 | const dma_addr_t *dst, const dma_addr_t *src, | |
617 | unsigned int src_cnt, const unsigned char *scf, | |
618 | size_t len, unsigned long flags) | |
619 | { | |
620 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
621 | struct ioat_chan_common *chan = &ioat->base; | |
622 | struct ioat_ring_ent *compl_desc; | |
623 | struct ioat_ring_ent *desc; | |
624 | struct ioat_ring_ent *ext; | |
625 | size_t total_len = len; | |
626 | struct ioat_pq_descriptor *pq; | |
627 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
628 | struct ioat_dma_descriptor *hw; | |
629 | u32 offset = 0; | |
630 | int num_descs; | |
631 | int with_ext; | |
632 | int i, s; | |
633 | u16 idx; | |
634 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; | |
635 | ||
636 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
637 | /* the engine requires at least two sources (we provide | |
638 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
639 | */ | |
640 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
641 | ||
642 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
643 | /* we need 2x the number of descriptors to cover greater than 3 | |
cd78809f DW |
644 | * sources (we need 1 extra source in the q-only continuation |
645 | * case and 3 extra sources in the p+q continuation case. | |
d69d235b | 646 | */ |
cd78809f DW |
647 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
648 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { | |
d69d235b DW |
649 | with_ext = 1; |
650 | num_descs *= 2; | |
651 | } else | |
652 | with_ext = 0; | |
653 | ||
654 | /* completion writes from the raid engine may pass completion | |
655 | * writes from the legacy engine, so we need one extra null | |
656 | * (legacy) descriptor to ensure all completion writes arrive in | |
657 | * order. | |
658 | */ | |
659 | if (likely(num_descs) && | |
660 | ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) | |
661 | /* pass */; | |
662 | else | |
663 | return NULL; | |
cdef57db DW |
664 | i = 0; |
665 | do { | |
d69d235b DW |
666 | struct ioat_raw_descriptor *descs[2]; |
667 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
668 | ||
669 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
670 | pq = desc->pq; | |
671 | ||
672 | /* save a branch by unconditionally retrieving the | |
673 | * extended descriptor pq_set_src() knows to not write | |
674 | * to it in the single descriptor case | |
675 | */ | |
676 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
677 | pq_ex = ext->pq_ex; | |
678 | ||
679 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
680 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
681 | ||
682 | for (s = 0; s < src_cnt; s++) | |
683 | pq_set_src(descs, src[s], offset, scf[s], s); | |
684 | ||
685 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
686 | if (dmaf_p_disabled_continue(flags)) | |
687 | pq_set_src(descs, dst[1], offset, 1, s++); | |
688 | else if (dmaf_continue(flags)) { | |
689 | pq_set_src(descs, dst[0], offset, 0, s++); | |
690 | pq_set_src(descs, dst[1], offset, 1, s++); | |
691 | pq_set_src(descs, dst[1], offset, 0, s++); | |
692 | } | |
693 | pq->size = xfer_size; | |
694 | pq->p_addr = dst[0] + offset; | |
695 | pq->q_addr = dst[1] + offset; | |
696 | pq->ctl = 0; | |
697 | pq->ctl_f.op = op; | |
698 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); | |
699 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
700 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
701 | ||
702 | len -= xfer_size; | |
703 | offset += xfer_size; | |
cdef57db | 704 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
705 | |
706 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
707 | desc->txd.flags = flags; | |
708 | desc->len = total_len; | |
709 | if (result) | |
710 | desc->result = result; | |
711 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
712 | dump_pq_desc_dbg(ioat, desc, ext); | |
713 | ||
714 | /* completion descriptor carries interrupt bit */ | |
715 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
716 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
717 | hw = compl_desc->hw; | |
718 | hw->ctl = 0; | |
719 | hw->ctl_f.null = 1; | |
720 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
721 | hw->ctl_f.compl_write = 1; | |
722 | hw->size = NULL_DESC_BUFFER_SIZE; | |
723 | dump_desc_dbg(ioat, compl_desc); | |
724 | ||
725 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 726 | return &compl_desc->txd; |
d69d235b DW |
727 | } |
728 | ||
729 | static struct dma_async_tx_descriptor * | |
730 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
731 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
732 | unsigned long flags) | |
733 | { | |
de581b65 DW |
734 | /* specify valid address for disabled result */ |
735 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
736 | dst[0] = dst[1]; | |
737 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
738 | dst[1] = dst[0]; | |
739 | ||
d69d235b DW |
740 | /* handle the single source multiply case from the raid6 |
741 | * recovery path | |
742 | */ | |
de581b65 | 743 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
744 | dma_addr_t single_source[2]; |
745 | unsigned char single_source_coef[2]; | |
746 | ||
747 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
748 | single_source[0] = src[0]; | |
749 | single_source[1] = src[0]; | |
750 | single_source_coef[0] = scf[0]; | |
751 | single_source_coef[1] = 0; | |
752 | ||
753 | return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
754 | single_source_coef, len, flags); | |
755 | } else | |
756 | return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf, | |
757 | len, flags); | |
758 | } | |
759 | ||
760 | struct dma_async_tx_descriptor * | |
761 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
762 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
763 | enum sum_check_flags *pqres, unsigned long flags) | |
764 | { | |
de581b65 DW |
765 | /* specify valid address for disabled result */ |
766 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
767 | pq[0] = pq[1]; | |
768 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
769 | pq[1] = pq[0]; | |
770 | ||
d69d235b DW |
771 | /* the cleanup routine only sets bits on validate failure, it |
772 | * does not clear bits on validate success... so clear it here | |
773 | */ | |
774 | *pqres = 0; | |
775 | ||
776 | return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
777 | flags); | |
778 | } | |
779 | ||
ae786624 DW |
780 | static struct dma_async_tx_descriptor * |
781 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
782 | unsigned int src_cnt, size_t len, unsigned long flags) | |
783 | { | |
784 | unsigned char scf[src_cnt]; | |
785 | dma_addr_t pq[2]; | |
786 | ||
787 | memset(scf, 0, src_cnt); | |
ae786624 | 788 | pq[0] = dst; |
de581b65 DW |
789 | flags |= DMA_PREP_PQ_DISABLE_Q; |
790 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 DW |
791 | |
792 | return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
793 | flags); | |
794 | } | |
795 | ||
796 | struct dma_async_tx_descriptor * | |
797 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
798 | unsigned int src_cnt, size_t len, | |
799 | enum sum_check_flags *result, unsigned long flags) | |
800 | { | |
801 | unsigned char scf[src_cnt]; | |
802 | dma_addr_t pq[2]; | |
803 | ||
804 | /* the cleanup routine only sets bits on validate failure, it | |
805 | * does not clear bits on validate success... so clear it here | |
806 | */ | |
807 | *result = 0; | |
808 | ||
809 | memset(scf, 0, src_cnt); | |
ae786624 | 810 | pq[0] = src[0]; |
de581b65 DW |
811 | flags |= DMA_PREP_PQ_DISABLE_Q; |
812 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 DW |
813 | |
814 | return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf, | |
815 | len, flags); | |
816 | } | |
817 | ||
58c8649e DW |
818 | static struct dma_async_tx_descriptor * |
819 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
820 | { | |
821 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
822 | struct ioat_ring_ent *desc; | |
823 | struct ioat_dma_descriptor *hw; | |
824 | u16 idx; | |
825 | ||
826 | if (ioat2_alloc_and_lock(&idx, ioat, 1) == 0) | |
827 | desc = ioat2_get_ring_ent(ioat, idx); | |
828 | else | |
829 | return NULL; | |
830 | ||
831 | hw = desc->hw; | |
832 | hw->ctl = 0; | |
833 | hw->ctl_f.null = 1; | |
834 | hw->ctl_f.int_en = 1; | |
835 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
836 | hw->ctl_f.compl_write = 1; | |
837 | hw->size = NULL_DESC_BUFFER_SIZE; | |
838 | hw->src_addr = 0; | |
839 | hw->dst_addr = 0; | |
840 | ||
841 | desc->txd.flags = flags; | |
842 | desc->len = 1; | |
843 | ||
844 | dump_desc_dbg(ioat, desc); | |
845 | ||
846 | /* we leave the channel locked to ensure in order submission */ | |
847 | return &desc->txd; | |
848 | } | |
849 | ||
9de6fc71 DW |
850 | static void __devinit ioat3_dma_test_callback(void *dma_async_param) |
851 | { | |
852 | struct completion *cmp = dma_async_param; | |
853 | ||
854 | complete(cmp); | |
855 | } | |
856 | ||
857 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
858 | static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device) | |
859 | { | |
860 | int i, src_idx; | |
861 | struct page *dest; | |
862 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
863 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
864 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
865 | dma_addr_t dma_addr, dest_dma; | |
866 | struct dma_async_tx_descriptor *tx; | |
867 | struct dma_chan *dma_chan; | |
868 | dma_cookie_t cookie; | |
869 | u8 cmp_byte = 0; | |
870 | u32 cmp_word; | |
871 | u32 xor_val_result; | |
872 | int err = 0; | |
873 | struct completion cmp; | |
874 | unsigned long tmo; | |
875 | struct device *dev = &device->pdev->dev; | |
876 | struct dma_device *dma = &device->common; | |
877 | ||
878 | dev_dbg(dev, "%s\n", __func__); | |
879 | ||
880 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
881 | return 0; | |
882 | ||
883 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
884 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
885 | if (!xor_srcs[src_idx]) { | |
886 | while (src_idx--) | |
887 | __free_page(xor_srcs[src_idx]); | |
888 | return -ENOMEM; | |
889 | } | |
890 | } | |
891 | ||
892 | dest = alloc_page(GFP_KERNEL); | |
893 | if (!dest) { | |
894 | while (src_idx--) | |
895 | __free_page(xor_srcs[src_idx]); | |
896 | return -ENOMEM; | |
897 | } | |
898 | ||
899 | /* Fill in src buffers */ | |
900 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
901 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
902 | for (i = 0; i < PAGE_SIZE; i++) | |
903 | ptr[i] = (1 << src_idx); | |
904 | } | |
905 | ||
906 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
907 | cmp_byte ^= (u8) (1 << src_idx); | |
908 | ||
909 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
910 | (cmp_byte << 8) | cmp_byte; | |
911 | ||
912 | memset(page_address(dest), 0, PAGE_SIZE); | |
913 | ||
914 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
915 | device_node); | |
916 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
917 | err = -ENODEV; | |
918 | goto out; | |
919 | } | |
920 | ||
921 | /* test xor */ | |
922 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
923 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
924 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
925 | DMA_TO_DEVICE); | |
926 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
927 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
928 | DMA_PREP_INTERRUPT); | |
929 | ||
930 | if (!tx) { | |
931 | dev_err(dev, "Self-test xor prep failed\n"); | |
932 | err = -ENODEV; | |
933 | goto free_resources; | |
934 | } | |
935 | ||
936 | async_tx_ack(tx); | |
937 | init_completion(&cmp); | |
938 | tx->callback = ioat3_dma_test_callback; | |
939 | tx->callback_param = &cmp; | |
940 | cookie = tx->tx_submit(tx); | |
941 | if (cookie < 0) { | |
942 | dev_err(dev, "Self-test xor setup failed\n"); | |
943 | err = -ENODEV; | |
944 | goto free_resources; | |
945 | } | |
946 | dma->device_issue_pending(dma_chan); | |
947 | ||
948 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
949 | ||
950 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
951 | dev_err(dev, "Self-test xor timed out\n"); | |
952 | err = -ENODEV; | |
953 | goto free_resources; | |
954 | } | |
955 | ||
956 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
957 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
958 | u32 *ptr = page_address(dest); | |
959 | if (ptr[i] != cmp_word) { | |
960 | dev_err(dev, "Self-test xor failed compare\n"); | |
961 | err = -ENODEV; | |
962 | goto free_resources; | |
963 | } | |
964 | } | |
965 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE); | |
966 | ||
967 | /* skip validate if the capability is not present */ | |
968 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
969 | goto free_resources; | |
970 | ||
971 | /* validate the sources with the destintation page */ | |
972 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
973 | xor_val_srcs[i] = xor_srcs[i]; | |
974 | xor_val_srcs[i] = dest; | |
975 | ||
976 | xor_val_result = 1; | |
977 | ||
978 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
979 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
980 | DMA_TO_DEVICE); | |
981 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
982 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
983 | &xor_val_result, DMA_PREP_INTERRUPT); | |
984 | if (!tx) { | |
985 | dev_err(dev, "Self-test zero prep failed\n"); | |
986 | err = -ENODEV; | |
987 | goto free_resources; | |
988 | } | |
989 | ||
990 | async_tx_ack(tx); | |
991 | init_completion(&cmp); | |
992 | tx->callback = ioat3_dma_test_callback; | |
993 | tx->callback_param = &cmp; | |
994 | cookie = tx->tx_submit(tx); | |
995 | if (cookie < 0) { | |
996 | dev_err(dev, "Self-test zero setup failed\n"); | |
997 | err = -ENODEV; | |
998 | goto free_resources; | |
999 | } | |
1000 | dma->device_issue_pending(dma_chan); | |
1001 | ||
1002 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1003 | ||
1004 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1005 | dev_err(dev, "Self-test validate timed out\n"); | |
1006 | err = -ENODEV; | |
1007 | goto free_resources; | |
1008 | } | |
1009 | ||
1010 | if (xor_val_result != 0) { | |
1011 | dev_err(dev, "Self-test validate failed compare\n"); | |
1012 | err = -ENODEV; | |
1013 | goto free_resources; | |
1014 | } | |
1015 | ||
1016 | /* skip memset if the capability is not present */ | |
1017 | if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) | |
1018 | goto free_resources; | |
1019 | ||
1020 | /* test memset */ | |
1021 | dma_addr = dma_map_page(dev, dest, 0, | |
1022 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1023 | tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, | |
1024 | DMA_PREP_INTERRUPT); | |
1025 | if (!tx) { | |
1026 | dev_err(dev, "Self-test memset prep failed\n"); | |
1027 | err = -ENODEV; | |
1028 | goto free_resources; | |
1029 | } | |
1030 | ||
1031 | async_tx_ack(tx); | |
1032 | init_completion(&cmp); | |
1033 | tx->callback = ioat3_dma_test_callback; | |
1034 | tx->callback_param = &cmp; | |
1035 | cookie = tx->tx_submit(tx); | |
1036 | if (cookie < 0) { | |
1037 | dev_err(dev, "Self-test memset setup failed\n"); | |
1038 | err = -ENODEV; | |
1039 | goto free_resources; | |
1040 | } | |
1041 | dma->device_issue_pending(dma_chan); | |
1042 | ||
1043 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1044 | ||
1045 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1046 | dev_err(dev, "Self-test memset timed out\n"); | |
1047 | err = -ENODEV; | |
1048 | goto free_resources; | |
1049 | } | |
1050 | ||
1051 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { | |
1052 | u32 *ptr = page_address(dest); | |
1053 | if (ptr[i]) { | |
1054 | dev_err(dev, "Self-test memset failed compare\n"); | |
1055 | err = -ENODEV; | |
1056 | goto free_resources; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | /* test for non-zero parity sum */ | |
1061 | xor_val_result = 0; | |
1062 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1063 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1064 | DMA_TO_DEVICE); | |
1065 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1066 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1067 | &xor_val_result, DMA_PREP_INTERRUPT); | |
1068 | if (!tx) { | |
1069 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1070 | err = -ENODEV; | |
1071 | goto free_resources; | |
1072 | } | |
1073 | ||
1074 | async_tx_ack(tx); | |
1075 | init_completion(&cmp); | |
1076 | tx->callback = ioat3_dma_test_callback; | |
1077 | tx->callback_param = &cmp; | |
1078 | cookie = tx->tx_submit(tx); | |
1079 | if (cookie < 0) { | |
1080 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1081 | err = -ENODEV; | |
1082 | goto free_resources; | |
1083 | } | |
1084 | dma->device_issue_pending(dma_chan); | |
1085 | ||
1086 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1087 | ||
1088 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1089 | dev_err(dev, "Self-test 2nd validate timed out\n"); | |
1090 | err = -ENODEV; | |
1091 | goto free_resources; | |
1092 | } | |
1093 | ||
1094 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1095 | dev_err(dev, "Self-test validate failed compare\n"); | |
1096 | err = -ENODEV; | |
1097 | goto free_resources; | |
1098 | } | |
1099 | ||
1100 | free_resources: | |
1101 | dma->device_free_chan_resources(dma_chan); | |
1102 | out: | |
1103 | src_idx = IOAT_NUM_SRC_TEST; | |
1104 | while (src_idx--) | |
1105 | __free_page(xor_srcs[src_idx]); | |
1106 | __free_page(dest); | |
1107 | return err; | |
1108 | } | |
1109 | ||
1110 | static int __devinit ioat3_dma_self_test(struct ioatdma_device *device) | |
1111 | { | |
1112 | int rc = ioat_dma_self_test(device); | |
1113 | ||
1114 | if (rc) | |
1115 | return rc; | |
1116 | ||
1117 | rc = ioat_xor_val_self_test(device); | |
1118 | if (rc) | |
1119 | return rc; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
a6d52d70 DW |
1124 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
1125 | { | |
1126 | /* throw away whatever the channel was doing and get it | |
1127 | * initialized, with ioat3 specific workarounds | |
1128 | */ | |
1129 | struct ioatdma_device *device = chan->device; | |
1130 | struct pci_dev *pdev = device->pdev; | |
1131 | u32 chanerr; | |
1132 | u16 dev_id; | |
1133 | int err; | |
1134 | ||
1135 | ioat2_quiesce(chan, msecs_to_jiffies(100)); | |
1136 | ||
1137 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
1138 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
1139 | ||
1140 | /* -= IOAT ver.3 workarounds =- */ | |
1141 | /* Write CHANERRMSK_INT with 3E07h to mask out the errors | |
1142 | * that can cause stability issues for IOAT ver.3, and clear any | |
1143 | * pending errors | |
1144 | */ | |
1145 | pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); | |
1146 | err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
1147 | if (err) { | |
1148 | dev_err(&pdev->dev, "channel error register unreachable\n"); | |
1149 | return err; | |
1150 | } | |
1151 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
1152 | ||
1153 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit | |
1154 | * (workaround for spurious config parity error after restart) | |
1155 | */ | |
1156 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1157 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) | |
1158 | pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); | |
1159 | ||
1160 | return ioat2_reset_sync(chan, msecs_to_jiffies(200)); | |
1161 | } | |
1162 | ||
bf40a686 DW |
1163 | int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) |
1164 | { | |
1165 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1166 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1167 | struct dma_device *dma; |
1168 | struct dma_chan *c; | |
1169 | struct ioat_chan_common *chan; | |
e3232714 | 1170 | bool is_raid_device = false; |
bf40a686 | 1171 | int err; |
bf40a686 DW |
1172 | u32 cap; |
1173 | ||
1174 | device->enumerate_channels = ioat2_enumerate_channels; | |
a6d52d70 | 1175 | device->reset_hw = ioat3_reset_hw; |
9de6fc71 | 1176 | device->self_test = ioat3_dma_self_test; |
bf40a686 DW |
1177 | dma = &device->common; |
1178 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1179 | dma->device_issue_pending = ioat2_issue_pending; | |
1180 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1181 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e DW |
1182 | |
1183 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); | |
1184 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1185 | ||
bf40a686 | 1186 | cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c DW |
1187 | |
1188 | /* dca is incompatible with raid operations */ | |
1189 | if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) | |
1190 | cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
1191 | ||
b094ad3b | 1192 | if (cap & IOAT_CAP_XOR) { |
e3232714 | 1193 | is_raid_device = true; |
b094ad3b DW |
1194 | dma->max_xor = 8; |
1195 | dma->xor_align = 2; | |
1196 | ||
1197 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1198 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1199 | ||
1200 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1201 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1202 | } | |
d69d235b | 1203 | if (cap & IOAT_CAP_PQ) { |
e3232714 | 1204 | is_raid_device = true; |
d69d235b DW |
1205 | dma_set_maxpq(dma, 8, 0); |
1206 | dma->pq_align = 2; | |
1207 | ||
1208 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1209 | dma->device_prep_dma_pq = ioat3_prep_pq; | |
1210 | ||
1211 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1212 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
ae786624 DW |
1213 | |
1214 | if (!(cap & IOAT_CAP_XOR)) { | |
1215 | dma->max_xor = 8; | |
1216 | dma->xor_align = 2; | |
1217 | ||
1218 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1219 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1220 | ||
1221 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1222 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1223 | } | |
d69d235b | 1224 | } |
e3232714 DW |
1225 | if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { |
1226 | dma_cap_set(DMA_MEMSET, dma->cap_mask); | |
1227 | dma->device_prep_dma_memset = ioat3_prep_memset_lock; | |
1228 | } | |
1229 | ||
1230 | ||
1231 | if (is_raid_device) { | |
1232 | dma->device_is_tx_complete = ioat3_is_complete; | |
1233 | device->cleanup_tasklet = ioat3_cleanup_tasklet; | |
1234 | device->timer_fn = ioat3_timer_event; | |
1235 | } else { | |
1236 | dma->device_is_tx_complete = ioat2_is_complete; | |
1237 | device->cleanup_tasklet = ioat2_cleanup_tasklet; | |
1238 | device->timer_fn = ioat2_timer_event; | |
1239 | } | |
bf40a686 | 1240 | |
7b3cc2b1 DW |
1241 | #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA |
1242 | dma_cap_clear(DMA_PQ_VAL, dma->cap_mask); | |
1243 | dma->device_prep_dma_pq_val = NULL; | |
1244 | #endif | |
1245 | ||
1246 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
1247 | dma_cap_clear(DMA_XOR_VAL, dma->cap_mask); | |
1248 | dma->device_prep_dma_xor_val = NULL; | |
1249 | #endif | |
1250 | ||
bf40a686 DW |
1251 | err = ioat_probe(device); |
1252 | if (err) | |
1253 | return err; | |
1254 | ioat_set_tcp_copy_break(262144); | |
1255 | ||
1256 | list_for_each_entry(c, &dma->channels, device_node) { | |
1257 | chan = to_chan_common(c); | |
1258 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1259 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1260 | } | |
1261 | ||
1262 | err = ioat_register(device); | |
1263 | if (err) | |
1264 | return err; | |
5669e31c DW |
1265 | |
1266 | ioat_kobject_add(device, &ioat2_ktype); | |
1267 | ||
bf40a686 DW |
1268 | if (dca) |
1269 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1270 | ||
1271 | return 0; | |
1272 | } |