Commit | Line | Data |
---|---|---|
0bbd5f4e | 1 | /* |
43d6e369 | 2 | * Intel I/OAT DMA Linux driver |
211a22ce | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
0bbd5f4e CL |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
43d6e369 SN |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. | |
0bbd5f4e CL |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
43d6e369 SN |
15 | * this program; if not, write to the Free Software Foundation, Inc., |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
0bbd5f4e | 20 | * |
0bbd5f4e CL |
21 | */ |
22 | ||
23 | /* | |
24 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous | |
25 | * copy operations. | |
26 | */ | |
27 | ||
28 | #include <linux/init.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
6b00c92c | 34 | #include <linux/dma-mapping.h> |
09177e85 | 35 | #include <linux/workqueue.h> |
3ad0b02e | 36 | #include <linux/i7300_idle.h> |
584ec227 DW |
37 | #include "dma.h" |
38 | #include "registers.h" | |
39 | #include "hw.h" | |
0bbd5f4e | 40 | |
5cbafa65 | 41 | int ioat_pending_level = 4; |
7bb67c14 SN |
42 | module_param(ioat_pending_level, int, 0644); |
43 | MODULE_PARM_DESC(ioat_pending_level, | |
44 | "high-water mark for pushing ioat descriptors (default: 4)"); | |
45 | ||
0bbd5f4e | 46 | /* internal functions */ |
5cbafa65 DW |
47 | static void ioat1_cleanup(struct ioat_dma_chan *ioat); |
48 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat); | |
3e037454 SN |
49 | |
50 | /** | |
51 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode | |
52 | * @irq: interrupt id | |
53 | * @data: interrupt data | |
54 | */ | |
55 | static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) | |
56 | { | |
57 | struct ioatdma_device *instance = data; | |
dcbc853a | 58 | struct ioat_chan_common *chan; |
3e037454 SN |
59 | unsigned long attnstatus; |
60 | int bit; | |
61 | u8 intrctrl; | |
62 | ||
63 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
64 | ||
65 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | |
66 | return IRQ_NONE; | |
67 | ||
68 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | |
69 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
70 | return IRQ_NONE; | |
71 | } | |
72 | ||
73 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); | |
74 | for_each_bit(bit, &attnstatus, BITS_PER_LONG) { | |
dcbc853a DW |
75 | chan = ioat_chan_by_index(instance, bit); |
76 | tasklet_schedule(&chan->cleanup_task); | |
3e037454 SN |
77 | } |
78 | ||
79 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
80 | return IRQ_HANDLED; | |
81 | } | |
82 | ||
83 | /** | |
84 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode | |
85 | * @irq: interrupt id | |
86 | * @data: interrupt data | |
87 | */ | |
88 | static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) | |
89 | { | |
dcbc853a | 90 | struct ioat_chan_common *chan = data; |
3e037454 | 91 | |
dcbc853a | 92 | tasklet_schedule(&chan->cleanup_task); |
3e037454 SN |
93 | |
94 | return IRQ_HANDLED; | |
95 | } | |
96 | ||
5cbafa65 DW |
97 | static void ioat1_cleanup_tasklet(unsigned long data); |
98 | ||
99 | /* common channel initialization */ | |
100 | void ioat_init_channel(struct ioatdma_device *device, | |
101 | struct ioat_chan_common *chan, int idx, | |
09c8a5b8 DW |
102 | void (*timer_fn)(unsigned long), |
103 | void (*tasklet)(unsigned long), | |
104 | unsigned long ioat) | |
5cbafa65 DW |
105 | { |
106 | struct dma_device *dma = &device->common; | |
107 | ||
108 | chan->device = device; | |
109 | chan->reg_base = device->reg_base + (0x80 * (idx + 1)); | |
5cbafa65 DW |
110 | spin_lock_init(&chan->cleanup_lock); |
111 | chan->common.device = dma; | |
112 | list_add_tail(&chan->common.device_node, &dma->channels); | |
113 | device->idx[idx] = chan; | |
09c8a5b8 DW |
114 | init_timer(&chan->timer); |
115 | chan->timer.function = timer_fn; | |
116 | chan->timer.data = ioat; | |
117 | tasklet_init(&chan->cleanup_task, tasklet, ioat); | |
5cbafa65 DW |
118 | tasklet_disable(&chan->cleanup_task); |
119 | } | |
120 | ||
09c8a5b8 | 121 | static void ioat1_timer_event(unsigned long data); |
3e037454 SN |
122 | |
123 | /** | |
5cbafa65 | 124 | * ioat1_dma_enumerate_channels - find and initialize the device's channels |
3e037454 SN |
125 | * @device: the device to be enumerated |
126 | */ | |
5cbafa65 | 127 | static int ioat1_enumerate_channels(struct ioatdma_device *device) |
0bbd5f4e CL |
128 | { |
129 | u8 xfercap_scale; | |
130 | u32 xfercap; | |
131 | int i; | |
dcbc853a | 132 | struct ioat_dma_chan *ioat; |
e6c0b69a | 133 | struct device *dev = &device->pdev->dev; |
f2427e27 | 134 | struct dma_device *dma = &device->common; |
0bbd5f4e | 135 | |
f2427e27 DW |
136 | INIT_LIST_HEAD(&dma->channels); |
137 | dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); | |
bb320786 DW |
138 | dma->chancnt &= 0x1f; /* bits [4:0] valid */ |
139 | if (dma->chancnt > ARRAY_SIZE(device->idx)) { | |
140 | dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", | |
141 | dma->chancnt, ARRAY_SIZE(device->idx)); | |
142 | dma->chancnt = ARRAY_SIZE(device->idx); | |
143 | } | |
e3828811 | 144 | xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
bb320786 | 145 | xfercap_scale &= 0x1f; /* bits [4:0] valid */ |
0bbd5f4e | 146 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); |
6df9183a | 147 | dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap); |
0bbd5f4e | 148 | |
f371be63 | 149 | #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL |
f2427e27 DW |
150 | if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) |
151 | dma->chancnt--; | |
27471fdb | 152 | #endif |
f2427e27 | 153 | for (i = 0; i < dma->chancnt; i++) { |
dcbc853a | 154 | ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); |
5cbafa65 | 155 | if (!ioat) |
0bbd5f4e | 156 | break; |
0bbd5f4e | 157 | |
5cbafa65 | 158 | ioat_init_channel(device, &ioat->base, i, |
09c8a5b8 | 159 | ioat1_timer_event, |
5cbafa65 DW |
160 | ioat1_cleanup_tasklet, |
161 | (unsigned long) ioat); | |
dcbc853a | 162 | ioat->xfercap = xfercap; |
dcbc853a DW |
163 | spin_lock_init(&ioat->desc_lock); |
164 | INIT_LIST_HEAD(&ioat->free_desc); | |
165 | INIT_LIST_HEAD(&ioat->used_desc); | |
0bbd5f4e | 166 | } |
5cbafa65 DW |
167 | dma->chancnt = i; |
168 | return i; | |
0bbd5f4e CL |
169 | } |
170 | ||
711924b1 SN |
171 | /** |
172 | * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended | |
173 | * descriptors to hw | |
174 | * @chan: DMA channel handle | |
175 | */ | |
bc3c7025 | 176 | static inline void |
dcbc853a | 177 | __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) |
711924b1 | 178 | { |
dcbc853a DW |
179 | void __iomem *reg_base = ioat->base.reg_base; |
180 | ||
6df9183a DW |
181 | dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n", |
182 | __func__, ioat->pending); | |
dcbc853a DW |
183 | ioat->pending = 0; |
184 | writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); | |
711924b1 SN |
185 | } |
186 | ||
187 | static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) | |
188 | { | |
dcbc853a | 189 | struct ioat_dma_chan *ioat = to_ioat_chan(chan); |
711924b1 | 190 | |
dcbc853a DW |
191 | if (ioat->pending > 0) { |
192 | spin_lock_bh(&ioat->desc_lock); | |
193 | __ioat1_dma_memcpy_issue_pending(ioat); | |
194 | spin_unlock_bh(&ioat->desc_lock); | |
711924b1 SN |
195 | } |
196 | } | |
197 | ||
09177e85 | 198 | /** |
5cbafa65 | 199 | * ioat1_reset_channel - restart a channel |
dcbc853a | 200 | * @ioat: IOAT DMA channel handle |
09177e85 | 201 | */ |
5cbafa65 | 202 | static void ioat1_reset_channel(struct ioat_dma_chan *ioat) |
09177e85 | 203 | { |
dcbc853a DW |
204 | struct ioat_chan_common *chan = &ioat->base; |
205 | void __iomem *reg_base = chan->reg_base; | |
09177e85 MS |
206 | u32 chansts, chanerr; |
207 | ||
09c8a5b8 | 208 | dev_warn(to_dev(chan), "reset\n"); |
dcbc853a | 209 | chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); |
09c8a5b8 | 210 | chansts = *chan->completion & IOAT_CHANSTS_STATUS; |
09177e85 | 211 | if (chanerr) { |
dcbc853a | 212 | dev_err(to_dev(chan), |
09177e85 | 213 | "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", |
dcbc853a DW |
214 | chan_num(chan), chansts, chanerr); |
215 | writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); | |
09177e85 MS |
216 | } |
217 | ||
218 | /* | |
219 | * whack it upside the head with a reset | |
220 | * and wait for things to settle out. | |
221 | * force the pending count to a really big negative | |
222 | * to make sure no one forces an issue_pending | |
223 | * while we're waiting. | |
224 | */ | |
225 | ||
dcbc853a | 226 | ioat->pending = INT_MIN; |
09177e85 | 227 | writeb(IOAT_CHANCMD_RESET, |
dcbc853a | 228 | reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
09c8a5b8 DW |
229 | set_bit(IOAT_RESET_PENDING, &chan->state); |
230 | mod_timer(&chan->timer, jiffies + RESET_DELAY); | |
09177e85 MS |
231 | } |
232 | ||
7bb67c14 | 233 | static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) |
7405f74b | 234 | { |
dcbc853a DW |
235 | struct dma_chan *c = tx->chan; |
236 | struct ioat_dma_chan *ioat = to_ioat_chan(c); | |
a0587bcf | 237 | struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); |
09c8a5b8 | 238 | struct ioat_chan_common *chan = &ioat->base; |
a0587bcf DW |
239 | struct ioat_desc_sw *first; |
240 | struct ioat_desc_sw *chain_tail; | |
7405f74b | 241 | dma_cookie_t cookie; |
7405f74b | 242 | |
dcbc853a | 243 | spin_lock_bh(&ioat->desc_lock); |
7405f74b | 244 | /* cookie incr and addition to used_list must be atomic */ |
dcbc853a | 245 | cookie = c->cookie; |
7405f74b DW |
246 | cookie++; |
247 | if (cookie < 0) | |
248 | cookie = 1; | |
dcbc853a DW |
249 | c->cookie = cookie; |
250 | tx->cookie = cookie; | |
6df9183a | 251 | dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); |
7405f74b DW |
252 | |
253 | /* write address into NextDescriptor field of last desc in chain */ | |
a0587bcf | 254 | first = to_ioat_desc(tx->tx_list.next); |
dcbc853a | 255 | chain_tail = to_ioat_desc(ioat->used_desc.prev); |
a0587bcf DW |
256 | /* make descriptor updates globally visible before chaining */ |
257 | wmb(); | |
258 | chain_tail->hw->next = first->txd.phys; | |
dcbc853a | 259 | list_splice_tail_init(&tx->tx_list, &ioat->used_desc); |
6df9183a DW |
260 | dump_desc_dbg(ioat, chain_tail); |
261 | dump_desc_dbg(ioat, first); | |
a0587bcf | 262 | |
09c8a5b8 DW |
263 | if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) |
264 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
265 | ||
5669e31c | 266 | ioat->active += desc->hw->tx_cnt; |
ad643f54 | 267 | ioat->pending += desc->hw->tx_cnt; |
dcbc853a DW |
268 | if (ioat->pending >= ioat_pending_level) |
269 | __ioat1_dma_memcpy_issue_pending(ioat); | |
270 | spin_unlock_bh(&ioat->desc_lock); | |
7405f74b | 271 | |
7bb67c14 SN |
272 | return cookie; |
273 | } | |
274 | ||
7bb67c14 SN |
275 | /** |
276 | * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair | |
dcbc853a | 277 | * @ioat: the channel supplying the memory pool for the descriptors |
7bb67c14 SN |
278 | * @flags: allocation flags |
279 | */ | |
bc3c7025 | 280 | static struct ioat_desc_sw * |
dcbc853a | 281 | ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) |
0bbd5f4e CL |
282 | { |
283 | struct ioat_dma_descriptor *desc; | |
284 | struct ioat_desc_sw *desc_sw; | |
8ab89567 | 285 | struct ioatdma_device *ioatdma_device; |
0bbd5f4e CL |
286 | dma_addr_t phys; |
287 | ||
dcbc853a | 288 | ioatdma_device = ioat->base.device; |
8ab89567 | 289 | desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); |
0bbd5f4e CL |
290 | if (unlikely(!desc)) |
291 | return NULL; | |
292 | ||
293 | desc_sw = kzalloc(sizeof(*desc_sw), flags); | |
294 | if (unlikely(!desc_sw)) { | |
8ab89567 | 295 | pci_pool_free(ioatdma_device->dma_pool, desc, phys); |
0bbd5f4e CL |
296 | return NULL; |
297 | } | |
298 | ||
299 | memset(desc, 0, sizeof(*desc)); | |
7bb67c14 | 300 | |
5cbafa65 DW |
301 | dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); |
302 | desc_sw->txd.tx_submit = ioat1_tx_submit; | |
0bbd5f4e | 303 | desc_sw->hw = desc; |
bc3c7025 | 304 | desc_sw->txd.phys = phys; |
6df9183a | 305 | set_desc_id(desc_sw, -1); |
0bbd5f4e CL |
306 | |
307 | return desc_sw; | |
308 | } | |
309 | ||
7bb67c14 SN |
310 | static int ioat_initial_desc_count = 256; |
311 | module_param(ioat_initial_desc_count, int, 0644); | |
312 | MODULE_PARM_DESC(ioat_initial_desc_count, | |
5cbafa65 | 313 | "ioat1: initial descriptors per channel (default: 256)"); |
7bb67c14 | 314 | /** |
5cbafa65 | 315 | * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors |
7bb67c14 SN |
316 | * @chan: the channel to be filled out |
317 | */ | |
5cbafa65 | 318 | static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) |
0bbd5f4e | 319 | { |
dcbc853a DW |
320 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
321 | struct ioat_chan_common *chan = &ioat->base; | |
711924b1 | 322 | struct ioat_desc_sw *desc; |
0bbd5f4e CL |
323 | u32 chanerr; |
324 | int i; | |
325 | LIST_HEAD(tmp_list); | |
326 | ||
e4223976 | 327 | /* have we already been set up? */ |
dcbc853a DW |
328 | if (!list_empty(&ioat->free_desc)) |
329 | return ioat->desccount; | |
0bbd5f4e | 330 | |
43d6e369 | 331 | /* Setup register to interrupt and write completion status on error */ |
f6ab95b5 | 332 | writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); |
0bbd5f4e | 333 | |
dcbc853a | 334 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
0bbd5f4e | 335 | if (chanerr) { |
dcbc853a DW |
336 | dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); |
337 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
0bbd5f4e CL |
338 | } |
339 | ||
340 | /* Allocate descriptors */ | |
7bb67c14 | 341 | for (i = 0; i < ioat_initial_desc_count; i++) { |
dcbc853a | 342 | desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL); |
0bbd5f4e | 343 | if (!desc) { |
dcbc853a | 344 | dev_err(to_dev(chan), "Only %d initial descriptors\n", i); |
0bbd5f4e CL |
345 | break; |
346 | } | |
6df9183a | 347 | set_desc_id(desc, i); |
0bbd5f4e CL |
348 | list_add_tail(&desc->node, &tmp_list); |
349 | } | |
dcbc853a DW |
350 | spin_lock_bh(&ioat->desc_lock); |
351 | ioat->desccount = i; | |
352 | list_splice(&tmp_list, &ioat->free_desc); | |
dcbc853a | 353 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e CL |
354 | |
355 | /* allocate a completion writeback area */ | |
356 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ | |
4fb9b9e8 DW |
357 | chan->completion = pci_pool_alloc(chan->device->completion_pool, |
358 | GFP_KERNEL, &chan->completion_dma); | |
359 | memset(chan->completion, 0, sizeof(*chan->completion)); | |
360 | writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, | |
dcbc853a | 361 | chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
4fb9b9e8 | 362 | writel(((u64) chan->completion_dma) >> 32, |
dcbc853a DW |
363 | chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
364 | ||
365 | tasklet_enable(&chan->cleanup_task); | |
5cbafa65 | 366 | ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ |
6df9183a DW |
367 | dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", |
368 | __func__, ioat->desccount); | |
dcbc853a | 369 | return ioat->desccount; |
0bbd5f4e CL |
370 | } |
371 | ||
7bb67c14 | 372 | /** |
5cbafa65 | 373 | * ioat1_dma_free_chan_resources - release all the descriptors |
7bb67c14 SN |
374 | * @chan: the channel to be cleaned |
375 | */ | |
5cbafa65 | 376 | static void ioat1_dma_free_chan_resources(struct dma_chan *c) |
0bbd5f4e | 377 | { |
dcbc853a DW |
378 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
379 | struct ioat_chan_common *chan = &ioat->base; | |
380 | struct ioatdma_device *ioatdma_device = chan->device; | |
0bbd5f4e | 381 | struct ioat_desc_sw *desc, *_desc; |
0bbd5f4e CL |
382 | int in_use_descs = 0; |
383 | ||
c3d4f44f MS |
384 | /* Before freeing channel resources first check |
385 | * if they have been previously allocated for this channel. | |
386 | */ | |
dcbc853a | 387 | if (ioat->desccount == 0) |
c3d4f44f MS |
388 | return; |
389 | ||
dcbc853a | 390 | tasklet_disable(&chan->cleanup_task); |
09c8a5b8 | 391 | del_timer_sync(&chan->timer); |
5cbafa65 | 392 | ioat1_cleanup(ioat); |
0bbd5f4e | 393 | |
3e037454 SN |
394 | /* Delay 100ms after reset to allow internal DMA logic to quiesce |
395 | * before removing DMA descriptor resources. | |
396 | */ | |
7bb67c14 | 397 | writeb(IOAT_CHANCMD_RESET, |
dcbc853a | 398 | chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
3e037454 | 399 | mdelay(100); |
0bbd5f4e | 400 | |
dcbc853a | 401 | spin_lock_bh(&ioat->desc_lock); |
6df9183a DW |
402 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
403 | dev_dbg(to_dev(chan), "%s: freeing %d from used list\n", | |
404 | __func__, desc_id(desc)); | |
405 | dump_desc_dbg(ioat, desc); | |
5cbafa65 DW |
406 | in_use_descs++; |
407 | list_del(&desc->node); | |
408 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, | |
409 | desc->txd.phys); | |
410 | kfree(desc); | |
411 | } | |
412 | list_for_each_entry_safe(desc, _desc, | |
413 | &ioat->free_desc, node) { | |
414 | list_del(&desc->node); | |
8ab89567 | 415 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
bc3c7025 | 416 | desc->txd.phys); |
0bbd5f4e CL |
417 | kfree(desc); |
418 | } | |
dcbc853a | 419 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e | 420 | |
8ab89567 | 421 | pci_pool_free(ioatdma_device->completion_pool, |
4fb9b9e8 DW |
422 | chan->completion, |
423 | chan->completion_dma); | |
0bbd5f4e CL |
424 | |
425 | /* one is ok since we left it on there on purpose */ | |
426 | if (in_use_descs > 1) | |
dcbc853a | 427 | dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", |
0bbd5f4e CL |
428 | in_use_descs - 1); |
429 | ||
4fb9b9e8 DW |
430 | chan->last_completion = 0; |
431 | chan->completion_dma = 0; | |
dcbc853a | 432 | ioat->pending = 0; |
dcbc853a | 433 | ioat->desccount = 0; |
3e037454 | 434 | } |
7f2b291f | 435 | |
3e037454 | 436 | /** |
dcbc853a DW |
437 | * ioat1_dma_get_next_descriptor - return the next available descriptor |
438 | * @ioat: IOAT DMA channel handle | |
3e037454 SN |
439 | * |
440 | * Gets the next descriptor from the chain, and must be called with the | |
441 | * channel's desc_lock held. Allocates more descriptors if the channel | |
442 | * has run out. | |
443 | */ | |
7f2b291f | 444 | static struct ioat_desc_sw * |
dcbc853a | 445 | ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) |
3e037454 | 446 | { |
711924b1 | 447 | struct ioat_desc_sw *new; |
3e037454 | 448 | |
dcbc853a DW |
449 | if (!list_empty(&ioat->free_desc)) { |
450 | new = to_ioat_desc(ioat->free_desc.next); | |
3e037454 SN |
451 | list_del(&new->node); |
452 | } else { | |
453 | /* try to get another desc */ | |
dcbc853a | 454 | new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); |
711924b1 | 455 | if (!new) { |
dcbc853a | 456 | dev_err(to_dev(&ioat->base), "alloc failed\n"); |
711924b1 SN |
457 | return NULL; |
458 | } | |
3e037454 | 459 | } |
6df9183a DW |
460 | dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n", |
461 | __func__, desc_id(new)); | |
3e037454 SN |
462 | prefetch(new->hw); |
463 | return new; | |
0bbd5f4e CL |
464 | } |
465 | ||
bc3c7025 | 466 | static struct dma_async_tx_descriptor * |
dcbc853a | 467 | ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, |
bc3c7025 | 468 | dma_addr_t dma_src, size_t len, unsigned long flags) |
0bbd5f4e | 469 | { |
dcbc853a | 470 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
a0587bcf DW |
471 | struct ioat_desc_sw *desc; |
472 | size_t copy; | |
473 | LIST_HEAD(chain); | |
474 | dma_addr_t src = dma_src; | |
475 | dma_addr_t dest = dma_dest; | |
476 | size_t total_len = len; | |
477 | struct ioat_dma_descriptor *hw = NULL; | |
478 | int tx_cnt = 0; | |
0bbd5f4e | 479 | |
dcbc853a | 480 | spin_lock_bh(&ioat->desc_lock); |
5cbafa65 | 481 | desc = ioat1_dma_get_next_descriptor(ioat); |
a0587bcf DW |
482 | do { |
483 | if (!desc) | |
484 | break; | |
0bbd5f4e | 485 | |
a0587bcf | 486 | tx_cnt++; |
dcbc853a | 487 | copy = min_t(size_t, len, ioat->xfercap); |
a0587bcf DW |
488 | |
489 | hw = desc->hw; | |
490 | hw->size = copy; | |
491 | hw->ctl = 0; | |
492 | hw->src_addr = src; | |
493 | hw->dst_addr = dest; | |
494 | ||
495 | list_add_tail(&desc->node, &chain); | |
496 | ||
497 | len -= copy; | |
498 | dest += copy; | |
499 | src += copy; | |
500 | if (len) { | |
501 | struct ioat_desc_sw *next; | |
502 | ||
503 | async_tx_ack(&desc->txd); | |
5cbafa65 | 504 | next = ioat1_dma_get_next_descriptor(ioat); |
a0587bcf | 505 | hw->next = next ? next->txd.phys : 0; |
6df9183a | 506 | dump_desc_dbg(ioat, desc); |
a0587bcf DW |
507 | desc = next; |
508 | } else | |
509 | hw->next = 0; | |
510 | } while (len); | |
511 | ||
512 | if (!desc) { | |
dcbc853a DW |
513 | struct ioat_chan_common *chan = &ioat->base; |
514 | ||
515 | dev_err(to_dev(chan), | |
5cbafa65 | 516 | "chan%d - get_next_desc failed\n", chan_num(chan)); |
dcbc853a DW |
517 | list_splice(&chain, &ioat->free_desc); |
518 | spin_unlock_bh(&ioat->desc_lock); | |
711924b1 | 519 | return NULL; |
09177e85 | 520 | } |
dcbc853a | 521 | spin_unlock_bh(&ioat->desc_lock); |
a0587bcf DW |
522 | |
523 | desc->txd.flags = flags; | |
a0587bcf DW |
524 | desc->len = total_len; |
525 | list_splice(&chain, &desc->txd.tx_list); | |
526 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
527 | hw->ctl_f.compl_write = 1; | |
ad643f54 | 528 | hw->tx_cnt = tx_cnt; |
6df9183a | 529 | dump_desc_dbg(ioat, desc); |
a0587bcf DW |
530 | |
531 | return &desc->txd; | |
0bbd5f4e CL |
532 | } |
533 | ||
5cbafa65 | 534 | static void ioat1_cleanup_tasklet(unsigned long data) |
3e037454 SN |
535 | { |
536 | struct ioat_dma_chan *chan = (void *)data; | |
f6ab95b5 | 537 | |
5cbafa65 | 538 | ioat1_cleanup(chan); |
f6ab95b5 | 539 | writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET); |
3e037454 SN |
540 | } |
541 | ||
5cbafa65 DW |
542 | void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, |
543 | size_t len, struct ioat_dma_descriptor *hw) | |
0bbd5f4e | 544 | { |
5cbafa65 DW |
545 | struct pci_dev *pdev = chan->device->pdev; |
546 | size_t offset = len - hw->size; | |
0bbd5f4e | 547 | |
5cbafa65 DW |
548 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) |
549 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
550 | PCI_DMA_FROMDEVICE, flags, 1); | |
0bbd5f4e | 551 | |
5cbafa65 DW |
552 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) |
553 | ioat_unmap(pdev, hw->src_addr - offset, len, | |
554 | PCI_DMA_TODEVICE, flags, 0); | |
555 | } | |
556 | ||
557 | unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) | |
558 | { | |
559 | unsigned long phys_complete; | |
4fb9b9e8 | 560 | u64 completion; |
0bbd5f4e | 561 | |
4fb9b9e8 | 562 | completion = *chan->completion; |
09c8a5b8 | 563 | phys_complete = ioat_chansts_to_addr(completion); |
0bbd5f4e | 564 | |
6df9183a DW |
565 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, |
566 | (unsigned long long) phys_complete); | |
567 | ||
09c8a5b8 DW |
568 | if (is_ioat_halted(completion)) { |
569 | u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
dcbc853a | 570 | dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", |
09c8a5b8 | 571 | chanerr); |
0bbd5f4e CL |
572 | |
573 | /* TODO do something to salvage the situation */ | |
574 | } | |
575 | ||
5cbafa65 DW |
576 | return phys_complete; |
577 | } | |
578 | ||
09c8a5b8 DW |
579 | bool ioat_cleanup_preamble(struct ioat_chan_common *chan, |
580 | unsigned long *phys_complete) | |
5cbafa65 | 581 | { |
09c8a5b8 DW |
582 | *phys_complete = ioat_get_current_completion(chan); |
583 | if (*phys_complete == chan->last_completion) | |
584 | return false; | |
585 | clear_bit(IOAT_COMPLETION_ACK, &chan->state); | |
586 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
5cbafa65 | 587 | |
09c8a5b8 DW |
588 | return true; |
589 | } | |
0bbd5f4e | 590 | |
09c8a5b8 DW |
591 | static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete) |
592 | { | |
593 | struct ioat_chan_common *chan = &ioat->base; | |
594 | struct list_head *_desc, *n; | |
595 | struct dma_async_tx_descriptor *tx; | |
09177e85 | 596 | |
6df9183a DW |
597 | dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n", |
598 | __func__, phys_complete); | |
09c8a5b8 DW |
599 | list_for_each_safe(_desc, n, &ioat->used_desc) { |
600 | struct ioat_desc_sw *desc; | |
601 | ||
602 | prefetch(n); | |
603 | desc = list_entry(_desc, typeof(*desc), node); | |
5cbafa65 DW |
604 | tx = &desc->txd; |
605 | /* | |
606 | * Incoming DMA requests may use multiple descriptors, | |
607 | * due to exceeding xfercap, perhaps. If so, only the | |
608 | * last one will have a cookie, and require unmapping. | |
609 | */ | |
6df9183a | 610 | dump_desc_dbg(ioat, desc); |
5cbafa65 | 611 | if (tx->cookie) { |
09c8a5b8 DW |
612 | chan->completed_cookie = tx->cookie; |
613 | tx->cookie = 0; | |
5cbafa65 | 614 | ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); |
5669e31c | 615 | ioat->active -= desc->hw->tx_cnt; |
5cbafa65 DW |
616 | if (tx->callback) { |
617 | tx->callback(tx->callback_param); | |
618 | tx->callback = NULL; | |
95218430 | 619 | } |
5cbafa65 | 620 | } |
0bbd5f4e | 621 | |
5cbafa65 DW |
622 | if (tx->phys != phys_complete) { |
623 | /* | |
624 | * a completed entry, but not the last, so clean | |
625 | * up if the client is done with the descriptor | |
626 | */ | |
627 | if (async_tx_test_ack(tx)) | |
628 | list_move_tail(&desc->node, &ioat->free_desc); | |
5cbafa65 DW |
629 | } else { |
630 | /* | |
631 | * last used desc. Do not remove, so we can | |
09c8a5b8 | 632 | * append from it. |
5cbafa65 | 633 | */ |
09c8a5b8 DW |
634 | |
635 | /* if nothing else is pending, cancel the | |
636 | * completion timeout | |
637 | */ | |
638 | if (n == &ioat->used_desc) { | |
639 | dev_dbg(to_dev(chan), | |
640 | "%s cancel completion timeout\n", | |
641 | __func__); | |
642 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
643 | } | |
0bbd5f4e | 644 | |
5cbafa65 | 645 | /* TODO check status bits? */ |
0bbd5f4e CL |
646 | break; |
647 | } | |
648 | } | |
649 | ||
09c8a5b8 DW |
650 | chan->last_completion = phys_complete; |
651 | } | |
652 | ||
653 | /** | |
654 | * ioat1_cleanup - cleanup up finished descriptors | |
655 | * @chan: ioat channel to be cleaned up | |
656 | * | |
657 | * To prevent lock contention we defer cleanup when the locks are | |
658 | * contended with a terminal timeout that forces cleanup and catches | |
659 | * completion notification errors. | |
660 | */ | |
661 | static void ioat1_cleanup(struct ioat_dma_chan *ioat) | |
662 | { | |
663 | struct ioat_chan_common *chan = &ioat->base; | |
664 | unsigned long phys_complete; | |
665 | ||
666 | prefetch(chan->completion); | |
667 | ||
668 | if (!spin_trylock_bh(&chan->cleanup_lock)) | |
669 | return; | |
670 | ||
671 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { | |
672 | spin_unlock_bh(&chan->cleanup_lock); | |
673 | return; | |
674 | } | |
675 | ||
676 | if (!spin_trylock_bh(&ioat->desc_lock)) { | |
677 | spin_unlock_bh(&chan->cleanup_lock); | |
678 | return; | |
679 | } | |
680 | ||
681 | __cleanup(ioat, phys_complete); | |
682 | ||
dcbc853a | 683 | spin_unlock_bh(&ioat->desc_lock); |
09c8a5b8 DW |
684 | spin_unlock_bh(&chan->cleanup_lock); |
685 | } | |
0bbd5f4e | 686 | |
09c8a5b8 DW |
687 | static void ioat1_timer_event(unsigned long data) |
688 | { | |
689 | struct ioat_dma_chan *ioat = (void *) data; | |
690 | struct ioat_chan_common *chan = &ioat->base; | |
0bbd5f4e | 691 | |
09c8a5b8 DW |
692 | dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state); |
693 | ||
694 | spin_lock_bh(&chan->cleanup_lock); | |
695 | if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) { | |
696 | struct ioat_desc_sw *desc; | |
697 | ||
698 | spin_lock_bh(&ioat->desc_lock); | |
699 | ||
700 | /* restart active descriptors */ | |
701 | desc = to_ioat_desc(ioat->used_desc.prev); | |
702 | ioat_set_chainaddr(ioat, desc->txd.phys); | |
703 | ioat_start(chan); | |
704 | ||
705 | ioat->pending = 0; | |
706 | set_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
707 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
708 | spin_unlock_bh(&ioat->desc_lock); | |
709 | } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { | |
710 | unsigned long phys_complete; | |
711 | ||
712 | spin_lock_bh(&ioat->desc_lock); | |
713 | /* if we haven't made progress and we have already | |
714 | * acknowledged a pending completion once, then be more | |
715 | * forceful with a restart | |
716 | */ | |
717 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
718 | __cleanup(ioat, phys_complete); | |
719 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) | |
720 | ioat1_reset_channel(ioat); | |
721 | else { | |
722 | u64 status = ioat_chansts(chan); | |
723 | ||
724 | /* manually update the last completion address */ | |
725 | if (ioat_chansts_to_addr(status) != 0) | |
726 | *chan->completion = status; | |
727 | ||
728 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
729 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
730 | } | |
731 | spin_unlock_bh(&ioat->desc_lock); | |
732 | } | |
dcbc853a | 733 | spin_unlock_bh(&chan->cleanup_lock); |
0bbd5f4e CL |
734 | } |
735 | ||
bc3c7025 | 736 | static enum dma_status |
5cbafa65 DW |
737 | ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, |
738 | dma_cookie_t *done, dma_cookie_t *used) | |
0bbd5f4e | 739 | { |
dcbc853a | 740 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
0bbd5f4e | 741 | |
5cbafa65 DW |
742 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) |
743 | return DMA_SUCCESS; | |
0bbd5f4e | 744 | |
5cbafa65 | 745 | ioat1_cleanup(ioat); |
0bbd5f4e | 746 | |
5cbafa65 | 747 | return ioat_is_complete(c, cookie, done, used); |
0bbd5f4e CL |
748 | } |
749 | ||
5cbafa65 | 750 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) |
0bbd5f4e | 751 | { |
dcbc853a | 752 | struct ioat_chan_common *chan = &ioat->base; |
0bbd5f4e | 753 | struct ioat_desc_sw *desc; |
c7984f4e | 754 | struct ioat_dma_descriptor *hw; |
0bbd5f4e | 755 | |
dcbc853a | 756 | spin_lock_bh(&ioat->desc_lock); |
0bbd5f4e | 757 | |
5cbafa65 | 758 | desc = ioat1_dma_get_next_descriptor(ioat); |
7f1b358a MS |
759 | |
760 | if (!desc) { | |
dcbc853a | 761 | dev_err(to_dev(chan), |
7f1b358a | 762 | "Unable to start null desc - get next desc failed\n"); |
dcbc853a | 763 | spin_unlock_bh(&ioat->desc_lock); |
7f1b358a MS |
764 | return; |
765 | } | |
766 | ||
c7984f4e DW |
767 | hw = desc->hw; |
768 | hw->ctl = 0; | |
769 | hw->ctl_f.null = 1; | |
770 | hw->ctl_f.int_en = 1; | |
771 | hw->ctl_f.compl_write = 1; | |
7f1b358a | 772 | /* set size to non-zero value (channel returns error when size is 0) */ |
c7984f4e DW |
773 | hw->size = NULL_DESC_BUFFER_SIZE; |
774 | hw->src_addr = 0; | |
775 | hw->dst_addr = 0; | |
bc3c7025 | 776 | async_tx_ack(&desc->txd); |
5cbafa65 DW |
777 | hw->next = 0; |
778 | list_add_tail(&desc->node, &ioat->used_desc); | |
6df9183a | 779 | dump_desc_dbg(ioat, desc); |
7bb67c14 | 780 | |
09c8a5b8 DW |
781 | ioat_set_chainaddr(ioat, desc->txd.phys); |
782 | ioat_start(chan); | |
dcbc853a | 783 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e CL |
784 | } |
785 | ||
786 | /* | |
787 | * Perform a IOAT transaction to verify the HW works. | |
788 | */ | |
789 | #define IOAT_TEST_SIZE 2000 | |
790 | ||
345d8523 | 791 | static void __devinit ioat_dma_test_callback(void *dma_async_param) |
95218430 | 792 | { |
b9bdcbba DW |
793 | struct completion *cmp = dma_async_param; |
794 | ||
795 | complete(cmp); | |
95218430 SN |
796 | } |
797 | ||
3e037454 SN |
798 | /** |
799 | * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. | |
800 | * @device: device to be tested | |
801 | */ | |
345d8523 | 802 | static int __devinit ioat_dma_self_test(struct ioatdma_device *device) |
0bbd5f4e CL |
803 | { |
804 | int i; | |
805 | u8 *src; | |
806 | u8 *dest; | |
bc3c7025 DW |
807 | struct dma_device *dma = &device->common; |
808 | struct device *dev = &device->pdev->dev; | |
0bbd5f4e | 809 | struct dma_chan *dma_chan; |
711924b1 | 810 | struct dma_async_tx_descriptor *tx; |
0036731c | 811 | dma_addr_t dma_dest, dma_src; |
0bbd5f4e CL |
812 | dma_cookie_t cookie; |
813 | int err = 0; | |
b9bdcbba | 814 | struct completion cmp; |
0c33e1ca | 815 | unsigned long tmo; |
4f005dbe | 816 | unsigned long flags; |
0bbd5f4e | 817 | |
e94b1766 | 818 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
0bbd5f4e CL |
819 | if (!src) |
820 | return -ENOMEM; | |
e94b1766 | 821 | dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
0bbd5f4e CL |
822 | if (!dest) { |
823 | kfree(src); | |
824 | return -ENOMEM; | |
825 | } | |
826 | ||
827 | /* Fill in src buffer */ | |
828 | for (i = 0; i < IOAT_TEST_SIZE; i++) | |
829 | src[i] = (u8)i; | |
830 | ||
831 | /* Start copy, using first DMA channel */ | |
bc3c7025 | 832 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
43d6e369 | 833 | device_node); |
bc3c7025 DW |
834 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
835 | dev_err(dev, "selftest cannot allocate chan resource\n"); | |
0bbd5f4e CL |
836 | err = -ENODEV; |
837 | goto out; | |
838 | } | |
839 | ||
bc3c7025 DW |
840 | dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
841 | dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); | |
a6a39ca1 DW |
842 | flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE | |
843 | DMA_PREP_INTERRUPT; | |
0036731c | 844 | tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, |
4f005dbe | 845 | IOAT_TEST_SIZE, flags); |
5149fd01 | 846 | if (!tx) { |
bc3c7025 | 847 | dev_err(dev, "Self-test prep failed, disabling\n"); |
5149fd01 SN |
848 | err = -ENODEV; |
849 | goto free_resources; | |
850 | } | |
851 | ||
7405f74b | 852 | async_tx_ack(tx); |
b9bdcbba | 853 | init_completion(&cmp); |
95218430 | 854 | tx->callback = ioat_dma_test_callback; |
b9bdcbba | 855 | tx->callback_param = &cmp; |
7bb67c14 | 856 | cookie = tx->tx_submit(tx); |
7f2b291f | 857 | if (cookie < 0) { |
bc3c7025 | 858 | dev_err(dev, "Self-test setup failed, disabling\n"); |
7f2b291f SN |
859 | err = -ENODEV; |
860 | goto free_resources; | |
861 | } | |
bc3c7025 | 862 | dma->device_issue_pending(dma_chan); |
532d3b1f | 863 | |
0c33e1ca | 864 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
0bbd5f4e | 865 | |
0c33e1ca | 866 | if (tmo == 0 || |
bc3c7025 | 867 | dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) |
7bb67c14 | 868 | != DMA_SUCCESS) { |
bc3c7025 | 869 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
0bbd5f4e CL |
870 | err = -ENODEV; |
871 | goto free_resources; | |
872 | } | |
873 | if (memcmp(src, dest, IOAT_TEST_SIZE)) { | |
bc3c7025 | 874 | dev_err(dev, "Self-test copy failed compare, disabling\n"); |
0bbd5f4e CL |
875 | err = -ENODEV; |
876 | goto free_resources; | |
877 | } | |
878 | ||
879 | free_resources: | |
bc3c7025 | 880 | dma->device_free_chan_resources(dma_chan); |
0bbd5f4e CL |
881 | out: |
882 | kfree(src); | |
883 | kfree(dest); | |
884 | return err; | |
885 | } | |
886 | ||
3e037454 SN |
887 | static char ioat_interrupt_style[32] = "msix"; |
888 | module_param_string(ioat_interrupt_style, ioat_interrupt_style, | |
889 | sizeof(ioat_interrupt_style), 0644); | |
890 | MODULE_PARM_DESC(ioat_interrupt_style, | |
891 | "set ioat interrupt style: msix (default), " | |
892 | "msix-single-vector, msi, intx)"); | |
893 | ||
894 | /** | |
895 | * ioat_dma_setup_interrupts - setup interrupt handler | |
896 | * @device: ioat device | |
897 | */ | |
898 | static int ioat_dma_setup_interrupts(struct ioatdma_device *device) | |
899 | { | |
dcbc853a | 900 | struct ioat_chan_common *chan; |
e6c0b69a DW |
901 | struct pci_dev *pdev = device->pdev; |
902 | struct device *dev = &pdev->dev; | |
903 | struct msix_entry *msix; | |
904 | int i, j, msixcnt; | |
905 | int err = -EINVAL; | |
3e037454 SN |
906 | u8 intrctrl = 0; |
907 | ||
908 | if (!strcmp(ioat_interrupt_style, "msix")) | |
909 | goto msix; | |
910 | if (!strcmp(ioat_interrupt_style, "msix-single-vector")) | |
911 | goto msix_single_vector; | |
912 | if (!strcmp(ioat_interrupt_style, "msi")) | |
913 | goto msi; | |
914 | if (!strcmp(ioat_interrupt_style, "intx")) | |
915 | goto intx; | |
e6c0b69a | 916 | dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); |
5149fd01 | 917 | goto err_no_irq; |
3e037454 SN |
918 | |
919 | msix: | |
920 | /* The number of MSI-X vectors should equal the number of channels */ | |
921 | msixcnt = device->common.chancnt; | |
922 | for (i = 0; i < msixcnt; i++) | |
923 | device->msix_entries[i].entry = i; | |
924 | ||
e6c0b69a | 925 | err = pci_enable_msix(pdev, device->msix_entries, msixcnt); |
3e037454 SN |
926 | if (err < 0) |
927 | goto msi; | |
928 | if (err > 0) | |
929 | goto msix_single_vector; | |
930 | ||
931 | for (i = 0; i < msixcnt; i++) { | |
e6c0b69a | 932 | msix = &device->msix_entries[i]; |
dcbc853a | 933 | chan = ioat_chan_by_index(device, i); |
e6c0b69a DW |
934 | err = devm_request_irq(dev, msix->vector, |
935 | ioat_dma_do_interrupt_msix, 0, | |
dcbc853a | 936 | "ioat-msix", chan); |
3e037454 SN |
937 | if (err) { |
938 | for (j = 0; j < i; j++) { | |
e6c0b69a | 939 | msix = &device->msix_entries[j]; |
dcbc853a DW |
940 | chan = ioat_chan_by_index(device, j); |
941 | devm_free_irq(dev, msix->vector, chan); | |
3e037454 SN |
942 | } |
943 | goto msix_single_vector; | |
944 | } | |
945 | } | |
946 | intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; | |
3e037454 SN |
947 | goto done; |
948 | ||
949 | msix_single_vector: | |
e6c0b69a DW |
950 | msix = &device->msix_entries[0]; |
951 | msix->entry = 0; | |
952 | err = pci_enable_msix(pdev, device->msix_entries, 1); | |
3e037454 SN |
953 | if (err) |
954 | goto msi; | |
955 | ||
e6c0b69a DW |
956 | err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0, |
957 | "ioat-msix", device); | |
3e037454 | 958 | if (err) { |
e6c0b69a | 959 | pci_disable_msix(pdev); |
3e037454 SN |
960 | goto msi; |
961 | } | |
3e037454 SN |
962 | goto done; |
963 | ||
964 | msi: | |
e6c0b69a | 965 | err = pci_enable_msi(pdev); |
3e037454 SN |
966 | if (err) |
967 | goto intx; | |
968 | ||
e6c0b69a DW |
969 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, |
970 | "ioat-msi", device); | |
3e037454 | 971 | if (err) { |
e6c0b69a | 972 | pci_disable_msi(pdev); |
3e037454 SN |
973 | goto intx; |
974 | } | |
3e037454 SN |
975 | goto done; |
976 | ||
977 | intx: | |
e6c0b69a DW |
978 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, |
979 | IRQF_SHARED, "ioat-intx", device); | |
3e037454 SN |
980 | if (err) |
981 | goto err_no_irq; | |
3e037454 SN |
982 | |
983 | done: | |
f2427e27 DW |
984 | if (device->intr_quirk) |
985 | device->intr_quirk(device); | |
3e037454 SN |
986 | intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; |
987 | writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
988 | return 0; | |
989 | ||
990 | err_no_irq: | |
991 | /* Disable all interrupt generation */ | |
992 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
e6c0b69a DW |
993 | dev_err(dev, "no usable interrupts\n"); |
994 | return err; | |
3e037454 SN |
995 | } |
996 | ||
e6c0b69a | 997 | static void ioat_disable_interrupts(struct ioatdma_device *device) |
3e037454 | 998 | { |
3e037454 SN |
999 | /* Disable all interrupt generation */ |
1000 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
3e037454 SN |
1001 | } |
1002 | ||
345d8523 | 1003 | int __devinit ioat_probe(struct ioatdma_device *device) |
0bbd5f4e | 1004 | { |
f2427e27 DW |
1005 | int err = -ENODEV; |
1006 | struct dma_device *dma = &device->common; | |
1007 | struct pci_dev *pdev = device->pdev; | |
e6c0b69a | 1008 | struct device *dev = &pdev->dev; |
0bbd5f4e CL |
1009 | |
1010 | /* DMA coherent memory pool for DMA descriptor allocations */ | |
1011 | device->dma_pool = pci_pool_create("dma_desc_pool", pdev, | |
8ab89567 SN |
1012 | sizeof(struct ioat_dma_descriptor), |
1013 | 64, 0); | |
0bbd5f4e CL |
1014 | if (!device->dma_pool) { |
1015 | err = -ENOMEM; | |
1016 | goto err_dma_pool; | |
1017 | } | |
1018 | ||
43d6e369 SN |
1019 | device->completion_pool = pci_pool_create("completion_pool", pdev, |
1020 | sizeof(u64), SMP_CACHE_BYTES, | |
1021 | SMP_CACHE_BYTES); | |
5cbafa65 | 1022 | |
0bbd5f4e CL |
1023 | if (!device->completion_pool) { |
1024 | err = -ENOMEM; | |
1025 | goto err_completion_pool; | |
1026 | } | |
1027 | ||
5cbafa65 | 1028 | device->enumerate_channels(device); |
0bbd5f4e | 1029 | |
f2427e27 | 1030 | dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
f2427e27 | 1031 | dma->dev = &pdev->dev; |
7bb67c14 | 1032 | |
bc3c7025 | 1033 | if (!dma->chancnt) { |
5669e31c | 1034 | dev_err(dev, "zero channels detected\n"); |
8b794b14 MS |
1035 | goto err_setup_interrupts; |
1036 | } | |
1037 | ||
3e037454 | 1038 | err = ioat_dma_setup_interrupts(device); |
8ab89567 | 1039 | if (err) |
3e037454 | 1040 | goto err_setup_interrupts; |
0bbd5f4e | 1041 | |
3e037454 | 1042 | err = ioat_dma_self_test(device); |
0bbd5f4e CL |
1043 | if (err) |
1044 | goto err_self_test; | |
1045 | ||
f2427e27 | 1046 | return 0; |
0bbd5f4e CL |
1047 | |
1048 | err_self_test: | |
e6c0b69a | 1049 | ioat_disable_interrupts(device); |
3e037454 | 1050 | err_setup_interrupts: |
0bbd5f4e CL |
1051 | pci_pool_destroy(device->completion_pool); |
1052 | err_completion_pool: | |
1053 | pci_pool_destroy(device->dma_pool); | |
1054 | err_dma_pool: | |
f2427e27 DW |
1055 | return err; |
1056 | } | |
1057 | ||
345d8523 | 1058 | int __devinit ioat_register(struct ioatdma_device *device) |
f2427e27 DW |
1059 | { |
1060 | int err = dma_async_device_register(&device->common); | |
1061 | ||
1062 | if (err) { | |
1063 | ioat_disable_interrupts(device); | |
1064 | pci_pool_destroy(device->completion_pool); | |
1065 | pci_pool_destroy(device->dma_pool); | |
1066 | } | |
1067 | ||
1068 | return err; | |
1069 | } | |
1070 | ||
1071 | /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */ | |
1072 | static void ioat1_intr_quirk(struct ioatdma_device *device) | |
1073 | { | |
1074 | struct pci_dev *pdev = device->pdev; | |
1075 | u32 dmactrl; | |
1076 | ||
1077 | pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); | |
1078 | if (pdev->msi_enabled) | |
1079 | dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; | |
1080 | else | |
1081 | dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN; | |
1082 | pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); | |
1083 | } | |
1084 | ||
5669e31c DW |
1085 | static ssize_t ring_size_show(struct dma_chan *c, char *page) |
1086 | { | |
1087 | struct ioat_dma_chan *ioat = to_ioat_chan(c); | |
1088 | ||
1089 | return sprintf(page, "%d\n", ioat->desccount); | |
1090 | } | |
1091 | static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); | |
1092 | ||
1093 | static ssize_t ring_active_show(struct dma_chan *c, char *page) | |
1094 | { | |
1095 | struct ioat_dma_chan *ioat = to_ioat_chan(c); | |
1096 | ||
1097 | return sprintf(page, "%d\n", ioat->active); | |
1098 | } | |
1099 | static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); | |
1100 | ||
1101 | static ssize_t cap_show(struct dma_chan *c, char *page) | |
1102 | { | |
1103 | struct dma_device *dma = c->device; | |
1104 | ||
1105 | return sprintf(page, "copy%s%s%s%s%s%s\n", | |
1106 | dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "", | |
1107 | dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "", | |
1108 | dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "", | |
1109 | dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "", | |
1110 | dma_has_cap(DMA_MEMSET, dma->cap_mask) ? " fill" : "", | |
1111 | dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : ""); | |
1112 | ||
1113 | } | |
1114 | struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap); | |
1115 | ||
1116 | static ssize_t version_show(struct dma_chan *c, char *page) | |
1117 | { | |
1118 | struct dma_device *dma = c->device; | |
1119 | struct ioatdma_device *device = to_ioatdma_device(dma); | |
1120 | ||
1121 | return sprintf(page, "%d.%d\n", | |
1122 | device->version >> 4, device->version & 0xf); | |
1123 | } | |
1124 | struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version); | |
1125 | ||
1126 | static struct attribute *ioat1_attrs[] = { | |
1127 | &ring_size_attr.attr, | |
1128 | &ring_active_attr.attr, | |
1129 | &ioat_cap_attr.attr, | |
1130 | &ioat_version_attr.attr, | |
1131 | NULL, | |
1132 | }; | |
1133 | ||
1134 | static ssize_t | |
1135 | ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page) | |
1136 | { | |
1137 | struct ioat_sysfs_entry *entry; | |
1138 | struct ioat_chan_common *chan; | |
1139 | ||
1140 | entry = container_of(attr, struct ioat_sysfs_entry, attr); | |
1141 | chan = container_of(kobj, struct ioat_chan_common, kobj); | |
1142 | ||
1143 | if (!entry->show) | |
1144 | return -EIO; | |
1145 | return entry->show(&chan->common, page); | |
1146 | } | |
1147 | ||
1148 | struct sysfs_ops ioat_sysfs_ops = { | |
1149 | .show = ioat_attr_show, | |
1150 | }; | |
1151 | ||
1152 | static struct kobj_type ioat1_ktype = { | |
1153 | .sysfs_ops = &ioat_sysfs_ops, | |
1154 | .default_attrs = ioat1_attrs, | |
1155 | }; | |
1156 | ||
1157 | void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type) | |
1158 | { | |
1159 | struct dma_device *dma = &device->common; | |
1160 | struct dma_chan *c; | |
1161 | ||
1162 | list_for_each_entry(c, &dma->channels, device_node) { | |
1163 | struct ioat_chan_common *chan = to_chan_common(c); | |
1164 | struct kobject *parent = &c->dev->device.kobj; | |
1165 | int err; | |
1166 | ||
1167 | err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata"); | |
1168 | if (err) { | |
1169 | dev_warn(to_dev(chan), | |
1170 | "sysfs init error (%d), continuing...\n", err); | |
1171 | kobject_put(&chan->kobj); | |
1172 | set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state); | |
1173 | } | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | void ioat_kobject_del(struct ioatdma_device *device) | |
1178 | { | |
1179 | struct dma_device *dma = &device->common; | |
1180 | struct dma_chan *c; | |
1181 | ||
1182 | list_for_each_entry(c, &dma->channels, device_node) { | |
1183 | struct ioat_chan_common *chan = to_chan_common(c); | |
1184 | ||
1185 | if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) { | |
1186 | kobject_del(&chan->kobj); | |
1187 | kobject_put(&chan->kobj); | |
1188 | } | |
1189 | } | |
1190 | } | |
1191 | ||
345d8523 | 1192 | int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) |
f2427e27 DW |
1193 | { |
1194 | struct pci_dev *pdev = device->pdev; | |
1195 | struct dma_device *dma; | |
1196 | int err; | |
1197 | ||
1198 | device->intr_quirk = ioat1_intr_quirk; | |
5cbafa65 | 1199 | device->enumerate_channels = ioat1_enumerate_channels; |
f2427e27 DW |
1200 | dma = &device->common; |
1201 | dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; | |
1202 | dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; | |
5cbafa65 DW |
1203 | dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; |
1204 | dma->device_free_chan_resources = ioat1_dma_free_chan_resources; | |
1205 | dma->device_is_tx_complete = ioat1_dma_is_complete; | |
f2427e27 DW |
1206 | |
1207 | err = ioat_probe(device); | |
1208 | if (err) | |
1209 | return err; | |
1210 | ioat_set_tcp_copy_break(4096); | |
1211 | err = ioat_register(device); | |
1212 | if (err) | |
1213 | return err; | |
5669e31c DW |
1214 | ioat_kobject_add(device, &ioat1_ktype); |
1215 | ||
f2427e27 DW |
1216 | if (dca) |
1217 | device->dca = ioat_dca_init(pdev, device->reg_base); | |
1218 | ||
f2427e27 DW |
1219 | return err; |
1220 | } | |
1221 | ||
345d8523 | 1222 | void __devexit ioat_dma_remove(struct ioatdma_device *device) |
0bbd5f4e | 1223 | { |
bc3c7025 | 1224 | struct dma_device *dma = &device->common; |
0bbd5f4e | 1225 | |
e6c0b69a | 1226 | ioat_disable_interrupts(device); |
8ab89567 | 1227 | |
5669e31c DW |
1228 | ioat_kobject_del(device); |
1229 | ||
bc3c7025 | 1230 | dma_async_device_unregister(dma); |
dfe2299e | 1231 | |
0bbd5f4e CL |
1232 | pci_pool_destroy(device->dma_pool); |
1233 | pci_pool_destroy(device->completion_pool); | |
8ab89567 | 1234 | |
dcbc853a | 1235 | INIT_LIST_HEAD(&dma->channels); |
0bbd5f4e | 1236 | } |