Commit | Line | Data |
---|---|---|
0bbd5f4e | 1 | /* |
43d6e369 | 2 | * Intel I/OAT DMA Linux driver |
85596a19 | 3 | * Copyright(c) 2004 - 2015 Intel Corporation. |
0bbd5f4e CL |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
43d6e369 SN |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. | |
0bbd5f4e CL |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
43d6e369 SN |
14 | * The full GNU General Public License is included in this distribution in |
15 | * the file called "COPYING". | |
0bbd5f4e | 16 | * |
0bbd5f4e CL |
17 | */ |
18 | ||
19 | /* | |
20 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous | |
21 | * copy operations. | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
0bbd5f4e CL |
27 | #include <linux/pci.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/dmaengine.h> | |
30 | #include <linux/delay.h> | |
6b00c92c | 31 | #include <linux/dma-mapping.h> |
09177e85 | 32 | #include <linux/workqueue.h> |
70c71606 | 33 | #include <linux/prefetch.h> |
dd4645eb | 34 | #include <linux/sizes.h> |
584ec227 DW |
35 | #include "dma.h" |
36 | #include "registers.h" | |
37 | #include "hw.h" | |
0bbd5f4e | 38 | |
d2ebfb33 RKAL |
39 | #include "../dmaengine.h" |
40 | ||
aed681d1 DJ |
41 | static char *chanerr_str[] = { |
42 | "DMA Transfer Destination Address Error", | |
43 | "Next Descriptor Address Error", | |
44 | "Descriptor Error", | |
45 | "Chan Address Value Error", | |
46 | "CHANCMD Error", | |
47 | "Chipset Uncorrectable Data Integrity Error", | |
48 | "DMA Uncorrectable Data Integrity Error", | |
49 | "Read Data Error", | |
50 | "Write Data Error", | |
51 | "Descriptor Control Error", | |
52 | "Descriptor Transfer Size Error", | |
53 | "Completion Address Error", | |
54 | "Interrupt Configuration Error", | |
55 | "Super extended descriptor Address Error", | |
56 | "Unaffiliated Error", | |
57 | "CRC or XOR P Error", | |
58 | "XOR Q Error", | |
59 | "Descriptor Count Error", | |
60 | "DIF All F detect Error", | |
61 | "Guard Tag verification Error", | |
62 | "Application Tag verification Error", | |
63 | "Reference Tag verification Error", | |
64 | "Bundle Bit Error", | |
65 | "Result DIF All F detect Error", | |
66 | "Result Guard Tag verification Error", | |
67 | "Result Application Tag verification Error", | |
68 | "Result Reference Tag verification Error", | |
aed681d1 DJ |
69 | }; |
70 | ||
3372de58 DJ |
71 | static void ioat_eh(struct ioatdma_chan *ioat_chan); |
72 | ||
aed681d1 DJ |
73 | static void ioat_print_chanerrs(struct ioatdma_chan *ioat_chan, u32 chanerr) |
74 | { | |
75 | int i; | |
76 | ||
1b779416 | 77 | for (i = 0; i < ARRAY_SIZE(chanerr_str); i++) { |
aed681d1 | 78 | if ((chanerr >> i) & 1) { |
1b779416 CIK |
79 | dev_err(to_dev(ioat_chan), "Err(%d): %s\n", |
80 | i, chanerr_str[i]); | |
aed681d1 DJ |
81 | } |
82 | } | |
83 | } | |
84 | ||
3e037454 SN |
85 | /** |
86 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode | |
87 | * @irq: interrupt id | |
88 | * @data: interrupt data | |
89 | */ | |
c0f28ce6 | 90 | irqreturn_t ioat_dma_do_interrupt(int irq, void *data) |
3e037454 SN |
91 | { |
92 | struct ioatdma_device *instance = data; | |
5a976888 | 93 | struct ioatdma_chan *ioat_chan; |
3e037454 SN |
94 | unsigned long attnstatus; |
95 | int bit; | |
96 | u8 intrctrl; | |
97 | ||
98 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
99 | ||
100 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | |
101 | return IRQ_NONE; | |
102 | ||
103 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | |
104 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
105 | return IRQ_NONE; | |
106 | } | |
107 | ||
108 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); | |
984b3f57 | 109 | for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) { |
5a976888 DJ |
110 | ioat_chan = ioat_chan_by_index(instance, bit); |
111 | if (test_bit(IOAT_RUN, &ioat_chan->state)) | |
112 | tasklet_schedule(&ioat_chan->cleanup_task); | |
3e037454 SN |
113 | } |
114 | ||
115 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
116 | return IRQ_HANDLED; | |
117 | } | |
118 | ||
119 | /** | |
120 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode | |
121 | * @irq: interrupt id | |
122 | * @data: interrupt data | |
123 | */ | |
c0f28ce6 | 124 | irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) |
3e037454 | 125 | { |
5a976888 | 126 | struct ioatdma_chan *ioat_chan = data; |
3e037454 | 127 | |
5a976888 DJ |
128 | if (test_bit(IOAT_RUN, &ioat_chan->state)) |
129 | tasklet_schedule(&ioat_chan->cleanup_task); | |
3e037454 SN |
130 | |
131 | return IRQ_HANDLED; | |
132 | } | |
133 | ||
5a976888 | 134 | void ioat_stop(struct ioatdma_chan *ioat_chan) |
da87ca4d | 135 | { |
55f878ec DJ |
136 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
137 | struct pci_dev *pdev = ioat_dma->pdev; | |
5a976888 | 138 | int chan_id = chan_num(ioat_chan); |
da87ca4d DW |
139 | struct msix_entry *msix; |
140 | ||
141 | /* 1/ stop irq from firing tasklets | |
142 | * 2/ stop the tasklet from re-arming irqs | |
143 | */ | |
5a976888 | 144 | clear_bit(IOAT_RUN, &ioat_chan->state); |
da87ca4d DW |
145 | |
146 | /* flush inflight interrupts */ | |
55f878ec | 147 | switch (ioat_dma->irq_mode) { |
da87ca4d | 148 | case IOAT_MSIX: |
55f878ec | 149 | msix = &ioat_dma->msix_entries[chan_id]; |
da87ca4d DW |
150 | synchronize_irq(msix->vector); |
151 | break; | |
152 | case IOAT_MSI: | |
153 | case IOAT_INTX: | |
154 | synchronize_irq(pdev->irq); | |
155 | break; | |
156 | default: | |
157 | break; | |
158 | } | |
159 | ||
160 | /* flush inflight timers */ | |
5a976888 | 161 | del_timer_sync(&ioat_chan->timer); |
da87ca4d DW |
162 | |
163 | /* flush inflight tasklet runs */ | |
5a976888 | 164 | tasklet_kill(&ioat_chan->cleanup_task); |
da87ca4d DW |
165 | |
166 | /* final cleanup now that everything is quiesced and can't re-arm */ | |
ef97bd0f | 167 | ioat_cleanup_event((unsigned long)&ioat_chan->dma_chan); |
da87ca4d DW |
168 | } |
169 | ||
3372de58 | 170 | static void __ioat_issue_pending(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
171 | { |
172 | ioat_chan->dmacount += ioat_ring_pending(ioat_chan); | |
173 | ioat_chan->issued = ioat_chan->head; | |
174 | writew(ioat_chan->dmacount, | |
175 | ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); | |
176 | dev_dbg(to_dev(ioat_chan), | |
177 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", | |
178 | __func__, ioat_chan->head, ioat_chan->tail, | |
179 | ioat_chan->issued, ioat_chan->dmacount); | |
180 | } | |
181 | ||
182 | void ioat_issue_pending(struct dma_chan *c) | |
183 | { | |
184 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
185 | ||
186 | if (ioat_ring_pending(ioat_chan)) { | |
187 | spin_lock_bh(&ioat_chan->prep_lock); | |
188 | __ioat_issue_pending(ioat_chan); | |
189 | spin_unlock_bh(&ioat_chan->prep_lock); | |
190 | } | |
191 | } | |
192 | ||
193 | /** | |
194 | * ioat_update_pending - log pending descriptors | |
195 | * @ioat: ioat+ channel | |
196 | * | |
197 | * Check if the number of unsubmitted descriptors has exceeded the | |
198 | * watermark. Called with prep_lock held | |
199 | */ | |
200 | static void ioat_update_pending(struct ioatdma_chan *ioat_chan) | |
201 | { | |
202 | if (ioat_ring_pending(ioat_chan) > ioat_pending_level) | |
203 | __ioat_issue_pending(ioat_chan); | |
204 | } | |
205 | ||
206 | static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan) | |
207 | { | |
208 | struct ioat_ring_ent *desc; | |
209 | struct ioat_dma_descriptor *hw; | |
210 | ||
211 | if (ioat_ring_space(ioat_chan) < 1) { | |
212 | dev_err(to_dev(ioat_chan), | |
213 | "Unable to start null desc - ring full\n"); | |
214 | return; | |
215 | } | |
216 | ||
217 | dev_dbg(to_dev(ioat_chan), | |
218 | "%s: head: %#x tail: %#x issued: %#x\n", | |
219 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); | |
220 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head); | |
221 | ||
222 | hw = desc->hw; | |
223 | hw->ctl = 0; | |
224 | hw->ctl_f.null = 1; | |
225 | hw->ctl_f.int_en = 1; | |
226 | hw->ctl_f.compl_write = 1; | |
227 | /* set size to non-zero value (channel returns error when size is 0) */ | |
228 | hw->size = NULL_DESC_BUFFER_SIZE; | |
229 | hw->src_addr = 0; | |
230 | hw->dst_addr = 0; | |
231 | async_tx_ack(&desc->txd); | |
232 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); | |
233 | dump_desc_dbg(ioat_chan, desc); | |
234 | /* make sure descriptors are written before we submit */ | |
235 | wmb(); | |
236 | ioat_chan->head += 1; | |
237 | __ioat_issue_pending(ioat_chan); | |
238 | } | |
239 | ||
c0f28ce6 | 240 | void ioat_start_null_desc(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
241 | { |
242 | spin_lock_bh(&ioat_chan->prep_lock); | |
ad4a7b50 DJ |
243 | if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
244 | __ioat_start_null_desc(ioat_chan); | |
885b2010 DJ |
245 | spin_unlock_bh(&ioat_chan->prep_lock); |
246 | } | |
247 | ||
3372de58 | 248 | static void __ioat_restart_chan(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
249 | { |
250 | /* set the tail to be re-issued */ | |
251 | ioat_chan->issued = ioat_chan->tail; | |
252 | ioat_chan->dmacount = 0; | |
885b2010 DJ |
253 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
254 | ||
255 | dev_dbg(to_dev(ioat_chan), | |
256 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", | |
257 | __func__, ioat_chan->head, ioat_chan->tail, | |
258 | ioat_chan->issued, ioat_chan->dmacount); | |
259 | ||
260 | if (ioat_ring_pending(ioat_chan)) { | |
261 | struct ioat_ring_ent *desc; | |
262 | ||
263 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
264 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); | |
265 | __ioat_issue_pending(ioat_chan); | |
266 | } else | |
267 | __ioat_start_null_desc(ioat_chan); | |
268 | } | |
269 | ||
3372de58 | 270 | static int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
885b2010 DJ |
271 | { |
272 | unsigned long end = jiffies + tmo; | |
273 | int err = 0; | |
274 | u32 status; | |
275 | ||
276 | status = ioat_chansts(ioat_chan); | |
277 | if (is_ioat_active(status) || is_ioat_idle(status)) | |
278 | ioat_suspend(ioat_chan); | |
279 | while (is_ioat_active(status) || is_ioat_idle(status)) { | |
280 | if (tmo && time_after(jiffies, end)) { | |
281 | err = -ETIMEDOUT; | |
282 | break; | |
283 | } | |
284 | status = ioat_chansts(ioat_chan); | |
285 | cpu_relax(); | |
286 | } | |
287 | ||
288 | return err; | |
289 | } | |
290 | ||
3372de58 | 291 | static int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
885b2010 DJ |
292 | { |
293 | unsigned long end = jiffies + tmo; | |
294 | int err = 0; | |
295 | ||
296 | ioat_reset(ioat_chan); | |
297 | while (ioat_reset_pending(ioat_chan)) { | |
298 | if (end && time_after(jiffies, end)) { | |
299 | err = -ETIMEDOUT; | |
300 | break; | |
301 | } | |
302 | cpu_relax(); | |
303 | } | |
304 | ||
305 | return err; | |
306 | } | |
307 | ||
885b2010 | 308 | static dma_cookie_t ioat_tx_submit_unlock(struct dma_async_tx_descriptor *tx) |
5c65cb93 | 309 | __releases(&ioat_chan->prep_lock) |
885b2010 DJ |
310 | { |
311 | struct dma_chan *c = tx->chan; | |
312 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
313 | dma_cookie_t cookie; | |
314 | ||
315 | cookie = dma_cookie_assign(tx); | |
316 | dev_dbg(to_dev(ioat_chan), "%s: cookie: %d\n", __func__, cookie); | |
317 | ||
318 | if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) | |
319 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
320 | ||
321 | /* make descriptor updates visible before advancing ioat->head, | |
322 | * this is purposefully not smp_wmb() since we are also | |
323 | * publishing the descriptor updates to a dma device | |
324 | */ | |
325 | wmb(); | |
326 | ||
327 | ioat_chan->head += ioat_chan->produce; | |
328 | ||
329 | ioat_update_pending(ioat_chan); | |
330 | spin_unlock_bh(&ioat_chan->prep_lock); | |
331 | ||
332 | return cookie; | |
333 | } | |
334 | ||
335 | static struct ioat_ring_ent * | |
dd4645eb | 336 | ioat_alloc_ring_ent(struct dma_chan *chan, int idx, gfp_t flags) |
885b2010 DJ |
337 | { |
338 | struct ioat_dma_descriptor *hw; | |
339 | struct ioat_ring_ent *desc; | |
340 | struct ioatdma_device *ioat_dma; | |
dd4645eb DJ |
341 | struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
342 | int chunk; | |
885b2010 | 343 | dma_addr_t phys; |
dd4645eb DJ |
344 | u8 *pos; |
345 | off_t offs; | |
885b2010 DJ |
346 | |
347 | ioat_dma = to_ioatdma_device(chan->device); | |
dd4645eb DJ |
348 | |
349 | chunk = idx / IOAT_DESCS_PER_2M; | |
350 | idx &= (IOAT_DESCS_PER_2M - 1); | |
351 | offs = idx * IOAT_DESC_SZ; | |
352 | pos = (u8 *)ioat_chan->descs[chunk].virt + offs; | |
353 | phys = ioat_chan->descs[chunk].hw + offs; | |
354 | hw = (struct ioat_dma_descriptor *)pos; | |
885b2010 DJ |
355 | memset(hw, 0, sizeof(*hw)); |
356 | ||
357 | desc = kmem_cache_zalloc(ioat_cache, flags); | |
dd4645eb | 358 | if (!desc) |
885b2010 | 359 | return NULL; |
885b2010 DJ |
360 | |
361 | dma_async_tx_descriptor_init(&desc->txd, chan); | |
362 | desc->txd.tx_submit = ioat_tx_submit_unlock; | |
363 | desc->hw = hw; | |
364 | desc->txd.phys = phys; | |
365 | return desc; | |
366 | } | |
367 | ||
c0f28ce6 | 368 | void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan) |
885b2010 | 369 | { |
885b2010 DJ |
370 | kmem_cache_free(ioat_cache, desc); |
371 | } | |
372 | ||
c0f28ce6 | 373 | struct ioat_ring_ent ** |
885b2010 DJ |
374 | ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags) |
375 | { | |
dd4645eb | 376 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
885b2010 | 377 | struct ioat_ring_ent **ring; |
dd4645eb DJ |
378 | int total_descs = 1 << order; |
379 | int i, chunks; | |
885b2010 DJ |
380 | |
381 | /* allocate the array to hold the software ring */ | |
dd4645eb | 382 | ring = kcalloc(total_descs, sizeof(*ring), flags); |
885b2010 DJ |
383 | if (!ring) |
384 | return NULL; | |
dd4645eb DJ |
385 | |
386 | ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M; | |
387 | ||
388 | for (i = 0; i < chunks; i++) { | |
389 | struct ioat_descs *descs = &ioat_chan->descs[i]; | |
390 | ||
391 | descs->virt = dma_alloc_coherent(to_dev(ioat_chan), | |
392 | SZ_2M, &descs->hw, flags); | |
393 | if (!descs->virt && (i > 0)) { | |
394 | int idx; | |
395 | ||
396 | for (idx = 0; idx < i; idx++) { | |
397 | dma_free_coherent(to_dev(ioat_chan), SZ_2M, | |
398 | descs->virt, descs->hw); | |
399 | descs->virt = NULL; | |
400 | descs->hw = 0; | |
401 | } | |
402 | ||
403 | ioat_chan->desc_chunks = 0; | |
404 | kfree(ring); | |
405 | return NULL; | |
406 | } | |
407 | } | |
408 | ||
409 | for (i = 0; i < total_descs; i++) { | |
410 | ring[i] = ioat_alloc_ring_ent(c, i, flags); | |
885b2010 | 411 | if (!ring[i]) { |
dd4645eb DJ |
412 | int idx; |
413 | ||
885b2010 DJ |
414 | while (i--) |
415 | ioat_free_ring_ent(ring[i], c); | |
dd4645eb DJ |
416 | |
417 | for (idx = 0; idx < ioat_chan->desc_chunks; idx++) { | |
418 | dma_free_coherent(to_dev(ioat_chan), | |
419 | SZ_2M, | |
420 | ioat_chan->descs[idx].virt, | |
421 | ioat_chan->descs[idx].hw); | |
422 | ioat_chan->descs[idx].virt = NULL; | |
423 | ioat_chan->descs[idx].hw = 0; | |
424 | } | |
425 | ||
426 | ioat_chan->desc_chunks = 0; | |
885b2010 DJ |
427 | kfree(ring); |
428 | return NULL; | |
429 | } | |
430 | set_desc_id(ring[i], i); | |
431 | } | |
432 | ||
433 | /* link descs */ | |
dd4645eb | 434 | for (i = 0; i < total_descs-1; i++) { |
885b2010 DJ |
435 | struct ioat_ring_ent *next = ring[i+1]; |
436 | struct ioat_dma_descriptor *hw = ring[i]->hw; | |
437 | ||
438 | hw->next = next->txd.phys; | |
439 | } | |
440 | ring[i]->hw->next = ring[0]->txd.phys; | |
441 | ||
442 | return ring; | |
443 | } | |
444 | ||
885b2010 DJ |
445 | /** |
446 | * ioat_check_space_lock - verify space and grab ring producer lock | |
447 | * @ioat: ioat,3 channel (ring) to operate on | |
448 | * @num_descs: allocation length | |
449 | */ | |
450 | int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs) | |
5c65cb93 | 451 | __acquires(&ioat_chan->prep_lock) |
885b2010 | 452 | { |
885b2010 DJ |
453 | spin_lock_bh(&ioat_chan->prep_lock); |
454 | /* never allow the last descriptor to be consumed, we need at | |
455 | * least one free at all times to allow for on-the-fly ring | |
456 | * resizing. | |
457 | */ | |
458 | if (likely(ioat_ring_space(ioat_chan) > num_descs)) { | |
459 | dev_dbg(to_dev(ioat_chan), "%s: num_descs: %d (%x:%x:%x)\n", | |
460 | __func__, num_descs, ioat_chan->head, | |
461 | ioat_chan->tail, ioat_chan->issued); | |
462 | ioat_chan->produce = num_descs; | |
463 | return 0; /* with ioat->prep_lock held */ | |
464 | } | |
885b2010 DJ |
465 | spin_unlock_bh(&ioat_chan->prep_lock); |
466 | ||
885b2010 DJ |
467 | dev_dbg_ratelimited(to_dev(ioat_chan), |
468 | "%s: ring full! num_descs: %d (%x:%x:%x)\n", | |
469 | __func__, num_descs, ioat_chan->head, | |
470 | ioat_chan->tail, ioat_chan->issued); | |
471 | ||
472 | /* progress reclaim in the allocation failure case we may be | |
473 | * called under bh_disabled so we need to trigger the timer | |
474 | * event directly | |
475 | */ | |
476 | if (time_is_before_jiffies(ioat_chan->timer.expires) | |
477 | && timer_pending(&ioat_chan->timer)) { | |
885b2010 | 478 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
ef97bd0f | 479 | ioat_timer_event((unsigned long)ioat_chan); |
885b2010 DJ |
480 | } |
481 | ||
482 | return -ENOMEM; | |
483 | } | |
3372de58 DJ |
484 | |
485 | static bool desc_has_ext(struct ioat_ring_ent *desc) | |
486 | { | |
487 | struct ioat_dma_descriptor *hw = desc->hw; | |
488 | ||
489 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
490 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
491 | struct ioat_xor_descriptor *xor = desc->xor; | |
492 | ||
493 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) | |
494 | return true; | |
495 | } else if (hw->ctl_f.op == IOAT_OP_PQ || | |
496 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
497 | struct ioat_pq_descriptor *pq = desc->pq; | |
498 | ||
499 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
500 | return true; | |
501 | } | |
502 | ||
503 | return false; | |
504 | } | |
505 | ||
506 | static void | |
507 | ioat_free_sed(struct ioatdma_device *ioat_dma, struct ioat_sed_ent *sed) | |
508 | { | |
509 | if (!sed) | |
510 | return; | |
511 | ||
512 | dma_pool_free(ioat_dma->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); | |
513 | kmem_cache_free(ioat_sed_cache, sed); | |
514 | } | |
515 | ||
516 | static u64 ioat_get_current_completion(struct ioatdma_chan *ioat_chan) | |
517 | { | |
518 | u64 phys_complete; | |
519 | u64 completion; | |
520 | ||
521 | completion = *ioat_chan->completion; | |
522 | phys_complete = ioat_chansts_to_addr(completion); | |
523 | ||
524 | dev_dbg(to_dev(ioat_chan), "%s: phys_complete: %#llx\n", __func__, | |
525 | (unsigned long long) phys_complete); | |
526 | ||
527 | return phys_complete; | |
528 | } | |
529 | ||
530 | static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, | |
531 | u64 *phys_complete) | |
532 | { | |
533 | *phys_complete = ioat_get_current_completion(ioat_chan); | |
534 | if (*phys_complete == ioat_chan->last_completion) | |
535 | return false; | |
536 | ||
537 | clear_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); | |
538 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
539 | ||
540 | return true; | |
541 | } | |
542 | ||
543 | static void | |
544 | desc_get_errstat(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc) | |
545 | { | |
546 | struct ioat_dma_descriptor *hw = desc->hw; | |
547 | ||
548 | switch (hw->ctl_f.op) { | |
549 | case IOAT_OP_PQ_VAL: | |
550 | case IOAT_OP_PQ_VAL_16S: | |
551 | { | |
552 | struct ioat_pq_descriptor *pq = desc->pq; | |
553 | ||
554 | /* check if there's error written */ | |
555 | if (!pq->dwbes_f.wbes) | |
556 | return; | |
557 | ||
558 | /* need to set a chanerr var for checking to clear later */ | |
559 | ||
560 | if (pq->dwbes_f.p_val_err) | |
561 | *desc->result |= SUM_CHECK_P_RESULT; | |
562 | ||
563 | if (pq->dwbes_f.q_val_err) | |
564 | *desc->result |= SUM_CHECK_Q_RESULT; | |
565 | ||
566 | return; | |
567 | } | |
568 | default: | |
569 | return; | |
570 | } | |
571 | } | |
572 | ||
573 | /** | |
574 | * __cleanup - reclaim used descriptors | |
575 | * @ioat: channel (ring) to clean | |
576 | */ | |
577 | static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete) | |
578 | { | |
579 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
580 | struct ioat_ring_ent *desc; | |
581 | bool seen_current = false; | |
582 | int idx = ioat_chan->tail, i; | |
583 | u16 active; | |
584 | ||
585 | dev_dbg(to_dev(ioat_chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
586 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); | |
587 | ||
588 | /* | |
589 | * At restart of the channel, the completion address and the | |
590 | * channel status will be 0 due to starting a new chain. Since | |
591 | * it's new chain and the first descriptor "fails", there is | |
592 | * nothing to clean up. We do not want to reap the entire submitted | |
593 | * chain due to this 0 address value and then BUG. | |
594 | */ | |
595 | if (!phys_complete) | |
596 | return; | |
597 | ||
598 | active = ioat_ring_active(ioat_chan); | |
599 | for (i = 0; i < active && !seen_current; i++) { | |
600 | struct dma_async_tx_descriptor *tx; | |
601 | ||
602 | smp_read_barrier_depends(); | |
603 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); | |
604 | desc = ioat_get_ring_ent(ioat_chan, idx + i); | |
605 | dump_desc_dbg(ioat_chan, desc); | |
606 | ||
607 | /* set err stat if we are using dwbes */ | |
608 | if (ioat_dma->cap & IOAT_CAP_DWBES) | |
609 | desc_get_errstat(ioat_chan, desc); | |
610 | ||
611 | tx = &desc->txd; | |
612 | if (tx->cookie) { | |
9546d4cd DJ |
613 | struct dmaengine_result res; |
614 | ||
3372de58 DJ |
615 | dma_cookie_complete(tx); |
616 | dma_descriptor_unmap(tx); | |
9546d4cd | 617 | res.result = DMA_TRANS_NOERROR; |
63992864 DJ |
618 | dmaengine_desc_get_callback_invoke(tx, NULL); |
619 | tx->callback = NULL; | |
9546d4cd | 620 | tx->callback_result = NULL; |
3372de58 DJ |
621 | } |
622 | ||
623 | if (tx->phys == phys_complete) | |
624 | seen_current = true; | |
625 | ||
626 | /* skip extended descriptors */ | |
627 | if (desc_has_ext(desc)) { | |
628 | BUG_ON(i + 1 >= active); | |
629 | i++; | |
630 | } | |
631 | ||
632 | /* cleanup super extended descriptors */ | |
633 | if (desc->sed) { | |
634 | ioat_free_sed(ioat_dma, desc->sed); | |
635 | desc->sed = NULL; | |
636 | } | |
637 | } | |
638 | ||
639 | /* finish all descriptor reads before incrementing tail */ | |
640 | smp_mb(); | |
641 | ioat_chan->tail = idx + i; | |
642 | /* no active descs have written a completion? */ | |
643 | BUG_ON(active && !seen_current); | |
644 | ioat_chan->last_completion = phys_complete; | |
645 | ||
646 | if (active - i == 0) { | |
647 | dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n", | |
648 | __func__); | |
3372de58 DJ |
649 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
650 | } | |
651 | ||
652 | /* 5 microsecond delay per pending descriptor */ | |
653 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), | |
654 | ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET); | |
655 | } | |
656 | ||
657 | static void ioat_cleanup(struct ioatdma_chan *ioat_chan) | |
658 | { | |
659 | u64 phys_complete; | |
660 | ||
661 | spin_lock_bh(&ioat_chan->cleanup_lock); | |
662 | ||
663 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
664 | __cleanup(ioat_chan, phys_complete); | |
665 | ||
666 | if (is_ioat_halted(*ioat_chan->completion)) { | |
667 | u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
668 | ||
9546d4cd DJ |
669 | if (chanerr & |
670 | (IOAT_CHANERR_HANDLE_MASK | IOAT_CHANERR_RECOVER_MASK)) { | |
3372de58 DJ |
671 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
672 | ioat_eh(ioat_chan); | |
673 | } | |
674 | } | |
675 | ||
676 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
677 | } | |
678 | ||
679 | void ioat_cleanup_event(unsigned long data) | |
680 | { | |
681 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); | |
682 | ||
683 | ioat_cleanup(ioat_chan); | |
684 | if (!test_bit(IOAT_RUN, &ioat_chan->state)) | |
685 | return; | |
686 | writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); | |
687 | } | |
688 | ||
689 | static void ioat_restart_channel(struct ioatdma_chan *ioat_chan) | |
690 | { | |
691 | u64 phys_complete; | |
692 | ||
693 | ioat_quiesce(ioat_chan, 0); | |
694 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
695 | __cleanup(ioat_chan, phys_complete); | |
696 | ||
697 | __ioat_restart_chan(ioat_chan); | |
698 | } | |
699 | ||
9546d4cd DJ |
700 | |
701 | static void ioat_abort_descs(struct ioatdma_chan *ioat_chan) | |
702 | { | |
703 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
704 | struct ioat_ring_ent *desc; | |
705 | u16 active; | |
706 | int idx = ioat_chan->tail, i; | |
707 | ||
708 | /* | |
709 | * We assume that the failed descriptor has been processed. | |
710 | * Now we are just returning all the remaining submitted | |
711 | * descriptors to abort. | |
712 | */ | |
713 | active = ioat_ring_active(ioat_chan); | |
714 | ||
715 | /* we skip the failed descriptor that tail points to */ | |
716 | for (i = 1; i < active; i++) { | |
717 | struct dma_async_tx_descriptor *tx; | |
718 | ||
719 | smp_read_barrier_depends(); | |
720 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); | |
721 | desc = ioat_get_ring_ent(ioat_chan, idx + i); | |
722 | ||
723 | tx = &desc->txd; | |
724 | if (tx->cookie) { | |
725 | struct dmaengine_result res; | |
726 | ||
727 | dma_cookie_complete(tx); | |
728 | dma_descriptor_unmap(tx); | |
729 | res.result = DMA_TRANS_ABORTED; | |
730 | dmaengine_desc_get_callback_invoke(tx, &res); | |
731 | tx->callback = NULL; | |
732 | tx->callback_result = NULL; | |
733 | } | |
734 | ||
735 | /* skip extended descriptors */ | |
736 | if (desc_has_ext(desc)) { | |
737 | WARN_ON(i + 1 >= active); | |
738 | i++; | |
739 | } | |
740 | ||
741 | /* cleanup super extended descriptors */ | |
742 | if (desc->sed) { | |
743 | ioat_free_sed(ioat_dma, desc->sed); | |
744 | desc->sed = NULL; | |
745 | } | |
746 | } | |
747 | ||
748 | smp_mb(); /* finish all descriptor reads before incrementing tail */ | |
749 | ioat_chan->tail = idx + active; | |
750 | ||
751 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
752 | ioat_chan->last_completion = *ioat_chan->completion = desc->txd.phys; | |
753 | } | |
754 | ||
3372de58 DJ |
755 | static void ioat_eh(struct ioatdma_chan *ioat_chan) |
756 | { | |
757 | struct pci_dev *pdev = to_pdev(ioat_chan); | |
758 | struct ioat_dma_descriptor *hw; | |
759 | struct dma_async_tx_descriptor *tx; | |
760 | u64 phys_complete; | |
761 | struct ioat_ring_ent *desc; | |
762 | u32 err_handled = 0; | |
763 | u32 chanerr_int; | |
764 | u32 chanerr; | |
9546d4cd DJ |
765 | bool abort = false; |
766 | struct dmaengine_result res; | |
3372de58 DJ |
767 | |
768 | /* cleanup so tail points to descriptor that caused the error */ | |
769 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
770 | __cleanup(ioat_chan, phys_complete); | |
771 | ||
772 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
773 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
774 | ||
775 | dev_dbg(to_dev(ioat_chan), "%s: error = %x:%x\n", | |
776 | __func__, chanerr, chanerr_int); | |
777 | ||
778 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
779 | hw = desc->hw; | |
780 | dump_desc_dbg(ioat_chan, desc); | |
781 | ||
782 | switch (hw->ctl_f.op) { | |
783 | case IOAT_OP_XOR_VAL: | |
784 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
785 | *desc->result |= SUM_CHECK_P_RESULT; | |
786 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
787 | } | |
788 | break; | |
789 | case IOAT_OP_PQ_VAL: | |
790 | case IOAT_OP_PQ_VAL_16S: | |
791 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
792 | *desc->result |= SUM_CHECK_P_RESULT; | |
793 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
794 | } | |
795 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
796 | *desc->result |= SUM_CHECK_Q_RESULT; | |
797 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
798 | } | |
799 | break; | |
800 | } | |
801 | ||
9546d4cd DJ |
802 | if (chanerr & IOAT_CHANERR_RECOVER_MASK) { |
803 | if (chanerr & IOAT_CHANERR_READ_DATA_ERR) { | |
804 | res.result = DMA_TRANS_READ_FAILED; | |
805 | err_handled |= IOAT_CHANERR_READ_DATA_ERR; | |
806 | } else if (chanerr & IOAT_CHANERR_WRITE_DATA_ERR) { | |
807 | res.result = DMA_TRANS_WRITE_FAILED; | |
808 | err_handled |= IOAT_CHANERR_WRITE_DATA_ERR; | |
809 | } | |
810 | ||
811 | abort = true; | |
812 | } else | |
813 | res.result = DMA_TRANS_NOERROR; | |
814 | ||
3372de58 DJ |
815 | /* fault on unhandled error or spurious halt */ |
816 | if (chanerr ^ err_handled || chanerr == 0) { | |
817 | dev_err(to_dev(ioat_chan), "%s: fatal error (%x:%x)\n", | |
818 | __func__, chanerr, err_handled); | |
aed681d1 DJ |
819 | dev_err(to_dev(ioat_chan), "Errors handled:\n"); |
820 | ioat_print_chanerrs(ioat_chan, err_handled); | |
821 | dev_err(to_dev(ioat_chan), "Errors not handled:\n"); | |
822 | ioat_print_chanerrs(ioat_chan, (chanerr & ~err_handled)); | |
823 | ||
3372de58 | 824 | BUG(); |
3372de58 DJ |
825 | } |
826 | ||
9546d4cd DJ |
827 | /* cleanup the faulty descriptor since we are continuing */ |
828 | tx = &desc->txd; | |
829 | if (tx->cookie) { | |
830 | dma_cookie_complete(tx); | |
831 | dma_descriptor_unmap(tx); | |
832 | dmaengine_desc_get_callback_invoke(tx, &res); | |
833 | tx->callback = NULL; | |
834 | tx->callback_result = NULL; | |
835 | } | |
3372de58 DJ |
836 | |
837 | /* mark faulting descriptor as complete */ | |
838 | *ioat_chan->completion = desc->txd.phys; | |
839 | ||
840 | spin_lock_bh(&ioat_chan->prep_lock); | |
9546d4cd DJ |
841 | /* we need abort all descriptors */ |
842 | if (abort) { | |
843 | ioat_abort_descs(ioat_chan); | |
844 | /* clean up the channel, we could be in weird state */ | |
845 | ioat_reset_hw(ioat_chan); | |
846 | } | |
847 | ||
848 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
849 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
850 | ||
3372de58 DJ |
851 | ioat_restart_channel(ioat_chan); |
852 | spin_unlock_bh(&ioat_chan->prep_lock); | |
853 | } | |
854 | ||
855 | static void check_active(struct ioatdma_chan *ioat_chan) | |
856 | { | |
857 | if (ioat_ring_active(ioat_chan)) { | |
858 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
859 | return; | |
860 | } | |
861 | ||
862 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) | |
863 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); | |
3372de58 DJ |
864 | } |
865 | ||
866 | void ioat_timer_event(unsigned long data) | |
867 | { | |
868 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); | |
869 | dma_addr_t phys_complete; | |
870 | u64 status; | |
871 | ||
872 | status = ioat_chansts(ioat_chan); | |
873 | ||
874 | /* when halted due to errors check for channel | |
875 | * programming errors before advancing the completion state | |
876 | */ | |
877 | if (is_ioat_halted(status)) { | |
878 | u32 chanerr; | |
879 | ||
880 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
881 | dev_err(to_dev(ioat_chan), "%s: Channel halted (%x)\n", | |
882 | __func__, chanerr); | |
aed681d1 DJ |
883 | dev_err(to_dev(ioat_chan), "Errors:\n"); |
884 | ioat_print_chanerrs(ioat_chan, chanerr); | |
885 | ||
9546d4cd DJ |
886 | if (test_bit(IOAT_RUN, &ioat_chan->state)) { |
887 | spin_lock_bh(&ioat_chan->cleanup_lock); | |
888 | spin_lock_bh(&ioat_chan->prep_lock); | |
889 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); | |
890 | spin_unlock_bh(&ioat_chan->prep_lock); | |
891 | ||
892 | ioat_abort_descs(ioat_chan); | |
893 | dev_warn(to_dev(ioat_chan), "Reset channel...\n"); | |
894 | ioat_reset_hw(ioat_chan); | |
895 | dev_warn(to_dev(ioat_chan), "Restart channel...\n"); | |
896 | ioat_restart_channel(ioat_chan); | |
897 | ||
898 | spin_lock_bh(&ioat_chan->prep_lock); | |
899 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); | |
900 | spin_unlock_bh(&ioat_chan->prep_lock); | |
901 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
902 | } | |
903 | ||
904 | return; | |
3372de58 DJ |
905 | } |
906 | ||
8a695db0 DJ |
907 | spin_lock_bh(&ioat_chan->cleanup_lock); |
908 | ||
909 | /* handle the no-actives case */ | |
910 | if (!ioat_ring_active(ioat_chan)) { | |
911 | spin_lock_bh(&ioat_chan->prep_lock); | |
912 | check_active(ioat_chan); | |
913 | spin_unlock_bh(&ioat_chan->prep_lock); | |
914 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
915 | return; | |
916 | } | |
917 | ||
3372de58 DJ |
918 | /* if we haven't made progress and we have already |
919 | * acknowledged a pending completion once, then be more | |
920 | * forceful with a restart | |
921 | */ | |
3372de58 DJ |
922 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
923 | __cleanup(ioat_chan, phys_complete); | |
924 | else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) { | |
8a695db0 DJ |
925 | u32 chanerr; |
926 | ||
927 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
aed681d1 DJ |
928 | dev_err(to_dev(ioat_chan), "CHANSTS: %#Lx CHANERR: %#x\n", |
929 | status, chanerr); | |
930 | dev_err(to_dev(ioat_chan), "Errors:\n"); | |
931 | ioat_print_chanerrs(ioat_chan, chanerr); | |
932 | ||
933 | dev_dbg(to_dev(ioat_chan), "Active descriptors: %d\n", | |
934 | ioat_ring_active(ioat_chan)); | |
8a695db0 | 935 | |
3372de58 | 936 | spin_lock_bh(&ioat_chan->prep_lock); |
9546d4cd DJ |
937 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
938 | spin_unlock_bh(&ioat_chan->prep_lock); | |
939 | ||
940 | ioat_abort_descs(ioat_chan); | |
941 | dev_warn(to_dev(ioat_chan), "Resetting channel...\n"); | |
942 | ioat_reset_hw(ioat_chan); | |
943 | dev_warn(to_dev(ioat_chan), "Restarting channel...\n"); | |
3372de58 | 944 | ioat_restart_channel(ioat_chan); |
9546d4cd DJ |
945 | |
946 | spin_lock_bh(&ioat_chan->prep_lock); | |
947 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); | |
3372de58 DJ |
948 | spin_unlock_bh(&ioat_chan->prep_lock); |
949 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
950 | return; | |
8a695db0 | 951 | } else |
3372de58 | 952 | set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); |
3372de58 | 953 | |
8a695db0 | 954 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
3372de58 DJ |
955 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
956 | } | |
957 | ||
958 | enum dma_status | |
959 | ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, | |
960 | struct dma_tx_state *txstate) | |
961 | { | |
962 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
963 | enum dma_status ret; | |
964 | ||
965 | ret = dma_cookie_status(c, cookie, txstate); | |
966 | if (ret == DMA_COMPLETE) | |
967 | return ret; | |
968 | ||
969 | ioat_cleanup(ioat_chan); | |
970 | ||
971 | return dma_cookie_status(c, cookie, txstate); | |
972 | } | |
973 | ||
3372de58 DJ |
974 | int ioat_reset_hw(struct ioatdma_chan *ioat_chan) |
975 | { | |
976 | /* throw away whatever the channel was doing and get it | |
977 | * initialized, with ioat3 specific workarounds | |
978 | */ | |
979 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
980 | struct pci_dev *pdev = ioat_dma->pdev; | |
981 | u32 chanerr; | |
982 | u16 dev_id; | |
983 | int err; | |
984 | ||
985 | ioat_quiesce(ioat_chan, msecs_to_jiffies(100)); | |
986 | ||
987 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
988 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
989 | ||
990 | if (ioat_dma->version < IOAT_VER_3_3) { | |
991 | /* clear any pending errors */ | |
992 | err = pci_read_config_dword(pdev, | |
993 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
994 | if (err) { | |
995 | dev_err(&pdev->dev, | |
996 | "channel error register unreachable\n"); | |
997 | return err; | |
998 | } | |
999 | pci_write_config_dword(pdev, | |
1000 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
1001 | ||
1002 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit | |
1003 | * (workaround for spurious config parity error after restart) | |
1004 | */ | |
1005 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1006 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
1007 | pci_write_config_dword(pdev, | |
1008 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
1009 | 0x10); | |
1010 | } | |
1011 | } | |
1012 | ||
c997e30e DJ |
1013 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { |
1014 | ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000); | |
1015 | ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008); | |
1016 | ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800); | |
1017 | } | |
1018 | ||
1019 | ||
3372de58 | 1020 | err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200)); |
c997e30e DJ |
1021 | if (!err) { |
1022 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { | |
1023 | writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000); | |
1024 | writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008); | |
1025 | writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800); | |
1026 | } | |
1027 | } | |
3372de58 DJ |
1028 | |
1029 | if (err) | |
1030 | dev_err(&pdev->dev, "Failed to reset: %d\n", err); | |
1031 | ||
1032 | return err; | |
1033 | } |