Commit | Line | Data |
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1ec1e82f SH |
1 | /* |
2 | * drivers/dma/imx-sdma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale Smart DMA engine | |
5 | * | |
6 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
7 | * | |
8 | * Based on code from Freescale: | |
9 | * | |
10 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
11 | * | |
12 | * The code contained herein is licensed under the GNU General Public | |
13 | * License. You may obtain a copy of the GNU General Public License | |
14 | * Version 2 or later at the following locations: | |
15 | * | |
16 | * http://www.opensource.org/licenses/gpl-license.html | |
17 | * http://www.gnu.org/copyleft/gpl.html | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
1d069bfa | 21 | #include <linux/iopoll.h> |
f8de8f4c | 22 | #include <linux/module.h> |
1ec1e82f | 23 | #include <linux/types.h> |
0bbc1413 | 24 | #include <linux/bitops.h> |
1ec1e82f SH |
25 | #include <linux/mm.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/clk.h> | |
2ccaef05 | 28 | #include <linux/delay.h> |
1ec1e82f SH |
29 | #include <linux/sched.h> |
30 | #include <linux/semaphore.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/device.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/firmware.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/dmaengine.h> | |
580975d7 | 38 | #include <linux/of.h> |
8391ecf4 | 39 | #include <linux/of_address.h> |
580975d7 | 40 | #include <linux/of_device.h> |
9479e17c | 41 | #include <linux/of_dma.h> |
1ec1e82f SH |
42 | |
43 | #include <asm/irq.h> | |
82906b13 AB |
44 | #include <linux/platform_data/dma-imx-sdma.h> |
45 | #include <linux/platform_data/dma-imx.h> | |
d078cd1b ZW |
46 | #include <linux/regmap.h> |
47 | #include <linux/mfd/syscon.h> | |
48 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
1ec1e82f | 49 | |
d2ebfb33 RKAL |
50 | #include "dmaengine.h" |
51 | ||
1ec1e82f SH |
52 | /* SDMA registers */ |
53 | #define SDMA_H_C0PTR 0x000 | |
54 | #define SDMA_H_INTR 0x004 | |
55 | #define SDMA_H_STATSTOP 0x008 | |
56 | #define SDMA_H_START 0x00c | |
57 | #define SDMA_H_EVTOVR 0x010 | |
58 | #define SDMA_H_DSPOVR 0x014 | |
59 | #define SDMA_H_HOSTOVR 0x018 | |
60 | #define SDMA_H_EVTPEND 0x01c | |
61 | #define SDMA_H_DSPENBL 0x020 | |
62 | #define SDMA_H_RESET 0x024 | |
63 | #define SDMA_H_EVTERR 0x028 | |
64 | #define SDMA_H_INTRMSK 0x02c | |
65 | #define SDMA_H_PSW 0x030 | |
66 | #define SDMA_H_EVTERRDBG 0x034 | |
67 | #define SDMA_H_CONFIG 0x038 | |
68 | #define SDMA_ONCE_ENB 0x040 | |
69 | #define SDMA_ONCE_DATA 0x044 | |
70 | #define SDMA_ONCE_INSTR 0x048 | |
71 | #define SDMA_ONCE_STAT 0x04c | |
72 | #define SDMA_ONCE_CMD 0x050 | |
73 | #define SDMA_EVT_MIRROR 0x054 | |
74 | #define SDMA_ILLINSTADDR 0x058 | |
75 | #define SDMA_CHN0ADDR 0x05c | |
76 | #define SDMA_ONCE_RTB 0x060 | |
77 | #define SDMA_XTRIG_CONF1 0x070 | |
78 | #define SDMA_XTRIG_CONF2 0x074 | |
62550cd7 SG |
79 | #define SDMA_CHNENBL0_IMX35 0x200 |
80 | #define SDMA_CHNENBL0_IMX31 0x080 | |
1ec1e82f SH |
81 | #define SDMA_CHNPRI_0 0x100 |
82 | ||
83 | /* | |
84 | * Buffer descriptor status values. | |
85 | */ | |
86 | #define BD_DONE 0x01 | |
87 | #define BD_WRAP 0x02 | |
88 | #define BD_CONT 0x04 | |
89 | #define BD_INTR 0x08 | |
90 | #define BD_RROR 0x10 | |
91 | #define BD_LAST 0x20 | |
92 | #define BD_EXTD 0x80 | |
93 | ||
94 | /* | |
95 | * Data Node descriptor status values. | |
96 | */ | |
97 | #define DND_END_OF_FRAME 0x80 | |
98 | #define DND_END_OF_XFER 0x40 | |
99 | #define DND_DONE 0x20 | |
100 | #define DND_UNUSED 0x01 | |
101 | ||
102 | /* | |
103 | * IPCV2 descriptor status values. | |
104 | */ | |
105 | #define BD_IPCV2_END_OF_FRAME 0x40 | |
106 | ||
107 | #define IPCV2_MAX_NODES 50 | |
108 | /* | |
109 | * Error bit set in the CCB status field by the SDMA, | |
110 | * in setbd routine, in case of a transfer error | |
111 | */ | |
112 | #define DATA_ERROR 0x10000000 | |
113 | ||
114 | /* | |
115 | * Buffer descriptor commands. | |
116 | */ | |
117 | #define C0_ADDR 0x01 | |
118 | #define C0_LOAD 0x02 | |
119 | #define C0_DUMP 0x03 | |
120 | #define C0_SETCTX 0x07 | |
121 | #define C0_GETCTX 0x03 | |
122 | #define C0_SETDM 0x01 | |
123 | #define C0_SETPM 0x04 | |
124 | #define C0_GETDM 0x02 | |
125 | #define C0_GETPM 0x08 | |
126 | /* | |
127 | * Change endianness indicator in the BD command field | |
128 | */ | |
129 | #define CHANGE_ENDIANNESS 0x80 | |
130 | ||
8391ecf4 SW |
131 | /* |
132 | * p_2_p watermark_level description | |
133 | * Bits Name Description | |
134 | * 0-7 Lower WML Lower watermark level | |
135 | * 8 PS 1: Pad Swallowing | |
136 | * 0: No Pad Swallowing | |
137 | * 9 PA 1: Pad Adding | |
138 | * 0: No Pad Adding | |
139 | * 10 SPDIF If this bit is set both source | |
140 | * and destination are on SPBA | |
141 | * 11 Source Bit(SP) 1: Source on SPBA | |
142 | * 0: Source on AIPS | |
143 | * 12 Destination Bit(DP) 1: Destination on SPBA | |
144 | * 0: Destination on AIPS | |
145 | * 13-15 --------- MUST BE 0 | |
146 | * 16-23 Higher WML HWML | |
147 | * 24-27 N Total number of samples after | |
148 | * which Pad adding/Swallowing | |
149 | * must be done. It must be odd. | |
150 | * 28 Lower WML Event(LWE) SDMA events reg to check for | |
151 | * LWML event mask | |
152 | * 0: LWE in EVENTS register | |
153 | * 1: LWE in EVENTS2 register | |
154 | * 29 Higher WML Event(HWE) SDMA events reg to check for | |
155 | * HWML event mask | |
156 | * 0: HWE in EVENTS register | |
157 | * 1: HWE in EVENTS2 register | |
158 | * 30 --------- MUST BE 0 | |
159 | * 31 CONT 1: Amount of samples to be | |
160 | * transferred is unknown and | |
161 | * script will keep on | |
162 | * transferring samples as long as | |
163 | * both events are detected and | |
164 | * script must be manually stopped | |
165 | * by the application | |
166 | * 0: The amount of samples to be | |
167 | * transferred is equal to the | |
168 | * count field of mode word | |
169 | */ | |
170 | #define SDMA_WATERMARK_LEVEL_LWML 0xFF | |
171 | #define SDMA_WATERMARK_LEVEL_PS BIT(8) | |
172 | #define SDMA_WATERMARK_LEVEL_PA BIT(9) | |
173 | #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) | |
174 | #define SDMA_WATERMARK_LEVEL_SP BIT(11) | |
175 | #define SDMA_WATERMARK_LEVEL_DP BIT(12) | |
176 | #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) | |
177 | #define SDMA_WATERMARK_LEVEL_LWE BIT(28) | |
178 | #define SDMA_WATERMARK_LEVEL_HWE BIT(29) | |
179 | #define SDMA_WATERMARK_LEVEL_CONT BIT(31) | |
180 | ||
1ec1e82f SH |
181 | /* |
182 | * Mode/Count of data node descriptors - IPCv2 | |
183 | */ | |
184 | struct sdma_mode_count { | |
185 | u32 count : 16; /* size of the buffer pointed by this BD */ | |
186 | u32 status : 8; /* E,R,I,C,W,D status bits stored here */ | |
e4b75760 | 187 | u32 command : 8; /* command mostly used for channel 0 */ |
1ec1e82f SH |
188 | }; |
189 | ||
190 | /* | |
191 | * Buffer descriptor | |
192 | */ | |
193 | struct sdma_buffer_descriptor { | |
194 | struct sdma_mode_count mode; | |
195 | u32 buffer_addr; /* address of the buffer described */ | |
196 | u32 ext_buffer_addr; /* extended buffer address */ | |
197 | } __attribute__ ((packed)); | |
198 | ||
199 | /** | |
200 | * struct sdma_channel_control - Channel control Block | |
201 | * | |
202 | * @current_bd_ptr current buffer descriptor processed | |
203 | * @base_bd_ptr first element of buffer descriptor array | |
204 | * @unused padding. The SDMA engine expects an array of 128 byte | |
205 | * control blocks | |
206 | */ | |
207 | struct sdma_channel_control { | |
208 | u32 current_bd_ptr; | |
209 | u32 base_bd_ptr; | |
210 | u32 unused[2]; | |
211 | } __attribute__ ((packed)); | |
212 | ||
213 | /** | |
214 | * struct sdma_state_registers - SDMA context for a channel | |
215 | * | |
216 | * @pc: program counter | |
217 | * @t: test bit: status of arithmetic & test instruction | |
218 | * @rpc: return program counter | |
219 | * @sf: source fault while loading data | |
220 | * @spc: loop start program counter | |
221 | * @df: destination fault while storing data | |
222 | * @epc: loop end program counter | |
223 | * @lm: loop mode | |
224 | */ | |
225 | struct sdma_state_registers { | |
226 | u32 pc :14; | |
227 | u32 unused1: 1; | |
228 | u32 t : 1; | |
229 | u32 rpc :14; | |
230 | u32 unused0: 1; | |
231 | u32 sf : 1; | |
232 | u32 spc :14; | |
233 | u32 unused2: 1; | |
234 | u32 df : 1; | |
235 | u32 epc :14; | |
236 | u32 lm : 2; | |
237 | } __attribute__ ((packed)); | |
238 | ||
239 | /** | |
240 | * struct sdma_context_data - sdma context specific to a channel | |
241 | * | |
242 | * @channel_state: channel state bits | |
243 | * @gReg: general registers | |
244 | * @mda: burst dma destination address register | |
245 | * @msa: burst dma source address register | |
246 | * @ms: burst dma status register | |
247 | * @md: burst dma data register | |
248 | * @pda: peripheral dma destination address register | |
249 | * @psa: peripheral dma source address register | |
250 | * @ps: peripheral dma status register | |
251 | * @pd: peripheral dma data register | |
252 | * @ca: CRC polynomial register | |
253 | * @cs: CRC accumulator register | |
254 | * @dda: dedicated core destination address register | |
255 | * @dsa: dedicated core source address register | |
256 | * @ds: dedicated core status register | |
257 | * @dd: dedicated core data register | |
258 | */ | |
259 | struct sdma_context_data { | |
260 | struct sdma_state_registers channel_state; | |
261 | u32 gReg[8]; | |
262 | u32 mda; | |
263 | u32 msa; | |
264 | u32 ms; | |
265 | u32 md; | |
266 | u32 pda; | |
267 | u32 psa; | |
268 | u32 ps; | |
269 | u32 pd; | |
270 | u32 ca; | |
271 | u32 cs; | |
272 | u32 dda; | |
273 | u32 dsa; | |
274 | u32 ds; | |
275 | u32 dd; | |
276 | u32 scratch0; | |
277 | u32 scratch1; | |
278 | u32 scratch2; | |
279 | u32 scratch3; | |
280 | u32 scratch4; | |
281 | u32 scratch5; | |
282 | u32 scratch6; | |
283 | u32 scratch7; | |
284 | } __attribute__ ((packed)); | |
285 | ||
286 | #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) | |
287 | ||
288 | struct sdma_engine; | |
289 | ||
290 | /** | |
291 | * struct sdma_channel - housekeeping for a SDMA channel | |
292 | * | |
293 | * @sdma pointer to the SDMA engine for this channel | |
23889c63 | 294 | * @channel the channel number, matches dmaengine chan_id + 1 |
1ec1e82f SH |
295 | * @direction transfer type. Needed for setting SDMA script |
296 | * @peripheral_type Peripheral type. Needed for setting SDMA script | |
297 | * @event_id0 aka dma request line | |
298 | * @event_id1 for channels that use 2 events | |
299 | * @word_size peripheral access size | |
300 | * @buf_tail ID of the buffer that was processed | |
85f57752 | 301 | * @buf_ptail ID of the previous buffer that was processed |
1ec1e82f SH |
302 | * @num_bd max NUM_BD. number of descriptors currently handling |
303 | */ | |
304 | struct sdma_channel { | |
305 | struct sdma_engine *sdma; | |
306 | unsigned int channel; | |
db8196df | 307 | enum dma_transfer_direction direction; |
1ec1e82f SH |
308 | enum sdma_peripheral_type peripheral_type; |
309 | unsigned int event_id0; | |
310 | unsigned int event_id1; | |
311 | enum dma_slave_buswidth word_size; | |
312 | unsigned int buf_tail; | |
85f57752 | 313 | unsigned int buf_ptail; |
1ec1e82f | 314 | unsigned int num_bd; |
d1a792f3 | 315 | unsigned int period_len; |
1ec1e82f SH |
316 | struct sdma_buffer_descriptor *bd; |
317 | dma_addr_t bd_phys; | |
318 | unsigned int pc_from_device, pc_to_device; | |
8391ecf4 | 319 | unsigned int device_to_device; |
1ec1e82f | 320 | unsigned long flags; |
8391ecf4 | 321 | dma_addr_t per_address, per_address2; |
0bbc1413 RZ |
322 | unsigned long event_mask[2]; |
323 | unsigned long watermark_level; | |
1ec1e82f SH |
324 | u32 shp_addr, per_addr; |
325 | struct dma_chan chan; | |
326 | spinlock_t lock; | |
327 | struct dma_async_tx_descriptor desc; | |
1ec1e82f | 328 | enum dma_status status; |
ab59a510 HS |
329 | unsigned int chn_count; |
330 | unsigned int chn_real_count; | |
abd9ccc8 | 331 | struct tasklet_struct tasklet; |
0b351865 | 332 | struct imx_dma_data data; |
1ec1e82f SH |
333 | }; |
334 | ||
0bbc1413 | 335 | #define IMX_DMA_SG_LOOP BIT(0) |
1ec1e82f SH |
336 | |
337 | #define MAX_DMA_CHANNELS 32 | |
338 | #define MXC_SDMA_DEFAULT_PRIORITY 1 | |
339 | #define MXC_SDMA_MIN_PRIORITY 1 | |
340 | #define MXC_SDMA_MAX_PRIORITY 7 | |
341 | ||
1ec1e82f SH |
342 | #define SDMA_FIRMWARE_MAGIC 0x414d4453 |
343 | ||
344 | /** | |
345 | * struct sdma_firmware_header - Layout of the firmware image | |
346 | * | |
347 | * @magic "SDMA" | |
348 | * @version_major increased whenever layout of struct sdma_script_start_addrs | |
349 | * changes. | |
350 | * @version_minor firmware minor version (for binary compatible changes) | |
351 | * @script_addrs_start offset of struct sdma_script_start_addrs in this image | |
352 | * @num_script_addrs Number of script addresses in this image | |
353 | * @ram_code_start offset of SDMA ram image in this firmware image | |
354 | * @ram_code_size size of SDMA ram image | |
355 | * @script_addrs Stores the start address of the SDMA scripts | |
356 | * (in SDMA memory space) | |
357 | */ | |
358 | struct sdma_firmware_header { | |
359 | u32 magic; | |
360 | u32 version_major; | |
361 | u32 version_minor; | |
362 | u32 script_addrs_start; | |
363 | u32 num_script_addrs; | |
364 | u32 ram_code_start; | |
365 | u32 ram_code_size; | |
366 | }; | |
367 | ||
17bba72f SH |
368 | struct sdma_driver_data { |
369 | int chnenbl0; | |
370 | int num_events; | |
dcfec3c0 | 371 | struct sdma_script_start_addrs *script_addrs; |
62550cd7 SG |
372 | }; |
373 | ||
1ec1e82f SH |
374 | struct sdma_engine { |
375 | struct device *dev; | |
b9b3f82f | 376 | struct device_dma_parameters dma_parms; |
1ec1e82f SH |
377 | struct sdma_channel channel[MAX_DMA_CHANNELS]; |
378 | struct sdma_channel_control *channel_control; | |
379 | void __iomem *regs; | |
1ec1e82f SH |
380 | struct sdma_context_data *context; |
381 | dma_addr_t context_phys; | |
382 | struct dma_device dma_device; | |
7560e3f3 SH |
383 | struct clk *clk_ipg; |
384 | struct clk *clk_ahb; | |
2ccaef05 | 385 | spinlock_t channel_0_lock; |
cd72b846 | 386 | u32 script_number; |
1ec1e82f | 387 | struct sdma_script_start_addrs *script_addrs; |
17bba72f | 388 | const struct sdma_driver_data *drvdata; |
8391ecf4 SW |
389 | u32 spba_start_addr; |
390 | u32 spba_end_addr; | |
5bb9dbb5 | 391 | unsigned int irq; |
17bba72f SH |
392 | }; |
393 | ||
e9fd58de | 394 | static struct sdma_driver_data sdma_imx31 = { |
17bba72f SH |
395 | .chnenbl0 = SDMA_CHNENBL0_IMX31, |
396 | .num_events = 32, | |
397 | }; | |
398 | ||
dcfec3c0 SH |
399 | static struct sdma_script_start_addrs sdma_script_imx25 = { |
400 | .ap_2_ap_addr = 729, | |
401 | .uart_2_mcu_addr = 904, | |
402 | .per_2_app_addr = 1255, | |
403 | .mcu_2_app_addr = 834, | |
404 | .uartsh_2_mcu_addr = 1120, | |
405 | .per_2_shp_addr = 1329, | |
406 | .mcu_2_shp_addr = 1048, | |
407 | .ata_2_mcu_addr = 1560, | |
408 | .mcu_2_ata_addr = 1479, | |
409 | .app_2_per_addr = 1189, | |
410 | .app_2_mcu_addr = 770, | |
411 | .shp_2_per_addr = 1407, | |
412 | .shp_2_mcu_addr = 979, | |
413 | }; | |
414 | ||
e9fd58de | 415 | static struct sdma_driver_data sdma_imx25 = { |
dcfec3c0 SH |
416 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
417 | .num_events = 48, | |
418 | .script_addrs = &sdma_script_imx25, | |
419 | }; | |
420 | ||
e9fd58de | 421 | static struct sdma_driver_data sdma_imx35 = { |
17bba72f SH |
422 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
423 | .num_events = 48, | |
1ec1e82f SH |
424 | }; |
425 | ||
dcfec3c0 SH |
426 | static struct sdma_script_start_addrs sdma_script_imx51 = { |
427 | .ap_2_ap_addr = 642, | |
428 | .uart_2_mcu_addr = 817, | |
429 | .mcu_2_app_addr = 747, | |
430 | .mcu_2_shp_addr = 961, | |
431 | .ata_2_mcu_addr = 1473, | |
432 | .mcu_2_ata_addr = 1392, | |
433 | .app_2_per_addr = 1033, | |
434 | .app_2_mcu_addr = 683, | |
435 | .shp_2_per_addr = 1251, | |
436 | .shp_2_mcu_addr = 892, | |
437 | }; | |
438 | ||
e9fd58de | 439 | static struct sdma_driver_data sdma_imx51 = { |
dcfec3c0 SH |
440 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
441 | .num_events = 48, | |
442 | .script_addrs = &sdma_script_imx51, | |
443 | }; | |
444 | ||
445 | static struct sdma_script_start_addrs sdma_script_imx53 = { | |
446 | .ap_2_ap_addr = 642, | |
447 | .app_2_mcu_addr = 683, | |
448 | .mcu_2_app_addr = 747, | |
449 | .uart_2_mcu_addr = 817, | |
450 | .shp_2_mcu_addr = 891, | |
451 | .mcu_2_shp_addr = 960, | |
452 | .uartsh_2_mcu_addr = 1032, | |
453 | .spdif_2_mcu_addr = 1100, | |
454 | .mcu_2_spdif_addr = 1134, | |
455 | .firi_2_mcu_addr = 1193, | |
456 | .mcu_2_firi_addr = 1290, | |
457 | }; | |
458 | ||
e9fd58de | 459 | static struct sdma_driver_data sdma_imx53 = { |
dcfec3c0 SH |
460 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
461 | .num_events = 48, | |
462 | .script_addrs = &sdma_script_imx53, | |
463 | }; | |
464 | ||
465 | static struct sdma_script_start_addrs sdma_script_imx6q = { | |
466 | .ap_2_ap_addr = 642, | |
467 | .uart_2_mcu_addr = 817, | |
468 | .mcu_2_app_addr = 747, | |
469 | .per_2_per_addr = 6331, | |
470 | .uartsh_2_mcu_addr = 1032, | |
471 | .mcu_2_shp_addr = 960, | |
472 | .app_2_mcu_addr = 683, | |
473 | .shp_2_mcu_addr = 891, | |
474 | .spdif_2_mcu_addr = 1100, | |
475 | .mcu_2_spdif_addr = 1134, | |
476 | }; | |
477 | ||
e9fd58de | 478 | static struct sdma_driver_data sdma_imx6q = { |
dcfec3c0 SH |
479 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
480 | .num_events = 48, | |
481 | .script_addrs = &sdma_script_imx6q, | |
482 | }; | |
483 | ||
b7d2648a FE |
484 | static struct sdma_script_start_addrs sdma_script_imx7d = { |
485 | .ap_2_ap_addr = 644, | |
486 | .uart_2_mcu_addr = 819, | |
487 | .mcu_2_app_addr = 749, | |
488 | .uartsh_2_mcu_addr = 1034, | |
489 | .mcu_2_shp_addr = 962, | |
490 | .app_2_mcu_addr = 685, | |
491 | .shp_2_mcu_addr = 893, | |
492 | .spdif_2_mcu_addr = 1102, | |
493 | .mcu_2_spdif_addr = 1136, | |
494 | }; | |
495 | ||
496 | static struct sdma_driver_data sdma_imx7d = { | |
497 | .chnenbl0 = SDMA_CHNENBL0_IMX35, | |
498 | .num_events = 48, | |
499 | .script_addrs = &sdma_script_imx7d, | |
500 | }; | |
501 | ||
afe7cded | 502 | static const struct platform_device_id sdma_devtypes[] = { |
62550cd7 | 503 | { |
dcfec3c0 SH |
504 | .name = "imx25-sdma", |
505 | .driver_data = (unsigned long)&sdma_imx25, | |
506 | }, { | |
62550cd7 | 507 | .name = "imx31-sdma", |
17bba72f | 508 | .driver_data = (unsigned long)&sdma_imx31, |
62550cd7 SG |
509 | }, { |
510 | .name = "imx35-sdma", | |
17bba72f | 511 | .driver_data = (unsigned long)&sdma_imx35, |
dcfec3c0 SH |
512 | }, { |
513 | .name = "imx51-sdma", | |
514 | .driver_data = (unsigned long)&sdma_imx51, | |
515 | }, { | |
516 | .name = "imx53-sdma", | |
517 | .driver_data = (unsigned long)&sdma_imx53, | |
518 | }, { | |
519 | .name = "imx6q-sdma", | |
520 | .driver_data = (unsigned long)&sdma_imx6q, | |
b7d2648a FE |
521 | }, { |
522 | .name = "imx7d-sdma", | |
523 | .driver_data = (unsigned long)&sdma_imx7d, | |
62550cd7 SG |
524 | }, { |
525 | /* sentinel */ | |
526 | } | |
527 | }; | |
528 | MODULE_DEVICE_TABLE(platform, sdma_devtypes); | |
529 | ||
580975d7 | 530 | static const struct of_device_id sdma_dt_ids[] = { |
dcfec3c0 SH |
531 | { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, |
532 | { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, | |
533 | { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, | |
17bba72f | 534 | { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, |
dcfec3c0 | 535 | { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, |
63edea16 | 536 | { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, |
b7d2648a | 537 | { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, |
580975d7 SG |
538 | { /* sentinel */ } |
539 | }; | |
540 | MODULE_DEVICE_TABLE(of, sdma_dt_ids); | |
541 | ||
0bbc1413 RZ |
542 | #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ |
543 | #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ | |
544 | #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ | |
1ec1e82f SH |
545 | #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ |
546 | ||
547 | static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) | |
548 | { | |
17bba72f | 549 | u32 chnenbl0 = sdma->drvdata->chnenbl0; |
1ec1e82f SH |
550 | return chnenbl0 + event * 4; |
551 | } | |
552 | ||
553 | static int sdma_config_ownership(struct sdma_channel *sdmac, | |
554 | bool event_override, bool mcu_override, bool dsp_override) | |
555 | { | |
556 | struct sdma_engine *sdma = sdmac->sdma; | |
557 | int channel = sdmac->channel; | |
0bbc1413 | 558 | unsigned long evt, mcu, dsp; |
1ec1e82f SH |
559 | |
560 | if (event_override && mcu_override && dsp_override) | |
561 | return -EINVAL; | |
562 | ||
c4b56857 RZ |
563 | evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); |
564 | mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); | |
565 | dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
566 | |
567 | if (dsp_override) | |
0bbc1413 | 568 | __clear_bit(channel, &dsp); |
1ec1e82f | 569 | else |
0bbc1413 | 570 | __set_bit(channel, &dsp); |
1ec1e82f SH |
571 | |
572 | if (event_override) | |
0bbc1413 | 573 | __clear_bit(channel, &evt); |
1ec1e82f | 574 | else |
0bbc1413 | 575 | __set_bit(channel, &evt); |
1ec1e82f SH |
576 | |
577 | if (mcu_override) | |
0bbc1413 | 578 | __clear_bit(channel, &mcu); |
1ec1e82f | 579 | else |
0bbc1413 | 580 | __set_bit(channel, &mcu); |
1ec1e82f | 581 | |
c4b56857 RZ |
582 | writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); |
583 | writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); | |
584 | writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
585 | |
586 | return 0; | |
587 | } | |
588 | ||
b9a59166 RZ |
589 | static void sdma_enable_channel(struct sdma_engine *sdma, int channel) |
590 | { | |
0bbc1413 | 591 | writel(BIT(channel), sdma->regs + SDMA_H_START); |
b9a59166 RZ |
592 | } |
593 | ||
1ec1e82f | 594 | /* |
2ccaef05 | 595 | * sdma_run_channel0 - run a channel and wait till it's done |
1ec1e82f | 596 | */ |
2ccaef05 | 597 | static int sdma_run_channel0(struct sdma_engine *sdma) |
1ec1e82f | 598 | { |
1ec1e82f | 599 | int ret; |
1d069bfa | 600 | u32 reg; |
1ec1e82f | 601 | |
2ccaef05 | 602 | sdma_enable_channel(sdma, 0); |
1ec1e82f | 603 | |
1d069bfa MO |
604 | ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, |
605 | reg, !(reg & 1), 1, 500); | |
606 | if (ret) | |
2ccaef05 | 607 | dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); |
1ec1e82f | 608 | |
855832e4 RG |
609 | /* Set bits of CONFIG register with dynamic context switching */ |
610 | if (readl(sdma->regs + SDMA_H_CONFIG) == 0) | |
611 | writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); | |
612 | ||
1d069bfa | 613 | return ret; |
1ec1e82f SH |
614 | } |
615 | ||
616 | static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, | |
617 | u32 address) | |
618 | { | |
619 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
620 | void *buf_virt; | |
621 | dma_addr_t buf_phys; | |
622 | int ret; | |
2ccaef05 | 623 | unsigned long flags; |
73eab978 | 624 | |
1ec1e82f SH |
625 | buf_virt = dma_alloc_coherent(NULL, |
626 | size, | |
627 | &buf_phys, GFP_KERNEL); | |
73eab978 | 628 | if (!buf_virt) { |
2ccaef05 | 629 | return -ENOMEM; |
73eab978 | 630 | } |
1ec1e82f | 631 | |
2ccaef05 RZ |
632 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
633 | ||
1ec1e82f SH |
634 | bd0->mode.command = C0_SETPM; |
635 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
636 | bd0->mode.count = size / 2; | |
637 | bd0->buffer_addr = buf_phys; | |
638 | bd0->ext_buffer_addr = address; | |
639 | ||
640 | memcpy(buf_virt, buf, size); | |
641 | ||
2ccaef05 | 642 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 643 | |
2ccaef05 | 644 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
1ec1e82f | 645 | |
2ccaef05 | 646 | dma_free_coherent(NULL, size, buf_virt, buf_phys); |
73eab978 | 647 | |
1ec1e82f SH |
648 | return ret; |
649 | } | |
650 | ||
651 | static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) | |
652 | { | |
653 | struct sdma_engine *sdma = sdmac->sdma; | |
654 | int channel = sdmac->channel; | |
0bbc1413 | 655 | unsigned long val; |
1ec1e82f SH |
656 | u32 chnenbl = chnenbl_ofs(sdma, event); |
657 | ||
c4b56857 | 658 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 659 | __set_bit(channel, &val); |
c4b56857 | 660 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
661 | } |
662 | ||
663 | static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) | |
664 | { | |
665 | struct sdma_engine *sdma = sdmac->sdma; | |
666 | int channel = sdmac->channel; | |
667 | u32 chnenbl = chnenbl_ofs(sdma, event); | |
0bbc1413 | 668 | unsigned long val; |
1ec1e82f | 669 | |
c4b56857 | 670 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 671 | __clear_bit(channel, &val); |
c4b56857 | 672 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
673 | } |
674 | ||
d1a792f3 | 675 | static void sdma_update_channel_loop(struct sdma_channel *sdmac) |
1ec1e82f SH |
676 | { |
677 | struct sdma_buffer_descriptor *bd; | |
5881826d NH |
678 | int error = 0; |
679 | enum dma_status old_status = sdmac->status; | |
1ec1e82f SH |
680 | |
681 | /* | |
682 | * loop mode. Iterate over descriptors, re-setup them and | |
683 | * call callback function. | |
684 | */ | |
685 | while (1) { | |
686 | bd = &sdmac->bd[sdmac->buf_tail]; | |
687 | ||
688 | if (bd->mode.status & BD_DONE) | |
689 | break; | |
690 | ||
5881826d NH |
691 | if (bd->mode.status & BD_RROR) { |
692 | bd->mode.status &= ~BD_RROR; | |
1ec1e82f | 693 | sdmac->status = DMA_ERROR; |
5881826d NH |
694 | error = -EIO; |
695 | } | |
1ec1e82f | 696 | |
5881826d NH |
697 | /* |
698 | * We use bd->mode.count to calculate the residue, since contains | |
699 | * the number of bytes present in the current buffer descriptor. | |
700 | */ | |
701 | ||
702 | sdmac->chn_real_count = bd->mode.count; | |
1ec1e82f | 703 | bd->mode.status |= BD_DONE; |
5881826d | 704 | bd->mode.count = sdmac->period_len; |
85f57752 NH |
705 | sdmac->buf_ptail = sdmac->buf_tail; |
706 | sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd; | |
15f30f51 NH |
707 | |
708 | /* | |
709 | * The callback is called from the interrupt context in order | |
710 | * to reduce latency and to avoid the risk of altering the | |
711 | * SDMA transaction status by the time the client tasklet is | |
712 | * executed. | |
713 | */ | |
714 | ||
553911c6 | 715 | dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL); |
15f30f51 | 716 | |
5881826d NH |
717 | if (error) |
718 | sdmac->status = old_status; | |
1ec1e82f SH |
719 | } |
720 | } | |
721 | ||
15f30f51 | 722 | static void mxc_sdma_handle_channel_normal(unsigned long data) |
1ec1e82f | 723 | { |
15f30f51 | 724 | struct sdma_channel *sdmac = (struct sdma_channel *) data; |
1ec1e82f SH |
725 | struct sdma_buffer_descriptor *bd; |
726 | int i, error = 0; | |
727 | ||
ab59a510 | 728 | sdmac->chn_real_count = 0; |
1ec1e82f SH |
729 | /* |
730 | * non loop mode. Iterate over all descriptors, collect | |
731 | * errors and call callback function | |
732 | */ | |
733 | for (i = 0; i < sdmac->num_bd; i++) { | |
734 | bd = &sdmac->bd[i]; | |
735 | ||
736 | if (bd->mode.status & (BD_DONE | BD_RROR)) | |
737 | error = -EIO; | |
ab59a510 | 738 | sdmac->chn_real_count += bd->mode.count; |
1ec1e82f SH |
739 | } |
740 | ||
741 | if (error) | |
742 | sdmac->status = DMA_ERROR; | |
743 | else | |
409bff6a | 744 | sdmac->status = DMA_COMPLETE; |
1ec1e82f | 745 | |
f7fbce07 | 746 | dma_cookie_complete(&sdmac->desc); |
48dc77e2 DJ |
747 | |
748 | dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL); | |
1ec1e82f SH |
749 | } |
750 | ||
1ec1e82f SH |
751 | static irqreturn_t sdma_int_handler(int irq, void *dev_id) |
752 | { | |
753 | struct sdma_engine *sdma = dev_id; | |
0bbc1413 | 754 | unsigned long stat; |
1ec1e82f | 755 | |
c4b56857 RZ |
756 | stat = readl_relaxed(sdma->regs + SDMA_H_INTR); |
757 | writel_relaxed(stat, sdma->regs + SDMA_H_INTR); | |
1d069bfa MO |
758 | /* channel 0 is special and not handled here, see run_channel0() */ |
759 | stat &= ~1; | |
1ec1e82f SH |
760 | |
761 | while (stat) { | |
762 | int channel = fls(stat) - 1; | |
763 | struct sdma_channel *sdmac = &sdma->channel[channel]; | |
764 | ||
d1a792f3 RKAL |
765 | if (sdmac->flags & IMX_DMA_SG_LOOP) |
766 | sdma_update_channel_loop(sdmac); | |
15f30f51 NH |
767 | else |
768 | tasklet_schedule(&sdmac->tasklet); | |
1ec1e82f | 769 | |
0bbc1413 | 770 | __clear_bit(channel, &stat); |
1ec1e82f SH |
771 | } |
772 | ||
773 | return IRQ_HANDLED; | |
774 | } | |
775 | ||
776 | /* | |
777 | * sets the pc of SDMA script according to the peripheral type | |
778 | */ | |
779 | static void sdma_get_pc(struct sdma_channel *sdmac, | |
780 | enum sdma_peripheral_type peripheral_type) | |
781 | { | |
782 | struct sdma_engine *sdma = sdmac->sdma; | |
783 | int per_2_emi = 0, emi_2_per = 0; | |
784 | /* | |
785 | * These are needed once we start to support transfers between | |
786 | * two peripherals or memory-to-memory transfers | |
787 | */ | |
0d605ba0 | 788 | int per_2_per = 0; |
1ec1e82f SH |
789 | |
790 | sdmac->pc_from_device = 0; | |
791 | sdmac->pc_to_device = 0; | |
8391ecf4 | 792 | sdmac->device_to_device = 0; |
1ec1e82f SH |
793 | |
794 | switch (peripheral_type) { | |
795 | case IMX_DMATYPE_MEMORY: | |
1ec1e82f SH |
796 | break; |
797 | case IMX_DMATYPE_DSP: | |
798 | emi_2_per = sdma->script_addrs->bp_2_ap_addr; | |
799 | per_2_emi = sdma->script_addrs->ap_2_bp_addr; | |
800 | break; | |
801 | case IMX_DMATYPE_FIRI: | |
802 | per_2_emi = sdma->script_addrs->firi_2_mcu_addr; | |
803 | emi_2_per = sdma->script_addrs->mcu_2_firi_addr; | |
804 | break; | |
805 | case IMX_DMATYPE_UART: | |
806 | per_2_emi = sdma->script_addrs->uart_2_mcu_addr; | |
807 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
808 | break; | |
809 | case IMX_DMATYPE_UART_SP: | |
810 | per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; | |
811 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
812 | break; | |
813 | case IMX_DMATYPE_ATA: | |
814 | per_2_emi = sdma->script_addrs->ata_2_mcu_addr; | |
815 | emi_2_per = sdma->script_addrs->mcu_2_ata_addr; | |
816 | break; | |
817 | case IMX_DMATYPE_CSPI: | |
818 | case IMX_DMATYPE_EXT: | |
819 | case IMX_DMATYPE_SSI: | |
29aebfde | 820 | case IMX_DMATYPE_SAI: |
1ec1e82f SH |
821 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; |
822 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
823 | break; | |
1a895578 NC |
824 | case IMX_DMATYPE_SSI_DUAL: |
825 | per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; | |
826 | emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; | |
827 | break; | |
1ec1e82f SH |
828 | case IMX_DMATYPE_SSI_SP: |
829 | case IMX_DMATYPE_MMC: | |
830 | case IMX_DMATYPE_SDHC: | |
831 | case IMX_DMATYPE_CSPI_SP: | |
832 | case IMX_DMATYPE_ESAI: | |
833 | case IMX_DMATYPE_MSHC_SP: | |
834 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
835 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
836 | break; | |
837 | case IMX_DMATYPE_ASRC: | |
838 | per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; | |
839 | emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; | |
840 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
841 | break; | |
f892afb0 NC |
842 | case IMX_DMATYPE_ASRC_SP: |
843 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
844 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
845 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
846 | break; | |
1ec1e82f SH |
847 | case IMX_DMATYPE_MSHC: |
848 | per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; | |
849 | emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; | |
850 | break; | |
851 | case IMX_DMATYPE_CCM: | |
852 | per_2_emi = sdma->script_addrs->dptc_dvfs_addr; | |
853 | break; | |
854 | case IMX_DMATYPE_SPDIF: | |
855 | per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; | |
856 | emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; | |
857 | break; | |
858 | case IMX_DMATYPE_IPU_MEMORY: | |
859 | emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; | |
860 | break; | |
861 | default: | |
862 | break; | |
863 | } | |
864 | ||
865 | sdmac->pc_from_device = per_2_emi; | |
866 | sdmac->pc_to_device = emi_2_per; | |
8391ecf4 | 867 | sdmac->device_to_device = per_2_per; |
1ec1e82f SH |
868 | } |
869 | ||
870 | static int sdma_load_context(struct sdma_channel *sdmac) | |
871 | { | |
872 | struct sdma_engine *sdma = sdmac->sdma; | |
873 | int channel = sdmac->channel; | |
874 | int load_address; | |
875 | struct sdma_context_data *context = sdma->context; | |
876 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
877 | int ret; | |
2ccaef05 | 878 | unsigned long flags; |
1ec1e82f | 879 | |
8391ecf4 | 880 | if (sdmac->direction == DMA_DEV_TO_MEM) |
1ec1e82f | 881 | load_address = sdmac->pc_from_device; |
8391ecf4 SW |
882 | else if (sdmac->direction == DMA_DEV_TO_DEV) |
883 | load_address = sdmac->device_to_device; | |
884 | else | |
1ec1e82f | 885 | load_address = sdmac->pc_to_device; |
1ec1e82f SH |
886 | |
887 | if (load_address < 0) | |
888 | return load_address; | |
889 | ||
890 | dev_dbg(sdma->dev, "load_address = %d\n", load_address); | |
0bbc1413 | 891 | dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); |
1ec1e82f SH |
892 | dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); |
893 | dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); | |
0bbc1413 RZ |
894 | dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); |
895 | dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); | |
1ec1e82f | 896 | |
2ccaef05 | 897 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
73eab978 | 898 | |
1ec1e82f SH |
899 | memset(context, 0, sizeof(*context)); |
900 | context->channel_state.pc = load_address; | |
901 | ||
902 | /* Send by context the event mask,base address for peripheral | |
903 | * and watermark level | |
904 | */ | |
0bbc1413 RZ |
905 | context->gReg[0] = sdmac->event_mask[1]; |
906 | context->gReg[1] = sdmac->event_mask[0]; | |
1ec1e82f SH |
907 | context->gReg[2] = sdmac->per_addr; |
908 | context->gReg[6] = sdmac->shp_addr; | |
909 | context->gReg[7] = sdmac->watermark_level; | |
910 | ||
911 | bd0->mode.command = C0_SETDM; | |
912 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
913 | bd0->mode.count = sizeof(*context) / 4; | |
914 | bd0->buffer_addr = sdma->context_phys; | |
915 | bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; | |
2ccaef05 | 916 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 917 | |
2ccaef05 | 918 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
73eab978 | 919 | |
1ec1e82f SH |
920 | return ret; |
921 | } | |
922 | ||
7b350ab0 MR |
923 | static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) |
924 | { | |
925 | return container_of(chan, struct sdma_channel, chan); | |
926 | } | |
927 | ||
928 | static int sdma_disable_channel(struct dma_chan *chan) | |
1ec1e82f | 929 | { |
7b350ab0 | 930 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1ec1e82f SH |
931 | struct sdma_engine *sdma = sdmac->sdma; |
932 | int channel = sdmac->channel; | |
933 | ||
0bbc1413 | 934 | writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); |
1ec1e82f | 935 | sdmac->status = DMA_ERROR; |
7b350ab0 MR |
936 | |
937 | return 0; | |
1ec1e82f SH |
938 | } |
939 | ||
8391ecf4 SW |
940 | static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) |
941 | { | |
942 | struct sdma_engine *sdma = sdmac->sdma; | |
943 | ||
944 | int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; | |
945 | int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; | |
946 | ||
947 | set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); | |
948 | set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); | |
949 | ||
950 | if (sdmac->event_id0 > 31) | |
951 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; | |
952 | ||
953 | if (sdmac->event_id1 > 31) | |
954 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; | |
955 | ||
956 | /* | |
957 | * If LWML(src_maxburst) > HWML(dst_maxburst), we need | |
958 | * swap LWML and HWML of INFO(A.3.2.5.1), also need swap | |
959 | * r0(event_mask[1]) and r1(event_mask[0]). | |
960 | */ | |
961 | if (lwml > hwml) { | |
962 | sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | | |
963 | SDMA_WATERMARK_LEVEL_HWML); | |
964 | sdmac->watermark_level |= hwml; | |
965 | sdmac->watermark_level |= lwml << 16; | |
966 | swap(sdmac->event_mask[0], sdmac->event_mask[1]); | |
967 | } | |
968 | ||
969 | if (sdmac->per_address2 >= sdma->spba_start_addr && | |
970 | sdmac->per_address2 <= sdma->spba_end_addr) | |
971 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; | |
972 | ||
973 | if (sdmac->per_address >= sdma->spba_start_addr && | |
974 | sdmac->per_address <= sdma->spba_end_addr) | |
975 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; | |
976 | ||
977 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; | |
978 | } | |
979 | ||
7b350ab0 | 980 | static int sdma_config_channel(struct dma_chan *chan) |
1ec1e82f | 981 | { |
7b350ab0 | 982 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1ec1e82f SH |
983 | int ret; |
984 | ||
7b350ab0 | 985 | sdma_disable_channel(chan); |
1ec1e82f | 986 | |
0bbc1413 RZ |
987 | sdmac->event_mask[0] = 0; |
988 | sdmac->event_mask[1] = 0; | |
1ec1e82f SH |
989 | sdmac->shp_addr = 0; |
990 | sdmac->per_addr = 0; | |
991 | ||
992 | if (sdmac->event_id0) { | |
17bba72f | 993 | if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) |
1ec1e82f SH |
994 | return -EINVAL; |
995 | sdma_event_enable(sdmac, sdmac->event_id0); | |
996 | } | |
997 | ||
8391ecf4 SW |
998 | if (sdmac->event_id1) { |
999 | if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) | |
1000 | return -EINVAL; | |
1001 | sdma_event_enable(sdmac, sdmac->event_id1); | |
1002 | } | |
1003 | ||
1ec1e82f SH |
1004 | switch (sdmac->peripheral_type) { |
1005 | case IMX_DMATYPE_DSP: | |
1006 | sdma_config_ownership(sdmac, false, true, true); | |
1007 | break; | |
1008 | case IMX_DMATYPE_MEMORY: | |
1009 | sdma_config_ownership(sdmac, false, true, false); | |
1010 | break; | |
1011 | default: | |
1012 | sdma_config_ownership(sdmac, true, true, false); | |
1013 | break; | |
1014 | } | |
1015 | ||
1016 | sdma_get_pc(sdmac, sdmac->peripheral_type); | |
1017 | ||
1018 | if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && | |
1019 | (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { | |
1020 | /* Handle multiple event channels differently */ | |
1021 | if (sdmac->event_id1) { | |
8391ecf4 SW |
1022 | if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || |
1023 | sdmac->peripheral_type == IMX_DMATYPE_ASRC) | |
1024 | sdma_set_watermarklevel_for_p2p(sdmac); | |
1025 | } else | |
0bbc1413 | 1026 | __set_bit(sdmac->event_id0, sdmac->event_mask); |
8391ecf4 | 1027 | |
1ec1e82f SH |
1028 | /* Address */ |
1029 | sdmac->shp_addr = sdmac->per_address; | |
8391ecf4 | 1030 | sdmac->per_addr = sdmac->per_address2; |
1ec1e82f SH |
1031 | } else { |
1032 | sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ | |
1033 | } | |
1034 | ||
1035 | ret = sdma_load_context(sdmac); | |
1036 | ||
1037 | return ret; | |
1038 | } | |
1039 | ||
1040 | static int sdma_set_channel_priority(struct sdma_channel *sdmac, | |
1041 | unsigned int priority) | |
1042 | { | |
1043 | struct sdma_engine *sdma = sdmac->sdma; | |
1044 | int channel = sdmac->channel; | |
1045 | ||
1046 | if (priority < MXC_SDMA_MIN_PRIORITY | |
1047 | || priority > MXC_SDMA_MAX_PRIORITY) { | |
1048 | return -EINVAL; | |
1049 | } | |
1050 | ||
c4b56857 | 1051 | writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); |
1ec1e82f SH |
1052 | |
1053 | return 0; | |
1054 | } | |
1055 | ||
1056 | static int sdma_request_channel(struct sdma_channel *sdmac) | |
1057 | { | |
1058 | struct sdma_engine *sdma = sdmac->sdma; | |
1059 | int channel = sdmac->channel; | |
1060 | int ret = -EBUSY; | |
1061 | ||
9f92d223 JP |
1062 | sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, |
1063 | GFP_KERNEL); | |
1ec1e82f SH |
1064 | if (!sdmac->bd) { |
1065 | ret = -ENOMEM; | |
1066 | goto out; | |
1067 | } | |
1068 | ||
1ec1e82f SH |
1069 | sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; |
1070 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1071 | ||
1ec1e82f | 1072 | sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); |
1ec1e82f SH |
1073 | return 0; |
1074 | out: | |
1075 | ||
1076 | return ret; | |
1077 | } | |
1078 | ||
1ec1e82f SH |
1079 | static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) |
1080 | { | |
f69f2e26 | 1081 | unsigned long flags; |
1ec1e82f | 1082 | struct sdma_channel *sdmac = to_sdma_chan(tx->chan); |
1ec1e82f SH |
1083 | dma_cookie_t cookie; |
1084 | ||
f69f2e26 | 1085 | spin_lock_irqsave(&sdmac->lock, flags); |
1ec1e82f | 1086 | |
884485e1 | 1087 | cookie = dma_cookie_assign(tx); |
1ec1e82f | 1088 | |
f69f2e26 | 1089 | spin_unlock_irqrestore(&sdmac->lock, flags); |
1ec1e82f SH |
1090 | |
1091 | return cookie; | |
1092 | } | |
1093 | ||
1094 | static int sdma_alloc_chan_resources(struct dma_chan *chan) | |
1095 | { | |
1096 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1097 | struct imx_dma_data *data = chan->private; | |
1098 | int prio, ret; | |
1099 | ||
1ec1e82f SH |
1100 | if (!data) |
1101 | return -EINVAL; | |
1102 | ||
1103 | switch (data->priority) { | |
1104 | case DMA_PRIO_HIGH: | |
1105 | prio = 3; | |
1106 | break; | |
1107 | case DMA_PRIO_MEDIUM: | |
1108 | prio = 2; | |
1109 | break; | |
1110 | case DMA_PRIO_LOW: | |
1111 | default: | |
1112 | prio = 1; | |
1113 | break; | |
1114 | } | |
1115 | ||
1116 | sdmac->peripheral_type = data->peripheral_type; | |
1117 | sdmac->event_id0 = data->dma_request; | |
8391ecf4 | 1118 | sdmac->event_id1 = data->dma_request2; |
c2c744d3 | 1119 | |
b93edcdd FE |
1120 | ret = clk_enable(sdmac->sdma->clk_ipg); |
1121 | if (ret) | |
1122 | return ret; | |
1123 | ret = clk_enable(sdmac->sdma->clk_ahb); | |
1124 | if (ret) | |
1125 | goto disable_clk_ipg; | |
c2c744d3 | 1126 | |
3bb5e7ca | 1127 | ret = sdma_request_channel(sdmac); |
1ec1e82f | 1128 | if (ret) |
b93edcdd | 1129 | goto disable_clk_ahb; |
1ec1e82f | 1130 | |
3bb5e7ca | 1131 | ret = sdma_set_channel_priority(sdmac, prio); |
1ec1e82f | 1132 | if (ret) |
b93edcdd | 1133 | goto disable_clk_ahb; |
1ec1e82f SH |
1134 | |
1135 | dma_async_tx_descriptor_init(&sdmac->desc, chan); | |
1136 | sdmac->desc.tx_submit = sdma_tx_submit; | |
1137 | /* txd.flags will be overwritten in prep funcs */ | |
1138 | sdmac->desc.flags = DMA_CTRL_ACK; | |
1139 | ||
1140 | return 0; | |
b93edcdd FE |
1141 | |
1142 | disable_clk_ahb: | |
1143 | clk_disable(sdmac->sdma->clk_ahb); | |
1144 | disable_clk_ipg: | |
1145 | clk_disable(sdmac->sdma->clk_ipg); | |
1146 | return ret; | |
1ec1e82f SH |
1147 | } |
1148 | ||
1149 | static void sdma_free_chan_resources(struct dma_chan *chan) | |
1150 | { | |
1151 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1152 | struct sdma_engine *sdma = sdmac->sdma; | |
1153 | ||
7b350ab0 | 1154 | sdma_disable_channel(chan); |
1ec1e82f SH |
1155 | |
1156 | if (sdmac->event_id0) | |
1157 | sdma_event_disable(sdmac, sdmac->event_id0); | |
1158 | if (sdmac->event_id1) | |
1159 | sdma_event_disable(sdmac, sdmac->event_id1); | |
1160 | ||
1161 | sdmac->event_id0 = 0; | |
1162 | sdmac->event_id1 = 0; | |
1163 | ||
1164 | sdma_set_channel_priority(sdmac, 0); | |
1165 | ||
1166 | dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); | |
1167 | ||
7560e3f3 SH |
1168 | clk_disable(sdma->clk_ipg); |
1169 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1170 | } |
1171 | ||
1172 | static struct dma_async_tx_descriptor *sdma_prep_slave_sg( | |
1173 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1174 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1175 | unsigned long flags, void *context) |
1ec1e82f SH |
1176 | { |
1177 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1178 | struct sdma_engine *sdma = sdmac->sdma; | |
1179 | int ret, i, count; | |
23889c63 | 1180 | int channel = sdmac->channel; |
1ec1e82f SH |
1181 | struct scatterlist *sg; |
1182 | ||
1183 | if (sdmac->status == DMA_IN_PROGRESS) | |
1184 | return NULL; | |
1185 | sdmac->status = DMA_IN_PROGRESS; | |
1186 | ||
1187 | sdmac->flags = 0; | |
1188 | ||
8e2e27c7 | 1189 | sdmac->buf_tail = 0; |
85f57752 NH |
1190 | sdmac->buf_ptail = 0; |
1191 | sdmac->chn_real_count = 0; | |
8e2e27c7 | 1192 | |
1ec1e82f SH |
1193 | dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", |
1194 | sg_len, channel); | |
1195 | ||
1196 | sdmac->direction = direction; | |
1197 | ret = sdma_load_context(sdmac); | |
1198 | if (ret) | |
1199 | goto err_out; | |
1200 | ||
1201 | if (sg_len > NUM_BD) { | |
1202 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1203 | channel, sg_len, NUM_BD); | |
1204 | ret = -EINVAL; | |
1205 | goto err_out; | |
1206 | } | |
1207 | ||
ab59a510 | 1208 | sdmac->chn_count = 0; |
1ec1e82f SH |
1209 | for_each_sg(sgl, sg, sg_len, i) { |
1210 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1211 | int param; | |
1212 | ||
d2f5c276 | 1213 | bd->buffer_addr = sg->dma_address; |
1ec1e82f | 1214 | |
fdaf9c4b | 1215 | count = sg_dma_len(sg); |
1ec1e82f SH |
1216 | |
1217 | if (count > 0xffff) { | |
1218 | dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", | |
1219 | channel, count, 0xffff); | |
1220 | ret = -EINVAL; | |
1221 | goto err_out; | |
1222 | } | |
1223 | ||
1224 | bd->mode.count = count; | |
ab59a510 | 1225 | sdmac->chn_count += count; |
1ec1e82f SH |
1226 | |
1227 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { | |
1228 | ret = -EINVAL; | |
1229 | goto err_out; | |
1230 | } | |
1fa81c27 SH |
1231 | |
1232 | switch (sdmac->word_size) { | |
1233 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1ec1e82f | 1234 | bd->mode.command = 0; |
1fa81c27 SH |
1235 | if (count & 3 || sg->dma_address & 3) |
1236 | return NULL; | |
1237 | break; | |
1238 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1239 | bd->mode.command = 2; | |
1240 | if (count & 1 || sg->dma_address & 1) | |
1241 | return NULL; | |
1242 | break; | |
1243 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1244 | bd->mode.command = 1; | |
1245 | break; | |
1246 | default: | |
1247 | return NULL; | |
1248 | } | |
1ec1e82f SH |
1249 | |
1250 | param = BD_DONE | BD_EXTD | BD_CONT; | |
1251 | ||
341b9419 | 1252 | if (i + 1 == sg_len) { |
1ec1e82f | 1253 | param |= BD_INTR; |
341b9419 SG |
1254 | param |= BD_LAST; |
1255 | param &= ~BD_CONT; | |
1ec1e82f SH |
1256 | } |
1257 | ||
c3cc74b2 OJ |
1258 | dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", |
1259 | i, count, (u64)sg->dma_address, | |
1ec1e82f SH |
1260 | param & BD_WRAP ? "wrap" : "", |
1261 | param & BD_INTR ? " intr" : ""); | |
1262 | ||
1263 | bd->mode.status = param; | |
1264 | } | |
1265 | ||
1266 | sdmac->num_bd = sg_len; | |
1267 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1268 | ||
1269 | return &sdmac->desc; | |
1270 | err_out: | |
4b2ce9dd | 1271 | sdmac->status = DMA_ERROR; |
1ec1e82f SH |
1272 | return NULL; |
1273 | } | |
1274 | ||
1275 | static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( | |
1276 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 1277 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1278 | unsigned long flags) |
1ec1e82f SH |
1279 | { |
1280 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1281 | struct sdma_engine *sdma = sdmac->sdma; | |
1282 | int num_periods = buf_len / period_len; | |
23889c63 | 1283 | int channel = sdmac->channel; |
1ec1e82f SH |
1284 | int ret, i = 0, buf = 0; |
1285 | ||
1286 | dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); | |
1287 | ||
1288 | if (sdmac->status == DMA_IN_PROGRESS) | |
1289 | return NULL; | |
1290 | ||
1291 | sdmac->status = DMA_IN_PROGRESS; | |
1292 | ||
8e2e27c7 | 1293 | sdmac->buf_tail = 0; |
85f57752 NH |
1294 | sdmac->buf_ptail = 0; |
1295 | sdmac->chn_real_count = 0; | |
d1a792f3 | 1296 | sdmac->period_len = period_len; |
8e2e27c7 | 1297 | |
1ec1e82f SH |
1298 | sdmac->flags |= IMX_DMA_SG_LOOP; |
1299 | sdmac->direction = direction; | |
1300 | ret = sdma_load_context(sdmac); | |
1301 | if (ret) | |
1302 | goto err_out; | |
1303 | ||
1304 | if (num_periods > NUM_BD) { | |
1305 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1306 | channel, num_periods, NUM_BD); | |
1307 | goto err_out; | |
1308 | } | |
1309 | ||
1310 | if (period_len > 0xffff) { | |
1311 | dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", | |
1312 | channel, period_len, 0xffff); | |
1313 | goto err_out; | |
1314 | } | |
1315 | ||
1316 | while (buf < buf_len) { | |
1317 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1318 | int param; | |
1319 | ||
1320 | bd->buffer_addr = dma_addr; | |
1321 | ||
1322 | bd->mode.count = period_len; | |
1323 | ||
1324 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1325 | goto err_out; | |
1326 | if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1327 | bd->mode.command = 0; | |
1328 | else | |
1329 | bd->mode.command = sdmac->word_size; | |
1330 | ||
1331 | param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; | |
1332 | if (i + 1 == num_periods) | |
1333 | param |= BD_WRAP; | |
1334 | ||
c3cc74b2 OJ |
1335 | dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", |
1336 | i, period_len, (u64)dma_addr, | |
1ec1e82f SH |
1337 | param & BD_WRAP ? "wrap" : "", |
1338 | param & BD_INTR ? " intr" : ""); | |
1339 | ||
1340 | bd->mode.status = param; | |
1341 | ||
1342 | dma_addr += period_len; | |
1343 | buf += period_len; | |
1344 | ||
1345 | i++; | |
1346 | } | |
1347 | ||
1348 | sdmac->num_bd = num_periods; | |
1349 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1350 | ||
1351 | return &sdmac->desc; | |
1352 | err_out: | |
1353 | sdmac->status = DMA_ERROR; | |
1354 | return NULL; | |
1355 | } | |
1356 | ||
7b350ab0 MR |
1357 | static int sdma_config(struct dma_chan *chan, |
1358 | struct dma_slave_config *dmaengine_cfg) | |
1ec1e82f SH |
1359 | { |
1360 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1ec1e82f | 1361 | |
7b350ab0 MR |
1362 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1363 | sdmac->per_address = dmaengine_cfg->src_addr; | |
1364 | sdmac->watermark_level = dmaengine_cfg->src_maxburst * | |
1365 | dmaengine_cfg->src_addr_width; | |
1366 | sdmac->word_size = dmaengine_cfg->src_addr_width; | |
8391ecf4 SW |
1367 | } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) { |
1368 | sdmac->per_address2 = dmaengine_cfg->src_addr; | |
1369 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1370 | sdmac->watermark_level = dmaengine_cfg->src_maxburst & | |
1371 | SDMA_WATERMARK_LEVEL_LWML; | |
1372 | sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & | |
1373 | SDMA_WATERMARK_LEVEL_HWML; | |
1374 | sdmac->word_size = dmaengine_cfg->dst_addr_width; | |
7b350ab0 MR |
1375 | } else { |
1376 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1377 | sdmac->watermark_level = dmaengine_cfg->dst_maxburst * | |
1378 | dmaengine_cfg->dst_addr_width; | |
1379 | sdmac->word_size = dmaengine_cfg->dst_addr_width; | |
1380 | } | |
1381 | sdmac->direction = dmaengine_cfg->direction; | |
1382 | return sdma_config_channel(chan); | |
1ec1e82f SH |
1383 | } |
1384 | ||
1385 | static enum dma_status sdma_tx_status(struct dma_chan *chan, | |
e8e3a790 AS |
1386 | dma_cookie_t cookie, |
1387 | struct dma_tx_state *txstate) | |
1ec1e82f SH |
1388 | { |
1389 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
d1a792f3 RKAL |
1390 | u32 residue; |
1391 | ||
1392 | if (sdmac->flags & IMX_DMA_SG_LOOP) | |
85f57752 | 1393 | residue = (sdmac->num_bd - sdmac->buf_ptail) * |
5881826d | 1394 | sdmac->period_len - sdmac->chn_real_count; |
d1a792f3 RKAL |
1395 | else |
1396 | residue = sdmac->chn_count - sdmac->chn_real_count; | |
1ec1e82f | 1397 | |
e8e3a790 | 1398 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, |
d1a792f3 | 1399 | residue); |
1ec1e82f | 1400 | |
8a965911 | 1401 | return sdmac->status; |
1ec1e82f SH |
1402 | } |
1403 | ||
1404 | static void sdma_issue_pending(struct dma_chan *chan) | |
1405 | { | |
2b4f130e SH |
1406 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1407 | struct sdma_engine *sdma = sdmac->sdma; | |
1408 | ||
1409 | if (sdmac->status == DMA_IN_PROGRESS) | |
1410 | sdma_enable_channel(sdma, sdmac->channel); | |
1ec1e82f SH |
1411 | } |
1412 | ||
5b28aa31 | 1413 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 |
cd72b846 | 1414 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 |
a572460b | 1415 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 |
b7d2648a | 1416 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 |
5b28aa31 SH |
1417 | |
1418 | static void sdma_add_scripts(struct sdma_engine *sdma, | |
1419 | const struct sdma_script_start_addrs *addr) | |
1420 | { | |
1421 | s32 *addr_arr = (u32 *)addr; | |
1422 | s32 *saddr_arr = (u32 *)sdma->script_addrs; | |
1423 | int i; | |
1424 | ||
70dabaed NC |
1425 | /* use the default firmware in ROM if missing external firmware */ |
1426 | if (!sdma->script_number) | |
1427 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1428 | ||
cd72b846 | 1429 | for (i = 0; i < sdma->script_number; i++) |
5b28aa31 SH |
1430 | if (addr_arr[i] > 0) |
1431 | saddr_arr[i] = addr_arr[i]; | |
1432 | } | |
1433 | ||
7b4b88e0 | 1434 | static void sdma_load_firmware(const struct firmware *fw, void *context) |
5b28aa31 | 1435 | { |
7b4b88e0 | 1436 | struct sdma_engine *sdma = context; |
5b28aa31 | 1437 | const struct sdma_firmware_header *header; |
5b28aa31 SH |
1438 | const struct sdma_script_start_addrs *addr; |
1439 | unsigned short *ram_code; | |
1440 | ||
7b4b88e0 | 1441 | if (!fw) { |
0f927a11 SH |
1442 | dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); |
1443 | /* In this case we just use the ROM firmware. */ | |
7b4b88e0 SH |
1444 | return; |
1445 | } | |
5b28aa31 SH |
1446 | |
1447 | if (fw->size < sizeof(*header)) | |
1448 | goto err_firmware; | |
1449 | ||
1450 | header = (struct sdma_firmware_header *)fw->data; | |
1451 | ||
1452 | if (header->magic != SDMA_FIRMWARE_MAGIC) | |
1453 | goto err_firmware; | |
1454 | if (header->ram_code_start + header->ram_code_size > fw->size) | |
1455 | goto err_firmware; | |
cd72b846 | 1456 | switch (header->version_major) { |
681d15ec AV |
1457 | case 1: |
1458 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1459 | break; | |
1460 | case 2: | |
1461 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; | |
1462 | break; | |
a572460b FE |
1463 | case 3: |
1464 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; | |
1465 | break; | |
b7d2648a FE |
1466 | case 4: |
1467 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; | |
1468 | break; | |
681d15ec AV |
1469 | default: |
1470 | dev_err(sdma->dev, "unknown firmware version\n"); | |
1471 | goto err_firmware; | |
cd72b846 | 1472 | } |
5b28aa31 SH |
1473 | |
1474 | addr = (void *)header + header->script_addrs_start; | |
1475 | ram_code = (void *)header + header->ram_code_start; | |
1476 | ||
7560e3f3 SH |
1477 | clk_enable(sdma->clk_ipg); |
1478 | clk_enable(sdma->clk_ahb); | |
5b28aa31 SH |
1479 | /* download the RAM image for SDMA */ |
1480 | sdma_load_script(sdma, ram_code, | |
1481 | header->ram_code_size, | |
6866fd3b | 1482 | addr->ram_code_start_addr); |
7560e3f3 SH |
1483 | clk_disable(sdma->clk_ipg); |
1484 | clk_disable(sdma->clk_ahb); | |
5b28aa31 SH |
1485 | |
1486 | sdma_add_scripts(sdma, addr); | |
1487 | ||
1488 | dev_info(sdma->dev, "loaded firmware %d.%d\n", | |
1489 | header->version_major, | |
1490 | header->version_minor); | |
1491 | ||
1492 | err_firmware: | |
1493 | release_firmware(fw); | |
7b4b88e0 SH |
1494 | } |
1495 | ||
d078cd1b ZW |
1496 | #define EVENT_REMAP_CELLS 3 |
1497 | ||
29f493da | 1498 | static int sdma_event_remap(struct sdma_engine *sdma) |
d078cd1b ZW |
1499 | { |
1500 | struct device_node *np = sdma->dev->of_node; | |
1501 | struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); | |
1502 | struct property *event_remap; | |
1503 | struct regmap *gpr; | |
1504 | char propname[] = "fsl,sdma-event-remap"; | |
1505 | u32 reg, val, shift, num_map, i; | |
1506 | int ret = 0; | |
1507 | ||
1508 | if (IS_ERR(np) || IS_ERR(gpr_np)) | |
1509 | goto out; | |
1510 | ||
1511 | event_remap = of_find_property(np, propname, NULL); | |
1512 | num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; | |
1513 | if (!num_map) { | |
ce078af7 | 1514 | dev_dbg(sdma->dev, "no event needs to be remapped\n"); |
d078cd1b ZW |
1515 | goto out; |
1516 | } else if (num_map % EVENT_REMAP_CELLS) { | |
1517 | dev_err(sdma->dev, "the property %s must modulo %d\n", | |
1518 | propname, EVENT_REMAP_CELLS); | |
1519 | ret = -EINVAL; | |
1520 | goto out; | |
1521 | } | |
1522 | ||
1523 | gpr = syscon_node_to_regmap(gpr_np); | |
1524 | if (IS_ERR(gpr)) { | |
1525 | dev_err(sdma->dev, "failed to get gpr regmap\n"); | |
1526 | ret = PTR_ERR(gpr); | |
1527 | goto out; | |
1528 | } | |
1529 | ||
1530 | for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { | |
1531 | ret = of_property_read_u32_index(np, propname, i, ®); | |
1532 | if (ret) { | |
1533 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
1534 | propname, i); | |
1535 | goto out; | |
1536 | } | |
1537 | ||
1538 | ret = of_property_read_u32_index(np, propname, i + 1, &shift); | |
1539 | if (ret) { | |
1540 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
1541 | propname, i + 1); | |
1542 | goto out; | |
1543 | } | |
1544 | ||
1545 | ret = of_property_read_u32_index(np, propname, i + 2, &val); | |
1546 | if (ret) { | |
1547 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
1548 | propname, i + 2); | |
1549 | goto out; | |
1550 | } | |
1551 | ||
1552 | regmap_update_bits(gpr, reg, BIT(shift), val << shift); | |
1553 | } | |
1554 | ||
1555 | out: | |
1556 | if (!IS_ERR(gpr_np)) | |
1557 | of_node_put(gpr_np); | |
1558 | ||
1559 | return ret; | |
1560 | } | |
1561 | ||
fe6cf289 | 1562 | static int sdma_get_firmware(struct sdma_engine *sdma, |
7b4b88e0 SH |
1563 | const char *fw_name) |
1564 | { | |
1565 | int ret; | |
1566 | ||
1567 | ret = request_firmware_nowait(THIS_MODULE, | |
1568 | FW_ACTION_HOTPLUG, fw_name, sdma->dev, | |
1569 | GFP_KERNEL, sdma, sdma_load_firmware); | |
5b28aa31 SH |
1570 | |
1571 | return ret; | |
1572 | } | |
1573 | ||
19bfc772 | 1574 | static int sdma_init(struct sdma_engine *sdma) |
1ec1e82f SH |
1575 | { |
1576 | int i, ret; | |
1577 | dma_addr_t ccb_phys; | |
1578 | ||
b93edcdd FE |
1579 | ret = clk_enable(sdma->clk_ipg); |
1580 | if (ret) | |
1581 | return ret; | |
1582 | ret = clk_enable(sdma->clk_ahb); | |
1583 | if (ret) | |
1584 | goto disable_clk_ipg; | |
1ec1e82f SH |
1585 | |
1586 | /* Be sure SDMA has not started yet */ | |
c4b56857 | 1587 | writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f SH |
1588 | |
1589 | sdma->channel_control = dma_alloc_coherent(NULL, | |
1590 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + | |
1591 | sizeof(struct sdma_context_data), | |
1592 | &ccb_phys, GFP_KERNEL); | |
1593 | ||
1594 | if (!sdma->channel_control) { | |
1595 | ret = -ENOMEM; | |
1596 | goto err_dma_alloc; | |
1597 | } | |
1598 | ||
1599 | sdma->context = (void *)sdma->channel_control + | |
1600 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1601 | sdma->context_phys = ccb_phys + | |
1602 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1603 | ||
1604 | /* Zero-out the CCB structures array just allocated */ | |
1605 | memset(sdma->channel_control, 0, | |
1606 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); | |
1607 | ||
1608 | /* disable all channels */ | |
17bba72f | 1609 | for (i = 0; i < sdma->drvdata->num_events; i++) |
c4b56857 | 1610 | writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); |
1ec1e82f SH |
1611 | |
1612 | /* All channels have priority 0 */ | |
1613 | for (i = 0; i < MAX_DMA_CHANNELS; i++) | |
c4b56857 | 1614 | writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); |
1ec1e82f SH |
1615 | |
1616 | ret = sdma_request_channel(&sdma->channel[0]); | |
1617 | if (ret) | |
1618 | goto err_dma_alloc; | |
1619 | ||
1620 | sdma_config_ownership(&sdma->channel[0], false, true, false); | |
1621 | ||
1622 | /* Set Command Channel (Channel Zero) */ | |
c4b56857 | 1623 | writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); |
1ec1e82f SH |
1624 | |
1625 | /* Set bits of CONFIG register but with static context switching */ | |
1626 | /* FIXME: Check whether to set ACR bit depending on clock ratios */ | |
c4b56857 | 1627 | writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); |
1ec1e82f | 1628 | |
c4b56857 | 1629 | writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f | 1630 | |
1ec1e82f SH |
1631 | /* Initializes channel's priorities */ |
1632 | sdma_set_channel_priority(&sdma->channel[0], 7); | |
1633 | ||
7560e3f3 SH |
1634 | clk_disable(sdma->clk_ipg); |
1635 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1636 | |
1637 | return 0; | |
1638 | ||
1639 | err_dma_alloc: | |
7560e3f3 | 1640 | clk_disable(sdma->clk_ahb); |
b93edcdd FE |
1641 | disable_clk_ipg: |
1642 | clk_disable(sdma->clk_ipg); | |
1ec1e82f SH |
1643 | dev_err(sdma->dev, "initialisation failed with %d\n", ret); |
1644 | return ret; | |
1645 | } | |
1646 | ||
9479e17c SG |
1647 | static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) |
1648 | { | |
0b351865 | 1649 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
9479e17c SG |
1650 | struct imx_dma_data *data = fn_param; |
1651 | ||
1652 | if (!imx_dma_is_general_purpose(chan)) | |
1653 | return false; | |
1654 | ||
0b351865 NC |
1655 | sdmac->data = *data; |
1656 | chan->private = &sdmac->data; | |
9479e17c SG |
1657 | |
1658 | return true; | |
1659 | } | |
1660 | ||
1661 | static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, | |
1662 | struct of_dma *ofdma) | |
1663 | { | |
1664 | struct sdma_engine *sdma = ofdma->of_dma_data; | |
1665 | dma_cap_mask_t mask = sdma->dma_device.cap_mask; | |
1666 | struct imx_dma_data data; | |
1667 | ||
1668 | if (dma_spec->args_count != 3) | |
1669 | return NULL; | |
1670 | ||
1671 | data.dma_request = dma_spec->args[0]; | |
1672 | data.peripheral_type = dma_spec->args[1]; | |
1673 | data.priority = dma_spec->args[2]; | |
8391ecf4 SW |
1674 | /* |
1675 | * init dma_request2 to zero, which is not used by the dts. | |
1676 | * For P2P, dma_request2 is init from dma_request_channel(), | |
1677 | * chan->private will point to the imx_dma_data, and in | |
1678 | * device_alloc_chan_resources(), imx_dma_data.dma_request2 will | |
1679 | * be set to sdmac->event_id1. | |
1680 | */ | |
1681 | data.dma_request2 = 0; | |
9479e17c SG |
1682 | |
1683 | return dma_request_channel(mask, sdma_filter_fn, &data); | |
1684 | } | |
1685 | ||
e34b731f | 1686 | static int sdma_probe(struct platform_device *pdev) |
1ec1e82f | 1687 | { |
580975d7 SG |
1688 | const struct of_device_id *of_id = |
1689 | of_match_device(sdma_dt_ids, &pdev->dev); | |
1690 | struct device_node *np = pdev->dev.of_node; | |
8391ecf4 | 1691 | struct device_node *spba_bus; |
580975d7 | 1692 | const char *fw_name; |
1ec1e82f | 1693 | int ret; |
1ec1e82f | 1694 | int irq; |
1ec1e82f | 1695 | struct resource *iores; |
8391ecf4 | 1696 | struct resource spba_res; |
d4adcc01 | 1697 | struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); |
1ec1e82f | 1698 | int i; |
1ec1e82f | 1699 | struct sdma_engine *sdma; |
36e2f21a | 1700 | s32 *saddr_arr; |
17bba72f SH |
1701 | const struct sdma_driver_data *drvdata = NULL; |
1702 | ||
1703 | if (of_id) | |
1704 | drvdata = of_id->data; | |
1705 | else if (pdev->id_entry) | |
1706 | drvdata = (void *)pdev->id_entry->driver_data; | |
1707 | ||
1708 | if (!drvdata) { | |
1709 | dev_err(&pdev->dev, "unable to find driver data\n"); | |
1710 | return -EINVAL; | |
1711 | } | |
1ec1e82f | 1712 | |
42536b9f PR |
1713 | ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
1714 | if (ret) | |
1715 | return ret; | |
1716 | ||
7f24e0ee | 1717 | sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); |
1ec1e82f SH |
1718 | if (!sdma) |
1719 | return -ENOMEM; | |
1720 | ||
2ccaef05 | 1721 | spin_lock_init(&sdma->channel_0_lock); |
73eab978 | 1722 | |
1ec1e82f | 1723 | sdma->dev = &pdev->dev; |
17bba72f | 1724 | sdma->drvdata = drvdata; |
1ec1e82f | 1725 | |
1ec1e82f | 1726 | irq = platform_get_irq(pdev, 0); |
7f24e0ee | 1727 | if (irq < 0) |
63c72e02 | 1728 | return irq; |
1ec1e82f | 1729 | |
7f24e0ee FE |
1730 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1731 | sdma->regs = devm_ioremap_resource(&pdev->dev, iores); | |
1732 | if (IS_ERR(sdma->regs)) | |
1733 | return PTR_ERR(sdma->regs); | |
1ec1e82f | 1734 | |
7560e3f3 | 1735 | sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
7f24e0ee FE |
1736 | if (IS_ERR(sdma->clk_ipg)) |
1737 | return PTR_ERR(sdma->clk_ipg); | |
1ec1e82f | 1738 | |
7560e3f3 | 1739 | sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
7f24e0ee FE |
1740 | if (IS_ERR(sdma->clk_ahb)) |
1741 | return PTR_ERR(sdma->clk_ahb); | |
7560e3f3 SH |
1742 | |
1743 | clk_prepare(sdma->clk_ipg); | |
1744 | clk_prepare(sdma->clk_ahb); | |
1745 | ||
7f24e0ee FE |
1746 | ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", |
1747 | sdma); | |
1ec1e82f | 1748 | if (ret) |
7f24e0ee | 1749 | return ret; |
1ec1e82f | 1750 | |
5bb9dbb5 VK |
1751 | sdma->irq = irq; |
1752 | ||
5b28aa31 | 1753 | sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); |
7f24e0ee FE |
1754 | if (!sdma->script_addrs) |
1755 | return -ENOMEM; | |
1ec1e82f | 1756 | |
36e2f21a SH |
1757 | /* initially no scripts available */ |
1758 | saddr_arr = (s32 *)sdma->script_addrs; | |
1759 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) | |
1760 | saddr_arr[i] = -EINVAL; | |
1761 | ||
7214a8b1 SH |
1762 | dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); |
1763 | dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); | |
1764 | ||
1ec1e82f SH |
1765 | INIT_LIST_HEAD(&sdma->dma_device.channels); |
1766 | /* Initialize channel parameters */ | |
1767 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
1768 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
1769 | ||
1770 | sdmac->sdma = sdma; | |
1771 | spin_lock_init(&sdmac->lock); | |
1772 | ||
1ec1e82f | 1773 | sdmac->chan.device = &sdma->dma_device; |
8ac69546 | 1774 | dma_cookie_init(&sdmac->chan); |
1ec1e82f SH |
1775 | sdmac->channel = i; |
1776 | ||
15f30f51 | 1777 | tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal, |
abd9ccc8 | 1778 | (unsigned long) sdmac); |
23889c63 SH |
1779 | /* |
1780 | * Add the channel to the DMAC list. Do not add channel 0 though | |
1781 | * because we need it internally in the SDMA driver. This also means | |
1782 | * that channel 0 in dmaengine counting matches sdma channel 1. | |
1783 | */ | |
1784 | if (i) | |
1785 | list_add_tail(&sdmac->chan.device_node, | |
1786 | &sdma->dma_device.channels); | |
1ec1e82f SH |
1787 | } |
1788 | ||
5b28aa31 | 1789 | ret = sdma_init(sdma); |
1ec1e82f SH |
1790 | if (ret) |
1791 | goto err_init; | |
1792 | ||
d078cd1b ZW |
1793 | ret = sdma_event_remap(sdma); |
1794 | if (ret) | |
1795 | goto err_init; | |
1796 | ||
dcfec3c0 SH |
1797 | if (sdma->drvdata->script_addrs) |
1798 | sdma_add_scripts(sdma, sdma->drvdata->script_addrs); | |
580975d7 | 1799 | if (pdata && pdata->script_addrs) |
5b28aa31 SH |
1800 | sdma_add_scripts(sdma, pdata->script_addrs); |
1801 | ||
580975d7 | 1802 | if (pdata) { |
6d0d7e2d FE |
1803 | ret = sdma_get_firmware(sdma, pdata->fw_name); |
1804 | if (ret) | |
ad1122e5 | 1805 | dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); |
580975d7 SG |
1806 | } else { |
1807 | /* | |
1808 | * Because that device tree does not encode ROM script address, | |
1809 | * the RAM script in firmware is mandatory for device tree | |
1810 | * probe, otherwise it fails. | |
1811 | */ | |
1812 | ret = of_property_read_string(np, "fsl,sdma-ram-script-name", | |
1813 | &fw_name); | |
6602b0dd | 1814 | if (ret) |
ad1122e5 | 1815 | dev_warn(&pdev->dev, "failed to get firmware name\n"); |
6602b0dd FE |
1816 | else { |
1817 | ret = sdma_get_firmware(sdma, fw_name); | |
1818 | if (ret) | |
ad1122e5 | 1819 | dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); |
580975d7 SG |
1820 | } |
1821 | } | |
5b28aa31 | 1822 | |
1ec1e82f SH |
1823 | sdma->dma_device.dev = &pdev->dev; |
1824 | ||
1825 | sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; | |
1826 | sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; | |
1827 | sdma->dma_device.device_tx_status = sdma_tx_status; | |
1828 | sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; | |
1829 | sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; | |
7b350ab0 MR |
1830 | sdma->dma_device.device_config = sdma_config; |
1831 | sdma->dma_device.device_terminate_all = sdma_disable_channel; | |
1e4a4f50 FE |
1832 | sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
1833 | sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
1834 | sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
6f3125ce | 1835 | sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; |
1ec1e82f | 1836 | sdma->dma_device.device_issue_pending = sdma_issue_pending; |
b9b3f82f SH |
1837 | sdma->dma_device.dev->dma_parms = &sdma->dma_parms; |
1838 | dma_set_max_seg_size(sdma->dma_device.dev, 65535); | |
1ec1e82f | 1839 | |
23e11811 VR |
1840 | platform_set_drvdata(pdev, sdma); |
1841 | ||
1ec1e82f SH |
1842 | ret = dma_async_device_register(&sdma->dma_device); |
1843 | if (ret) { | |
1844 | dev_err(&pdev->dev, "unable to register\n"); | |
1845 | goto err_init; | |
1846 | } | |
1847 | ||
9479e17c SG |
1848 | if (np) { |
1849 | ret = of_dma_controller_register(np, sdma_xlate, sdma); | |
1850 | if (ret) { | |
1851 | dev_err(&pdev->dev, "failed to register controller\n"); | |
1852 | goto err_register; | |
1853 | } | |
8391ecf4 SW |
1854 | |
1855 | spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); | |
1856 | ret = of_address_to_resource(spba_bus, 0, &spba_res); | |
1857 | if (!ret) { | |
1858 | sdma->spba_start_addr = spba_res.start; | |
1859 | sdma->spba_end_addr = spba_res.end; | |
1860 | } | |
1861 | of_node_put(spba_bus); | |
9479e17c SG |
1862 | } |
1863 | ||
1ec1e82f SH |
1864 | return 0; |
1865 | ||
9479e17c SG |
1866 | err_register: |
1867 | dma_async_device_unregister(&sdma->dma_device); | |
1ec1e82f SH |
1868 | err_init: |
1869 | kfree(sdma->script_addrs); | |
939fd4f0 | 1870 | return ret; |
1ec1e82f SH |
1871 | } |
1872 | ||
1d1bbd30 | 1873 | static int sdma_remove(struct platform_device *pdev) |
1ec1e82f | 1874 | { |
23e11811 | 1875 | struct sdma_engine *sdma = platform_get_drvdata(pdev); |
c12fe497 | 1876 | int i; |
23e11811 | 1877 | |
5bb9dbb5 | 1878 | devm_free_irq(&pdev->dev, sdma->irq, sdma); |
23e11811 VR |
1879 | dma_async_device_unregister(&sdma->dma_device); |
1880 | kfree(sdma->script_addrs); | |
c12fe497 VR |
1881 | /* Kill the tasklet */ |
1882 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
1883 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
1884 | ||
1885 | tasklet_kill(&sdmac->tasklet); | |
1886 | } | |
23e11811 VR |
1887 | |
1888 | platform_set_drvdata(pdev, NULL); | |
23e11811 | 1889 | return 0; |
1ec1e82f SH |
1890 | } |
1891 | ||
1892 | static struct platform_driver sdma_driver = { | |
1893 | .driver = { | |
1894 | .name = "imx-sdma", | |
580975d7 | 1895 | .of_match_table = sdma_dt_ids, |
1ec1e82f | 1896 | }, |
62550cd7 | 1897 | .id_table = sdma_devtypes, |
1d1bbd30 | 1898 | .remove = sdma_remove, |
23e11811 | 1899 | .probe = sdma_probe, |
1ec1e82f SH |
1900 | }; |
1901 | ||
23e11811 | 1902 | module_platform_driver(sdma_driver); |
1ec1e82f SH |
1903 | |
1904 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1905 | MODULE_DESCRIPTION("i.MX SDMA driver"); | |
1906 | MODULE_LICENSE("GPL"); |