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c01faaca FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // drivers/dma/imx-sdma.c | |
4 | // | |
5 | // This file contains a driver for the Freescale Smart DMA engine | |
6 | // | |
7 | // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
8 | // | |
9 | // Based on code from Freescale: | |
10 | // | |
11 | // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
1ec1e82f SH |
12 | |
13 | #include <linux/init.h> | |
1d069bfa | 14 | #include <linux/iopoll.h> |
f8de8f4c | 15 | #include <linux/module.h> |
1ec1e82f | 16 | #include <linux/types.h> |
824a0a02 | 17 | #include <linux/bitfield.h> |
0bbc1413 | 18 | #include <linux/bitops.h> |
1ec1e82f SH |
19 | #include <linux/mm.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/clk.h> | |
2ccaef05 | 22 | #include <linux/delay.h> |
1ec1e82f SH |
23 | #include <linux/sched.h> |
24 | #include <linux/semaphore.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/firmware.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/dmaengine.h> | |
580975d7 | 32 | #include <linux/of.h> |
8391ecf4 | 33 | #include <linux/of_address.h> |
580975d7 | 34 | #include <linux/of_device.h> |
9479e17c | 35 | #include <linux/of_dma.h> |
b8603d2a | 36 | #include <linux/workqueue.h> |
1ec1e82f SH |
37 | |
38 | #include <asm/irq.h> | |
c6547c2e | 39 | #include <linux/dma/imx-dma.h> |
d078cd1b ZW |
40 | #include <linux/regmap.h> |
41 | #include <linux/mfd/syscon.h> | |
42 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
1ec1e82f | 43 | |
d2ebfb33 | 44 | #include "dmaengine.h" |
57b772b8 | 45 | #include "virt-dma.h" |
d2ebfb33 | 46 | |
1ec1e82f SH |
47 | /* SDMA registers */ |
48 | #define SDMA_H_C0PTR 0x000 | |
49 | #define SDMA_H_INTR 0x004 | |
50 | #define SDMA_H_STATSTOP 0x008 | |
51 | #define SDMA_H_START 0x00c | |
52 | #define SDMA_H_EVTOVR 0x010 | |
53 | #define SDMA_H_DSPOVR 0x014 | |
54 | #define SDMA_H_HOSTOVR 0x018 | |
55 | #define SDMA_H_EVTPEND 0x01c | |
56 | #define SDMA_H_DSPENBL 0x020 | |
57 | #define SDMA_H_RESET 0x024 | |
58 | #define SDMA_H_EVTERR 0x028 | |
59 | #define SDMA_H_INTRMSK 0x02c | |
60 | #define SDMA_H_PSW 0x030 | |
61 | #define SDMA_H_EVTERRDBG 0x034 | |
62 | #define SDMA_H_CONFIG 0x038 | |
63 | #define SDMA_ONCE_ENB 0x040 | |
64 | #define SDMA_ONCE_DATA 0x044 | |
65 | #define SDMA_ONCE_INSTR 0x048 | |
66 | #define SDMA_ONCE_STAT 0x04c | |
67 | #define SDMA_ONCE_CMD 0x050 | |
68 | #define SDMA_EVT_MIRROR 0x054 | |
69 | #define SDMA_ILLINSTADDR 0x058 | |
70 | #define SDMA_CHN0ADDR 0x05c | |
71 | #define SDMA_ONCE_RTB 0x060 | |
72 | #define SDMA_XTRIG_CONF1 0x070 | |
73 | #define SDMA_XTRIG_CONF2 0x074 | |
62550cd7 SG |
74 | #define SDMA_CHNENBL0_IMX35 0x200 |
75 | #define SDMA_CHNENBL0_IMX31 0x080 | |
1ec1e82f | 76 | #define SDMA_CHNPRI_0 0x100 |
824a0a02 | 77 | #define SDMA_DONE0_CONFIG 0x1000 |
1ec1e82f SH |
78 | |
79 | /* | |
80 | * Buffer descriptor status values. | |
81 | */ | |
82 | #define BD_DONE 0x01 | |
83 | #define BD_WRAP 0x02 | |
84 | #define BD_CONT 0x04 | |
85 | #define BD_INTR 0x08 | |
86 | #define BD_RROR 0x10 | |
87 | #define BD_LAST 0x20 | |
88 | #define BD_EXTD 0x80 | |
89 | ||
90 | /* | |
91 | * Data Node descriptor status values. | |
92 | */ | |
93 | #define DND_END_OF_FRAME 0x80 | |
94 | #define DND_END_OF_XFER 0x40 | |
95 | #define DND_DONE 0x20 | |
96 | #define DND_UNUSED 0x01 | |
97 | ||
98 | /* | |
99 | * IPCV2 descriptor status values. | |
100 | */ | |
101 | #define BD_IPCV2_END_OF_FRAME 0x40 | |
102 | ||
103 | #define IPCV2_MAX_NODES 50 | |
104 | /* | |
105 | * Error bit set in the CCB status field by the SDMA, | |
106 | * in setbd routine, in case of a transfer error | |
107 | */ | |
108 | #define DATA_ERROR 0x10000000 | |
109 | ||
110 | /* | |
111 | * Buffer descriptor commands. | |
112 | */ | |
113 | #define C0_ADDR 0x01 | |
114 | #define C0_LOAD 0x02 | |
115 | #define C0_DUMP 0x03 | |
116 | #define C0_SETCTX 0x07 | |
117 | #define C0_GETCTX 0x03 | |
118 | #define C0_SETDM 0x01 | |
119 | #define C0_SETPM 0x04 | |
120 | #define C0_GETDM 0x02 | |
121 | #define C0_GETPM 0x08 | |
122 | /* | |
123 | * Change endianness indicator in the BD command field | |
124 | */ | |
125 | #define CHANGE_ENDIANNESS 0x80 | |
126 | ||
8391ecf4 SW |
127 | /* |
128 | * p_2_p watermark_level description | |
129 | * Bits Name Description | |
130 | * 0-7 Lower WML Lower watermark level | |
131 | * 8 PS 1: Pad Swallowing | |
132 | * 0: No Pad Swallowing | |
133 | * 9 PA 1: Pad Adding | |
134 | * 0: No Pad Adding | |
135 | * 10 SPDIF If this bit is set both source | |
136 | * and destination are on SPBA | |
137 | * 11 Source Bit(SP) 1: Source on SPBA | |
138 | * 0: Source on AIPS | |
139 | * 12 Destination Bit(DP) 1: Destination on SPBA | |
140 | * 0: Destination on AIPS | |
141 | * 13-15 --------- MUST BE 0 | |
142 | * 16-23 Higher WML HWML | |
143 | * 24-27 N Total number of samples after | |
144 | * which Pad adding/Swallowing | |
145 | * must be done. It must be odd. | |
146 | * 28 Lower WML Event(LWE) SDMA events reg to check for | |
147 | * LWML event mask | |
148 | * 0: LWE in EVENTS register | |
149 | * 1: LWE in EVENTS2 register | |
150 | * 29 Higher WML Event(HWE) SDMA events reg to check for | |
151 | * HWML event mask | |
152 | * 0: HWE in EVENTS register | |
153 | * 1: HWE in EVENTS2 register | |
154 | * 30 --------- MUST BE 0 | |
155 | * 31 CONT 1: Amount of samples to be | |
156 | * transferred is unknown and | |
157 | * script will keep on | |
158 | * transferring samples as long as | |
159 | * both events are detected and | |
160 | * script must be manually stopped | |
161 | * by the application | |
162 | * 0: The amount of samples to be | |
163 | * transferred is equal to the | |
164 | * count field of mode word | |
165 | */ | |
166 | #define SDMA_WATERMARK_LEVEL_LWML 0xFF | |
167 | #define SDMA_WATERMARK_LEVEL_PS BIT(8) | |
168 | #define SDMA_WATERMARK_LEVEL_PA BIT(9) | |
169 | #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) | |
170 | #define SDMA_WATERMARK_LEVEL_SP BIT(11) | |
171 | #define SDMA_WATERMARK_LEVEL_DP BIT(12) | |
172 | #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) | |
173 | #define SDMA_WATERMARK_LEVEL_LWE BIT(28) | |
174 | #define SDMA_WATERMARK_LEVEL_HWE BIT(29) | |
175 | #define SDMA_WATERMARK_LEVEL_CONT BIT(31) | |
176 | ||
f9d4a398 NC |
177 | #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
178 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
179 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
180 | ||
181 | #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ | |
182 | BIT(DMA_MEM_TO_DEV) | \ | |
183 | BIT(DMA_DEV_TO_DEV)) | |
184 | ||
824a0a02 | 185 | #define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12) |
e0c7ea83 SW |
186 | #define SDMA_WATERMARK_LEVEL_OFF_FIFOS GENMASK(19, 16) |
187 | #define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO GENMASK(31, 28) | |
824a0a02 SH |
188 | #define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23) |
189 | ||
190 | #define SDMA_DONE0_CONFIG_DONE_SEL BIT(7) | |
191 | #define SDMA_DONE0_CONFIG_DONE_DIS BIT(6) | |
192 | ||
01eafd4b | 193 | /* |
8d11cfb0 VZ |
194 | * struct sdma_script_start_addrs - SDMA script start pointers |
195 | * | |
196 | * start addresses of the different functions in the physical | |
197 | * address space of the SDMA engine. | |
198 | */ | |
199 | struct sdma_script_start_addrs { | |
200 | s32 ap_2_ap_addr; | |
201 | s32 ap_2_bp_addr; | |
202 | s32 ap_2_ap_fixed_addr; | |
203 | s32 bp_2_ap_addr; | |
204 | s32 loopback_on_dsp_side_addr; | |
205 | s32 mcu_interrupt_only_addr; | |
206 | s32 firi_2_per_addr; | |
207 | s32 firi_2_mcu_addr; | |
208 | s32 per_2_firi_addr; | |
209 | s32 mcu_2_firi_addr; | |
210 | s32 uart_2_per_addr; | |
a3ae97f4 | 211 | s32 uart_2_mcu_addr; |
8d11cfb0 VZ |
212 | s32 per_2_app_addr; |
213 | s32 mcu_2_app_addr; | |
214 | s32 per_2_per_addr; | |
215 | s32 uartsh_2_per_addr; | |
a3ae97f4 | 216 | s32 uartsh_2_mcu_addr; |
8d11cfb0 VZ |
217 | s32 per_2_shp_addr; |
218 | s32 mcu_2_shp_addr; | |
219 | s32 ata_2_mcu_addr; | |
220 | s32 mcu_2_ata_addr; | |
221 | s32 app_2_per_addr; | |
222 | s32 app_2_mcu_addr; | |
223 | s32 shp_2_per_addr; | |
224 | s32 shp_2_mcu_addr; | |
225 | s32 mshc_2_mcu_addr; | |
226 | s32 mcu_2_mshc_addr; | |
227 | s32 spdif_2_mcu_addr; | |
228 | s32 mcu_2_spdif_addr; | |
229 | s32 asrc_2_mcu_addr; | |
230 | s32 ext_mem_2_ipu_addr; | |
231 | s32 descrambler_addr; | |
232 | s32 dptc_dvfs_addr; | |
233 | s32 utra_addr; | |
234 | s32 ram_code_start_addr; | |
235 | /* End of v1 array */ | |
236 | s32 mcu_2_ssish_addr; | |
237 | s32 ssish_2_mcu_addr; | |
238 | s32 hdmi_dma_addr; | |
239 | /* End of v2 array */ | |
240 | s32 zcanfd_2_mcu_addr; | |
241 | s32 zqspi_2_mcu_addr; | |
242 | s32 mcu_2_ecspi_addr; | |
b98ce2f4 RG |
243 | s32 mcu_2_sai_addr; |
244 | s32 sai_2_mcu_addr; | |
a3ae97f4 KG |
245 | s32 uart_2_mcu_rom_addr; |
246 | s32 uartsh_2_mcu_rom_addr; | |
8d11cfb0 VZ |
247 | /* End of v3 array */ |
248 | s32 mcu_2_zqspi_addr; | |
249 | /* End of v4 array */ | |
250 | }; | |
251 | ||
1ec1e82f SH |
252 | /* |
253 | * Mode/Count of data node descriptors - IPCv2 | |
254 | */ | |
255 | struct sdma_mode_count { | |
4a6b2e8a | 256 | #define SDMA_BD_MAX_CNT 0xffff |
1ec1e82f SH |
257 | u32 count : 16; /* size of the buffer pointed by this BD */ |
258 | u32 status : 8; /* E,R,I,C,W,D status bits stored here */ | |
e4b75760 | 259 | u32 command : 8; /* command mostly used for channel 0 */ |
1ec1e82f SH |
260 | }; |
261 | ||
262 | /* | |
263 | * Buffer descriptor | |
264 | */ | |
265 | struct sdma_buffer_descriptor { | |
266 | struct sdma_mode_count mode; | |
267 | u32 buffer_addr; /* address of the buffer described */ | |
268 | u32 ext_buffer_addr; /* extended buffer address */ | |
269 | } __attribute__ ((packed)); | |
270 | ||
271 | /** | |
272 | * struct sdma_channel_control - Channel control Block | |
273 | * | |
24ca312d RG |
274 | * @current_bd_ptr: current buffer descriptor processed |
275 | * @base_bd_ptr: first element of buffer descriptor array | |
276 | * @unused: padding. The SDMA engine expects an array of 128 byte | |
1ec1e82f SH |
277 | * control blocks |
278 | */ | |
279 | struct sdma_channel_control { | |
280 | u32 current_bd_ptr; | |
281 | u32 base_bd_ptr; | |
282 | u32 unused[2]; | |
283 | } __attribute__ ((packed)); | |
284 | ||
285 | /** | |
286 | * struct sdma_state_registers - SDMA context for a channel | |
287 | * | |
288 | * @pc: program counter | |
24ca312d | 289 | * @unused1: unused |
1ec1e82f SH |
290 | * @t: test bit: status of arithmetic & test instruction |
291 | * @rpc: return program counter | |
24ca312d | 292 | * @unused0: unused |
1ec1e82f SH |
293 | * @sf: source fault while loading data |
294 | * @spc: loop start program counter | |
24ca312d | 295 | * @unused2: unused |
1ec1e82f SH |
296 | * @df: destination fault while storing data |
297 | * @epc: loop end program counter | |
298 | * @lm: loop mode | |
299 | */ | |
300 | struct sdma_state_registers { | |
301 | u32 pc :14; | |
302 | u32 unused1: 1; | |
303 | u32 t : 1; | |
304 | u32 rpc :14; | |
305 | u32 unused0: 1; | |
306 | u32 sf : 1; | |
307 | u32 spc :14; | |
308 | u32 unused2: 1; | |
309 | u32 df : 1; | |
310 | u32 epc :14; | |
311 | u32 lm : 2; | |
312 | } __attribute__ ((packed)); | |
313 | ||
314 | /** | |
315 | * struct sdma_context_data - sdma context specific to a channel | |
316 | * | |
317 | * @channel_state: channel state bits | |
318 | * @gReg: general registers | |
319 | * @mda: burst dma destination address register | |
320 | * @msa: burst dma source address register | |
321 | * @ms: burst dma status register | |
322 | * @md: burst dma data register | |
323 | * @pda: peripheral dma destination address register | |
324 | * @psa: peripheral dma source address register | |
325 | * @ps: peripheral dma status register | |
326 | * @pd: peripheral dma data register | |
327 | * @ca: CRC polynomial register | |
328 | * @cs: CRC accumulator register | |
329 | * @dda: dedicated core destination address register | |
330 | * @dsa: dedicated core source address register | |
331 | * @ds: dedicated core status register | |
332 | * @dd: dedicated core data register | |
24ca312d RG |
333 | * @scratch0: 1st word of dedicated ram for context switch |
334 | * @scratch1: 2nd word of dedicated ram for context switch | |
335 | * @scratch2: 3rd word of dedicated ram for context switch | |
336 | * @scratch3: 4th word of dedicated ram for context switch | |
337 | * @scratch4: 5th word of dedicated ram for context switch | |
338 | * @scratch5: 6th word of dedicated ram for context switch | |
339 | * @scratch6: 7th word of dedicated ram for context switch | |
340 | * @scratch7: 8th word of dedicated ram for context switch | |
1ec1e82f SH |
341 | */ |
342 | struct sdma_context_data { | |
343 | struct sdma_state_registers channel_state; | |
344 | u32 gReg[8]; | |
345 | u32 mda; | |
346 | u32 msa; | |
347 | u32 ms; | |
348 | u32 md; | |
349 | u32 pda; | |
350 | u32 psa; | |
351 | u32 ps; | |
352 | u32 pd; | |
353 | u32 ca; | |
354 | u32 cs; | |
355 | u32 dda; | |
356 | u32 dsa; | |
357 | u32 ds; | |
358 | u32 dd; | |
359 | u32 scratch0; | |
360 | u32 scratch1; | |
361 | u32 scratch2; | |
362 | u32 scratch3; | |
363 | u32 scratch4; | |
364 | u32 scratch5; | |
365 | u32 scratch6; | |
366 | u32 scratch7; | |
367 | } __attribute__ ((packed)); | |
368 | ||
1ec1e82f SH |
369 | |
370 | struct sdma_engine; | |
371 | ||
76c33d27 SH |
372 | /** |
373 | * struct sdma_desc - descriptor structor for one transfer | |
24ca312d RG |
374 | * @vd: descriptor for virt dma |
375 | * @num_bd: number of descriptors currently handling | |
376 | * @bd_phys: physical address of bd | |
377 | * @buf_tail: ID of the buffer that was processed | |
378 | * @buf_ptail: ID of the previous buffer that was processed | |
379 | * @period_len: period length, used in cyclic. | |
380 | * @chn_real_count: the real count updated from bd->mode.count | |
381 | * @chn_count: the transfer count set | |
382 | * @sdmac: sdma_channel pointer | |
383 | * @bd: pointer of allocate bd | |
76c33d27 SH |
384 | */ |
385 | struct sdma_desc { | |
57b772b8 | 386 | struct virt_dma_desc vd; |
76c33d27 SH |
387 | unsigned int num_bd; |
388 | dma_addr_t bd_phys; | |
389 | unsigned int buf_tail; | |
390 | unsigned int buf_ptail; | |
391 | unsigned int period_len; | |
392 | unsigned int chn_real_count; | |
393 | unsigned int chn_count; | |
394 | struct sdma_channel *sdmac; | |
395 | struct sdma_buffer_descriptor *bd; | |
396 | }; | |
397 | ||
1ec1e82f SH |
398 | /** |
399 | * struct sdma_channel - housekeeping for a SDMA channel | |
400 | * | |
24ca312d RG |
401 | * @vc: virt_dma base structure |
402 | * @desc: sdma description including vd and other special member | |
403 | * @sdma: pointer to the SDMA engine for this channel | |
404 | * @channel: the channel number, matches dmaengine chan_id + 1 | |
405 | * @direction: transfer type. Needed for setting SDMA script | |
d0c4a149 | 406 | * @slave_config: Slave configuration |
24ca312d RG |
407 | * @peripheral_type: Peripheral type. Needed for setting SDMA script |
408 | * @event_id0: aka dma request line | |
409 | * @event_id1: for channels that use 2 events | |
410 | * @word_size: peripheral access size | |
411 | * @pc_from_device: script address for those device_2_memory | |
412 | * @pc_to_device: script address for those memory_2_device | |
413 | * @device_to_device: script address for those device_2_device | |
0f06c027 | 414 | * @pc_to_pc: script address for those memory_2_memory |
24ca312d RG |
415 | * @flags: loop mode or not |
416 | * @per_address: peripheral source or destination address in common case | |
417 | * destination address in p_2_p case | |
418 | * @per_address2: peripheral source address in p_2_p case | |
419 | * @event_mask: event mask used in p_2_p script | |
420 | * @watermark_level: value for gReg[7], some script will extend it from | |
421 | * basic watermark such as p_2_p | |
422 | * @shp_addr: value for gReg[6] | |
423 | * @per_addr: value for gReg[2] | |
424 | * @status: status of dma channel | |
d0c4a149 | 425 | * @context_loaded: ensure context is only loaded once |
24ca312d RG |
426 | * @data: specific sdma interface structure |
427 | * @bd_pool: dma_pool for bd | |
d0c4a149 | 428 | * @terminate_worker: used to call back into terminate work function |
01eafd4b SW |
429 | * @terminated: terminated list |
430 | * @is_ram_script: flag for script in ram | |
431 | * @n_fifos_src: number of source device fifos | |
432 | * @n_fifos_dst: number of destination device fifos | |
433 | * @sw_done: software done flag | |
e0c7ea83 SW |
434 | * @stride_fifos_src: stride for source device FIFOs |
435 | * @stride_fifos_dst: stride for destination device FIFOs | |
436 | * @words_per_fifo: copy number of words one time for one FIFO | |
1ec1e82f SH |
437 | */ |
438 | struct sdma_channel { | |
57b772b8 | 439 | struct virt_dma_chan vc; |
76c33d27 | 440 | struct sdma_desc *desc; |
1ec1e82f SH |
441 | struct sdma_engine *sdma; |
442 | unsigned int channel; | |
db8196df | 443 | enum dma_transfer_direction direction; |
107d0644 | 444 | struct dma_slave_config slave_config; |
1ec1e82f SH |
445 | enum sdma_peripheral_type peripheral_type; |
446 | unsigned int event_id0; | |
447 | unsigned int event_id1; | |
448 | enum dma_slave_buswidth word_size; | |
1ec1e82f | 449 | unsigned int pc_from_device, pc_to_device; |
8391ecf4 | 450 | unsigned int device_to_device; |
0f06c027 | 451 | unsigned int pc_to_pc; |
1ec1e82f | 452 | unsigned long flags; |
8391ecf4 | 453 | dma_addr_t per_address, per_address2; |
0bbc1413 RZ |
454 | unsigned long event_mask[2]; |
455 | unsigned long watermark_level; | |
1ec1e82f | 456 | u32 shp_addr, per_addr; |
1ec1e82f | 457 | enum dma_status status; |
0b351865 | 458 | struct imx_dma_data data; |
b8603d2a | 459 | struct work_struct terminate_worker; |
4e2b10be | 460 | struct list_head terminated; |
e8fafa50 | 461 | bool is_ram_script; |
824a0a02 SH |
462 | unsigned int n_fifos_src; |
463 | unsigned int n_fifos_dst; | |
e0c7ea83 SW |
464 | unsigned int stride_fifos_src; |
465 | unsigned int stride_fifos_dst; | |
466 | unsigned int words_per_fifo; | |
824a0a02 | 467 | bool sw_done; |
1ec1e82f SH |
468 | }; |
469 | ||
0bbc1413 | 470 | #define IMX_DMA_SG_LOOP BIT(0) |
1ec1e82f SH |
471 | |
472 | #define MAX_DMA_CHANNELS 32 | |
473 | #define MXC_SDMA_DEFAULT_PRIORITY 1 | |
474 | #define MXC_SDMA_MIN_PRIORITY 1 | |
475 | #define MXC_SDMA_MAX_PRIORITY 7 | |
476 | ||
1ec1e82f SH |
477 | #define SDMA_FIRMWARE_MAGIC 0x414d4453 |
478 | ||
479 | /** | |
480 | * struct sdma_firmware_header - Layout of the firmware image | |
481 | * | |
24ca312d RG |
482 | * @magic: "SDMA" |
483 | * @version_major: increased whenever layout of struct | |
484 | * sdma_script_start_addrs changes. | |
485 | * @version_minor: firmware minor version (for binary compatible changes) | |
486 | * @script_addrs_start: offset of struct sdma_script_start_addrs in this image | |
487 | * @num_script_addrs: Number of script addresses in this image | |
488 | * @ram_code_start: offset of SDMA ram image in this firmware image | |
489 | * @ram_code_size: size of SDMA ram image | |
490 | * @script_addrs: Stores the start address of the SDMA scripts | |
1ec1e82f SH |
491 | * (in SDMA memory space) |
492 | */ | |
493 | struct sdma_firmware_header { | |
494 | u32 magic; | |
495 | u32 version_major; | |
496 | u32 version_minor; | |
497 | u32 script_addrs_start; | |
498 | u32 num_script_addrs; | |
499 | u32 ram_code_start; | |
500 | u32 ram_code_size; | |
501 | }; | |
502 | ||
17bba72f SH |
503 | struct sdma_driver_data { |
504 | int chnenbl0; | |
505 | int num_events; | |
dcfec3c0 | 506 | struct sdma_script_start_addrs *script_addrs; |
941acd56 | 507 | bool check_ratio; |
4852e9a2 RG |
508 | /* |
509 | * ecspi ERR009165 fixed should be done in sdma script | |
510 | * and it has been fixed in soc from i.mx6ul. | |
511 | * please get more information from the below link: | |
512 | * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf | |
513 | */ | |
514 | bool ecspi_fixed; | |
62550cd7 SG |
515 | }; |
516 | ||
1ec1e82f SH |
517 | struct sdma_engine { |
518 | struct device *dev; | |
519 | struct sdma_channel channel[MAX_DMA_CHANNELS]; | |
520 | struct sdma_channel_control *channel_control; | |
521 | void __iomem *regs; | |
1ec1e82f SH |
522 | struct sdma_context_data *context; |
523 | dma_addr_t context_phys; | |
524 | struct dma_device dma_device; | |
7560e3f3 SH |
525 | struct clk *clk_ipg; |
526 | struct clk *clk_ahb; | |
2ccaef05 | 527 | spinlock_t channel_0_lock; |
cd72b846 | 528 | u32 script_number; |
1ec1e82f | 529 | struct sdma_script_start_addrs *script_addrs; |
17bba72f | 530 | const struct sdma_driver_data *drvdata; |
8391ecf4 SW |
531 | u32 spba_start_addr; |
532 | u32 spba_end_addr; | |
5bb9dbb5 | 533 | unsigned int irq; |
76c33d27 SH |
534 | dma_addr_t bd0_phys; |
535 | struct sdma_buffer_descriptor *bd0; | |
25aaa75d AAP |
536 | /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ |
537 | bool clk_ratio; | |
e8fafa50 | 538 | bool fw_loaded; |
17bba72f SH |
539 | }; |
540 | ||
107d0644 VK |
541 | static int sdma_config_write(struct dma_chan *chan, |
542 | struct dma_slave_config *dmaengine_cfg, | |
543 | enum dma_transfer_direction direction); | |
544 | ||
e9fd58de | 545 | static struct sdma_driver_data sdma_imx31 = { |
17bba72f SH |
546 | .chnenbl0 = SDMA_CHNENBL0_IMX31, |
547 | .num_events = 32, | |
548 | }; | |
549 | ||
dcfec3c0 SH |
550 | static struct sdma_script_start_addrs sdma_script_imx25 = { |
551 | .ap_2_ap_addr = 729, | |
552 | .uart_2_mcu_addr = 904, | |
553 | .per_2_app_addr = 1255, | |
554 | .mcu_2_app_addr = 834, | |
555 | .uartsh_2_mcu_addr = 1120, | |
556 | .per_2_shp_addr = 1329, | |
557 | .mcu_2_shp_addr = 1048, | |
558 | .ata_2_mcu_addr = 1560, | |
559 | .mcu_2_ata_addr = 1479, | |
560 | .app_2_per_addr = 1189, | |
561 | .app_2_mcu_addr = 770, | |
562 | .shp_2_per_addr = 1407, | |
563 | .shp_2_mcu_addr = 979, | |
564 | }; | |
565 | ||
e9fd58de | 566 | static struct sdma_driver_data sdma_imx25 = { |
dcfec3c0 SH |
567 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
568 | .num_events = 48, | |
569 | .script_addrs = &sdma_script_imx25, | |
570 | }; | |
571 | ||
e9fd58de | 572 | static struct sdma_driver_data sdma_imx35 = { |
17bba72f SH |
573 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
574 | .num_events = 48, | |
1ec1e82f SH |
575 | }; |
576 | ||
dcfec3c0 SH |
577 | static struct sdma_script_start_addrs sdma_script_imx51 = { |
578 | .ap_2_ap_addr = 642, | |
579 | .uart_2_mcu_addr = 817, | |
580 | .mcu_2_app_addr = 747, | |
581 | .mcu_2_shp_addr = 961, | |
582 | .ata_2_mcu_addr = 1473, | |
583 | .mcu_2_ata_addr = 1392, | |
584 | .app_2_per_addr = 1033, | |
585 | .app_2_mcu_addr = 683, | |
586 | .shp_2_per_addr = 1251, | |
587 | .shp_2_mcu_addr = 892, | |
588 | }; | |
589 | ||
e9fd58de | 590 | static struct sdma_driver_data sdma_imx51 = { |
dcfec3c0 SH |
591 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
592 | .num_events = 48, | |
593 | .script_addrs = &sdma_script_imx51, | |
594 | }; | |
595 | ||
596 | static struct sdma_script_start_addrs sdma_script_imx53 = { | |
597 | .ap_2_ap_addr = 642, | |
598 | .app_2_mcu_addr = 683, | |
599 | .mcu_2_app_addr = 747, | |
600 | .uart_2_mcu_addr = 817, | |
601 | .shp_2_mcu_addr = 891, | |
602 | .mcu_2_shp_addr = 960, | |
603 | .uartsh_2_mcu_addr = 1032, | |
604 | .spdif_2_mcu_addr = 1100, | |
605 | .mcu_2_spdif_addr = 1134, | |
606 | .firi_2_mcu_addr = 1193, | |
607 | .mcu_2_firi_addr = 1290, | |
608 | }; | |
609 | ||
e9fd58de | 610 | static struct sdma_driver_data sdma_imx53 = { |
dcfec3c0 SH |
611 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
612 | .num_events = 48, | |
613 | .script_addrs = &sdma_script_imx53, | |
614 | }; | |
615 | ||
616 | static struct sdma_script_start_addrs sdma_script_imx6q = { | |
617 | .ap_2_ap_addr = 642, | |
618 | .uart_2_mcu_addr = 817, | |
619 | .mcu_2_app_addr = 747, | |
620 | .per_2_per_addr = 6331, | |
621 | .uartsh_2_mcu_addr = 1032, | |
622 | .mcu_2_shp_addr = 960, | |
623 | .app_2_mcu_addr = 683, | |
624 | .shp_2_mcu_addr = 891, | |
625 | .spdif_2_mcu_addr = 1100, | |
626 | .mcu_2_spdif_addr = 1134, | |
627 | }; | |
628 | ||
e9fd58de | 629 | static struct sdma_driver_data sdma_imx6q = { |
dcfec3c0 SH |
630 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
631 | .num_events = 48, | |
632 | .script_addrs = &sdma_script_imx6q, | |
633 | }; | |
634 | ||
4852e9a2 RG |
635 | static struct sdma_driver_data sdma_imx6ul = { |
636 | .chnenbl0 = SDMA_CHNENBL0_IMX35, | |
637 | .num_events = 48, | |
638 | .script_addrs = &sdma_script_imx6q, | |
639 | .ecspi_fixed = true, | |
640 | }; | |
641 | ||
b7d2648a FE |
642 | static struct sdma_script_start_addrs sdma_script_imx7d = { |
643 | .ap_2_ap_addr = 644, | |
644 | .uart_2_mcu_addr = 819, | |
645 | .mcu_2_app_addr = 749, | |
646 | .uartsh_2_mcu_addr = 1034, | |
647 | .mcu_2_shp_addr = 962, | |
648 | .app_2_mcu_addr = 685, | |
649 | .shp_2_mcu_addr = 893, | |
650 | .spdif_2_mcu_addr = 1102, | |
651 | .mcu_2_spdif_addr = 1136, | |
652 | }; | |
653 | ||
654 | static struct sdma_driver_data sdma_imx7d = { | |
655 | .chnenbl0 = SDMA_CHNENBL0_IMX35, | |
656 | .num_events = 48, | |
657 | .script_addrs = &sdma_script_imx7d, | |
658 | }; | |
659 | ||
941acd56 AAP |
660 | static struct sdma_driver_data sdma_imx8mq = { |
661 | .chnenbl0 = SDMA_CHNENBL0_IMX35, | |
662 | .num_events = 48, | |
663 | .script_addrs = &sdma_script_imx7d, | |
664 | .check_ratio = 1, | |
665 | }; | |
666 | ||
580975d7 | 667 | static const struct of_device_id sdma_dt_ids[] = { |
dcfec3c0 SH |
668 | { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, |
669 | { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, | |
670 | { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, | |
17bba72f | 671 | { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, |
dcfec3c0 | 672 | { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, |
63edea16 | 673 | { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, |
b7d2648a | 674 | { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, |
4852e9a2 | 675 | { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, }, |
941acd56 | 676 | { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, }, |
580975d7 SG |
677 | { /* sentinel */ } |
678 | }; | |
679 | MODULE_DEVICE_TABLE(of, sdma_dt_ids); | |
680 | ||
0bbc1413 RZ |
681 | #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ |
682 | #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ | |
683 | #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ | |
1ec1e82f SH |
684 | #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ |
685 | ||
686 | static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) | |
687 | { | |
17bba72f | 688 | u32 chnenbl0 = sdma->drvdata->chnenbl0; |
1ec1e82f SH |
689 | return chnenbl0 + event * 4; |
690 | } | |
691 | ||
692 | static int sdma_config_ownership(struct sdma_channel *sdmac, | |
693 | bool event_override, bool mcu_override, bool dsp_override) | |
694 | { | |
695 | struct sdma_engine *sdma = sdmac->sdma; | |
696 | int channel = sdmac->channel; | |
0bbc1413 | 697 | unsigned long evt, mcu, dsp; |
1ec1e82f SH |
698 | |
699 | if (event_override && mcu_override && dsp_override) | |
700 | return -EINVAL; | |
701 | ||
c4b56857 RZ |
702 | evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); |
703 | mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); | |
704 | dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
705 | |
706 | if (dsp_override) | |
0bbc1413 | 707 | __clear_bit(channel, &dsp); |
1ec1e82f | 708 | else |
0bbc1413 | 709 | __set_bit(channel, &dsp); |
1ec1e82f SH |
710 | |
711 | if (event_override) | |
0bbc1413 | 712 | __clear_bit(channel, &evt); |
1ec1e82f | 713 | else |
0bbc1413 | 714 | __set_bit(channel, &evt); |
1ec1e82f SH |
715 | |
716 | if (mcu_override) | |
0bbc1413 | 717 | __clear_bit(channel, &mcu); |
1ec1e82f | 718 | else |
0bbc1413 | 719 | __set_bit(channel, &mcu); |
1ec1e82f | 720 | |
c4b56857 RZ |
721 | writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); |
722 | writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); | |
723 | writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
724 | |
725 | return 0; | |
726 | } | |
727 | ||
5b215c28 TM |
728 | static int is_sdma_channel_enabled(struct sdma_engine *sdma, int channel) |
729 | { | |
730 | return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel)); | |
731 | } | |
732 | ||
b9a59166 RZ |
733 | static void sdma_enable_channel(struct sdma_engine *sdma, int channel) |
734 | { | |
0bbc1413 | 735 | writel(BIT(channel), sdma->regs + SDMA_H_START); |
b9a59166 RZ |
736 | } |
737 | ||
1ec1e82f | 738 | /* |
2ccaef05 | 739 | * sdma_run_channel0 - run a channel and wait till it's done |
1ec1e82f | 740 | */ |
2ccaef05 | 741 | static int sdma_run_channel0(struct sdma_engine *sdma) |
1ec1e82f | 742 | { |
1ec1e82f | 743 | int ret; |
1d069bfa | 744 | u32 reg; |
1ec1e82f | 745 | |
2ccaef05 | 746 | sdma_enable_channel(sdma, 0); |
1ec1e82f | 747 | |
1d069bfa MO |
748 | ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, |
749 | reg, !(reg & 1), 1, 500); | |
750 | if (ret) | |
2ccaef05 | 751 | dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); |
1ec1e82f | 752 | |
855832e4 | 753 | /* Set bits of CONFIG register with dynamic context switching */ |
25aaa75d AAP |
754 | reg = readl(sdma->regs + SDMA_H_CONFIG); |
755 | if ((reg & SDMA_H_CONFIG_CSM) == 0) { | |
756 | reg |= SDMA_H_CONFIG_CSM; | |
757 | writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); | |
758 | } | |
855832e4 | 759 | |
1d069bfa | 760 | return ret; |
1ec1e82f SH |
761 | } |
762 | ||
763 | static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, | |
764 | u32 address) | |
765 | { | |
76c33d27 | 766 | struct sdma_buffer_descriptor *bd0 = sdma->bd0; |
1ec1e82f SH |
767 | void *buf_virt; |
768 | dma_addr_t buf_phys; | |
769 | int ret; | |
2ccaef05 | 770 | unsigned long flags; |
73eab978 | 771 | |
ceaf5226 | 772 | buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); |
ef6c1dad | 773 | if (!buf_virt) |
2ccaef05 | 774 | return -ENOMEM; |
1ec1e82f | 775 | |
2ccaef05 RZ |
776 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
777 | ||
1ec1e82f | 778 | bd0->mode.command = C0_SETPM; |
3f93a4f2 | 779 | bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; |
1ec1e82f SH |
780 | bd0->mode.count = size / 2; |
781 | bd0->buffer_addr = buf_phys; | |
782 | bd0->ext_buffer_addr = address; | |
783 | ||
784 | memcpy(buf_virt, buf, size); | |
785 | ||
2ccaef05 | 786 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 787 | |
2ccaef05 | 788 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
1ec1e82f | 789 | |
ceaf5226 | 790 | dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); |
73eab978 | 791 | |
1ec1e82f SH |
792 | return ret; |
793 | } | |
794 | ||
795 | static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) | |
796 | { | |
797 | struct sdma_engine *sdma = sdmac->sdma; | |
798 | int channel = sdmac->channel; | |
0bbc1413 | 799 | unsigned long val; |
1ec1e82f SH |
800 | u32 chnenbl = chnenbl_ofs(sdma, event); |
801 | ||
c4b56857 | 802 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 803 | __set_bit(channel, &val); |
c4b56857 | 804 | writel_relaxed(val, sdma->regs + chnenbl); |
824a0a02 SH |
805 | |
806 | /* Set SDMA_DONEx_CONFIG is sw_done enabled */ | |
807 | if (sdmac->sw_done) { | |
808 | val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); | |
809 | val |= SDMA_DONE0_CONFIG_DONE_SEL; | |
810 | val &= ~SDMA_DONE0_CONFIG_DONE_DIS; | |
811 | writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); | |
812 | } | |
1ec1e82f SH |
813 | } |
814 | ||
815 | static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) | |
816 | { | |
817 | struct sdma_engine *sdma = sdmac->sdma; | |
818 | int channel = sdmac->channel; | |
819 | u32 chnenbl = chnenbl_ofs(sdma, event); | |
0bbc1413 | 820 | unsigned long val; |
1ec1e82f | 821 | |
c4b56857 | 822 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 823 | __clear_bit(channel, &val); |
c4b56857 | 824 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
825 | } |
826 | ||
57b772b8 RG |
827 | static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t) |
828 | { | |
829 | return container_of(t, struct sdma_desc, vd.tx); | |
830 | } | |
831 | ||
832 | static void sdma_start_desc(struct sdma_channel *sdmac) | |
833 | { | |
834 | struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); | |
835 | struct sdma_desc *desc; | |
836 | struct sdma_engine *sdma = sdmac->sdma; | |
837 | int channel = sdmac->channel; | |
838 | ||
839 | if (!vd) { | |
840 | sdmac->desc = NULL; | |
841 | return; | |
842 | } | |
843 | sdmac->desc = desc = to_sdma_desc(&vd->tx); | |
02939cd1 SH |
844 | |
845 | list_del(&vd->node); | |
57b772b8 RG |
846 | |
847 | sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; | |
848 | sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; | |
849 | sdma_enable_channel(sdma, sdmac->channel); | |
850 | } | |
851 | ||
d1a792f3 | 852 | static void sdma_update_channel_loop(struct sdma_channel *sdmac) |
1ec1e82f SH |
853 | { |
854 | struct sdma_buffer_descriptor *bd; | |
5881826d NH |
855 | int error = 0; |
856 | enum dma_status old_status = sdmac->status; | |
1ec1e82f SH |
857 | |
858 | /* | |
859 | * loop mode. Iterate over descriptors, re-setup them and | |
860 | * call callback function. | |
861 | */ | |
57b772b8 | 862 | while (sdmac->desc) { |
76c33d27 SH |
863 | struct sdma_desc *desc = sdmac->desc; |
864 | ||
865 | bd = &desc->bd[desc->buf_tail]; | |
1ec1e82f SH |
866 | |
867 | if (bd->mode.status & BD_DONE) | |
868 | break; | |
869 | ||
5881826d NH |
870 | if (bd->mode.status & BD_RROR) { |
871 | bd->mode.status &= ~BD_RROR; | |
1ec1e82f | 872 | sdmac->status = DMA_ERROR; |
5881826d NH |
873 | error = -EIO; |
874 | } | |
1ec1e82f | 875 | |
5881826d NH |
876 | /* |
877 | * We use bd->mode.count to calculate the residue, since contains | |
878 | * the number of bytes present in the current buffer descriptor. | |
879 | */ | |
880 | ||
76c33d27 | 881 | desc->chn_real_count = bd->mode.count; |
76c33d27 SH |
882 | bd->mode.count = desc->period_len; |
883 | desc->buf_ptail = desc->buf_tail; | |
884 | desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; | |
15f30f51 NH |
885 | |
886 | /* | |
887 | * The callback is called from the interrupt context in order | |
888 | * to reduce latency and to avoid the risk of altering the | |
889 | * SDMA transaction status by the time the client tasklet is | |
890 | * executed. | |
891 | */ | |
57b772b8 RG |
892 | spin_unlock(&sdmac->vc.lock); |
893 | dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); | |
894 | spin_lock(&sdmac->vc.lock); | |
15f30f51 | 895 | |
177360e0 TM |
896 | /* Assign buffer ownership to SDMA */ |
897 | bd->mode.status |= BD_DONE; | |
898 | ||
5881826d NH |
899 | if (error) |
900 | sdmac->status = old_status; | |
1ec1e82f | 901 | } |
5b215c28 TM |
902 | |
903 | /* | |
904 | * SDMA stops cyclic channel when DMA request triggers a channel and no SDMA | |
905 | * owned buffer is available (i.e. BD_DONE was set too late). | |
906 | */ | |
09f7b80f | 907 | if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) { |
5b215c28 TM |
908 | dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel); |
909 | sdma_enable_channel(sdmac->sdma, sdmac->channel); | |
910 | } | |
1ec1e82f SH |
911 | } |
912 | ||
57b772b8 | 913 | static void mxc_sdma_handle_channel_normal(struct sdma_channel *data) |
1ec1e82f | 914 | { |
15f30f51 | 915 | struct sdma_channel *sdmac = (struct sdma_channel *) data; |
1ec1e82f SH |
916 | struct sdma_buffer_descriptor *bd; |
917 | int i, error = 0; | |
918 | ||
76c33d27 | 919 | sdmac->desc->chn_real_count = 0; |
1ec1e82f SH |
920 | /* |
921 | * non loop mode. Iterate over all descriptors, collect | |
922 | * errors and call callback function | |
923 | */ | |
76c33d27 SH |
924 | for (i = 0; i < sdmac->desc->num_bd; i++) { |
925 | bd = &sdmac->desc->bd[i]; | |
1ec1e82f | 926 | |
fb7a444a | 927 | if (bd->mode.status & (BD_DONE | BD_RROR)) |
1ec1e82f | 928 | error = -EIO; |
fb7a444a | 929 | sdmac->desc->chn_real_count += bd->mode.count; |
1ec1e82f SH |
930 | } |
931 | ||
932 | if (error) | |
933 | sdmac->status = DMA_ERROR; | |
934 | else | |
409bff6a | 935 | sdmac->status = DMA_COMPLETE; |
1ec1e82f SH |
936 | } |
937 | ||
1ec1e82f SH |
938 | static irqreturn_t sdma_int_handler(int irq, void *dev_id) |
939 | { | |
940 | struct sdma_engine *sdma = dev_id; | |
0bbc1413 | 941 | unsigned long stat; |
1ec1e82f | 942 | |
c4b56857 RZ |
943 | stat = readl_relaxed(sdma->regs + SDMA_H_INTR); |
944 | writel_relaxed(stat, sdma->regs + SDMA_H_INTR); | |
1d069bfa MO |
945 | /* channel 0 is special and not handled here, see run_channel0() */ |
946 | stat &= ~1; | |
1ec1e82f SH |
947 | |
948 | while (stat) { | |
949 | int channel = fls(stat) - 1; | |
950 | struct sdma_channel *sdmac = &sdma->channel[channel]; | |
57b772b8 RG |
951 | struct sdma_desc *desc; |
952 | ||
953 | spin_lock(&sdmac->vc.lock); | |
954 | desc = sdmac->desc; | |
955 | if (desc) { | |
956 | if (sdmac->flags & IMX_DMA_SG_LOOP) { | |
e873d432 JZ |
957 | if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) |
958 | sdma_update_channel_loop(sdmac); | |
959 | else | |
960 | vchan_cyclic_callback(&desc->vd); | |
57b772b8 RG |
961 | } else { |
962 | mxc_sdma_handle_channel_normal(sdmac); | |
963 | vchan_cookie_complete(&desc->vd); | |
964 | sdma_start_desc(sdmac); | |
965 | } | |
966 | } | |
1ec1e82f | 967 | |
57b772b8 | 968 | spin_unlock(&sdmac->vc.lock); |
0bbc1413 | 969 | __clear_bit(channel, &stat); |
1ec1e82f SH |
970 | } |
971 | ||
972 | return IRQ_HANDLED; | |
973 | } | |
974 | ||
975 | /* | |
976 | * sets the pc of SDMA script according to the peripheral type | |
977 | */ | |
625d8936 | 978 | static int sdma_get_pc(struct sdma_channel *sdmac, |
1ec1e82f SH |
979 | enum sdma_peripheral_type peripheral_type) |
980 | { | |
981 | struct sdma_engine *sdma = sdmac->sdma; | |
982 | int per_2_emi = 0, emi_2_per = 0; | |
983 | /* | |
984 | * These are needed once we start to support transfers between | |
985 | * two peripherals or memory-to-memory transfers | |
986 | */ | |
0f06c027 | 987 | int per_2_per = 0, emi_2_emi = 0; |
1ec1e82f SH |
988 | |
989 | sdmac->pc_from_device = 0; | |
990 | sdmac->pc_to_device = 0; | |
8391ecf4 | 991 | sdmac->device_to_device = 0; |
0f06c027 | 992 | sdmac->pc_to_pc = 0; |
e8fafa50 | 993 | sdmac->is_ram_script = false; |
1ec1e82f SH |
994 | |
995 | switch (peripheral_type) { | |
996 | case IMX_DMATYPE_MEMORY: | |
0f06c027 | 997 | emi_2_emi = sdma->script_addrs->ap_2_ap_addr; |
1ec1e82f SH |
998 | break; |
999 | case IMX_DMATYPE_DSP: | |
1000 | emi_2_per = sdma->script_addrs->bp_2_ap_addr; | |
1001 | per_2_emi = sdma->script_addrs->ap_2_bp_addr; | |
1002 | break; | |
1003 | case IMX_DMATYPE_FIRI: | |
1004 | per_2_emi = sdma->script_addrs->firi_2_mcu_addr; | |
1005 | emi_2_per = sdma->script_addrs->mcu_2_firi_addr; | |
1006 | break; | |
1007 | case IMX_DMATYPE_UART: | |
1008 | per_2_emi = sdma->script_addrs->uart_2_mcu_addr; | |
1009 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
1010 | break; | |
1011 | case IMX_DMATYPE_UART_SP: | |
1012 | per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; | |
1013 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
1014 | break; | |
1015 | case IMX_DMATYPE_ATA: | |
1016 | per_2_emi = sdma->script_addrs->ata_2_mcu_addr; | |
1017 | emi_2_per = sdma->script_addrs->mcu_2_ata_addr; | |
1018 | break; | |
1019 | case IMX_DMATYPE_CSPI: | |
a4965888 | 1020 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; |
4852e9a2 RG |
1021 | |
1022 | /* Use rom script mcu_2_app if ERR009165 fixed */ | |
1023 | if (sdmac->sdma->drvdata->ecspi_fixed) { | |
1024 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
1025 | } else { | |
1026 | emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; | |
1027 | sdmac->is_ram_script = true; | |
1028 | } | |
1029 | ||
a4965888 | 1030 | break; |
1ec1e82f SH |
1031 | case IMX_DMATYPE_EXT: |
1032 | case IMX_DMATYPE_SSI: | |
29aebfde | 1033 | case IMX_DMATYPE_SAI: |
1ec1e82f SH |
1034 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; |
1035 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
1036 | break; | |
1a895578 NC |
1037 | case IMX_DMATYPE_SSI_DUAL: |
1038 | per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; | |
1039 | emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; | |
e8fafa50 | 1040 | sdmac->is_ram_script = true; |
1a895578 | 1041 | break; |
1ec1e82f SH |
1042 | case IMX_DMATYPE_SSI_SP: |
1043 | case IMX_DMATYPE_MMC: | |
1044 | case IMX_DMATYPE_SDHC: | |
1045 | case IMX_DMATYPE_CSPI_SP: | |
1046 | case IMX_DMATYPE_ESAI: | |
1047 | case IMX_DMATYPE_MSHC_SP: | |
1048 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
1049 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
1050 | break; | |
1051 | case IMX_DMATYPE_ASRC: | |
1052 | per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; | |
1053 | emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; | |
1054 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
e8fafa50 | 1055 | sdmac->is_ram_script = true; |
1ec1e82f | 1056 | break; |
f892afb0 NC |
1057 | case IMX_DMATYPE_ASRC_SP: |
1058 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
1059 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
1060 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
1061 | break; | |
1ec1e82f SH |
1062 | case IMX_DMATYPE_MSHC: |
1063 | per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; | |
1064 | emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; | |
1065 | break; | |
1066 | case IMX_DMATYPE_CCM: | |
1067 | per_2_emi = sdma->script_addrs->dptc_dvfs_addr; | |
1068 | break; | |
1069 | case IMX_DMATYPE_SPDIF: | |
1070 | per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; | |
1071 | emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; | |
1072 | break; | |
1073 | case IMX_DMATYPE_IPU_MEMORY: | |
1074 | emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; | |
1075 | break; | |
824a0a02 SH |
1076 | case IMX_DMATYPE_MULTI_SAI: |
1077 | per_2_emi = sdma->script_addrs->sai_2_mcu_addr; | |
1078 | emi_2_per = sdma->script_addrs->mcu_2_sai_addr; | |
1ec1e82f | 1079 | break; |
e873d432 JZ |
1080 | case IMX_DMATYPE_HDMI: |
1081 | emi_2_per = sdma->script_addrs->hdmi_dma_addr; | |
1082 | sdmac->is_ram_script = true; | |
1083 | break; | |
1ec1e82f | 1084 | default: |
625d8936 SH |
1085 | dev_err(sdma->dev, "Unsupported transfer type %d\n", |
1086 | peripheral_type); | |
1087 | return -EINVAL; | |
1ec1e82f SH |
1088 | } |
1089 | ||
1090 | sdmac->pc_from_device = per_2_emi; | |
1091 | sdmac->pc_to_device = emi_2_per; | |
8391ecf4 | 1092 | sdmac->device_to_device = per_2_per; |
0f06c027 | 1093 | sdmac->pc_to_pc = emi_2_emi; |
625d8936 SH |
1094 | |
1095 | return 0; | |
1ec1e82f SH |
1096 | } |
1097 | ||
1098 | static int sdma_load_context(struct sdma_channel *sdmac) | |
1099 | { | |
1100 | struct sdma_engine *sdma = sdmac->sdma; | |
1101 | int channel = sdmac->channel; | |
1102 | int load_address; | |
1103 | struct sdma_context_data *context = sdma->context; | |
76c33d27 | 1104 | struct sdma_buffer_descriptor *bd0 = sdma->bd0; |
1ec1e82f | 1105 | int ret; |
2ccaef05 | 1106 | unsigned long flags; |
1ec1e82f | 1107 | |
8391ecf4 | 1108 | if (sdmac->direction == DMA_DEV_TO_MEM) |
1ec1e82f | 1109 | load_address = sdmac->pc_from_device; |
8391ecf4 SW |
1110 | else if (sdmac->direction == DMA_DEV_TO_DEV) |
1111 | load_address = sdmac->device_to_device; | |
0f06c027 RG |
1112 | else if (sdmac->direction == DMA_MEM_TO_MEM) |
1113 | load_address = sdmac->pc_to_pc; | |
8391ecf4 | 1114 | else |
1ec1e82f | 1115 | load_address = sdmac->pc_to_device; |
1ec1e82f SH |
1116 | |
1117 | if (load_address < 0) | |
1118 | return load_address; | |
1119 | ||
1120 | dev_dbg(sdma->dev, "load_address = %d\n", load_address); | |
0bbc1413 | 1121 | dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); |
1ec1e82f SH |
1122 | dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); |
1123 | dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); | |
0bbc1413 RZ |
1124 | dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); |
1125 | dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); | |
1ec1e82f | 1126 | |
2ccaef05 | 1127 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
73eab978 | 1128 | |
1ec1e82f SH |
1129 | memset(context, 0, sizeof(*context)); |
1130 | context->channel_state.pc = load_address; | |
1131 | ||
1132 | /* Send by context the event mask,base address for peripheral | |
1133 | * and watermark level | |
1134 | */ | |
e873d432 JZ |
1135 | if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { |
1136 | context->gReg[4] = sdmac->per_addr; | |
1137 | context->gReg[6] = sdmac->shp_addr; | |
1138 | } else { | |
1139 | context->gReg[0] = sdmac->event_mask[1]; | |
1140 | context->gReg[1] = sdmac->event_mask[0]; | |
1141 | context->gReg[2] = sdmac->per_addr; | |
1142 | context->gReg[6] = sdmac->shp_addr; | |
1143 | context->gReg[7] = sdmac->watermark_level; | |
1144 | } | |
1ec1e82f SH |
1145 | |
1146 | bd0->mode.command = C0_SETDM; | |
3f93a4f2 | 1147 | bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; |
1ec1e82f SH |
1148 | bd0->mode.count = sizeof(*context) / 4; |
1149 | bd0->buffer_addr = sdma->context_phys; | |
1150 | bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; | |
2ccaef05 | 1151 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 1152 | |
2ccaef05 | 1153 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
73eab978 | 1154 | |
1ec1e82f SH |
1155 | return ret; |
1156 | } | |
1157 | ||
7b350ab0 MR |
1158 | static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) |
1159 | { | |
57b772b8 | 1160 | return container_of(chan, struct sdma_channel, vc.chan); |
7b350ab0 MR |
1161 | } |
1162 | ||
1163 | static int sdma_disable_channel(struct dma_chan *chan) | |
1ec1e82f | 1164 | { |
7b350ab0 | 1165 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1ec1e82f SH |
1166 | struct sdma_engine *sdma = sdmac->sdma; |
1167 | int channel = sdmac->channel; | |
1168 | ||
0bbc1413 | 1169 | writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); |
1ec1e82f | 1170 | sdmac->status = DMA_ERROR; |
7b350ab0 MR |
1171 | |
1172 | return 0; | |
1ec1e82f | 1173 | } |
b8603d2a | 1174 | static void sdma_channel_terminate_work(struct work_struct *work) |
7f3ff14b | 1175 | { |
b8603d2a LS |
1176 | struct sdma_channel *sdmac = container_of(work, struct sdma_channel, |
1177 | terminate_worker); | |
7f3ff14b JW |
1178 | /* |
1179 | * According to NXP R&D team a delay of one BD SDMA cost time | |
1180 | * (maximum is 1ms) should be added after disable of the channel | |
1181 | * bit, to ensure SDMA core has really been stopped after SDMA | |
1182 | * clients call .device_terminate_all. | |
1183 | */ | |
b8603d2a LS |
1184 | usleep_range(1000, 2000); |
1185 | ||
4e2b10be | 1186 | vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated); |
b8603d2a LS |
1187 | } |
1188 | ||
a80f2787 | 1189 | static int sdma_terminate_all(struct dma_chan *chan) |
b8603d2a LS |
1190 | { |
1191 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
02939cd1 SH |
1192 | unsigned long flags; |
1193 | ||
1194 | spin_lock_irqsave(&sdmac->vc.lock, flags); | |
b8603d2a LS |
1195 | |
1196 | sdma_disable_channel(chan); | |
1197 | ||
02939cd1 SH |
1198 | if (sdmac->desc) { |
1199 | vchan_terminate_vdesc(&sdmac->desc->vd); | |
4e2b10be RG |
1200 | /* |
1201 | * move out current descriptor into terminated list so that | |
1202 | * it could be free in sdma_channel_terminate_work alone | |
1203 | * later without potential involving next descriptor raised | |
1204 | * up before the last descriptor terminated. | |
1205 | */ | |
1206 | vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated); | |
02939cd1 | 1207 | sdmac->desc = NULL; |
b8603d2a | 1208 | schedule_work(&sdmac->terminate_worker); |
02939cd1 SH |
1209 | } |
1210 | ||
1211 | spin_unlock_irqrestore(&sdmac->vc.lock, flags); | |
7f3ff14b JW |
1212 | |
1213 | return 0; | |
1214 | } | |
1215 | ||
b8603d2a LS |
1216 | static void sdma_channel_synchronize(struct dma_chan *chan) |
1217 | { | |
1218 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1219 | ||
1220 | vchan_synchronize(&sdmac->vc); | |
1221 | ||
1222 | flush_work(&sdmac->terminate_worker); | |
1223 | } | |
1224 | ||
8391ecf4 SW |
1225 | static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) |
1226 | { | |
1227 | struct sdma_engine *sdma = sdmac->sdma; | |
1228 | ||
1229 | int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; | |
1230 | int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; | |
1231 | ||
1232 | set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); | |
1233 | set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); | |
1234 | ||
1235 | if (sdmac->event_id0 > 31) | |
1236 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; | |
1237 | ||
1238 | if (sdmac->event_id1 > 31) | |
1239 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; | |
1240 | ||
1241 | /* | |
1242 | * If LWML(src_maxburst) > HWML(dst_maxburst), we need | |
1243 | * swap LWML and HWML of INFO(A.3.2.5.1), also need swap | |
1244 | * r0(event_mask[1]) and r1(event_mask[0]). | |
1245 | */ | |
1246 | if (lwml > hwml) { | |
1247 | sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | | |
1248 | SDMA_WATERMARK_LEVEL_HWML); | |
1249 | sdmac->watermark_level |= hwml; | |
1250 | sdmac->watermark_level |= lwml << 16; | |
1251 | swap(sdmac->event_mask[0], sdmac->event_mask[1]); | |
1252 | } | |
1253 | ||
1254 | if (sdmac->per_address2 >= sdma->spba_start_addr && | |
1255 | sdmac->per_address2 <= sdma->spba_end_addr) | |
1256 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; | |
1257 | ||
1258 | if (sdmac->per_address >= sdma->spba_start_addr && | |
1259 | sdmac->per_address <= sdma->spba_end_addr) | |
1260 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; | |
1261 | ||
1262 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; | |
1263 | } | |
1264 | ||
824a0a02 SH |
1265 | static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac) |
1266 | { | |
1267 | unsigned int n_fifos; | |
e0c7ea83 SW |
1268 | unsigned int stride_fifos; |
1269 | unsigned int words_per_fifo; | |
824a0a02 SH |
1270 | |
1271 | if (sdmac->sw_done) | |
1272 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE; | |
1273 | ||
e0c7ea83 | 1274 | if (sdmac->direction == DMA_DEV_TO_MEM) { |
824a0a02 | 1275 | n_fifos = sdmac->n_fifos_src; |
e0c7ea83 SW |
1276 | stride_fifos = sdmac->stride_fifos_src; |
1277 | } else { | |
824a0a02 | 1278 | n_fifos = sdmac->n_fifos_dst; |
e0c7ea83 SW |
1279 | stride_fifos = sdmac->stride_fifos_dst; |
1280 | } | |
1281 | ||
1282 | words_per_fifo = sdmac->words_per_fifo; | |
824a0a02 SH |
1283 | |
1284 | sdmac->watermark_level |= | |
1285 | FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, n_fifos); | |
e0c7ea83 SW |
1286 | sdmac->watermark_level |= |
1287 | FIELD_PREP(SDMA_WATERMARK_LEVEL_OFF_FIFOS, stride_fifos); | |
1288 | if (words_per_fifo) | |
1289 | sdmac->watermark_level |= | |
1290 | FIELD_PREP(SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO, (words_per_fifo - 1)); | |
824a0a02 SH |
1291 | } |
1292 | ||
7b350ab0 | 1293 | static int sdma_config_channel(struct dma_chan *chan) |
1ec1e82f | 1294 | { |
7b350ab0 | 1295 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
625d8936 | 1296 | int ret; |
1ec1e82f | 1297 | |
7b350ab0 | 1298 | sdma_disable_channel(chan); |
1ec1e82f | 1299 | |
0bbc1413 RZ |
1300 | sdmac->event_mask[0] = 0; |
1301 | sdmac->event_mask[1] = 0; | |
1ec1e82f SH |
1302 | sdmac->shp_addr = 0; |
1303 | sdmac->per_addr = 0; | |
1304 | ||
1ec1e82f SH |
1305 | switch (sdmac->peripheral_type) { |
1306 | case IMX_DMATYPE_DSP: | |
1307 | sdma_config_ownership(sdmac, false, true, true); | |
1308 | break; | |
1309 | case IMX_DMATYPE_MEMORY: | |
1310 | sdma_config_ownership(sdmac, false, true, false); | |
1311 | break; | |
1312 | default: | |
1313 | sdma_config_ownership(sdmac, true, true, false); | |
1314 | break; | |
1315 | } | |
1316 | ||
625d8936 SH |
1317 | ret = sdma_get_pc(sdmac, sdmac->peripheral_type); |
1318 | if (ret) | |
1319 | return ret; | |
1ec1e82f SH |
1320 | |
1321 | if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && | |
1322 | (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { | |
1323 | /* Handle multiple event channels differently */ | |
1324 | if (sdmac->event_id1) { | |
8391ecf4 SW |
1325 | if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || |
1326 | sdmac->peripheral_type == IMX_DMATYPE_ASRC) | |
1327 | sdma_set_watermarklevel_for_p2p(sdmac); | |
1f8595ef | 1328 | } else { |
824a0a02 SH |
1329 | if (sdmac->peripheral_type == |
1330 | IMX_DMATYPE_MULTI_SAI) | |
1331 | sdma_set_watermarklevel_for_sais(sdmac); | |
1332 | ||
0bbc1413 | 1333 | __set_bit(sdmac->event_id0, sdmac->event_mask); |
1f8595ef | 1334 | } |
8391ecf4 | 1335 | |
1ec1e82f SH |
1336 | /* Address */ |
1337 | sdmac->shp_addr = sdmac->per_address; | |
8391ecf4 | 1338 | sdmac->per_addr = sdmac->per_address2; |
1ec1e82f SH |
1339 | } else { |
1340 | sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ | |
1341 | } | |
1342 | ||
e555a03b | 1343 | return 0; |
1ec1e82f SH |
1344 | } |
1345 | ||
1346 | static int sdma_set_channel_priority(struct sdma_channel *sdmac, | |
df7cc2aa | 1347 | unsigned int priority) |
1ec1e82f SH |
1348 | { |
1349 | struct sdma_engine *sdma = sdmac->sdma; | |
1350 | int channel = sdmac->channel; | |
1351 | ||
1352 | if (priority < MXC_SDMA_MIN_PRIORITY | |
1353 | || priority > MXC_SDMA_MAX_PRIORITY) { | |
1354 | return -EINVAL; | |
1355 | } | |
1356 | ||
c4b56857 | 1357 | writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); |
1ec1e82f SH |
1358 | |
1359 | return 0; | |
1360 | } | |
1361 | ||
57b772b8 | 1362 | static int sdma_request_channel0(struct sdma_engine *sdma) |
1ec1e82f | 1363 | { |
1ec1e82f SH |
1364 | int ret = -EBUSY; |
1365 | ||
31ef489a | 1366 | sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, |
df7cc2aa | 1367 | GFP_NOWAIT); |
57b772b8 | 1368 | if (!sdma->bd0) { |
1ec1e82f SH |
1369 | ret = -ENOMEM; |
1370 | goto out; | |
1371 | } | |
1372 | ||
57b772b8 RG |
1373 | sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; |
1374 | sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; | |
1ec1e82f | 1375 | |
57b772b8 | 1376 | sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); |
1ec1e82f SH |
1377 | return 0; |
1378 | out: | |
1379 | ||
1380 | return ret; | |
1381 | } | |
1382 | ||
57b772b8 RG |
1383 | |
1384 | static int sdma_alloc_bd(struct sdma_desc *desc) | |
1ec1e82f | 1385 | { |
ebb853b1 | 1386 | u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); |
57b772b8 | 1387 | int ret = 0; |
1ec1e82f | 1388 | |
31ef489a | 1389 | desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, |
df7cc2aa | 1390 | &desc->bd_phys, GFP_NOWAIT); |
57b772b8 RG |
1391 | if (!desc->bd) { |
1392 | ret = -ENOMEM; | |
1393 | goto out; | |
1394 | } | |
1395 | out: | |
1396 | return ret; | |
1397 | } | |
1ec1e82f | 1398 | |
57b772b8 RG |
1399 | static void sdma_free_bd(struct sdma_desc *desc) |
1400 | { | |
ebb853b1 LS |
1401 | u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); |
1402 | ||
ceaf5226 AD |
1403 | dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, |
1404 | desc->bd_phys); | |
57b772b8 | 1405 | } |
1ec1e82f | 1406 | |
57b772b8 RG |
1407 | static void sdma_desc_free(struct virt_dma_desc *vd) |
1408 | { | |
1409 | struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd); | |
1410 | ||
1411 | sdma_free_bd(desc); | |
1412 | kfree(desc); | |
1ec1e82f SH |
1413 | } |
1414 | ||
1415 | static int sdma_alloc_chan_resources(struct dma_chan *chan) | |
1416 | { | |
1417 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1418 | struct imx_dma_data *data = chan->private; | |
0f06c027 | 1419 | struct imx_dma_data mem_data; |
1ec1e82f SH |
1420 | int prio, ret; |
1421 | ||
0f06c027 RG |
1422 | /* |
1423 | * MEMCPY may never setup chan->private by filter function such as | |
1424 | * dmatest, thus create 'struct imx_dma_data mem_data' for this case. | |
1425 | * Please note in any other slave case, you have to setup chan->private | |
1426 | * with 'struct imx_dma_data' in your own filter function if you want to | |
1427 | * request dma channel by dma_request_channel() rather than | |
1428 | * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear | |
1429 | * to warn you to correct your filter function. | |
1430 | */ | |
1431 | if (!data) { | |
1432 | dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); | |
1433 | mem_data.priority = 2; | |
1434 | mem_data.peripheral_type = IMX_DMATYPE_MEMORY; | |
1435 | mem_data.dma_request = 0; | |
1436 | mem_data.dma_request2 = 0; | |
1437 | data = &mem_data; | |
1438 | ||
625d8936 SH |
1439 | ret = sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY); |
1440 | if (ret) | |
1441 | return ret; | |
0f06c027 | 1442 | } |
1ec1e82f SH |
1443 | |
1444 | switch (data->priority) { | |
1445 | case DMA_PRIO_HIGH: | |
1446 | prio = 3; | |
1447 | break; | |
1448 | case DMA_PRIO_MEDIUM: | |
1449 | prio = 2; | |
1450 | break; | |
1451 | case DMA_PRIO_LOW: | |
1452 | default: | |
1453 | prio = 1; | |
1454 | break; | |
1455 | } | |
1456 | ||
1457 | sdmac->peripheral_type = data->peripheral_type; | |
1458 | sdmac->event_id0 = data->dma_request; | |
8391ecf4 | 1459 | sdmac->event_id1 = data->dma_request2; |
c2c744d3 | 1460 | |
b93edcdd FE |
1461 | ret = clk_enable(sdmac->sdma->clk_ipg); |
1462 | if (ret) | |
1463 | return ret; | |
1464 | ret = clk_enable(sdmac->sdma->clk_ahb); | |
1465 | if (ret) | |
1466 | goto disable_clk_ipg; | |
c2c744d3 | 1467 | |
3bb5e7ca | 1468 | ret = sdma_set_channel_priority(sdmac, prio); |
1ec1e82f | 1469 | if (ret) |
b93edcdd | 1470 | goto disable_clk_ahb; |
1ec1e82f | 1471 | |
1ec1e82f | 1472 | return 0; |
b93edcdd FE |
1473 | |
1474 | disable_clk_ahb: | |
1475 | clk_disable(sdmac->sdma->clk_ahb); | |
1476 | disable_clk_ipg: | |
1477 | clk_disable(sdmac->sdma->clk_ipg); | |
1478 | return ret; | |
1ec1e82f SH |
1479 | } |
1480 | ||
1481 | static void sdma_free_chan_resources(struct dma_chan *chan) | |
1482 | { | |
1483 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1484 | struct sdma_engine *sdma = sdmac->sdma; | |
1485 | ||
a80f2787 | 1486 | sdma_terminate_all(chan); |
b8603d2a LS |
1487 | |
1488 | sdma_channel_synchronize(chan); | |
1ec1e82f | 1489 | |
2f57b8d5 | 1490 | sdma_event_disable(sdmac, sdmac->event_id0); |
1ec1e82f SH |
1491 | if (sdmac->event_id1) |
1492 | sdma_event_disable(sdmac, sdmac->event_id1); | |
1493 | ||
1494 | sdmac->event_id0 = 0; | |
1495 | sdmac->event_id1 = 0; | |
1496 | ||
1497 | sdma_set_channel_priority(sdmac, 0); | |
1498 | ||
7560e3f3 SH |
1499 | clk_disable(sdma->clk_ipg); |
1500 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1501 | } |
1502 | ||
21420841 RG |
1503 | static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, |
1504 | enum dma_transfer_direction direction, u32 bds) | |
1505 | { | |
1506 | struct sdma_desc *desc; | |
1507 | ||
e8fafa50 RG |
1508 | if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { |
1509 | dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); | |
1510 | goto err_out; | |
1511 | } | |
1512 | ||
21420841 RG |
1513 | desc = kzalloc((sizeof(*desc)), GFP_NOWAIT); |
1514 | if (!desc) | |
1515 | goto err_out; | |
1516 | ||
1517 | sdmac->status = DMA_IN_PROGRESS; | |
1518 | sdmac->direction = direction; | |
1519 | sdmac->flags = 0; | |
1520 | ||
1521 | desc->chn_count = 0; | |
1522 | desc->chn_real_count = 0; | |
1523 | desc->buf_tail = 0; | |
1524 | desc->buf_ptail = 0; | |
1525 | desc->sdmac = sdmac; | |
1526 | desc->num_bd = bds; | |
1527 | ||
e873d432 | 1528 | if (bds && sdma_alloc_bd(desc)) |
21420841 RG |
1529 | goto err_desc_out; |
1530 | ||
0f06c027 RG |
1531 | /* No slave_config called in MEMCPY case, so do here */ |
1532 | if (direction == DMA_MEM_TO_MEM) | |
1533 | sdma_config_ownership(sdmac, false, true, false); | |
1534 | ||
21420841 | 1535 | if (sdma_load_context(sdmac)) |
1417f59a | 1536 | goto err_bd_out; |
21420841 RG |
1537 | |
1538 | return desc; | |
1539 | ||
1417f59a HW |
1540 | err_bd_out: |
1541 | sdma_free_bd(desc); | |
21420841 RG |
1542 | err_desc_out: |
1543 | kfree(desc); | |
1544 | err_out: | |
1545 | return NULL; | |
1546 | } | |
1547 | ||
0f06c027 RG |
1548 | static struct dma_async_tx_descriptor *sdma_prep_memcpy( |
1549 | struct dma_chan *chan, dma_addr_t dma_dst, | |
1550 | dma_addr_t dma_src, size_t len, unsigned long flags) | |
1551 | { | |
1552 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1553 | struct sdma_engine *sdma = sdmac->sdma; | |
1554 | int channel = sdmac->channel; | |
1555 | size_t count; | |
1556 | int i = 0, param; | |
1557 | struct sdma_buffer_descriptor *bd; | |
1558 | struct sdma_desc *desc; | |
1559 | ||
1560 | if (!chan || !len) | |
1561 | return NULL; | |
1562 | ||
1563 | dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", | |
1564 | &dma_src, &dma_dst, len, channel); | |
1565 | ||
1566 | desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM, | |
1567 | len / SDMA_BD_MAX_CNT + 1); | |
1568 | if (!desc) | |
1569 | return NULL; | |
1570 | ||
1571 | do { | |
1572 | count = min_t(size_t, len, SDMA_BD_MAX_CNT); | |
1573 | bd = &desc->bd[i]; | |
1574 | bd->buffer_addr = dma_src; | |
1575 | bd->ext_buffer_addr = dma_dst; | |
1576 | bd->mode.count = count; | |
1577 | desc->chn_count += count; | |
1578 | bd->mode.command = 0; | |
1579 | ||
1580 | dma_src += count; | |
1581 | dma_dst += count; | |
1582 | len -= count; | |
1583 | i++; | |
1584 | ||
1585 | param = BD_DONE | BD_EXTD | BD_CONT; | |
1586 | /* last bd */ | |
1587 | if (!len) { | |
1588 | param |= BD_INTR; | |
1589 | param |= BD_LAST; | |
1590 | param &= ~BD_CONT; | |
1591 | } | |
1592 | ||
1593 | dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", | |
1594 | i, count, bd->buffer_addr, | |
1595 | param & BD_WRAP ? "wrap" : "", | |
1596 | param & BD_INTR ? " intr" : ""); | |
1597 | ||
1598 | bd->mode.status = param; | |
1599 | } while (len); | |
1600 | ||
1601 | return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); | |
1602 | } | |
1603 | ||
1ec1e82f SH |
1604 | static struct dma_async_tx_descriptor *sdma_prep_slave_sg( |
1605 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1606 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1607 | unsigned long flags, void *context) |
1ec1e82f SH |
1608 | { |
1609 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1610 | struct sdma_engine *sdma = sdmac->sdma; | |
ad78b000 | 1611 | int i, count; |
23889c63 | 1612 | int channel = sdmac->channel; |
1ec1e82f | 1613 | struct scatterlist *sg; |
57b772b8 | 1614 | struct sdma_desc *desc; |
1ec1e82f | 1615 | |
107d0644 VK |
1616 | sdma_config_write(chan, &sdmac->slave_config, direction); |
1617 | ||
21420841 | 1618 | desc = sdma_transfer_init(sdmac, direction, sg_len); |
57b772b8 RG |
1619 | if (!desc) |
1620 | goto err_out; | |
1621 | ||
1ec1e82f SH |
1622 | dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", |
1623 | sg_len, channel); | |
1624 | ||
1ec1e82f | 1625 | for_each_sg(sgl, sg, sg_len, i) { |
76c33d27 | 1626 | struct sdma_buffer_descriptor *bd = &desc->bd[i]; |
1ec1e82f SH |
1627 | int param; |
1628 | ||
d2f5c276 | 1629 | bd->buffer_addr = sg->dma_address; |
1ec1e82f | 1630 | |
fdaf9c4b | 1631 | count = sg_dma_len(sg); |
1ec1e82f | 1632 | |
4a6b2e8a | 1633 | if (count > SDMA_BD_MAX_CNT) { |
1ec1e82f | 1634 | dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", |
4a6b2e8a | 1635 | channel, count, SDMA_BD_MAX_CNT); |
57b772b8 | 1636 | goto err_bd_out; |
1ec1e82f SH |
1637 | } |
1638 | ||
1639 | bd->mode.count = count; | |
76c33d27 | 1640 | desc->chn_count += count; |
1ec1e82f | 1641 | |
ad78b000 | 1642 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) |
57b772b8 | 1643 | goto err_bd_out; |
1fa81c27 SH |
1644 | |
1645 | switch (sdmac->word_size) { | |
1646 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1ec1e82f | 1647 | bd->mode.command = 0; |
1fa81c27 | 1648 | if (count & 3 || sg->dma_address & 3) |
57b772b8 | 1649 | goto err_bd_out; |
1fa81c27 SH |
1650 | break; |
1651 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1652 | bd->mode.command = 2; | |
1653 | if (count & 1 || sg->dma_address & 1) | |
57b772b8 | 1654 | goto err_bd_out; |
1fa81c27 SH |
1655 | break; |
1656 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1657 | bd->mode.command = 1; | |
1658 | break; | |
1659 | default: | |
57b772b8 | 1660 | goto err_bd_out; |
1fa81c27 | 1661 | } |
1ec1e82f SH |
1662 | |
1663 | param = BD_DONE | BD_EXTD | BD_CONT; | |
1664 | ||
341b9419 | 1665 | if (i + 1 == sg_len) { |
1ec1e82f | 1666 | param |= BD_INTR; |
341b9419 SG |
1667 | param |= BD_LAST; |
1668 | param &= ~BD_CONT; | |
1ec1e82f SH |
1669 | } |
1670 | ||
c3cc74b2 OJ |
1671 | dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", |
1672 | i, count, (u64)sg->dma_address, | |
1ec1e82f SH |
1673 | param & BD_WRAP ? "wrap" : "", |
1674 | param & BD_INTR ? " intr" : ""); | |
1675 | ||
1676 | bd->mode.status = param; | |
1677 | } | |
1678 | ||
57b772b8 RG |
1679 | return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); |
1680 | err_bd_out: | |
1681 | sdma_free_bd(desc); | |
1682 | kfree(desc); | |
1ec1e82f | 1683 | err_out: |
4b2ce9dd | 1684 | sdmac->status = DMA_ERROR; |
1ec1e82f SH |
1685 | return NULL; |
1686 | } | |
1687 | ||
1688 | static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( | |
1689 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 1690 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1691 | unsigned long flags) |
1ec1e82f SH |
1692 | { |
1693 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1694 | struct sdma_engine *sdma = sdmac->sdma; | |
e873d432 | 1695 | int num_periods = 0; |
23889c63 | 1696 | int channel = sdmac->channel; |
21420841 | 1697 | int i = 0, buf = 0; |
57b772b8 | 1698 | struct sdma_desc *desc; |
1ec1e82f SH |
1699 | |
1700 | dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); | |
1701 | ||
e873d432 JZ |
1702 | if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) |
1703 | num_periods = buf_len / period_len; | |
1704 | ||
107d0644 VK |
1705 | sdma_config_write(chan, &sdmac->slave_config, direction); |
1706 | ||
21420841 | 1707 | desc = sdma_transfer_init(sdmac, direction, num_periods); |
57b772b8 RG |
1708 | if (!desc) |
1709 | goto err_out; | |
1710 | ||
76c33d27 | 1711 | desc->period_len = period_len; |
8e2e27c7 | 1712 | |
1ec1e82f | 1713 | sdmac->flags |= IMX_DMA_SG_LOOP; |
1ec1e82f | 1714 | |
4a6b2e8a | 1715 | if (period_len > SDMA_BD_MAX_CNT) { |
ba6ab3b3 | 1716 | dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", |
4a6b2e8a | 1717 | channel, period_len, SDMA_BD_MAX_CNT); |
57b772b8 | 1718 | goto err_bd_out; |
1ec1e82f SH |
1719 | } |
1720 | ||
e873d432 JZ |
1721 | if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) |
1722 | return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); | |
1723 | ||
1ec1e82f | 1724 | while (buf < buf_len) { |
76c33d27 | 1725 | struct sdma_buffer_descriptor *bd = &desc->bd[i]; |
1ec1e82f SH |
1726 | int param; |
1727 | ||
1728 | bd->buffer_addr = dma_addr; | |
1729 | ||
1730 | bd->mode.count = period_len; | |
1731 | ||
1732 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) | |
57b772b8 | 1733 | goto err_bd_out; |
1ec1e82f SH |
1734 | if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) |
1735 | bd->mode.command = 0; | |
1736 | else | |
1737 | bd->mode.command = sdmac->word_size; | |
1738 | ||
1739 | param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; | |
1740 | if (i + 1 == num_periods) | |
1741 | param |= BD_WRAP; | |
1742 | ||
ba6ab3b3 | 1743 | dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", |
c3cc74b2 | 1744 | i, period_len, (u64)dma_addr, |
1ec1e82f SH |
1745 | param & BD_WRAP ? "wrap" : "", |
1746 | param & BD_INTR ? " intr" : ""); | |
1747 | ||
1748 | bd->mode.status = param; | |
1749 | ||
1750 | dma_addr += period_len; | |
1751 | buf += period_len; | |
1752 | ||
1753 | i++; | |
1754 | } | |
1755 | ||
57b772b8 RG |
1756 | return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); |
1757 | err_bd_out: | |
1758 | sdma_free_bd(desc); | |
1759 | kfree(desc); | |
1ec1e82f SH |
1760 | err_out: |
1761 | sdmac->status = DMA_ERROR; | |
1762 | return NULL; | |
1763 | } | |
1764 | ||
107d0644 VK |
1765 | static int sdma_config_write(struct dma_chan *chan, |
1766 | struct dma_slave_config *dmaengine_cfg, | |
1767 | enum dma_transfer_direction direction) | |
1ec1e82f SH |
1768 | { |
1769 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1ec1e82f | 1770 | |
107d0644 | 1771 | if (direction == DMA_DEV_TO_MEM) { |
7b350ab0 MR |
1772 | sdmac->per_address = dmaengine_cfg->src_addr; |
1773 | sdmac->watermark_level = dmaengine_cfg->src_maxburst * | |
1774 | dmaengine_cfg->src_addr_width; | |
1775 | sdmac->word_size = dmaengine_cfg->src_addr_width; | |
107d0644 | 1776 | } else if (direction == DMA_DEV_TO_DEV) { |
8391ecf4 SW |
1777 | sdmac->per_address2 = dmaengine_cfg->src_addr; |
1778 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1779 | sdmac->watermark_level = dmaengine_cfg->src_maxburst & | |
1780 | SDMA_WATERMARK_LEVEL_LWML; | |
1781 | sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & | |
1782 | SDMA_WATERMARK_LEVEL_HWML; | |
1783 | sdmac->word_size = dmaengine_cfg->dst_addr_width; | |
e873d432 JZ |
1784 | } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { |
1785 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1786 | sdmac->per_address2 = dmaengine_cfg->src_addr; | |
1787 | sdmac->watermark_level = 0; | |
7b350ab0 MR |
1788 | } else { |
1789 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1790 | sdmac->watermark_level = dmaengine_cfg->dst_maxburst * | |
1791 | dmaengine_cfg->dst_addr_width; | |
1792 | sdmac->word_size = dmaengine_cfg->dst_addr_width; | |
1793 | } | |
107d0644 | 1794 | sdmac->direction = direction; |
7b350ab0 | 1795 | return sdma_config_channel(chan); |
1ec1e82f SH |
1796 | } |
1797 | ||
107d0644 VK |
1798 | static int sdma_config(struct dma_chan *chan, |
1799 | struct dma_slave_config *dmaengine_cfg) | |
1800 | { | |
1801 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
824a0a02 | 1802 | struct sdma_engine *sdma = sdmac->sdma; |
107d0644 VK |
1803 | |
1804 | memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); | |
1805 | ||
824a0a02 SH |
1806 | if (dmaengine_cfg->peripheral_config) { |
1807 | struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config; | |
1808 | if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) { | |
1809 | dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n", | |
1810 | dmaengine_cfg->peripheral_size, | |
1811 | sizeof(struct sdma_peripheral_config)); | |
1812 | return -EINVAL; | |
1813 | } | |
1814 | sdmac->n_fifos_src = sdmacfg->n_fifos_src; | |
1815 | sdmac->n_fifos_dst = sdmacfg->n_fifos_dst; | |
e0c7ea83 SW |
1816 | sdmac->stride_fifos_src = sdmacfg->stride_fifos_src; |
1817 | sdmac->stride_fifos_dst = sdmacfg->stride_fifos_dst; | |
1818 | sdmac->words_per_fifo = sdmacfg->words_per_fifo; | |
824a0a02 SH |
1819 | sdmac->sw_done = sdmacfg->sw_done; |
1820 | } | |
1821 | ||
107d0644 | 1822 | /* Set ENBLn earlier to make sure dma request triggered after that */ |
2f57b8d5 FE |
1823 | if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) |
1824 | return -EINVAL; | |
1825 | sdma_event_enable(sdmac, sdmac->event_id0); | |
107d0644 VK |
1826 | |
1827 | if (sdmac->event_id1) { | |
1828 | if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) | |
1829 | return -EINVAL; | |
1830 | sdma_event_enable(sdmac, sdmac->event_id1); | |
1831 | } | |
1832 | ||
1833 | return 0; | |
1834 | } | |
1835 | ||
1ec1e82f | 1836 | static enum dma_status sdma_tx_status(struct dma_chan *chan, |
e8e3a790 AS |
1837 | dma_cookie_t cookie, |
1838 | struct dma_tx_state *txstate) | |
1ec1e82f SH |
1839 | { |
1840 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
a1ff6a07 | 1841 | struct sdma_desc *desc = NULL; |
d1a792f3 | 1842 | u32 residue; |
57b772b8 RG |
1843 | struct virt_dma_desc *vd; |
1844 | enum dma_status ret; | |
1845 | unsigned long flags; | |
d1a792f3 | 1846 | |
57b772b8 RG |
1847 | ret = dma_cookie_status(chan, cookie, txstate); |
1848 | if (ret == DMA_COMPLETE || !txstate) | |
1849 | return ret; | |
1850 | ||
1851 | spin_lock_irqsave(&sdmac->vc.lock, flags); | |
a1ff6a07 | 1852 | |
57b772b8 | 1853 | vd = vchan_find_desc(&sdmac->vc, cookie); |
a1ff6a07 | 1854 | if (vd) |
57b772b8 | 1855 | desc = to_sdma_desc(&vd->tx); |
a1ff6a07 SH |
1856 | else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) |
1857 | desc = sdmac->desc; | |
1858 | ||
1859 | if (desc) { | |
57b772b8 RG |
1860 | if (sdmac->flags & IMX_DMA_SG_LOOP) |
1861 | residue = (desc->num_bd - desc->buf_ptail) * | |
1862 | desc->period_len - desc->chn_real_count; | |
1863 | else | |
1864 | residue = desc->chn_count - desc->chn_real_count; | |
57b772b8 RG |
1865 | } else { |
1866 | residue = 0; | |
1867 | } | |
a1ff6a07 | 1868 | |
57b772b8 | 1869 | spin_unlock_irqrestore(&sdmac->vc.lock, flags); |
1ec1e82f | 1870 | |
e8e3a790 | 1871 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, |
d1a792f3 | 1872 | residue); |
1ec1e82f | 1873 | |
8a965911 | 1874 | return sdmac->status; |
1ec1e82f SH |
1875 | } |
1876 | ||
1877 | static void sdma_issue_pending(struct dma_chan *chan) | |
1878 | { | |
2b4f130e | 1879 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
57b772b8 | 1880 | unsigned long flags; |
2b4f130e | 1881 | |
57b772b8 RG |
1882 | spin_lock_irqsave(&sdmac->vc.lock, flags); |
1883 | if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) | |
1884 | sdma_start_desc(sdmac); | |
1885 | spin_unlock_irqrestore(&sdmac->vc.lock, flags); | |
1ec1e82f SH |
1886 | } |
1887 | ||
5b28aa31 | 1888 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 |
cd72b846 | 1889 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 |
b98ce2f4 RG |
1890 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45 |
1891 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46 | |
5b28aa31 SH |
1892 | |
1893 | static void sdma_add_scripts(struct sdma_engine *sdma, | |
df7cc2aa | 1894 | const struct sdma_script_start_addrs *addr) |
5b28aa31 SH |
1895 | { |
1896 | s32 *addr_arr = (u32 *)addr; | |
1897 | s32 *saddr_arr = (u32 *)sdma->script_addrs; | |
1898 | int i; | |
1899 | ||
70dabaed NC |
1900 | /* use the default firmware in ROM if missing external firmware */ |
1901 | if (!sdma->script_number) | |
1902 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1903 | ||
bd73dfab RG |
1904 | if (sdma->script_number > sizeof(struct sdma_script_start_addrs) |
1905 | / sizeof(s32)) { | |
1906 | dev_err(sdma->dev, | |
1907 | "SDMA script number %d not match with firmware.\n", | |
1908 | sdma->script_number); | |
1909 | return; | |
1910 | } | |
1911 | ||
cd72b846 | 1912 | for (i = 0; i < sdma->script_number; i++) |
5b28aa31 SH |
1913 | if (addr_arr[i] > 0) |
1914 | saddr_arr[i] = addr_arr[i]; | |
b98ce2f4 RG |
1915 | |
1916 | /* | |
a3ae97f4 KG |
1917 | * For compatibility with NXP internal legacy kernel before 4.19 which |
1918 | * is based on uart ram script and mainline kernel based on uart rom | |
1919 | * script, both uart ram/rom scripts are present in newer sdma | |
1920 | * firmware. Use the rom versions if they are present (V3 or newer). | |
b98ce2f4 | 1921 | */ |
a3ae97f4 KG |
1922 | if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { |
1923 | if (addr->uart_2_mcu_rom_addr) | |
1924 | sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; | |
1925 | if (addr->uartsh_2_mcu_rom_addr) | |
1926 | sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; | |
1927 | } | |
5b28aa31 SH |
1928 | } |
1929 | ||
7b4b88e0 | 1930 | static void sdma_load_firmware(const struct firmware *fw, void *context) |
5b28aa31 | 1931 | { |
7b4b88e0 | 1932 | struct sdma_engine *sdma = context; |
5b28aa31 | 1933 | const struct sdma_firmware_header *header; |
5b28aa31 SH |
1934 | const struct sdma_script_start_addrs *addr; |
1935 | unsigned short *ram_code; | |
1936 | ||
7b4b88e0 | 1937 | if (!fw) { |
0f927a11 SH |
1938 | dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); |
1939 | /* In this case we just use the ROM firmware. */ | |
7b4b88e0 SH |
1940 | return; |
1941 | } | |
5b28aa31 SH |
1942 | |
1943 | if (fw->size < sizeof(*header)) | |
1944 | goto err_firmware; | |
1945 | ||
1946 | header = (struct sdma_firmware_header *)fw->data; | |
1947 | ||
1948 | if (header->magic != SDMA_FIRMWARE_MAGIC) | |
1949 | goto err_firmware; | |
1950 | if (header->ram_code_start + header->ram_code_size > fw->size) | |
1951 | goto err_firmware; | |
cd72b846 | 1952 | switch (header->version_major) { |
681d15ec AV |
1953 | case 1: |
1954 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1955 | break; | |
1956 | case 2: | |
1957 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; | |
1958 | break; | |
a572460b FE |
1959 | case 3: |
1960 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; | |
1961 | break; | |
b7d2648a FE |
1962 | case 4: |
1963 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; | |
1964 | break; | |
681d15ec AV |
1965 | default: |
1966 | dev_err(sdma->dev, "unknown firmware version\n"); | |
1967 | goto err_firmware; | |
cd72b846 | 1968 | } |
5b28aa31 SH |
1969 | |
1970 | addr = (void *)header + header->script_addrs_start; | |
1971 | ram_code = (void *)header + header->ram_code_start; | |
1972 | ||
7560e3f3 SH |
1973 | clk_enable(sdma->clk_ipg); |
1974 | clk_enable(sdma->clk_ahb); | |
5b28aa31 SH |
1975 | /* download the RAM image for SDMA */ |
1976 | sdma_load_script(sdma, ram_code, | |
df7cc2aa FS |
1977 | header->ram_code_size, |
1978 | addr->ram_code_start_addr); | |
7560e3f3 SH |
1979 | clk_disable(sdma->clk_ipg); |
1980 | clk_disable(sdma->clk_ahb); | |
5b28aa31 SH |
1981 | |
1982 | sdma_add_scripts(sdma, addr); | |
1983 | ||
e8fafa50 RG |
1984 | sdma->fw_loaded = true; |
1985 | ||
5b28aa31 | 1986 | dev_info(sdma->dev, "loaded firmware %d.%d\n", |
df7cc2aa FS |
1987 | header->version_major, |
1988 | header->version_minor); | |
5b28aa31 SH |
1989 | |
1990 | err_firmware: | |
1991 | release_firmware(fw); | |
7b4b88e0 SH |
1992 | } |
1993 | ||
d078cd1b ZW |
1994 | #define EVENT_REMAP_CELLS 3 |
1995 | ||
29f493da | 1996 | static int sdma_event_remap(struct sdma_engine *sdma) |
d078cd1b ZW |
1997 | { |
1998 | struct device_node *np = sdma->dev->of_node; | |
1999 | struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); | |
2000 | struct property *event_remap; | |
2001 | struct regmap *gpr; | |
2002 | char propname[] = "fsl,sdma-event-remap"; | |
2003 | u32 reg, val, shift, num_map, i; | |
2004 | int ret = 0; | |
2005 | ||
7104b9cb | 2006 | if (IS_ERR(np) || !gpr_np) |
d078cd1b ZW |
2007 | goto out; |
2008 | ||
2009 | event_remap = of_find_property(np, propname, NULL); | |
2010 | num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; | |
2011 | if (!num_map) { | |
ce078af7 | 2012 | dev_dbg(sdma->dev, "no event needs to be remapped\n"); |
d078cd1b ZW |
2013 | goto out; |
2014 | } else if (num_map % EVENT_REMAP_CELLS) { | |
2015 | dev_err(sdma->dev, "the property %s must modulo %d\n", | |
2016 | propname, EVENT_REMAP_CELLS); | |
2017 | ret = -EINVAL; | |
2018 | goto out; | |
2019 | } | |
2020 | ||
2021 | gpr = syscon_node_to_regmap(gpr_np); | |
2022 | if (IS_ERR(gpr)) { | |
2023 | dev_err(sdma->dev, "failed to get gpr regmap\n"); | |
2024 | ret = PTR_ERR(gpr); | |
2025 | goto out; | |
2026 | } | |
2027 | ||
2028 | for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { | |
2029 | ret = of_property_read_u32_index(np, propname, i, ®); | |
2030 | if (ret) { | |
2031 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
2032 | propname, i); | |
2033 | goto out; | |
2034 | } | |
2035 | ||
2036 | ret = of_property_read_u32_index(np, propname, i + 1, &shift); | |
2037 | if (ret) { | |
2038 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
2039 | propname, i + 1); | |
2040 | goto out; | |
2041 | } | |
2042 | ||
2043 | ret = of_property_read_u32_index(np, propname, i + 2, &val); | |
2044 | if (ret) { | |
2045 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
2046 | propname, i + 2); | |
2047 | goto out; | |
2048 | } | |
2049 | ||
2050 | regmap_update_bits(gpr, reg, BIT(shift), val << shift); | |
2051 | } | |
2052 | ||
2053 | out: | |
7104b9cb | 2054 | if (gpr_np) |
d078cd1b ZW |
2055 | of_node_put(gpr_np); |
2056 | ||
2057 | return ret; | |
2058 | } | |
2059 | ||
fe6cf289 | 2060 | static int sdma_get_firmware(struct sdma_engine *sdma, |
7b4b88e0 SH |
2061 | const char *fw_name) |
2062 | { | |
2063 | int ret; | |
2064 | ||
2065 | ret = request_firmware_nowait(THIS_MODULE, | |
0733d839 | 2066 | FW_ACTION_UEVENT, fw_name, sdma->dev, |
7b4b88e0 | 2067 | GFP_KERNEL, sdma, sdma_load_firmware); |
5b28aa31 SH |
2068 | |
2069 | return ret; | |
2070 | } | |
2071 | ||
19bfc772 | 2072 | static int sdma_init(struct sdma_engine *sdma) |
1ec1e82f SH |
2073 | { |
2074 | int i, ret; | |
2075 | dma_addr_t ccb_phys; | |
2076 | ||
b93edcdd FE |
2077 | ret = clk_enable(sdma->clk_ipg); |
2078 | if (ret) | |
2079 | return ret; | |
2080 | ret = clk_enable(sdma->clk_ahb); | |
2081 | if (ret) | |
2082 | goto disable_clk_ipg; | |
1ec1e82f | 2083 | |
941acd56 AAP |
2084 | if (sdma->drvdata->check_ratio && |
2085 | (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) | |
25aaa75d AAP |
2086 | sdma->clk_ratio = 1; |
2087 | ||
1ec1e82f | 2088 | /* Be sure SDMA has not started yet */ |
c4b56857 | 2089 | writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f | 2090 | |
ceaf5226 | 2091 | sdma->channel_control = dma_alloc_coherent(sdma->dev, |
635156d9 | 2092 | MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control) + |
1ec1e82f SH |
2093 | sizeof(struct sdma_context_data), |
2094 | &ccb_phys, GFP_KERNEL); | |
2095 | ||
2096 | if (!sdma->channel_control) { | |
2097 | ret = -ENOMEM; | |
2098 | goto err_dma_alloc; | |
2099 | } | |
2100 | ||
2101 | sdma->context = (void *)sdma->channel_control + | |
635156d9 | 2102 | MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control); |
1ec1e82f | 2103 | sdma->context_phys = ccb_phys + |
635156d9 | 2104 | MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control); |
1ec1e82f | 2105 | |
1ec1e82f | 2106 | /* disable all channels */ |
17bba72f | 2107 | for (i = 0; i < sdma->drvdata->num_events; i++) |
c4b56857 | 2108 | writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); |
1ec1e82f SH |
2109 | |
2110 | /* All channels have priority 0 */ | |
2111 | for (i = 0; i < MAX_DMA_CHANNELS; i++) | |
c4b56857 | 2112 | writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); |
1ec1e82f | 2113 | |
57b772b8 | 2114 | ret = sdma_request_channel0(sdma); |
1ec1e82f SH |
2115 | if (ret) |
2116 | goto err_dma_alloc; | |
2117 | ||
2118 | sdma_config_ownership(&sdma->channel[0], false, true, false); | |
2119 | ||
2120 | /* Set Command Channel (Channel Zero) */ | |
c4b56857 | 2121 | writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); |
1ec1e82f SH |
2122 | |
2123 | /* Set bits of CONFIG register but with static context switching */ | |
25aaa75d AAP |
2124 | if (sdma->clk_ratio) |
2125 | writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); | |
2126 | else | |
2127 | writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); | |
1ec1e82f | 2128 | |
c4b56857 | 2129 | writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f | 2130 | |
1ec1e82f SH |
2131 | /* Initializes channel's priorities */ |
2132 | sdma_set_channel_priority(&sdma->channel[0], 7); | |
2133 | ||
7560e3f3 SH |
2134 | clk_disable(sdma->clk_ipg); |
2135 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
2136 | |
2137 | return 0; | |
2138 | ||
2139 | err_dma_alloc: | |
7560e3f3 | 2140 | clk_disable(sdma->clk_ahb); |
b93edcdd FE |
2141 | disable_clk_ipg: |
2142 | clk_disable(sdma->clk_ipg); | |
1ec1e82f SH |
2143 | dev_err(sdma->dev, "initialisation failed with %d\n", ret); |
2144 | return ret; | |
2145 | } | |
2146 | ||
9479e17c SG |
2147 | static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) |
2148 | { | |
0b351865 | 2149 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
9479e17c SG |
2150 | struct imx_dma_data *data = fn_param; |
2151 | ||
2152 | if (!imx_dma_is_general_purpose(chan)) | |
2153 | return false; | |
2154 | ||
0b351865 NC |
2155 | sdmac->data = *data; |
2156 | chan->private = &sdmac->data; | |
9479e17c SG |
2157 | |
2158 | return true; | |
2159 | } | |
2160 | ||
2161 | static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, | |
2162 | struct of_dma *ofdma) | |
2163 | { | |
2164 | struct sdma_engine *sdma = ofdma->of_dma_data; | |
2165 | dma_cap_mask_t mask = sdma->dma_device.cap_mask; | |
2166 | struct imx_dma_data data; | |
2167 | ||
2168 | if (dma_spec->args_count != 3) | |
2169 | return NULL; | |
2170 | ||
2171 | data.dma_request = dma_spec->args[0]; | |
2172 | data.peripheral_type = dma_spec->args[1]; | |
2173 | data.priority = dma_spec->args[2]; | |
8391ecf4 SW |
2174 | /* |
2175 | * init dma_request2 to zero, which is not used by the dts. | |
2176 | * For P2P, dma_request2 is init from dma_request_channel(), | |
2177 | * chan->private will point to the imx_dma_data, and in | |
2178 | * device_alloc_chan_resources(), imx_dma_data.dma_request2 will | |
2179 | * be set to sdmac->event_id1. | |
2180 | */ | |
2181 | data.dma_request2 = 0; | |
9479e17c | 2182 | |
990c0b53 BW |
2183 | return __dma_request_channel(&mask, sdma_filter_fn, &data, |
2184 | ofdma->of_node); | |
9479e17c SG |
2185 | } |
2186 | ||
e34b731f | 2187 | static int sdma_probe(struct platform_device *pdev) |
1ec1e82f | 2188 | { |
580975d7 | 2189 | struct device_node *np = pdev->dev.of_node; |
8391ecf4 | 2190 | struct device_node *spba_bus; |
580975d7 | 2191 | const char *fw_name; |
1ec1e82f | 2192 | int ret; |
1ec1e82f | 2193 | int irq; |
8391ecf4 | 2194 | struct resource spba_res; |
1ec1e82f | 2195 | int i; |
1ec1e82f | 2196 | struct sdma_engine *sdma; |
36e2f21a | 2197 | s32 *saddr_arr; |
1ec1e82f | 2198 | |
42536b9f PR |
2199 | ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
2200 | if (ret) | |
2201 | return ret; | |
2202 | ||
7f24e0ee | 2203 | sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); |
1ec1e82f SH |
2204 | if (!sdma) |
2205 | return -ENOMEM; | |
2206 | ||
2ccaef05 | 2207 | spin_lock_init(&sdma->channel_0_lock); |
73eab978 | 2208 | |
1ec1e82f | 2209 | sdma->dev = &pdev->dev; |
32996419 | 2210 | sdma->drvdata = of_device_get_match_data(sdma->dev); |
1ec1e82f | 2211 | |
1ec1e82f | 2212 | irq = platform_get_irq(pdev, 0); |
7f24e0ee | 2213 | if (irq < 0) |
63c72e02 | 2214 | return irq; |
1ec1e82f | 2215 | |
4b23603a | 2216 | sdma->regs = devm_platform_ioremap_resource(pdev, 0); |
7f24e0ee FE |
2217 | if (IS_ERR(sdma->regs)) |
2218 | return PTR_ERR(sdma->regs); | |
1ec1e82f | 2219 | |
7560e3f3 | 2220 | sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
7f24e0ee FE |
2221 | if (IS_ERR(sdma->clk_ipg)) |
2222 | return PTR_ERR(sdma->clk_ipg); | |
1ec1e82f | 2223 | |
7560e3f3 | 2224 | sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
7f24e0ee FE |
2225 | if (IS_ERR(sdma->clk_ahb)) |
2226 | return PTR_ERR(sdma->clk_ahb); | |
7560e3f3 | 2227 | |
fb9caf37 AY |
2228 | ret = clk_prepare(sdma->clk_ipg); |
2229 | if (ret) | |
2230 | return ret; | |
2231 | ||
2232 | ret = clk_prepare(sdma->clk_ahb); | |
2233 | if (ret) | |
2234 | goto err_clk; | |
7560e3f3 | 2235 | |
0951a90e FE |
2236 | ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, |
2237 | dev_name(&pdev->dev), sdma); | |
1ec1e82f | 2238 | if (ret) |
fb9caf37 | 2239 | goto err_irq; |
1ec1e82f | 2240 | |
5bb9dbb5 VK |
2241 | sdma->irq = irq; |
2242 | ||
5b28aa31 | 2243 | sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); |
fb9caf37 AY |
2244 | if (!sdma->script_addrs) { |
2245 | ret = -ENOMEM; | |
2246 | goto err_irq; | |
2247 | } | |
1ec1e82f | 2248 | |
36e2f21a SH |
2249 | /* initially no scripts available */ |
2250 | saddr_arr = (s32 *)sdma->script_addrs; | |
be4cf718 | 2251 | for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) |
36e2f21a SH |
2252 | saddr_arr[i] = -EINVAL; |
2253 | ||
7214a8b1 SH |
2254 | dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); |
2255 | dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); | |
0f06c027 | 2256 | dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); |
8d1b7bd5 | 2257 | dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask); |
7214a8b1 | 2258 | |
1ec1e82f SH |
2259 | INIT_LIST_HEAD(&sdma->dma_device.channels); |
2260 | /* Initialize channel parameters */ | |
2261 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
2262 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
2263 | ||
2264 | sdmac->sdma = sdma; | |
1ec1e82f | 2265 | |
1ec1e82f | 2266 | sdmac->channel = i; |
57b772b8 | 2267 | sdmac->vc.desc_free = sdma_desc_free; |
4e2b10be | 2268 | INIT_LIST_HEAD(&sdmac->terminated); |
b8603d2a LS |
2269 | INIT_WORK(&sdmac->terminate_worker, |
2270 | sdma_channel_terminate_work); | |
23889c63 SH |
2271 | /* |
2272 | * Add the channel to the DMAC list. Do not add channel 0 though | |
2273 | * because we need it internally in the SDMA driver. This also means | |
2274 | * that channel 0 in dmaengine counting matches sdma channel 1. | |
2275 | */ | |
2276 | if (i) | |
57b772b8 | 2277 | vchan_init(&sdmac->vc, &sdma->dma_device); |
1ec1e82f SH |
2278 | } |
2279 | ||
5b28aa31 | 2280 | ret = sdma_init(sdma); |
1ec1e82f SH |
2281 | if (ret) |
2282 | goto err_init; | |
2283 | ||
d078cd1b ZW |
2284 | ret = sdma_event_remap(sdma); |
2285 | if (ret) | |
2286 | goto err_init; | |
2287 | ||
dcfec3c0 SH |
2288 | if (sdma->drvdata->script_addrs) |
2289 | sdma_add_scripts(sdma, sdma->drvdata->script_addrs); | |
5b28aa31 | 2290 | |
1ec1e82f SH |
2291 | sdma->dma_device.dev = &pdev->dev; |
2292 | ||
2293 | sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; | |
2294 | sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; | |
2295 | sdma->dma_device.device_tx_status = sdma_tx_status; | |
2296 | sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; | |
2297 | sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; | |
7b350ab0 | 2298 | sdma->dma_device.device_config = sdma_config; |
a80f2787 | 2299 | sdma->dma_device.device_terminate_all = sdma_terminate_all; |
b8603d2a | 2300 | sdma->dma_device.device_synchronize = sdma_channel_synchronize; |
f9d4a398 NC |
2301 | sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; |
2302 | sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; | |
2303 | sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; | |
6f3125ce | 2304 | sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; |
0f06c027 | 2305 | sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; |
1ec1e82f | 2306 | sdma->dma_device.device_issue_pending = sdma_issue_pending; |
a3711d49 | 2307 | sdma->dma_device.copy_align = 2; |
4a6b2e8a | 2308 | dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); |
1ec1e82f | 2309 | |
23e11811 VR |
2310 | platform_set_drvdata(pdev, sdma); |
2311 | ||
1ec1e82f SH |
2312 | ret = dma_async_device_register(&sdma->dma_device); |
2313 | if (ret) { | |
2314 | dev_err(&pdev->dev, "unable to register\n"); | |
2315 | goto err_init; | |
2316 | } | |
2317 | ||
9479e17c SG |
2318 | if (np) { |
2319 | ret = of_dma_controller_register(np, sdma_xlate, sdma); | |
2320 | if (ret) { | |
2321 | dev_err(&pdev->dev, "failed to register controller\n"); | |
2322 | goto err_register; | |
2323 | } | |
8391ecf4 SW |
2324 | |
2325 | spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); | |
2326 | ret = of_address_to_resource(spba_bus, 0, &spba_res); | |
2327 | if (!ret) { | |
2328 | sdma->spba_start_addr = spba_res.start; | |
2329 | sdma->spba_end_addr = spba_res.end; | |
2330 | } | |
2331 | of_node_put(spba_bus); | |
9479e17c SG |
2332 | } |
2333 | ||
2b8066c3 | 2334 | /* |
d07b6621 FE |
2335 | * Because that device tree does not encode ROM script address, |
2336 | * the RAM script in firmware is mandatory for device tree | |
2337 | * probe, otherwise it fails. | |
2b8066c3 | 2338 | */ |
d07b6621 FE |
2339 | ret = of_property_read_string(np, "fsl,sdma-ram-script-name", |
2340 | &fw_name); | |
2341 | if (ret) { | |
2342 | dev_warn(&pdev->dev, "failed to get firmware name\n"); | |
2b8066c3 | 2343 | } else { |
d07b6621 FE |
2344 | ret = sdma_get_firmware(sdma, fw_name); |
2345 | if (ret) | |
2346 | dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); | |
2b8066c3 SVA |
2347 | } |
2348 | ||
1ec1e82f SH |
2349 | return 0; |
2350 | ||
9479e17c SG |
2351 | err_register: |
2352 | dma_async_device_unregister(&sdma->dma_device); | |
1ec1e82f SH |
2353 | err_init: |
2354 | kfree(sdma->script_addrs); | |
fb9caf37 AY |
2355 | err_irq: |
2356 | clk_unprepare(sdma->clk_ahb); | |
2357 | err_clk: | |
2358 | clk_unprepare(sdma->clk_ipg); | |
939fd4f0 | 2359 | return ret; |
1ec1e82f SH |
2360 | } |
2361 | ||
1d1bbd30 | 2362 | static int sdma_remove(struct platform_device *pdev) |
1ec1e82f | 2363 | { |
23e11811 | 2364 | struct sdma_engine *sdma = platform_get_drvdata(pdev); |
c12fe497 | 2365 | int i; |
23e11811 | 2366 | |
5bb9dbb5 | 2367 | devm_free_irq(&pdev->dev, sdma->irq, sdma); |
23e11811 VR |
2368 | dma_async_device_unregister(&sdma->dma_device); |
2369 | kfree(sdma->script_addrs); | |
fb9caf37 AY |
2370 | clk_unprepare(sdma->clk_ahb); |
2371 | clk_unprepare(sdma->clk_ipg); | |
c12fe497 VR |
2372 | /* Kill the tasklet */ |
2373 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
2374 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
2375 | ||
57b772b8 RG |
2376 | tasklet_kill(&sdmac->vc.task); |
2377 | sdma_free_chan_resources(&sdmac->vc.chan); | |
c12fe497 | 2378 | } |
23e11811 VR |
2379 | |
2380 | platform_set_drvdata(pdev, NULL); | |
23e11811 | 2381 | return 0; |
1ec1e82f SH |
2382 | } |
2383 | ||
2384 | static struct platform_driver sdma_driver = { | |
2385 | .driver = { | |
2386 | .name = "imx-sdma", | |
580975d7 | 2387 | .of_match_table = sdma_dt_ids, |
1ec1e82f | 2388 | }, |
1d1bbd30 | 2389 | .remove = sdma_remove, |
23e11811 | 2390 | .probe = sdma_probe, |
1ec1e82f SH |
2391 | }; |
2392 | ||
23e11811 | 2393 | module_platform_driver(sdma_driver); |
1ec1e82f SH |
2394 | |
2395 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
2396 | MODULE_DESCRIPTION("i.MX SDMA driver"); | |
c0879342 NC |
2397 | #if IS_ENABLED(CONFIG_SOC_IMX6Q) |
2398 | MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin"); | |
2399 | #endif | |
a7cd3cf0 | 2400 | #if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M) |
c0879342 NC |
2401 | MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin"); |
2402 | #endif | |
1ec1e82f | 2403 | MODULE_LICENSE("GPL"); |