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ce9c28ca FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // drivers/dma/imx-dma.c | |
4 | // | |
5 | // This file contains a driver for the Freescale i.MX DMA engine | |
6 | // found on i.MX1/21/27 | |
7 | // | |
8 | // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9 | // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> | |
10 | ||
7331205a | 11 | #include <linux/err.h> |
1f1846c6 SH |
12 | #include <linux/init.h> |
13 | #include <linux/types.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/platform_device.h> | |
6bd08127 | 21 | #include <linux/clk.h> |
1f1846c6 | 22 | #include <linux/dmaengine.h> |
5c45ad77 | 23 | #include <linux/module.h> |
290ad0f9 MP |
24 | #include <linux/of_device.h> |
25 | #include <linux/of_dma.h> | |
1f1846c6 SH |
26 | |
27 | #include <asm/irq.h> | |
82906b13 | 28 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 29 | |
d2ebfb33 | 30 | #include "dmaengine.h" |
9e15db7c | 31 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
32 | #define IMX_DMA_CHANNELS 16 |
33 | ||
f606ab89 JM |
34 | #define IMX_DMA_2D_SLOTS 2 |
35 | #define IMX_DMA_2D_SLOT_A 0 | |
36 | #define IMX_DMA_2D_SLOT_B 1 | |
37 | ||
6bd08127 JM |
38 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
39 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
40 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
41 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
42 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
43 | #define IMX_DMA_TYPE_2D (1 << 10) | |
44 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
45 | ||
46 | #define IMX_DMA_ERR_BURST (1 << 0) | |
47 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
48 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
49 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
50 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
51 | ||
52 | #define DMA_DCR 0x00 /* Control Register */ | |
53 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
54 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
55 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
56 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
57 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
58 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
59 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
60 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
61 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
62 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
63 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
64 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
65 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
66 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
67 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
68 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
69 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
70 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
71 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
72 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
73 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
74 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
75 | ||
76 | #define DCR_DRST (1<<1) | |
77 | #define DCR_DEN (1<<0) | |
78 | #define DBTOCR_EN (1<<15) | |
79 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
80 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
81 | #define CCR_ACRPT (1<<14) | |
82 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
83 | #define CCR_DMOD_2D (0x1 << 12) | |
84 | #define CCR_DMOD_FIFO (0x2 << 12) | |
85 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
86 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
87 | #define CCR_SMOD_2D (0x1 << 10) | |
88 | #define CCR_SMOD_FIFO (0x2 << 10) | |
89 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
90 | #define CCR_MDIR_DEC (1<<9) | |
91 | #define CCR_MSEL_B (1<<8) | |
92 | #define CCR_DSIZ_32 (0x0 << 6) | |
93 | #define CCR_DSIZ_8 (0x1 << 6) | |
94 | #define CCR_DSIZ_16 (0x2 << 6) | |
95 | #define CCR_SSIZ_32 (0x0 << 4) | |
96 | #define CCR_SSIZ_8 (0x1 << 4) | |
97 | #define CCR_SSIZ_16 (0x2 << 4) | |
98 | #define CCR_REN (1<<3) | |
99 | #define CCR_RPT (1<<2) | |
100 | #define CCR_FRC (1<<1) | |
101 | #define CCR_CEN (1<<0) | |
102 | #define RTOR_EN (1<<15) | |
103 | #define RTOR_CLK (1<<14) | |
104 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
105 | |
106 | enum imxdma_prep_type { | |
107 | IMXDMA_DESC_MEMCPY, | |
108 | IMXDMA_DESC_INTERLEAVED, | |
109 | IMXDMA_DESC_SLAVE_SG, | |
110 | IMXDMA_DESC_CYCLIC, | |
111 | }; | |
112 | ||
f606ab89 JM |
113 | struct imx_dma_2d_config { |
114 | u16 xsr; | |
115 | u16 ysr; | |
116 | u16 wsr; | |
117 | int count; | |
118 | }; | |
119 | ||
9e15db7c JM |
120 | struct imxdma_desc { |
121 | struct list_head node; | |
122 | struct dma_async_tx_descriptor desc; | |
123 | enum dma_status status; | |
124 | dma_addr_t src; | |
125 | dma_addr_t dest; | |
126 | size_t len; | |
2efc3449 | 127 | enum dma_transfer_direction direction; |
9e15db7c JM |
128 | enum imxdma_prep_type type; |
129 | /* For memcpy and interleaved */ | |
130 | unsigned int config_port; | |
131 | unsigned int config_mem; | |
132 | /* For interleaved transfers */ | |
133 | unsigned int x; | |
134 | unsigned int y; | |
135 | unsigned int w; | |
136 | /* For slave sg and cyclic */ | |
137 | struct scatterlist *sg; | |
138 | unsigned int sgcount; | |
139 | }; | |
140 | ||
1f1846c6 | 141 | struct imxdma_channel { |
2d9c2fc5 JM |
142 | int hw_chaining; |
143 | struct timer_list watchdog; | |
1f1846c6 SH |
144 | struct imxdma_engine *imxdma; |
145 | unsigned int channel; | |
1f1846c6 | 146 | |
9e15db7c JM |
147 | struct tasklet_struct dma_tasklet; |
148 | struct list_head ld_free; | |
149 | struct list_head ld_queue; | |
150 | struct list_head ld_active; | |
151 | int descs_allocated; | |
1f1846c6 SH |
152 | enum dma_slave_buswidth word_size; |
153 | dma_addr_t per_address; | |
154 | u32 watermark_level; | |
155 | struct dma_chan chan; | |
1f1846c6 | 156 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
157 | enum dma_status status; |
158 | int dma_request; | |
159 | struct scatterlist *sg_list; | |
359291a1 JM |
160 | u32 ccr_from_device; |
161 | u32 ccr_to_device; | |
f606ab89 JM |
162 | bool enabled_2d; |
163 | int slot_2d; | |
ea62aa80 | 164 | unsigned int irq; |
1f1846c6 SH |
165 | }; |
166 | ||
e51d0f0a SG |
167 | enum imx_dma_type { |
168 | IMX1_DMA, | |
169 | IMX21_DMA, | |
170 | IMX27_DMA, | |
171 | }; | |
172 | ||
1f1846c6 SH |
173 | struct imxdma_engine { |
174 | struct device *dev; | |
1e070a60 | 175 | struct device_dma_parameters dma_parms; |
1f1846c6 | 176 | struct dma_device dma_device; |
cd5cf9da | 177 | void __iomem *base; |
a2367db2 FE |
178 | struct clk *dma_ahb; |
179 | struct clk *dma_ipg; | |
f606ab89 JM |
180 | spinlock_t lock; |
181 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 182 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 183 | enum imx_dma_type devtype; |
ea62aa80 VK |
184 | unsigned int irq; |
185 | unsigned int irq_err; | |
186 | ||
1f1846c6 SH |
187 | }; |
188 | ||
290ad0f9 MP |
189 | struct imxdma_filter_data { |
190 | struct imxdma_engine *imxdma; | |
191 | int request; | |
192 | }; | |
193 | ||
afe7cded | 194 | static const struct platform_device_id imx_dma_devtype[] = { |
e51d0f0a SG |
195 | { |
196 | .name = "imx1-dma", | |
197 | .driver_data = IMX1_DMA, | |
198 | }, { | |
199 | .name = "imx21-dma", | |
200 | .driver_data = IMX21_DMA, | |
201 | }, { | |
202 | .name = "imx27-dma", | |
203 | .driver_data = IMX27_DMA, | |
204 | }, { | |
205 | /* sentinel */ | |
206 | } | |
207 | }; | |
208 | MODULE_DEVICE_TABLE(platform, imx_dma_devtype); | |
209 | ||
290ad0f9 MP |
210 | static const struct of_device_id imx_dma_of_dev_id[] = { |
211 | { | |
212 | .compatible = "fsl,imx1-dma", | |
213 | .data = &imx_dma_devtype[IMX1_DMA], | |
214 | }, { | |
215 | .compatible = "fsl,imx21-dma", | |
216 | .data = &imx_dma_devtype[IMX21_DMA], | |
217 | }, { | |
218 | .compatible = "fsl,imx27-dma", | |
219 | .data = &imx_dma_devtype[IMX27_DMA], | |
220 | }, { | |
221 | /* sentinel */ | |
222 | } | |
223 | }; | |
224 | MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); | |
225 | ||
e51d0f0a SG |
226 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) |
227 | { | |
228 | return imxdma->devtype == IMX1_DMA; | |
229 | } | |
230 | ||
e51d0f0a SG |
231 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) |
232 | { | |
233 | return imxdma->devtype == IMX27_DMA; | |
234 | } | |
235 | ||
1f1846c6 SH |
236 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
237 | { | |
238 | return container_of(chan, struct imxdma_channel, chan); | |
239 | } | |
240 | ||
9e15db7c | 241 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 242 | { |
9e15db7c JM |
243 | struct imxdma_desc *desc; |
244 | ||
245 | if (!list_empty(&imxdmac->ld_active)) { | |
246 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
247 | node); | |
248 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
249 | return true; | |
250 | } | |
251 | return false; | |
1f1846c6 SH |
252 | } |
253 | ||
6bd08127 | 254 | |
cd5cf9da JM |
255 | |
256 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
257 | unsigned offset) | |
6bd08127 | 258 | { |
cd5cf9da | 259 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
260 | } |
261 | ||
cd5cf9da | 262 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 263 | { |
cd5cf9da | 264 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 265 | } |
1f1846c6 | 266 | |
2d9c2fc5 | 267 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 268 | { |
e51d0f0a SG |
269 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
270 | ||
271 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 272 | return imxdmac->hw_chaining; |
6bd08127 JM |
273 | else |
274 | return 0; | |
275 | } | |
276 | ||
277 | /* | |
278 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
279 | */ | |
a6cbb2d8 | 280 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 281 | { |
2efc3449 | 282 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 283 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 284 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
285 | unsigned long now; |
286 | ||
fdaf9c4b | 287 | now = min(d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
288 | if (d->len != IMX_DMA_LENGTH_LOOP) |
289 | d->len -= now; | |
6bd08127 | 290 | |
2efc3449 | 291 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
292 | imx_dmav1_writel(imxdma, sg->dma_address, |
293 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 294 | else |
cd5cf9da JM |
295 | imx_dmav1_writel(imxdma, sg->dma_address, |
296 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 297 | |
cd5cf9da | 298 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 299 | |
f9b283a6 JM |
300 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
301 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
302 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
303 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
304 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
6bd08127 JM |
305 | |
306 | return now; | |
1f1846c6 SH |
307 | } |
308 | ||
2efc3449 | 309 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 310 | { |
2efc3449 | 311 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 312 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
313 | int channel = imxdmac->channel; |
314 | unsigned long flags; | |
315 | ||
f9b283a6 | 316 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 317 | |
6bd08127 JM |
318 | local_irq_save(flags); |
319 | ||
cd5cf9da JM |
320 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
321 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
322 | ~(1 << channel), DMA_DIMR); | |
323 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
324 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 325 | |
e51d0f0a | 326 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 327 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
328 | d->sg = sg_next(d->sg); |
329 | if (d->sg) { | |
6bd08127 | 330 | u32 tmp; |
a6cbb2d8 | 331 | imxdma_sg_next(d); |
cd5cf9da JM |
332 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
333 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
334 | DMA_CCR(channel)); | |
6bd08127 JM |
335 | } |
336 | } | |
6bd08127 JM |
337 | |
338 | local_irq_restore(flags); | |
339 | } | |
340 | ||
341 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
342 | { | |
cd5cf9da | 343 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
344 | int channel = imxdmac->channel; |
345 | unsigned long flags; | |
346 | ||
f9b283a6 | 347 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 348 | |
2d9c2fc5 JM |
349 | if (imxdma_hw_chain(imxdmac)) |
350 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
351 | |
352 | local_irq_save(flags); | |
cd5cf9da JM |
353 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
354 | (1 << channel), DMA_DIMR); | |
355 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
356 | ~CCR_CEN, DMA_CCR(channel)); | |
357 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
358 | local_irq_restore(flags); |
359 | } | |
360 | ||
bcdc4bd3 | 361 | static void imxdma_watchdog(struct timer_list *t) |
1f1846c6 | 362 | { |
bcdc4bd3 | 363 | struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog); |
cd5cf9da | 364 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 365 | int channel = imxdmac->channel; |
1f1846c6 | 366 | |
cd5cf9da | 367 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 368 | |
6bd08127 | 369 | /* Tasklet watchdog error handler */ |
9e15db7c | 370 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
371 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
372 | imxdmac->channel); | |
1f1846c6 SH |
373 | } |
374 | ||
6bd08127 | 375 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 376 | { |
6bd08127 | 377 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
378 | unsigned int err_mask; |
379 | int i, disr; | |
380 | int errcode; | |
381 | ||
cd5cf9da | 382 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 383 | |
cd5cf9da JM |
384 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
385 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
386 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
387 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
388 | |
389 | if (!err_mask) | |
390 | return IRQ_HANDLED; | |
391 | ||
cd5cf9da | 392 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
393 | |
394 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
395 | if (!(err_mask & (1 << i))) | |
396 | continue; | |
6bd08127 JM |
397 | errcode = 0; |
398 | ||
cd5cf9da JM |
399 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
400 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
401 | errcode |= IMX_DMA_ERR_BURST; |
402 | } | |
cd5cf9da JM |
403 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
404 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
405 | errcode |= IMX_DMA_ERR_REQUEST; |
406 | } | |
cd5cf9da JM |
407 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
408 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
409 | errcode |= IMX_DMA_ERR_TRANSFER; |
410 | } | |
cd5cf9da JM |
411 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
412 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
413 | errcode |= IMX_DMA_ERR_BUFFER; |
414 | } | |
415 | /* Tasklet error handler */ | |
416 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
417 | ||
1d94fe06 AS |
418 | dev_warn(imxdma->dev, |
419 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
420 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
421 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
422 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
423 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
6bd08127 JM |
424 | } |
425 | return IRQ_HANDLED; | |
1f1846c6 SH |
426 | } |
427 | ||
6bd08127 | 428 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 429 | { |
cd5cf9da | 430 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 431 | int chno = imxdmac->channel; |
2efc3449 | 432 | struct imxdma_desc *desc; |
5a276fa6 | 433 | unsigned long flags; |
6bd08127 | 434 | |
5a276fa6 | 435 | spin_lock_irqsave(&imxdma->lock, flags); |
833bc03b | 436 | if (list_empty(&imxdmac->ld_active)) { |
5a276fa6 | 437 | spin_unlock_irqrestore(&imxdma->lock, flags); |
833bc03b JM |
438 | goto out; |
439 | } | |
2efc3449 | 440 | |
833bc03b JM |
441 | desc = list_first_entry(&imxdmac->ld_active, |
442 | struct imxdma_desc, | |
443 | node); | |
5a276fa6 | 444 | spin_unlock_irqrestore(&imxdma->lock, flags); |
2efc3449 | 445 | |
833bc03b JM |
446 | if (desc->sg) { |
447 | u32 tmp; | |
448 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 449 | |
833bc03b | 450 | if (desc->sg) { |
a6cbb2d8 | 451 | imxdma_sg_next(desc); |
6bd08127 | 452 | |
cd5cf9da | 453 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 454 | |
2d9c2fc5 | 455 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
456 | /* FIXME: The timeout should probably be |
457 | * configurable | |
458 | */ | |
2d9c2fc5 | 459 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
460 | jiffies + msecs_to_jiffies(500)); |
461 | ||
462 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 463 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 464 | } else { |
cd5cf9da JM |
465 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
466 | DMA_CCR(chno)); | |
6bd08127 JM |
467 | tmp |= CCR_CEN; |
468 | } | |
469 | ||
cd5cf9da | 470 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
471 | |
472 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
473 | /* Tasklet progression */ | |
474 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 475 | |
6bd08127 JM |
476 | return; |
477 | } | |
478 | ||
2d9c2fc5 JM |
479 | if (imxdma_hw_chain(imxdmac)) { |
480 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
481 | return; |
482 | } | |
483 | } | |
484 | ||
2efc3449 | 485 | out: |
cd5cf9da | 486 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 487 | /* Tasklet irq */ |
9e15db7c JM |
488 | tasklet_schedule(&imxdmac->dma_tasklet); |
489 | } | |
490 | ||
6bd08127 JM |
491 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
492 | { | |
493 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
494 | int i, disr; |
495 | ||
e51d0f0a | 496 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
497 | imxdma_err_handler(irq, dev_id); |
498 | ||
cd5cf9da | 499 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 500 | |
f9b283a6 | 501 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 502 | |
cd5cf9da | 503 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 504 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 505 | if (disr & (1 << i)) |
6bd08127 | 506 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
507 | } |
508 | ||
509 | return IRQ_HANDLED; | |
510 | } | |
511 | ||
9e15db7c JM |
512 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
513 | { | |
514 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 515 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
516 | int slot = -1; |
517 | int i; | |
9e15db7c JM |
518 | |
519 | /* Configure and enable */ | |
520 | switch (d->type) { | |
f606ab89 JM |
521 | case IMXDMA_DESC_INTERLEAVED: |
522 | /* Try to get a free 2D slot */ | |
f606ab89 JM |
523 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { |
524 | if ((imxdma->slots_2d[i].count > 0) && | |
525 | ((imxdma->slots_2d[i].xsr != d->x) || | |
526 | (imxdma->slots_2d[i].ysr != d->y) || | |
527 | (imxdma->slots_2d[i].wsr != d->w))) | |
528 | continue; | |
529 | slot = i; | |
530 | break; | |
531 | } | |
5a276fa6 | 532 | if (slot < 0) |
f606ab89 JM |
533 | return -EBUSY; |
534 | ||
535 | imxdma->slots_2d[slot].xsr = d->x; | |
536 | imxdma->slots_2d[slot].ysr = d->y; | |
537 | imxdma->slots_2d[slot].wsr = d->w; | |
538 | imxdma->slots_2d[slot].count++; | |
539 | ||
540 | imxdmac->slot_2d = slot; | |
541 | imxdmac->enabled_2d = true; | |
f606ab89 JM |
542 | |
543 | if (slot == IMX_DMA_2D_SLOT_A) { | |
544 | d->config_mem &= ~CCR_MSEL_B; | |
545 | d->config_port &= ~CCR_MSEL_B; | |
546 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
547 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
548 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
549 | } else { | |
550 | d->config_mem |= CCR_MSEL_B; | |
551 | d->config_port |= CCR_MSEL_B; | |
552 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
553 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
554 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
555 | } | |
556 | /* | |
557 | * We fall-through here intentionally, since a 2D transfer is | |
558 | * similar to MEMCPY just adding the 2D slot configuration. | |
559 | */ | |
9e15db7c | 560 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
561 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
562 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
563 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 564 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 565 | |
cd5cf9da | 566 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc | 567 | |
ac806a1c RK |
568 | dev_dbg(imxdma->dev, |
569 | "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n", | |
570 | __func__, imxdmac->channel, | |
571 | (unsigned long long)d->dest, | |
572 | (unsigned long long)d->src, d->len); | |
3b4b6dfc JM |
573 | |
574 | break; | |
6bd08127 | 575 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 576 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 577 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 578 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 579 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 580 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 581 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
582 | DMA_CCR(imxdmac->channel)); |
583 | ||
ac806a1c RK |
584 | dev_dbg(imxdma->dev, |
585 | "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n", | |
586 | __func__, imxdmac->channel, | |
587 | d->sg, d->sgcount, d->len, | |
588 | (unsigned long long)imxdmac->per_address); | |
359291a1 | 589 | } else if (d->direction == DMA_MEM_TO_DEV) { |
cd5cf9da | 590 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 591 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 592 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
593 | DMA_CCR(imxdmac->channel)); |
594 | ||
ac806a1c RK |
595 | dev_dbg(imxdma->dev, |
596 | "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n", | |
597 | __func__, imxdmac->channel, | |
598 | d->sg, d->sgcount, d->len, | |
599 | (unsigned long long)imxdmac->per_address); | |
359291a1 JM |
600 | } else { |
601 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
602 | __func__, imxdmac->channel); | |
603 | return -EINVAL; | |
604 | } | |
605 | ||
a6cbb2d8 | 606 | imxdma_sg_next(d); |
1f1846c6 | 607 | |
9e15db7c JM |
608 | break; |
609 | default: | |
610 | return -EINVAL; | |
611 | } | |
2efc3449 | 612 | imxdma_enable_hw(d); |
9e15db7c | 613 | return 0; |
1f1846c6 SH |
614 | } |
615 | ||
9e15db7c | 616 | static void imxdma_tasklet(unsigned long data) |
1f1846c6 | 617 | { |
9e15db7c JM |
618 | struct imxdma_channel *imxdmac = (void *)data; |
619 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
620 | struct imxdma_desc *desc; | |
5a276fa6 | 621 | unsigned long flags; |
1f1846c6 | 622 | |
5a276fa6 | 623 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
624 | |
625 | if (list_empty(&imxdmac->ld_active)) { | |
626 | /* Someone might have called terminate all */ | |
fcaaba6c MG |
627 | spin_unlock_irqrestore(&imxdma->lock, flags); |
628 | return; | |
9e15db7c JM |
629 | } |
630 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
631 | ||
d73111c6 MI |
632 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
633 | * and dont mark the descriptor as complete. | |
60f2951e VK |
634 | * Only in non-cyclic cases it would be marked as complete |
635 | */ | |
9e15db7c JM |
636 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
637 | goto out; | |
60f2951e VK |
638 | else |
639 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 640 | |
f606ab89 JM |
641 | /* Free 2D slot if it was an interleaved transfer */ |
642 | if (imxdmac->enabled_2d) { | |
643 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
644 | imxdmac->enabled_2d = false; | |
645 | } | |
646 | ||
9e15db7c JM |
647 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
648 | ||
649 | if (!list_empty(&imxdmac->ld_queue)) { | |
650 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
651 | node); | |
652 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
653 | if (imxdma_xfer_desc(desc) < 0) | |
654 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
655 | __func__, imxdmac->channel); | |
656 | } | |
657 | out: | |
5a276fa6 | 658 | spin_unlock_irqrestore(&imxdma->lock, flags); |
fcaaba6c | 659 | |
be5af285 | 660 | dmaengine_desc_get_callback_invoke(&desc->desc, NULL); |
1f1846c6 SH |
661 | } |
662 | ||
502c2ef2 | 663 | static int imxdma_terminate_all(struct dma_chan *chan) |
1f1846c6 SH |
664 | { |
665 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
cd5cf9da | 666 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 667 | unsigned long flags; |
9e15db7c | 668 | |
502c2ef2 | 669 | imxdma_disable_hw(imxdmac); |
1f1846c6 | 670 | |
502c2ef2 MR |
671 | spin_lock_irqsave(&imxdma->lock, flags); |
672 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
673 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
674 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
675 | return 0; | |
676 | } | |
bef2a8d3 | 677 | |
502c2ef2 MR |
678 | static int imxdma_config(struct dma_chan *chan, |
679 | struct dma_slave_config *dmaengine_cfg) | |
680 | { | |
681 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
682 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
683 | unsigned int mode = 0; | |
bdc0c753 | 684 | |
502c2ef2 MR |
685 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
686 | imxdmac->per_address = dmaengine_cfg->src_addr; | |
687 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
688 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
689 | } else { | |
690 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
691 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
692 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
693 | } | |
1f1846c6 | 694 | |
502c2ef2 MR |
695 | switch (imxdmac->word_size) { |
696 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
697 | mode = IMX_DMA_MEMSIZE_8; | |
698 | break; | |
699 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
700 | mode = IMX_DMA_MEMSIZE_16; | |
701 | break; | |
1f1846c6 | 702 | default: |
502c2ef2 MR |
703 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
704 | mode = IMX_DMA_MEMSIZE_32; | |
705 | break; | |
1f1846c6 SH |
706 | } |
707 | ||
502c2ef2 MR |
708 | imxdmac->hw_chaining = 0; |
709 | ||
710 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | | |
711 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | | |
712 | CCR_REN; | |
713 | imxdmac->ccr_to_device = | |
714 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | | |
715 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
716 | imx_dmav1_writel(imxdma, imxdmac->dma_request, | |
717 | DMA_RSSR(imxdmac->channel)); | |
718 | ||
719 | /* Set burst length */ | |
720 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * | |
721 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
722 | ||
723 | return 0; | |
1f1846c6 SH |
724 | } |
725 | ||
726 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
727 | dma_cookie_t cookie, | |
728 | struct dma_tx_state *txstate) | |
729 | { | |
96a2af41 | 730 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
731 | } |
732 | ||
733 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
734 | { | |
735 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 736 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 737 | dma_cookie_t cookie; |
9e15db7c | 738 | unsigned long flags; |
1f1846c6 | 739 | |
f606ab89 | 740 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 741 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 742 | cookie = dma_cookie_assign(tx); |
f606ab89 | 743 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
744 | |
745 | return cookie; | |
746 | } | |
747 | ||
748 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
749 | { | |
750 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
751 | struct imx_dma_data *data = chan->private; | |
752 | ||
6c05f091 JM |
753 | if (data != NULL) |
754 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 755 | |
9e15db7c JM |
756 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
757 | struct imxdma_desc *desc; | |
1f1846c6 | 758 | |
9e15db7c JM |
759 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
760 | if (!desc) | |
761 | break; | |
ff5fdafc | 762 | memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor)); |
9e15db7c JM |
763 | dma_async_tx_descriptor_init(&desc->desc, chan); |
764 | desc->desc.tx_submit = imxdma_tx_submit; | |
765 | /* txd.flags will be overwritten in prep funcs */ | |
766 | desc->desc.flags = DMA_CTRL_ACK; | |
3ded1ad1 | 767 | desc->status = DMA_COMPLETE; |
9e15db7c JM |
768 | |
769 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
770 | imxdmac->descs_allocated++; | |
771 | } | |
1f1846c6 | 772 | |
9e15db7c JM |
773 | if (!imxdmac->descs_allocated) |
774 | return -ENOMEM; | |
775 | ||
776 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
777 | } |
778 | ||
779 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
780 | { | |
781 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 782 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
783 | struct imxdma_desc *desc, *_desc; |
784 | unsigned long flags; | |
785 | ||
f606ab89 | 786 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 787 | |
6bd08127 | 788 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
789 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
790 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 791 | |
f606ab89 | 792 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
793 | |
794 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
795 | kfree(desc); | |
796 | imxdmac->descs_allocated--; | |
797 | } | |
798 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 | 799 | |
06f8db4b SK |
800 | kfree(imxdmac->sg_list); |
801 | imxdmac->sg_list = NULL; | |
1f1846c6 SH |
802 | } |
803 | ||
804 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
805 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 806 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 807 | unsigned long flags, void *context) |
1f1846c6 SH |
808 | { |
809 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
810 | struct scatterlist *sg; | |
9e15db7c JM |
811 | int i, dma_length = 0; |
812 | struct imxdma_desc *desc; | |
1f1846c6 | 813 | |
9e15db7c JM |
814 | if (list_empty(&imxdmac->ld_free) || |
815 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
816 | return NULL; |
817 | ||
9e15db7c | 818 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
819 | |
820 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 821 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
822 | } |
823 | ||
d07102a1 SH |
824 | switch (imxdmac->word_size) { |
825 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 826 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
827 | return NULL; |
828 | break; | |
829 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 830 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
831 | return NULL; |
832 | break; | |
833 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
834 | break; | |
835 | default: | |
836 | return NULL; | |
837 | } | |
838 | ||
9e15db7c JM |
839 | desc->type = IMXDMA_DESC_SLAVE_SG; |
840 | desc->sg = sgl; | |
841 | desc->sgcount = sg_len; | |
842 | desc->len = dma_length; | |
2efc3449 | 843 | desc->direction = direction; |
9e15db7c | 844 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
845 | desc->src = imxdmac->per_address; |
846 | } else { | |
9e15db7c JM |
847 | desc->dest = imxdmac->per_address; |
848 | } | |
849 | desc->desc.callback = NULL; | |
850 | desc->desc.callback_param = NULL; | |
1f1846c6 | 851 | |
9e15db7c | 852 | return &desc->desc; |
1f1846c6 SH |
853 | } |
854 | ||
855 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
856 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 857 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 858 | unsigned long flags) |
1f1846c6 SH |
859 | { |
860 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
861 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
862 | struct imxdma_desc *desc; |
863 | int i; | |
1f1846c6 | 864 | unsigned int periods = buf_len / period_len; |
1f1846c6 | 865 | |
ac806a1c | 866 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n", |
1f1846c6 SH |
867 | __func__, imxdmac->channel, buf_len, period_len); |
868 | ||
9e15db7c JM |
869 | if (list_empty(&imxdmac->ld_free) || |
870 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 871 | return NULL; |
1f1846c6 | 872 | |
9e15db7c | 873 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 | 874 | |
96a3713e | 875 | kfree(imxdmac->sg_list); |
1f1846c6 SH |
876 | |
877 | imxdmac->sg_list = kcalloc(periods + 1, | |
edc530fe | 878 | sizeof(struct scatterlist), GFP_ATOMIC); |
1f1846c6 SH |
879 | if (!imxdmac->sg_list) |
880 | return NULL; | |
881 | ||
882 | sg_init_table(imxdmac->sg_list, periods); | |
883 | ||
884 | for (i = 0; i < periods; i++) { | |
ce818013 | 885 | sg_assign_page(&imxdmac->sg_list[i], NULL); |
1f1846c6 SH |
886 | imxdmac->sg_list[i].offset = 0; |
887 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 888 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
889 | dma_addr += period_len; |
890 | } | |
891 | ||
892 | /* close the loop */ | |
ce818013 | 893 | sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list); |
1f1846c6 | 894 | |
9e15db7c JM |
895 | desc->type = IMXDMA_DESC_CYCLIC; |
896 | desc->sg = imxdmac->sg_list; | |
897 | desc->sgcount = periods; | |
898 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 899 | desc->direction = direction; |
9e15db7c | 900 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
901 | desc->src = imxdmac->per_address; |
902 | } else { | |
9e15db7c JM |
903 | desc->dest = imxdmac->per_address; |
904 | } | |
905 | desc->desc.callback = NULL; | |
906 | desc->desc.callback_param = NULL; | |
1f1846c6 | 907 | |
9e15db7c | 908 | return &desc->desc; |
1f1846c6 SH |
909 | } |
910 | ||
6c05f091 JM |
911 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
912 | struct dma_chan *chan, dma_addr_t dest, | |
913 | dma_addr_t src, size_t len, unsigned long flags) | |
914 | { | |
915 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
916 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 917 | struct imxdma_desc *desc; |
1f1846c6 | 918 | |
ac806a1c RK |
919 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n", |
920 | __func__, imxdmac->channel, (unsigned long long)src, | |
921 | (unsigned long long)dest, len); | |
6c05f091 | 922 | |
9e15db7c JM |
923 | if (list_empty(&imxdmac->ld_free) || |
924 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
925 | return NULL; |
926 | ||
9e15db7c | 927 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 928 | |
9e15db7c JM |
929 | desc->type = IMXDMA_DESC_MEMCPY; |
930 | desc->src = src; | |
931 | desc->dest = dest; | |
932 | desc->len = len; | |
2efc3449 | 933 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
934 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
935 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
936 | desc->desc.callback = NULL; | |
937 | desc->desc.callback_param = NULL; | |
6c05f091 | 938 | |
9e15db7c | 939 | return &desc->desc; |
6c05f091 JM |
940 | } |
941 | ||
f606ab89 JM |
942 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
943 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
944 | unsigned long flags) | |
945 | { | |
946 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
947 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
948 | struct imxdma_desc *desc; | |
949 | ||
ac806a1c RK |
950 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n" |
951 | " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__, | |
952 | imxdmac->channel, (unsigned long long)xt->src_start, | |
953 | (unsigned long long) xt->dst_start, | |
f606ab89 JM |
954 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", |
955 | xt->numf, xt->frame_size); | |
956 | ||
957 | if (list_empty(&imxdmac->ld_free) || | |
958 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
959 | return NULL; | |
960 | ||
961 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
962 | return NULL; | |
963 | ||
964 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
965 | ||
966 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
967 | desc->src = xt->src_start; | |
968 | desc->dest = xt->dst_start; | |
969 | desc->x = xt->sgl[0].size; | |
970 | desc->y = xt->numf; | |
971 | desc->w = xt->sgl[0].icg + desc->x; | |
972 | desc->len = desc->x * desc->y; | |
973 | desc->direction = DMA_MEM_TO_MEM; | |
974 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
975 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
976 | if (xt->src_sgl) | |
977 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
978 | if (xt->dst_sgl) | |
979 | desc->config_port |= IMX_DMA_TYPE_2D; | |
980 | desc->desc.callback = NULL; | |
981 | desc->desc.callback_param = NULL; | |
982 | ||
983 | return &desc->desc; | |
1f1846c6 SH |
984 | } |
985 | ||
986 | static void imxdma_issue_pending(struct dma_chan *chan) | |
987 | { | |
5b316876 | 988 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
989 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
990 | struct imxdma_desc *desc; | |
991 | unsigned long flags; | |
992 | ||
f606ab89 | 993 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
994 | if (list_empty(&imxdmac->ld_active) && |
995 | !list_empty(&imxdmac->ld_queue)) { | |
996 | desc = list_first_entry(&imxdmac->ld_queue, | |
997 | struct imxdma_desc, node); | |
998 | ||
999 | if (imxdma_xfer_desc(desc) < 0) { | |
1000 | dev_warn(imxdma->dev, | |
1001 | "%s: channel: %d couldn't issue DMA xfer\n", | |
1002 | __func__, imxdmac->channel); | |
1003 | } else { | |
1004 | list_move_tail(imxdmac->ld_queue.next, | |
1005 | &imxdmac->ld_active); | |
1006 | } | |
1007 | } | |
f606ab89 | 1008 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
1009 | } |
1010 | ||
290ad0f9 MP |
1011 | static bool imxdma_filter_fn(struct dma_chan *chan, void *param) |
1012 | { | |
1013 | struct imxdma_filter_data *fdata = param; | |
1014 | struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); | |
1015 | ||
1016 | if (chan->device->dev != fdata->imxdma->dev) | |
1017 | return false; | |
1018 | ||
1019 | imxdma_chan->dma_request = fdata->request; | |
1020 | chan->private = NULL; | |
1021 | ||
1022 | return true; | |
1023 | } | |
1024 | ||
1025 | static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, | |
1026 | struct of_dma *ofdma) | |
1027 | { | |
1028 | int count = dma_spec->args_count; | |
1029 | struct imxdma_engine *imxdma = ofdma->of_dma_data; | |
1030 | struct imxdma_filter_data fdata = { | |
1031 | .imxdma = imxdma, | |
1032 | }; | |
1033 | ||
1034 | if (count != 1) | |
1035 | return NULL; | |
1036 | ||
1037 | fdata.request = dma_spec->args[0]; | |
1038 | ||
1039 | return dma_request_channel(imxdma->dma_device.cap_mask, | |
1040 | imxdma_filter_fn, &fdata); | |
1041 | } | |
1042 | ||
1f1846c6 | 1043 | static int __init imxdma_probe(struct platform_device *pdev) |
71c6b663 | 1044 | { |
1f1846c6 | 1045 | struct imxdma_engine *imxdma; |
73930eb3 | 1046 | struct resource *res; |
290ad0f9 | 1047 | const struct of_device_id *of_id; |
1f1846c6 | 1048 | int ret, i; |
73930eb3 | 1049 | int irq, irq_err; |
cd5cf9da | 1050 | |
290ad0f9 MP |
1051 | of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev); |
1052 | if (of_id) | |
1053 | pdev->id_entry = of_id->data; | |
1054 | ||
04bbd8ef | 1055 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1056 | if (!imxdma) |
1057 | return -ENOMEM; | |
1058 | ||
5c6b3e77 | 1059 | imxdma->dev = &pdev->dev; |
e51d0f0a SG |
1060 | imxdma->devtype = pdev->id_entry->driver_data; |
1061 | ||
73930eb3 | 1062 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1063 | imxdma->base = devm_ioremap_resource(&pdev->dev, res); |
1064 | if (IS_ERR(imxdma->base)) | |
1065 | return PTR_ERR(imxdma->base); | |
73930eb3 SG |
1066 | |
1067 | irq = platform_get_irq(pdev, 0); | |
1068 | if (irq < 0) | |
1069 | return irq; | |
6bd08127 | 1070 | |
a2367db2 | 1071 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1072 | if (IS_ERR(imxdma->dma_ipg)) |
1073 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1074 | |
1075 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1076 | if (IS_ERR(imxdma->dma_ahb)) |
1077 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 | 1078 | |
fce9a74b FE |
1079 | ret = clk_prepare_enable(imxdma->dma_ipg); |
1080 | if (ret) | |
1081 | return ret; | |
1082 | ret = clk_prepare_enable(imxdma->dma_ahb); | |
1083 | if (ret) | |
1084 | goto disable_dma_ipg_clk; | |
6bd08127 JM |
1085 | |
1086 | /* reset DMA module */ | |
cd5cf9da | 1087 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1088 | |
e51d0f0a | 1089 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1090 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1091 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1092 | if (ret) { |
f9b283a6 | 1093 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
fce9a74b | 1094 | goto disable_dma_ahb_clk; |
6bd08127 | 1095 | } |
ea62aa80 | 1096 | imxdma->irq = irq; |
6bd08127 | 1097 | |
73930eb3 SG |
1098 | irq_err = platform_get_irq(pdev, 1); |
1099 | if (irq_err < 0) { | |
1100 | ret = irq_err; | |
fce9a74b | 1101 | goto disable_dma_ahb_clk; |
73930eb3 SG |
1102 | } |
1103 | ||
1104 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1105 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1106 | if (ret) { |
f9b283a6 | 1107 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
fce9a74b | 1108 | goto disable_dma_ahb_clk; |
6bd08127 | 1109 | } |
ea62aa80 | 1110 | imxdma->irq_err = irq_err; |
6bd08127 JM |
1111 | } |
1112 | ||
1113 | /* enable DMA module */ | |
cd5cf9da | 1114 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1115 | |
1116 | /* clear all interrupts */ | |
cd5cf9da | 1117 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1118 | |
1119 | /* disable interrupts */ | |
cd5cf9da | 1120 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1121 | |
1122 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1123 | ||
f8a356ff SH |
1124 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1125 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1126 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1127 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1128 | ||
1129 | /* Initialize 2D global parameters */ | |
1130 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1131 | imxdma->slots_2d[i].count = 0; | |
1132 | ||
1133 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1134 | |
1f1846c6 | 1135 | /* Initialize channel parameters */ |
6bd08127 | 1136 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1137 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1138 | ||
e51d0f0a | 1139 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1140 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1141 | dma_irq_handler, 0, "DMA", imxdma); |
1142 | if (ret) { | |
f9b283a6 JM |
1143 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1144 | "for DMA channel %d\n", | |
73930eb3 | 1145 | irq + i, i); |
fce9a74b | 1146 | goto disable_dma_ahb_clk; |
6bd08127 | 1147 | } |
ea62aa80 VK |
1148 | |
1149 | imxdmac->irq = irq + i; | |
bcdc4bd3 | 1150 | timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0); |
8267f16e | 1151 | } |
1f1846c6 | 1152 | |
1f1846c6 | 1153 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1154 | |
9e15db7c JM |
1155 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1156 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1157 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1158 | ||
1159 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
1160 | (unsigned long)imxdmac); | |
1f1846c6 | 1161 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1162 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1163 | imxdmac->channel = i; |
1164 | ||
1165 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1166 | list_add_tail(&imxdmac->chan.device_node, |
1167 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1168 | } |
1169 | ||
1f1846c6 SH |
1170 | imxdma->dma_device.dev = &pdev->dev; |
1171 | ||
1172 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1173 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1174 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1175 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1176 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1177 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1178 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
502c2ef2 MR |
1179 | imxdma->dma_device.device_config = imxdma_config; |
1180 | imxdma->dma_device.device_terminate_all = imxdma_terminate_all; | |
1f1846c6 SH |
1181 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; |
1182 | ||
1183 | platform_set_drvdata(pdev, imxdma); | |
1184 | ||
77a68e56 | 1185 | imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES; |
1e070a60 SH |
1186 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
1187 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
1188 | ||
1f1846c6 SH |
1189 | ret = dma_async_device_register(&imxdma->dma_device); |
1190 | if (ret) { | |
1191 | dev_err(&pdev->dev, "unable to register\n"); | |
fce9a74b | 1192 | goto disable_dma_ahb_clk; |
1f1846c6 SH |
1193 | } |
1194 | ||
290ad0f9 MP |
1195 | if (pdev->dev.of_node) { |
1196 | ret = of_dma_controller_register(pdev->dev.of_node, | |
1197 | imxdma_xlate, imxdma); | |
1198 | if (ret) { | |
1199 | dev_err(&pdev->dev, "unable to register of_dma_controller\n"); | |
1200 | goto err_of_dma_controller; | |
1201 | } | |
1202 | } | |
1203 | ||
1f1846c6 SH |
1204 | return 0; |
1205 | ||
290ad0f9 MP |
1206 | err_of_dma_controller: |
1207 | dma_async_device_unregister(&imxdma->dma_device); | |
fce9a74b | 1208 | disable_dma_ahb_clk: |
a2367db2 | 1209 | clk_disable_unprepare(imxdma->dma_ahb); |
fce9a74b FE |
1210 | disable_dma_ipg_clk: |
1211 | clk_disable_unprepare(imxdma->dma_ipg); | |
1f1846c6 SH |
1212 | return ret; |
1213 | } | |
1214 | ||
ea62aa80 VK |
1215 | static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma) |
1216 | { | |
1217 | int i; | |
1218 | ||
1219 | if (is_imx1_dma(imxdma)) { | |
1220 | disable_irq(imxdma->irq); | |
1221 | disable_irq(imxdma->irq_err); | |
1222 | } | |
1223 | ||
1224 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
1225 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; | |
1226 | ||
1227 | if (!is_imx1_dma(imxdma)) | |
1228 | disable_irq(imxdmac->irq); | |
1229 | ||
1230 | tasklet_kill(&imxdmac->dma_tasklet); | |
1231 | } | |
1232 | } | |
1233 | ||
1d1bbd30 | 1234 | static int imxdma_remove(struct platform_device *pdev) |
1f1846c6 SH |
1235 | { |
1236 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 | 1237 | |
ea62aa80 VK |
1238 | imxdma_free_irq(pdev, imxdma); |
1239 | ||
1f1846c6 SH |
1240 | dma_async_device_unregister(&imxdma->dma_device); |
1241 | ||
290ad0f9 MP |
1242 | if (pdev->dev.of_node) |
1243 | of_dma_controller_free(pdev->dev.of_node); | |
1244 | ||
a2367db2 FE |
1245 | clk_disable_unprepare(imxdma->dma_ipg); |
1246 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1247 | |
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | static struct platform_driver imxdma_driver = { | |
1252 | .driver = { | |
1253 | .name = "imx-dma", | |
290ad0f9 | 1254 | .of_match_table = imx_dma_of_dev_id, |
1f1846c6 | 1255 | }, |
e51d0f0a | 1256 | .id_table = imx_dma_devtype, |
1d1bbd30 | 1257 | .remove = imxdma_remove, |
1f1846c6 SH |
1258 | }; |
1259 | ||
1260 | static int __init imxdma_module_init(void) | |
1261 | { | |
1262 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1263 | } | |
1264 | subsys_initcall(imxdma_module_init); | |
1265 | ||
1266 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1267 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1268 | MODULE_LICENSE("GPL"); |