Commit | Line | Data |
---|---|---|
1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
7331205a | 17 | #include <linux/err.h> |
1f1846c6 SH |
18 | #include <linux/init.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5c45ad77 | 29 | #include <linux/module.h> |
1f1846c6 SH |
30 | |
31 | #include <asm/irq.h> | |
82906b13 | 32 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 33 | |
d2ebfb33 | 34 | #include "dmaengine.h" |
9e15db7c | 35 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
36 | #define IMX_DMA_CHANNELS 16 |
37 | ||
f606ab89 JM |
38 | #define IMX_DMA_2D_SLOTS 2 |
39 | #define IMX_DMA_2D_SLOT_A 0 | |
40 | #define IMX_DMA_2D_SLOT_B 1 | |
41 | ||
6bd08127 JM |
42 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
43 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
44 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
45 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
46 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
47 | #define IMX_DMA_TYPE_2D (1 << 10) | |
48 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
49 | ||
50 | #define IMX_DMA_ERR_BURST (1 << 0) | |
51 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
52 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
53 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
54 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
55 | ||
56 | #define DMA_DCR 0x00 /* Control Register */ | |
57 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
58 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
59 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
60 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
61 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
62 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
63 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
64 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
65 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
66 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
67 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
68 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
69 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
70 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
71 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
72 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
73 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
74 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
75 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
76 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
77 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
78 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
79 | ||
80 | #define DCR_DRST (1<<1) | |
81 | #define DCR_DEN (1<<0) | |
82 | #define DBTOCR_EN (1<<15) | |
83 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
84 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
85 | #define CCR_ACRPT (1<<14) | |
86 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
87 | #define CCR_DMOD_2D (0x1 << 12) | |
88 | #define CCR_DMOD_FIFO (0x2 << 12) | |
89 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
90 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
91 | #define CCR_SMOD_2D (0x1 << 10) | |
92 | #define CCR_SMOD_FIFO (0x2 << 10) | |
93 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
94 | #define CCR_MDIR_DEC (1<<9) | |
95 | #define CCR_MSEL_B (1<<8) | |
96 | #define CCR_DSIZ_32 (0x0 << 6) | |
97 | #define CCR_DSIZ_8 (0x1 << 6) | |
98 | #define CCR_DSIZ_16 (0x2 << 6) | |
99 | #define CCR_SSIZ_32 (0x0 << 4) | |
100 | #define CCR_SSIZ_8 (0x1 << 4) | |
101 | #define CCR_SSIZ_16 (0x2 << 4) | |
102 | #define CCR_REN (1<<3) | |
103 | #define CCR_RPT (1<<2) | |
104 | #define CCR_FRC (1<<1) | |
105 | #define CCR_CEN (1<<0) | |
106 | #define RTOR_EN (1<<15) | |
107 | #define RTOR_CLK (1<<14) | |
108 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
109 | |
110 | enum imxdma_prep_type { | |
111 | IMXDMA_DESC_MEMCPY, | |
112 | IMXDMA_DESC_INTERLEAVED, | |
113 | IMXDMA_DESC_SLAVE_SG, | |
114 | IMXDMA_DESC_CYCLIC, | |
115 | }; | |
116 | ||
f606ab89 JM |
117 | struct imx_dma_2d_config { |
118 | u16 xsr; | |
119 | u16 ysr; | |
120 | u16 wsr; | |
121 | int count; | |
122 | }; | |
123 | ||
9e15db7c JM |
124 | struct imxdma_desc { |
125 | struct list_head node; | |
126 | struct dma_async_tx_descriptor desc; | |
127 | enum dma_status status; | |
128 | dma_addr_t src; | |
129 | dma_addr_t dest; | |
130 | size_t len; | |
2efc3449 | 131 | enum dma_transfer_direction direction; |
9e15db7c JM |
132 | enum imxdma_prep_type type; |
133 | /* For memcpy and interleaved */ | |
134 | unsigned int config_port; | |
135 | unsigned int config_mem; | |
136 | /* For interleaved transfers */ | |
137 | unsigned int x; | |
138 | unsigned int y; | |
139 | unsigned int w; | |
140 | /* For slave sg and cyclic */ | |
141 | struct scatterlist *sg; | |
142 | unsigned int sgcount; | |
143 | }; | |
144 | ||
1f1846c6 | 145 | struct imxdma_channel { |
2d9c2fc5 JM |
146 | int hw_chaining; |
147 | struct timer_list watchdog; | |
1f1846c6 SH |
148 | struct imxdma_engine *imxdma; |
149 | unsigned int channel; | |
1f1846c6 | 150 | |
9e15db7c JM |
151 | struct tasklet_struct dma_tasklet; |
152 | struct list_head ld_free; | |
153 | struct list_head ld_queue; | |
154 | struct list_head ld_active; | |
155 | int descs_allocated; | |
1f1846c6 SH |
156 | enum dma_slave_buswidth word_size; |
157 | dma_addr_t per_address; | |
158 | u32 watermark_level; | |
159 | struct dma_chan chan; | |
1f1846c6 | 160 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
161 | enum dma_status status; |
162 | int dma_request; | |
163 | struct scatterlist *sg_list; | |
359291a1 JM |
164 | u32 ccr_from_device; |
165 | u32 ccr_to_device; | |
f606ab89 JM |
166 | bool enabled_2d; |
167 | int slot_2d; | |
1f1846c6 SH |
168 | }; |
169 | ||
e51d0f0a SG |
170 | enum imx_dma_type { |
171 | IMX1_DMA, | |
172 | IMX21_DMA, | |
173 | IMX27_DMA, | |
174 | }; | |
175 | ||
1f1846c6 SH |
176 | struct imxdma_engine { |
177 | struct device *dev; | |
1e070a60 | 178 | struct device_dma_parameters dma_parms; |
1f1846c6 | 179 | struct dma_device dma_device; |
cd5cf9da | 180 | void __iomem *base; |
a2367db2 FE |
181 | struct clk *dma_ahb; |
182 | struct clk *dma_ipg; | |
f606ab89 JM |
183 | spinlock_t lock; |
184 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 185 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 186 | enum imx_dma_type devtype; |
1f1846c6 SH |
187 | }; |
188 | ||
e51d0f0a SG |
189 | static struct platform_device_id imx_dma_devtype[] = { |
190 | { | |
191 | .name = "imx1-dma", | |
192 | .driver_data = IMX1_DMA, | |
193 | }, { | |
194 | .name = "imx21-dma", | |
195 | .driver_data = IMX21_DMA, | |
196 | }, { | |
197 | .name = "imx27-dma", | |
198 | .driver_data = IMX27_DMA, | |
199 | }, { | |
200 | /* sentinel */ | |
201 | } | |
202 | }; | |
203 | MODULE_DEVICE_TABLE(platform, imx_dma_devtype); | |
204 | ||
205 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) | |
206 | { | |
207 | return imxdma->devtype == IMX1_DMA; | |
208 | } | |
209 | ||
210 | static inline int is_imx21_dma(struct imxdma_engine *imxdma) | |
211 | { | |
212 | return imxdma->devtype == IMX21_DMA; | |
213 | } | |
214 | ||
215 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) | |
216 | { | |
217 | return imxdma->devtype == IMX27_DMA; | |
218 | } | |
219 | ||
1f1846c6 SH |
220 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
221 | { | |
222 | return container_of(chan, struct imxdma_channel, chan); | |
223 | } | |
224 | ||
9e15db7c | 225 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 226 | { |
9e15db7c JM |
227 | struct imxdma_desc *desc; |
228 | ||
229 | if (!list_empty(&imxdmac->ld_active)) { | |
230 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
231 | node); | |
232 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
233 | return true; | |
234 | } | |
235 | return false; | |
1f1846c6 SH |
236 | } |
237 | ||
6bd08127 | 238 | |
cd5cf9da JM |
239 | |
240 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
241 | unsigned offset) | |
6bd08127 | 242 | { |
cd5cf9da | 243 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
244 | } |
245 | ||
cd5cf9da | 246 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 247 | { |
cd5cf9da | 248 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 249 | } |
1f1846c6 | 250 | |
2d9c2fc5 | 251 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 252 | { |
e51d0f0a SG |
253 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
254 | ||
255 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 256 | return imxdmac->hw_chaining; |
6bd08127 JM |
257 | else |
258 | return 0; | |
259 | } | |
260 | ||
261 | /* | |
262 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
263 | */ | |
a6cbb2d8 | 264 | static inline int imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 265 | { |
2efc3449 | 266 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 267 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 268 | struct scatterlist *sg = d->sg; |
6bd08127 JM |
269 | unsigned long now; |
270 | ||
fdaf9c4b | 271 | now = min(d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
272 | if (d->len != IMX_DMA_LENGTH_LOOP) |
273 | d->len -= now; | |
6bd08127 | 274 | |
2efc3449 | 275 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
276 | imx_dmav1_writel(imxdma, sg->dma_address, |
277 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 278 | else |
cd5cf9da JM |
279 | imx_dmav1_writel(imxdma, sg->dma_address, |
280 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 281 | |
cd5cf9da | 282 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 283 | |
f9b283a6 JM |
284 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
285 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
286 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
287 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
288 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
6bd08127 JM |
289 | |
290 | return now; | |
1f1846c6 SH |
291 | } |
292 | ||
2efc3449 | 293 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 294 | { |
2efc3449 | 295 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 296 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
297 | int channel = imxdmac->channel; |
298 | unsigned long flags; | |
299 | ||
f9b283a6 | 300 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 301 | |
6bd08127 JM |
302 | local_irq_save(flags); |
303 | ||
cd5cf9da JM |
304 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
305 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
306 | ~(1 << channel), DMA_DIMR); | |
307 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
308 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 309 | |
e51d0f0a | 310 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 311 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
312 | d->sg = sg_next(d->sg); |
313 | if (d->sg) { | |
6bd08127 | 314 | u32 tmp; |
a6cbb2d8 | 315 | imxdma_sg_next(d); |
cd5cf9da JM |
316 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
317 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
318 | DMA_CCR(channel)); | |
6bd08127 JM |
319 | } |
320 | } | |
6bd08127 JM |
321 | |
322 | local_irq_restore(flags); | |
323 | } | |
324 | ||
325 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
326 | { | |
cd5cf9da | 327 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
328 | int channel = imxdmac->channel; |
329 | unsigned long flags; | |
330 | ||
f9b283a6 | 331 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 332 | |
2d9c2fc5 JM |
333 | if (imxdma_hw_chain(imxdmac)) |
334 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
335 | |
336 | local_irq_save(flags); | |
cd5cf9da JM |
337 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
338 | (1 << channel), DMA_DIMR); | |
339 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
340 | ~CCR_CEN, DMA_CCR(channel)); | |
341 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
342 | local_irq_restore(flags); |
343 | } | |
344 | ||
6bd08127 | 345 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 346 | { |
6bd08127 | 347 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
cd5cf9da | 348 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 349 | int channel = imxdmac->channel; |
1f1846c6 | 350 | |
cd5cf9da | 351 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 352 | |
6bd08127 | 353 | /* Tasklet watchdog error handler */ |
9e15db7c | 354 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
355 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
356 | imxdmac->channel); | |
1f1846c6 SH |
357 | } |
358 | ||
6bd08127 | 359 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 360 | { |
6bd08127 | 361 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
362 | unsigned int err_mask; |
363 | int i, disr; | |
364 | int errcode; | |
365 | ||
cd5cf9da | 366 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 367 | |
cd5cf9da JM |
368 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
369 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
370 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
371 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
372 | |
373 | if (!err_mask) | |
374 | return IRQ_HANDLED; | |
375 | ||
cd5cf9da | 376 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
377 | |
378 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
379 | if (!(err_mask & (1 << i))) | |
380 | continue; | |
6bd08127 JM |
381 | errcode = 0; |
382 | ||
cd5cf9da JM |
383 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
384 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
385 | errcode |= IMX_DMA_ERR_BURST; |
386 | } | |
cd5cf9da JM |
387 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
388 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
389 | errcode |= IMX_DMA_ERR_REQUEST; |
390 | } | |
cd5cf9da JM |
391 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
392 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
393 | errcode |= IMX_DMA_ERR_TRANSFER; |
394 | } | |
cd5cf9da JM |
395 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
396 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
397 | errcode |= IMX_DMA_ERR_BUFFER; |
398 | } | |
399 | /* Tasklet error handler */ | |
400 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
401 | ||
402 | printk(KERN_WARNING | |
403 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
404 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
405 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
406 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
407 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
408 | } | |
409 | return IRQ_HANDLED; | |
1f1846c6 SH |
410 | } |
411 | ||
6bd08127 | 412 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 413 | { |
cd5cf9da | 414 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 415 | int chno = imxdmac->channel; |
2efc3449 | 416 | struct imxdma_desc *desc; |
6bd08127 | 417 | |
f606ab89 | 418 | spin_lock(&imxdma->lock); |
833bc03b | 419 | if (list_empty(&imxdmac->ld_active)) { |
f606ab89 | 420 | spin_unlock(&imxdma->lock); |
833bc03b JM |
421 | goto out; |
422 | } | |
2efc3449 | 423 | |
833bc03b JM |
424 | desc = list_first_entry(&imxdmac->ld_active, |
425 | struct imxdma_desc, | |
426 | node); | |
f606ab89 | 427 | spin_unlock(&imxdma->lock); |
2efc3449 | 428 | |
833bc03b JM |
429 | if (desc->sg) { |
430 | u32 tmp; | |
431 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 432 | |
833bc03b | 433 | if (desc->sg) { |
a6cbb2d8 | 434 | imxdma_sg_next(desc); |
6bd08127 | 435 | |
cd5cf9da | 436 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 437 | |
2d9c2fc5 | 438 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
439 | /* FIXME: The timeout should probably be |
440 | * configurable | |
441 | */ | |
2d9c2fc5 | 442 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
443 | jiffies + msecs_to_jiffies(500)); |
444 | ||
445 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 446 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 447 | } else { |
cd5cf9da JM |
448 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
449 | DMA_CCR(chno)); | |
6bd08127 JM |
450 | tmp |= CCR_CEN; |
451 | } | |
452 | ||
cd5cf9da | 453 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
454 | |
455 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
456 | /* Tasklet progression */ | |
457 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 458 | |
6bd08127 JM |
459 | return; |
460 | } | |
461 | ||
2d9c2fc5 JM |
462 | if (imxdma_hw_chain(imxdmac)) { |
463 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
464 | return; |
465 | } | |
466 | } | |
467 | ||
2efc3449 | 468 | out: |
cd5cf9da | 469 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 470 | /* Tasklet irq */ |
9e15db7c JM |
471 | tasklet_schedule(&imxdmac->dma_tasklet); |
472 | } | |
473 | ||
6bd08127 JM |
474 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
475 | { | |
476 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
477 | int i, disr; |
478 | ||
e51d0f0a | 479 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
480 | imxdma_err_handler(irq, dev_id); |
481 | ||
cd5cf9da | 482 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 483 | |
f9b283a6 | 484 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 485 | |
cd5cf9da | 486 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 487 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 488 | if (disr & (1 << i)) |
6bd08127 | 489 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
490 | } |
491 | ||
492 | return IRQ_HANDLED; | |
493 | } | |
494 | ||
9e15db7c JM |
495 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
496 | { | |
497 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 498 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
499 | unsigned long flags; |
500 | int slot = -1; | |
501 | int i; | |
9e15db7c JM |
502 | |
503 | /* Configure and enable */ | |
504 | switch (d->type) { | |
f606ab89 JM |
505 | case IMXDMA_DESC_INTERLEAVED: |
506 | /* Try to get a free 2D slot */ | |
507 | spin_lock_irqsave(&imxdma->lock, flags); | |
508 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { | |
509 | if ((imxdma->slots_2d[i].count > 0) && | |
510 | ((imxdma->slots_2d[i].xsr != d->x) || | |
511 | (imxdma->slots_2d[i].ysr != d->y) || | |
512 | (imxdma->slots_2d[i].wsr != d->w))) | |
513 | continue; | |
514 | slot = i; | |
515 | break; | |
516 | } | |
720dfd25 WY |
517 | if (slot < 0) { |
518 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
f606ab89 | 519 | return -EBUSY; |
720dfd25 | 520 | } |
f606ab89 JM |
521 | |
522 | imxdma->slots_2d[slot].xsr = d->x; | |
523 | imxdma->slots_2d[slot].ysr = d->y; | |
524 | imxdma->slots_2d[slot].wsr = d->w; | |
525 | imxdma->slots_2d[slot].count++; | |
526 | ||
527 | imxdmac->slot_2d = slot; | |
528 | imxdmac->enabled_2d = true; | |
529 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
530 | ||
531 | if (slot == IMX_DMA_2D_SLOT_A) { | |
532 | d->config_mem &= ~CCR_MSEL_B; | |
533 | d->config_port &= ~CCR_MSEL_B; | |
534 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
535 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
536 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
537 | } else { | |
538 | d->config_mem |= CCR_MSEL_B; | |
539 | d->config_port |= CCR_MSEL_B; | |
540 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
541 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
542 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
543 | } | |
544 | /* | |
545 | * We fall-through here intentionally, since a 2D transfer is | |
546 | * similar to MEMCPY just adding the 2D slot configuration. | |
547 | */ | |
9e15db7c | 548 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
549 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
550 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
551 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 552 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 553 | |
cd5cf9da | 554 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc JM |
555 | |
556 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
557 | "dma_length=%d\n", __func__, imxdmac->channel, | |
558 | d->dest, d->src, d->len); | |
559 | ||
560 | break; | |
6bd08127 | 561 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 562 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 563 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 564 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 565 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 566 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 567 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
568 | DMA_CCR(imxdmac->channel)); |
569 | ||
570 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
571 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
572 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
573 | d->len, imxdmac->per_address); | |
574 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
cd5cf9da | 575 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 576 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 577 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
578 | DMA_CCR(imxdmac->channel)); |
579 | ||
580 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
581 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
582 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
583 | d->len, imxdmac->per_address); | |
584 | } else { | |
585 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
586 | __func__, imxdmac->channel); | |
587 | return -EINVAL; | |
588 | } | |
589 | ||
a6cbb2d8 | 590 | imxdma_sg_next(d); |
1f1846c6 | 591 | |
9e15db7c JM |
592 | break; |
593 | default: | |
594 | return -EINVAL; | |
595 | } | |
2efc3449 | 596 | imxdma_enable_hw(d); |
9e15db7c | 597 | return 0; |
1f1846c6 SH |
598 | } |
599 | ||
9e15db7c | 600 | static void imxdma_tasklet(unsigned long data) |
1f1846c6 | 601 | { |
9e15db7c JM |
602 | struct imxdma_channel *imxdmac = (void *)data; |
603 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
604 | struct imxdma_desc *desc; | |
1f1846c6 | 605 | |
f606ab89 | 606 | spin_lock(&imxdma->lock); |
9e15db7c JM |
607 | |
608 | if (list_empty(&imxdmac->ld_active)) { | |
609 | /* Someone might have called terminate all */ | |
610 | goto out; | |
611 | } | |
612 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
613 | ||
614 | if (desc->desc.callback) | |
615 | desc->desc.callback(desc->desc.callback_param); | |
616 | ||
d73111c6 MI |
617 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
618 | * and dont mark the descriptor as complete. | |
60f2951e VK |
619 | * Only in non-cyclic cases it would be marked as complete |
620 | */ | |
9e15db7c JM |
621 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
622 | goto out; | |
60f2951e VK |
623 | else |
624 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 625 | |
f606ab89 JM |
626 | /* Free 2D slot if it was an interleaved transfer */ |
627 | if (imxdmac->enabled_2d) { | |
628 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
629 | imxdmac->enabled_2d = false; | |
630 | } | |
631 | ||
9e15db7c JM |
632 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
633 | ||
634 | if (!list_empty(&imxdmac->ld_queue)) { | |
635 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
636 | node); | |
637 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
638 | if (imxdma_xfer_desc(desc) < 0) | |
639 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
640 | __func__, imxdmac->channel); | |
641 | } | |
642 | out: | |
f606ab89 | 643 | spin_unlock(&imxdma->lock); |
1f1846c6 SH |
644 | } |
645 | ||
646 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
647 | unsigned long arg) | |
648 | { | |
649 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
650 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
cd5cf9da | 651 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 652 | unsigned long flags; |
1f1846c6 SH |
653 | unsigned int mode = 0; |
654 | ||
655 | switch (cmd) { | |
656 | case DMA_TERMINATE_ALL: | |
6bd08127 | 657 | imxdma_disable_hw(imxdmac); |
9e15db7c | 658 | |
f606ab89 | 659 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
660 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
661 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
f606ab89 | 662 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
663 | return 0; |
664 | case DMA_SLAVE_CONFIG: | |
db8196df | 665 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
666 | imxdmac->per_address = dmaengine_cfg->src_addr; |
667 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
668 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
669 | } else { | |
670 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
671 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
672 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
673 | } | |
674 | ||
675 | switch (imxdmac->word_size) { | |
676 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
677 | mode = IMX_DMA_MEMSIZE_8; | |
678 | break; | |
679 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
680 | mode = IMX_DMA_MEMSIZE_16; | |
681 | break; | |
682 | default: | |
683 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
684 | mode = IMX_DMA_MEMSIZE_32; | |
685 | break; | |
686 | } | |
1f1846c6 | 687 | |
bef2a8d3 JM |
688 | imxdmac->hw_chaining = 0; |
689 | ||
359291a1 | 690 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
691 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
692 | CCR_REN; | |
359291a1 | 693 | imxdmac->ccr_to_device = |
bdc0c753 JM |
694 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
695 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
cd5cf9da | 696 | imx_dmav1_writel(imxdma, imxdmac->dma_request, |
bdc0c753 JM |
697 | DMA_RSSR(imxdmac->channel)); |
698 | ||
6bd08127 | 699 | /* Set burst length */ |
cd5cf9da JM |
700 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * |
701 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
702 | |
703 | return 0; | |
704 | default: | |
705 | return -ENOSYS; | |
706 | } | |
707 | ||
708 | return -EINVAL; | |
709 | } | |
710 | ||
711 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
712 | dma_cookie_t cookie, | |
713 | struct dma_tx_state *txstate) | |
714 | { | |
96a2af41 | 715 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
716 | } |
717 | ||
718 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
719 | { | |
720 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 721 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 722 | dma_cookie_t cookie; |
9e15db7c | 723 | unsigned long flags; |
1f1846c6 | 724 | |
f606ab89 | 725 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 726 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 727 | cookie = dma_cookie_assign(tx); |
f606ab89 | 728 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
729 | |
730 | return cookie; | |
731 | } | |
732 | ||
733 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
734 | { | |
735 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
736 | struct imx_dma_data *data = chan->private; | |
737 | ||
6c05f091 JM |
738 | if (data != NULL) |
739 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 740 | |
9e15db7c JM |
741 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
742 | struct imxdma_desc *desc; | |
1f1846c6 | 743 | |
9e15db7c JM |
744 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
745 | if (!desc) | |
746 | break; | |
747 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
748 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
749 | desc->desc.tx_submit = imxdma_tx_submit; | |
750 | /* txd.flags will be overwritten in prep funcs */ | |
751 | desc->desc.flags = DMA_CTRL_ACK; | |
752 | desc->status = DMA_SUCCESS; | |
753 | ||
754 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
755 | imxdmac->descs_allocated++; | |
756 | } | |
1f1846c6 | 757 | |
9e15db7c JM |
758 | if (!imxdmac->descs_allocated) |
759 | return -ENOMEM; | |
760 | ||
761 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
762 | } |
763 | ||
764 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
765 | { | |
766 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 767 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
768 | struct imxdma_desc *desc, *_desc; |
769 | unsigned long flags; | |
770 | ||
f606ab89 | 771 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 772 | |
6bd08127 | 773 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
774 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
775 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 776 | |
f606ab89 | 777 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
778 | |
779 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
780 | kfree(desc); | |
781 | imxdmac->descs_allocated--; | |
782 | } | |
783 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 SH |
784 | |
785 | if (imxdmac->sg_list) { | |
786 | kfree(imxdmac->sg_list); | |
787 | imxdmac->sg_list = NULL; | |
788 | } | |
789 | } | |
790 | ||
791 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
792 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 793 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 794 | unsigned long flags, void *context) |
1f1846c6 SH |
795 | { |
796 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
797 | struct scatterlist *sg; | |
9e15db7c JM |
798 | int i, dma_length = 0; |
799 | struct imxdma_desc *desc; | |
1f1846c6 | 800 | |
9e15db7c JM |
801 | if (list_empty(&imxdmac->ld_free) || |
802 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
803 | return NULL; |
804 | ||
9e15db7c | 805 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
806 | |
807 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 808 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
809 | } |
810 | ||
d07102a1 SH |
811 | switch (imxdmac->word_size) { |
812 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 813 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
814 | return NULL; |
815 | break; | |
816 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 817 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
818 | return NULL; |
819 | break; | |
820 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
821 | break; | |
822 | default: | |
823 | return NULL; | |
824 | } | |
825 | ||
9e15db7c JM |
826 | desc->type = IMXDMA_DESC_SLAVE_SG; |
827 | desc->sg = sgl; | |
828 | desc->sgcount = sg_len; | |
829 | desc->len = dma_length; | |
2efc3449 | 830 | desc->direction = direction; |
9e15db7c | 831 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
832 | desc->src = imxdmac->per_address; |
833 | } else { | |
9e15db7c JM |
834 | desc->dest = imxdmac->per_address; |
835 | } | |
836 | desc->desc.callback = NULL; | |
837 | desc->desc.callback_param = NULL; | |
1f1846c6 | 838 | |
9e15db7c | 839 | return &desc->desc; |
1f1846c6 SH |
840 | } |
841 | ||
842 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
843 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 844 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 845 | unsigned long flags, void *context) |
1f1846c6 SH |
846 | { |
847 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
848 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
849 | struct imxdma_desc *desc; |
850 | int i; | |
1f1846c6 | 851 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
852 | |
853 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
854 | __func__, imxdmac->channel, buf_len, period_len); | |
855 | ||
9e15db7c JM |
856 | if (list_empty(&imxdmac->ld_free) || |
857 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 858 | return NULL; |
1f1846c6 | 859 | |
9e15db7c | 860 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
861 | |
862 | if (imxdmac->sg_list) | |
863 | kfree(imxdmac->sg_list); | |
864 | ||
865 | imxdmac->sg_list = kcalloc(periods + 1, | |
866 | sizeof(struct scatterlist), GFP_KERNEL); | |
867 | if (!imxdmac->sg_list) | |
868 | return NULL; | |
869 | ||
870 | sg_init_table(imxdmac->sg_list, periods); | |
871 | ||
872 | for (i = 0; i < periods; i++) { | |
873 | imxdmac->sg_list[i].page_link = 0; | |
874 | imxdmac->sg_list[i].offset = 0; | |
875 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 876 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
877 | dma_addr += period_len; |
878 | } | |
879 | ||
880 | /* close the loop */ | |
881 | imxdmac->sg_list[periods].offset = 0; | |
fdaf9c4b | 882 | sg_dma_len(&imxdmac->sg_list[periods]) = 0; |
1f1846c6 SH |
883 | imxdmac->sg_list[periods].page_link = |
884 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
885 | ||
9e15db7c JM |
886 | desc->type = IMXDMA_DESC_CYCLIC; |
887 | desc->sg = imxdmac->sg_list; | |
888 | desc->sgcount = periods; | |
889 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 890 | desc->direction = direction; |
9e15db7c | 891 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
892 | desc->src = imxdmac->per_address; |
893 | } else { | |
9e15db7c JM |
894 | desc->dest = imxdmac->per_address; |
895 | } | |
896 | desc->desc.callback = NULL; | |
897 | desc->desc.callback_param = NULL; | |
1f1846c6 | 898 | |
9e15db7c | 899 | return &desc->desc; |
1f1846c6 SH |
900 | } |
901 | ||
6c05f091 JM |
902 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
903 | struct dma_chan *chan, dma_addr_t dest, | |
904 | dma_addr_t src, size_t len, unsigned long flags) | |
905 | { | |
906 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
907 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 908 | struct imxdma_desc *desc; |
1f1846c6 | 909 | |
6c05f091 JM |
910 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", |
911 | __func__, imxdmac->channel, src, dest, len); | |
912 | ||
9e15db7c JM |
913 | if (list_empty(&imxdmac->ld_free) || |
914 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
915 | return NULL; |
916 | ||
9e15db7c | 917 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 918 | |
9e15db7c JM |
919 | desc->type = IMXDMA_DESC_MEMCPY; |
920 | desc->src = src; | |
921 | desc->dest = dest; | |
922 | desc->len = len; | |
2efc3449 | 923 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
924 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
925 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
926 | desc->desc.callback = NULL; | |
927 | desc->desc.callback_param = NULL; | |
6c05f091 | 928 | |
9e15db7c | 929 | return &desc->desc; |
6c05f091 JM |
930 | } |
931 | ||
f606ab89 JM |
932 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
933 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
934 | unsigned long flags) | |
935 | { | |
936 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
937 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
938 | struct imxdma_desc *desc; | |
939 | ||
940 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n" | |
941 | " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__, | |
942 | imxdmac->channel, xt->src_start, xt->dst_start, | |
943 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", | |
944 | xt->numf, xt->frame_size); | |
945 | ||
946 | if (list_empty(&imxdmac->ld_free) || | |
947 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
948 | return NULL; | |
949 | ||
950 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
951 | return NULL; | |
952 | ||
953 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
954 | ||
955 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
956 | desc->src = xt->src_start; | |
957 | desc->dest = xt->dst_start; | |
958 | desc->x = xt->sgl[0].size; | |
959 | desc->y = xt->numf; | |
960 | desc->w = xt->sgl[0].icg + desc->x; | |
961 | desc->len = desc->x * desc->y; | |
962 | desc->direction = DMA_MEM_TO_MEM; | |
963 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
964 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
965 | if (xt->src_sgl) | |
966 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
967 | if (xt->dst_sgl) | |
968 | desc->config_port |= IMX_DMA_TYPE_2D; | |
969 | desc->desc.callback = NULL; | |
970 | desc->desc.callback_param = NULL; | |
971 | ||
972 | return &desc->desc; | |
1f1846c6 SH |
973 | } |
974 | ||
975 | static void imxdma_issue_pending(struct dma_chan *chan) | |
976 | { | |
5b316876 | 977 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
978 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
979 | struct imxdma_desc *desc; | |
980 | unsigned long flags; | |
981 | ||
f606ab89 | 982 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
983 | if (list_empty(&imxdmac->ld_active) && |
984 | !list_empty(&imxdmac->ld_queue)) { | |
985 | desc = list_first_entry(&imxdmac->ld_queue, | |
986 | struct imxdma_desc, node); | |
987 | ||
988 | if (imxdma_xfer_desc(desc) < 0) { | |
989 | dev_warn(imxdma->dev, | |
990 | "%s: channel: %d couldn't issue DMA xfer\n", | |
991 | __func__, imxdmac->channel); | |
992 | } else { | |
993 | list_move_tail(imxdmac->ld_queue.next, | |
994 | &imxdmac->ld_active); | |
995 | } | |
996 | } | |
f606ab89 | 997 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
998 | } |
999 | ||
1000 | static int __init imxdma_probe(struct platform_device *pdev) | |
6bd08127 | 1001 | { |
1f1846c6 | 1002 | struct imxdma_engine *imxdma; |
73930eb3 | 1003 | struct resource *res; |
1f1846c6 | 1004 | int ret, i; |
73930eb3 | 1005 | int irq, irq_err; |
cd5cf9da | 1006 | |
04bbd8ef | 1007 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1008 | if (!imxdma) |
1009 | return -ENOMEM; | |
1010 | ||
e51d0f0a SG |
1011 | imxdma->devtype = pdev->id_entry->driver_data; |
1012 | ||
73930eb3 | 1013 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1014 | imxdma->base = devm_ioremap_resource(&pdev->dev, res); |
1015 | if (IS_ERR(imxdma->base)) | |
1016 | return PTR_ERR(imxdma->base); | |
73930eb3 SG |
1017 | |
1018 | irq = platform_get_irq(pdev, 0); | |
1019 | if (irq < 0) | |
1020 | return irq; | |
6bd08127 | 1021 | |
a2367db2 | 1022 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1023 | if (IS_ERR(imxdma->dma_ipg)) |
1024 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1025 | |
1026 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1027 | if (IS_ERR(imxdma->dma_ahb)) |
1028 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 FE |
1029 | |
1030 | clk_prepare_enable(imxdma->dma_ipg); | |
1031 | clk_prepare_enable(imxdma->dma_ahb); | |
6bd08127 JM |
1032 | |
1033 | /* reset DMA module */ | |
cd5cf9da | 1034 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1035 | |
e51d0f0a | 1036 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1037 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1038 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1039 | if (ret) { |
f9b283a6 | 1040 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
04bbd8ef | 1041 | goto err; |
6bd08127 JM |
1042 | } |
1043 | ||
73930eb3 SG |
1044 | irq_err = platform_get_irq(pdev, 1); |
1045 | if (irq_err < 0) { | |
1046 | ret = irq_err; | |
1047 | goto err; | |
1048 | } | |
1049 | ||
1050 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1051 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1052 | if (ret) { |
f9b283a6 | 1053 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
04bbd8ef | 1054 | goto err; |
6bd08127 JM |
1055 | } |
1056 | } | |
1057 | ||
1058 | /* enable DMA module */ | |
cd5cf9da | 1059 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1060 | |
1061 | /* clear all interrupts */ | |
cd5cf9da | 1062 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1063 | |
1064 | /* disable interrupts */ | |
cd5cf9da | 1065 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1066 | |
1067 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1068 | ||
f8a356ff SH |
1069 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1070 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1071 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1072 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1073 | ||
1074 | /* Initialize 2D global parameters */ | |
1075 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1076 | imxdma->slots_2d[i].count = 0; | |
1077 | ||
1078 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1079 | |
1f1846c6 | 1080 | /* Initialize channel parameters */ |
6bd08127 | 1081 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1082 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1083 | ||
e51d0f0a | 1084 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1085 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1086 | dma_irq_handler, 0, "DMA", imxdma); |
1087 | if (ret) { | |
f9b283a6 JM |
1088 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1089 | "for DMA channel %d\n", | |
73930eb3 | 1090 | irq + i, i); |
04bbd8ef | 1091 | goto err; |
6bd08127 | 1092 | } |
2d9c2fc5 JM |
1093 | init_timer(&imxdmac->watchdog); |
1094 | imxdmac->watchdog.function = &imxdma_watchdog; | |
1095 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 1096 | } |
1f1846c6 | 1097 | |
1f1846c6 | 1098 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1099 | |
9e15db7c JM |
1100 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1101 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1102 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1103 | ||
1104 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
1105 | (unsigned long)imxdmac); | |
1f1846c6 | 1106 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1107 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1108 | imxdmac->channel = i; |
1109 | ||
1110 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1111 | list_add_tail(&imxdmac->chan.device_node, |
1112 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1113 | } |
1114 | ||
1115 | imxdma->dev = &pdev->dev; | |
1116 | imxdma->dma_device.dev = &pdev->dev; | |
1117 | ||
1118 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1119 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1120 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1121 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1122 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1123 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1124 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
1f1846c6 SH |
1125 | imxdma->dma_device.device_control = imxdma_control; |
1126 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
1127 | ||
1128 | platform_set_drvdata(pdev, imxdma); | |
1129 | ||
6c05f091 | 1130 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
1131 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
1132 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
1133 | ||
1f1846c6 SH |
1134 | ret = dma_async_device_register(&imxdma->dma_device); |
1135 | if (ret) { | |
1136 | dev_err(&pdev->dev, "unable to register\n"); | |
04bbd8ef | 1137 | goto err; |
1f1846c6 SH |
1138 | } |
1139 | ||
1140 | return 0; | |
1141 | ||
04bbd8ef | 1142 | err: |
a2367db2 FE |
1143 | clk_disable_unprepare(imxdma->dma_ipg); |
1144 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1145 | return ret; |
1146 | } | |
1147 | ||
1148 | static int __exit imxdma_remove(struct platform_device *pdev) | |
1149 | { | |
1150 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 SH |
1151 | |
1152 | dma_async_device_unregister(&imxdma->dma_device); | |
1153 | ||
a2367db2 FE |
1154 | clk_disable_unprepare(imxdma->dma_ipg); |
1155 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1156 | |
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | static struct platform_driver imxdma_driver = { | |
1161 | .driver = { | |
1162 | .name = "imx-dma", | |
1163 | }, | |
e51d0f0a | 1164 | .id_table = imx_dma_devtype, |
1f1846c6 SH |
1165 | .remove = __exit_p(imxdma_remove), |
1166 | }; | |
1167 | ||
1168 | static int __init imxdma_module_init(void) | |
1169 | { | |
1170 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1171 | } | |
1172 | subsys_initcall(imxdma_module_init); | |
1173 | ||
1174 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1175 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1176 | MODULE_LICENSE("GPL"); |