Commit | Line | Data |
---|---|---|
ce9c28ca FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // drivers/dma/imx-dma.c | |
4 | // | |
5 | // This file contains a driver for the Freescale i.MX DMA engine | |
6 | // found on i.MX1/21/27 | |
7 | // | |
8 | // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9 | // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> | |
10 | ||
7331205a | 11 | #include <linux/err.h> |
1f1846c6 SH |
12 | #include <linux/init.h> |
13 | #include <linux/types.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/platform_device.h> | |
6bd08127 | 21 | #include <linux/clk.h> |
1f1846c6 | 22 | #include <linux/dmaengine.h> |
5c45ad77 | 23 | #include <linux/module.h> |
290ad0f9 MP |
24 | #include <linux/of_device.h> |
25 | #include <linux/of_dma.h> | |
1f1846c6 SH |
26 | |
27 | #include <asm/irq.h> | |
82906b13 | 28 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 29 | |
d2ebfb33 | 30 | #include "dmaengine.h" |
9e15db7c | 31 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
32 | #define IMX_DMA_CHANNELS 16 |
33 | ||
f606ab89 JM |
34 | #define IMX_DMA_2D_SLOTS 2 |
35 | #define IMX_DMA_2D_SLOT_A 0 | |
36 | #define IMX_DMA_2D_SLOT_B 1 | |
37 | ||
6bd08127 JM |
38 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
39 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
40 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
41 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
42 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
43 | #define IMX_DMA_TYPE_2D (1 << 10) | |
44 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
45 | ||
46 | #define IMX_DMA_ERR_BURST (1 << 0) | |
47 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
48 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
49 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
50 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
51 | ||
52 | #define DMA_DCR 0x00 /* Control Register */ | |
53 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
54 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
55 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
56 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
57 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
58 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
59 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
60 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
61 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
62 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
63 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
64 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
65 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
66 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
67 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
68 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
69 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
70 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
71 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
72 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
73 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
74 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
75 | ||
76 | #define DCR_DRST (1<<1) | |
77 | #define DCR_DEN (1<<0) | |
78 | #define DBTOCR_EN (1<<15) | |
79 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
80 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
81 | #define CCR_ACRPT (1<<14) | |
82 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
83 | #define CCR_DMOD_2D (0x1 << 12) | |
84 | #define CCR_DMOD_FIFO (0x2 << 12) | |
85 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
86 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
87 | #define CCR_SMOD_2D (0x1 << 10) | |
88 | #define CCR_SMOD_FIFO (0x2 << 10) | |
89 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
90 | #define CCR_MDIR_DEC (1<<9) | |
91 | #define CCR_MSEL_B (1<<8) | |
92 | #define CCR_DSIZ_32 (0x0 << 6) | |
93 | #define CCR_DSIZ_8 (0x1 << 6) | |
94 | #define CCR_DSIZ_16 (0x2 << 6) | |
95 | #define CCR_SSIZ_32 (0x0 << 4) | |
96 | #define CCR_SSIZ_8 (0x1 << 4) | |
97 | #define CCR_SSIZ_16 (0x2 << 4) | |
98 | #define CCR_REN (1<<3) | |
99 | #define CCR_RPT (1<<2) | |
100 | #define CCR_FRC (1<<1) | |
101 | #define CCR_CEN (1<<0) | |
102 | #define RTOR_EN (1<<15) | |
103 | #define RTOR_CLK (1<<14) | |
104 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
105 | |
106 | enum imxdma_prep_type { | |
107 | IMXDMA_DESC_MEMCPY, | |
108 | IMXDMA_DESC_INTERLEAVED, | |
109 | IMXDMA_DESC_SLAVE_SG, | |
110 | IMXDMA_DESC_CYCLIC, | |
111 | }; | |
112 | ||
f606ab89 JM |
113 | struct imx_dma_2d_config { |
114 | u16 xsr; | |
115 | u16 ysr; | |
116 | u16 wsr; | |
117 | int count; | |
118 | }; | |
119 | ||
9e15db7c JM |
120 | struct imxdma_desc { |
121 | struct list_head node; | |
122 | struct dma_async_tx_descriptor desc; | |
123 | enum dma_status status; | |
124 | dma_addr_t src; | |
125 | dma_addr_t dest; | |
126 | size_t len; | |
2efc3449 | 127 | enum dma_transfer_direction direction; |
9e15db7c JM |
128 | enum imxdma_prep_type type; |
129 | /* For memcpy and interleaved */ | |
130 | unsigned int config_port; | |
131 | unsigned int config_mem; | |
132 | /* For interleaved transfers */ | |
133 | unsigned int x; | |
134 | unsigned int y; | |
135 | unsigned int w; | |
136 | /* For slave sg and cyclic */ | |
137 | struct scatterlist *sg; | |
138 | unsigned int sgcount; | |
139 | }; | |
140 | ||
1f1846c6 | 141 | struct imxdma_channel { |
2d9c2fc5 JM |
142 | int hw_chaining; |
143 | struct timer_list watchdog; | |
1f1846c6 SH |
144 | struct imxdma_engine *imxdma; |
145 | unsigned int channel; | |
1f1846c6 | 146 | |
9e15db7c JM |
147 | struct tasklet_struct dma_tasklet; |
148 | struct list_head ld_free; | |
149 | struct list_head ld_queue; | |
150 | struct list_head ld_active; | |
151 | int descs_allocated; | |
1f1846c6 SH |
152 | enum dma_slave_buswidth word_size; |
153 | dma_addr_t per_address; | |
154 | u32 watermark_level; | |
155 | struct dma_chan chan; | |
1f1846c6 | 156 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
157 | enum dma_status status; |
158 | int dma_request; | |
159 | struct scatterlist *sg_list; | |
359291a1 JM |
160 | u32 ccr_from_device; |
161 | u32 ccr_to_device; | |
f606ab89 JM |
162 | bool enabled_2d; |
163 | int slot_2d; | |
ea62aa80 | 164 | unsigned int irq; |
dea7a9fb | 165 | struct dma_slave_config config; |
1f1846c6 SH |
166 | }; |
167 | ||
e51d0f0a SG |
168 | enum imx_dma_type { |
169 | IMX1_DMA, | |
170 | IMX21_DMA, | |
171 | IMX27_DMA, | |
172 | }; | |
173 | ||
1f1846c6 SH |
174 | struct imxdma_engine { |
175 | struct device *dev; | |
176 | struct dma_device dma_device; | |
cd5cf9da | 177 | void __iomem *base; |
a2367db2 FE |
178 | struct clk *dma_ahb; |
179 | struct clk *dma_ipg; | |
f606ab89 JM |
180 | spinlock_t lock; |
181 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 182 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 183 | enum imx_dma_type devtype; |
ea62aa80 VK |
184 | unsigned int irq; |
185 | unsigned int irq_err; | |
186 | ||
1f1846c6 SH |
187 | }; |
188 | ||
290ad0f9 MP |
189 | struct imxdma_filter_data { |
190 | struct imxdma_engine *imxdma; | |
191 | int request; | |
192 | }; | |
193 | ||
290ad0f9 MP |
194 | static const struct of_device_id imx_dma_of_dev_id[] = { |
195 | { | |
0ab785c8 | 196 | .compatible = "fsl,imx1-dma", .data = (const void *)IMX1_DMA, |
290ad0f9 | 197 | }, { |
0ab785c8 | 198 | .compatible = "fsl,imx21-dma", .data = (const void *)IMX21_DMA, |
290ad0f9 | 199 | }, { |
0ab785c8 | 200 | .compatible = "fsl,imx27-dma", .data = (const void *)IMX27_DMA, |
290ad0f9 MP |
201 | }, { |
202 | /* sentinel */ | |
203 | } | |
204 | }; | |
205 | MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); | |
206 | ||
e51d0f0a SG |
207 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) |
208 | { | |
209 | return imxdma->devtype == IMX1_DMA; | |
210 | } | |
211 | ||
e51d0f0a SG |
212 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) |
213 | { | |
214 | return imxdma->devtype == IMX27_DMA; | |
215 | } | |
216 | ||
1f1846c6 SH |
217 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
218 | { | |
219 | return container_of(chan, struct imxdma_channel, chan); | |
220 | } | |
221 | ||
9e15db7c | 222 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 223 | { |
9e15db7c JM |
224 | struct imxdma_desc *desc; |
225 | ||
226 | if (!list_empty(&imxdmac->ld_active)) { | |
227 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
228 | node); | |
229 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
230 | return true; | |
231 | } | |
232 | return false; | |
1f1846c6 SH |
233 | } |
234 | ||
6bd08127 | 235 | |
cd5cf9da JM |
236 | |
237 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
238 | unsigned offset) | |
6bd08127 | 239 | { |
cd5cf9da | 240 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
241 | } |
242 | ||
cd5cf9da | 243 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 244 | { |
cd5cf9da | 245 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 246 | } |
1f1846c6 | 247 | |
2d9c2fc5 | 248 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 249 | { |
e51d0f0a SG |
250 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
251 | ||
252 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 253 | return imxdmac->hw_chaining; |
6bd08127 JM |
254 | else |
255 | return 0; | |
256 | } | |
257 | ||
258 | /* | |
259 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
260 | */ | |
452fd6dc | 261 | static inline void imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 262 | { |
2efc3449 | 263 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 264 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 265 | struct scatterlist *sg = d->sg; |
da5035f3 | 266 | size_t now; |
6bd08127 | 267 | |
9227ab56 | 268 | now = min_t(size_t, d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
269 | if (d->len != IMX_DMA_LENGTH_LOOP) |
270 | d->len -= now; | |
6bd08127 | 271 | |
2efc3449 | 272 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
273 | imx_dmav1_writel(imxdma, sg->dma_address, |
274 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 275 | else |
cd5cf9da JM |
276 | imx_dmav1_writel(imxdma, sg->dma_address, |
277 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 278 | |
cd5cf9da | 279 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 280 | |
f9b283a6 JM |
281 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
282 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
283 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
284 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
285 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
1f1846c6 SH |
286 | } |
287 | ||
2efc3449 | 288 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 289 | { |
2efc3449 | 290 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 291 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
292 | int channel = imxdmac->channel; |
293 | unsigned long flags; | |
294 | ||
f9b283a6 | 295 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 296 | |
6bd08127 JM |
297 | local_irq_save(flags); |
298 | ||
cd5cf9da JM |
299 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
300 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
301 | ~(1 << channel), DMA_DIMR); | |
302 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
303 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 304 | |
e51d0f0a | 305 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 306 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
307 | d->sg = sg_next(d->sg); |
308 | if (d->sg) { | |
6bd08127 | 309 | u32 tmp; |
a6cbb2d8 | 310 | imxdma_sg_next(d); |
cd5cf9da JM |
311 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
312 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
313 | DMA_CCR(channel)); | |
6bd08127 JM |
314 | } |
315 | } | |
6bd08127 JM |
316 | |
317 | local_irq_restore(flags); | |
318 | } | |
319 | ||
320 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
321 | { | |
cd5cf9da | 322 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
323 | int channel = imxdmac->channel; |
324 | unsigned long flags; | |
325 | ||
f9b283a6 | 326 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 327 | |
2d9c2fc5 JM |
328 | if (imxdma_hw_chain(imxdmac)) |
329 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
330 | |
331 | local_irq_save(flags); | |
cd5cf9da JM |
332 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
333 | (1 << channel), DMA_DIMR); | |
334 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
335 | ~CCR_CEN, DMA_CCR(channel)); | |
336 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
337 | local_irq_restore(flags); |
338 | } | |
339 | ||
bcdc4bd3 | 340 | static void imxdma_watchdog(struct timer_list *t) |
1f1846c6 | 341 | { |
bcdc4bd3 | 342 | struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog); |
cd5cf9da | 343 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 344 | int channel = imxdmac->channel; |
1f1846c6 | 345 | |
cd5cf9da | 346 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 347 | |
6bd08127 | 348 | /* Tasklet watchdog error handler */ |
9e15db7c | 349 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
350 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
351 | imxdmac->channel); | |
1f1846c6 SH |
352 | } |
353 | ||
6bd08127 | 354 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 355 | { |
6bd08127 | 356 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
357 | unsigned int err_mask; |
358 | int i, disr; | |
359 | int errcode; | |
360 | ||
cd5cf9da | 361 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 362 | |
cd5cf9da JM |
363 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
364 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
365 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
366 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
367 | |
368 | if (!err_mask) | |
369 | return IRQ_HANDLED; | |
370 | ||
cd5cf9da | 371 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
372 | |
373 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
374 | if (!(err_mask & (1 << i))) | |
375 | continue; | |
6bd08127 JM |
376 | errcode = 0; |
377 | ||
cd5cf9da JM |
378 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
379 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
380 | errcode |= IMX_DMA_ERR_BURST; |
381 | } | |
cd5cf9da JM |
382 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
383 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
384 | errcode |= IMX_DMA_ERR_REQUEST; |
385 | } | |
cd5cf9da JM |
386 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
387 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
388 | errcode |= IMX_DMA_ERR_TRANSFER; |
389 | } | |
cd5cf9da JM |
390 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
391 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
392 | errcode |= IMX_DMA_ERR_BUFFER; |
393 | } | |
394 | /* Tasklet error handler */ | |
395 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
396 | ||
1d94fe06 AS |
397 | dev_warn(imxdma->dev, |
398 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
399 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
400 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
401 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
402 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
6bd08127 JM |
403 | } |
404 | return IRQ_HANDLED; | |
1f1846c6 SH |
405 | } |
406 | ||
6bd08127 | 407 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 408 | { |
cd5cf9da | 409 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 410 | int chno = imxdmac->channel; |
2efc3449 | 411 | struct imxdma_desc *desc; |
5a276fa6 | 412 | unsigned long flags; |
6bd08127 | 413 | |
5a276fa6 | 414 | spin_lock_irqsave(&imxdma->lock, flags); |
833bc03b | 415 | if (list_empty(&imxdmac->ld_active)) { |
5a276fa6 | 416 | spin_unlock_irqrestore(&imxdma->lock, flags); |
833bc03b JM |
417 | goto out; |
418 | } | |
2efc3449 | 419 | |
833bc03b JM |
420 | desc = list_first_entry(&imxdmac->ld_active, |
421 | struct imxdma_desc, | |
422 | node); | |
5a276fa6 | 423 | spin_unlock_irqrestore(&imxdma->lock, flags); |
2efc3449 | 424 | |
833bc03b JM |
425 | if (desc->sg) { |
426 | u32 tmp; | |
427 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 428 | |
833bc03b | 429 | if (desc->sg) { |
a6cbb2d8 | 430 | imxdma_sg_next(desc); |
6bd08127 | 431 | |
cd5cf9da | 432 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 433 | |
2d9c2fc5 | 434 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
435 | /* FIXME: The timeout should probably be |
436 | * configurable | |
437 | */ | |
2d9c2fc5 | 438 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
439 | jiffies + msecs_to_jiffies(500)); |
440 | ||
441 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 442 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 443 | } else { |
cd5cf9da JM |
444 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
445 | DMA_CCR(chno)); | |
6bd08127 JM |
446 | tmp |= CCR_CEN; |
447 | } | |
448 | ||
cd5cf9da | 449 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
450 | |
451 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
452 | /* Tasklet progression */ | |
453 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 454 | |
6bd08127 JM |
455 | return; |
456 | } | |
457 | ||
2d9c2fc5 JM |
458 | if (imxdma_hw_chain(imxdmac)) { |
459 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
460 | return; |
461 | } | |
462 | } | |
463 | ||
2efc3449 | 464 | out: |
cd5cf9da | 465 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 466 | /* Tasklet irq */ |
9e15db7c JM |
467 | tasklet_schedule(&imxdmac->dma_tasklet); |
468 | } | |
469 | ||
6bd08127 JM |
470 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
471 | { | |
472 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
473 | int i, disr; |
474 | ||
e51d0f0a | 475 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
476 | imxdma_err_handler(irq, dev_id); |
477 | ||
cd5cf9da | 478 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 479 | |
f9b283a6 | 480 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 481 | |
cd5cf9da | 482 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 483 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 484 | if (disr & (1 << i)) |
6bd08127 | 485 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
486 | } |
487 | ||
488 | return IRQ_HANDLED; | |
489 | } | |
490 | ||
9e15db7c JM |
491 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
492 | { | |
493 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 494 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
495 | int slot = -1; |
496 | int i; | |
9e15db7c JM |
497 | |
498 | /* Configure and enable */ | |
499 | switch (d->type) { | |
f606ab89 JM |
500 | case IMXDMA_DESC_INTERLEAVED: |
501 | /* Try to get a free 2D slot */ | |
f606ab89 JM |
502 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { |
503 | if ((imxdma->slots_2d[i].count > 0) && | |
504 | ((imxdma->slots_2d[i].xsr != d->x) || | |
505 | (imxdma->slots_2d[i].ysr != d->y) || | |
506 | (imxdma->slots_2d[i].wsr != d->w))) | |
507 | continue; | |
508 | slot = i; | |
509 | break; | |
510 | } | |
5a276fa6 | 511 | if (slot < 0) |
f606ab89 JM |
512 | return -EBUSY; |
513 | ||
514 | imxdma->slots_2d[slot].xsr = d->x; | |
515 | imxdma->slots_2d[slot].ysr = d->y; | |
516 | imxdma->slots_2d[slot].wsr = d->w; | |
517 | imxdma->slots_2d[slot].count++; | |
518 | ||
519 | imxdmac->slot_2d = slot; | |
520 | imxdmac->enabled_2d = true; | |
f606ab89 JM |
521 | |
522 | if (slot == IMX_DMA_2D_SLOT_A) { | |
523 | d->config_mem &= ~CCR_MSEL_B; | |
524 | d->config_port &= ~CCR_MSEL_B; | |
525 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
526 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
527 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
528 | } else { | |
529 | d->config_mem |= CCR_MSEL_B; | |
530 | d->config_port |= CCR_MSEL_B; | |
531 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
532 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
533 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
534 | } | |
535 | /* | |
536 | * We fall-through here intentionally, since a 2D transfer is | |
537 | * similar to MEMCPY just adding the 2D slot configuration. | |
538 | */ | |
df561f66 | 539 | fallthrough; |
9e15db7c | 540 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
541 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
542 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
543 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 544 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 545 | |
cd5cf9da | 546 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc | 547 | |
ac806a1c RK |
548 | dev_dbg(imxdma->dev, |
549 | "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n", | |
550 | __func__, imxdmac->channel, | |
551 | (unsigned long long)d->dest, | |
552 | (unsigned long long)d->src, d->len); | |
3b4b6dfc JM |
553 | |
554 | break; | |
6bd08127 | 555 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 556 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 557 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 558 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 559 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 560 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 561 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
562 | DMA_CCR(imxdmac->channel)); |
563 | ||
ac806a1c RK |
564 | dev_dbg(imxdma->dev, |
565 | "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n", | |
566 | __func__, imxdmac->channel, | |
567 | d->sg, d->sgcount, d->len, | |
568 | (unsigned long long)imxdmac->per_address); | |
359291a1 | 569 | } else if (d->direction == DMA_MEM_TO_DEV) { |
cd5cf9da | 570 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 571 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 572 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
573 | DMA_CCR(imxdmac->channel)); |
574 | ||
ac806a1c RK |
575 | dev_dbg(imxdma->dev, |
576 | "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n", | |
577 | __func__, imxdmac->channel, | |
578 | d->sg, d->sgcount, d->len, | |
579 | (unsigned long long)imxdmac->per_address); | |
359291a1 JM |
580 | } else { |
581 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
582 | __func__, imxdmac->channel); | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
a6cbb2d8 | 586 | imxdma_sg_next(d); |
1f1846c6 | 587 | |
9e15db7c JM |
588 | break; |
589 | default: | |
590 | return -EINVAL; | |
591 | } | |
2efc3449 | 592 | imxdma_enable_hw(d); |
9e15db7c | 593 | return 0; |
1f1846c6 SH |
594 | } |
595 | ||
cce010a5 | 596 | static void imxdma_tasklet(struct tasklet_struct *t) |
1f1846c6 | 597 | { |
cce010a5 | 598 | struct imxdma_channel *imxdmac = from_tasklet(imxdmac, t, dma_tasklet); |
9e15db7c | 599 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
341198ed | 600 | struct imxdma_desc *desc, *next_desc; |
5a276fa6 | 601 | unsigned long flags; |
1f1846c6 | 602 | |
5a276fa6 | 603 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
604 | |
605 | if (list_empty(&imxdmac->ld_active)) { | |
606 | /* Someone might have called terminate all */ | |
fcaaba6c MG |
607 | spin_unlock_irqrestore(&imxdma->lock, flags); |
608 | return; | |
9e15db7c JM |
609 | } |
610 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
611 | ||
d73111c6 MI |
612 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
613 | * and dont mark the descriptor as complete. | |
60f2951e VK |
614 | * Only in non-cyclic cases it would be marked as complete |
615 | */ | |
9e15db7c JM |
616 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
617 | goto out; | |
60f2951e VK |
618 | else |
619 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 620 | |
f606ab89 JM |
621 | /* Free 2D slot if it was an interleaved transfer */ |
622 | if (imxdmac->enabled_2d) { | |
623 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
624 | imxdmac->enabled_2d = false; | |
625 | } | |
626 | ||
9e15db7c JM |
627 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
628 | ||
629 | if (!list_empty(&imxdmac->ld_queue)) { | |
341198ed LI |
630 | next_desc = list_first_entry(&imxdmac->ld_queue, |
631 | struct imxdma_desc, node); | |
9e15db7c | 632 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); |
341198ed | 633 | if (imxdma_xfer_desc(next_desc) < 0) |
9e15db7c JM |
634 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", |
635 | __func__, imxdmac->channel); | |
636 | } | |
637 | out: | |
5a276fa6 | 638 | spin_unlock_irqrestore(&imxdma->lock, flags); |
fcaaba6c | 639 | |
be5af285 | 640 | dmaengine_desc_get_callback_invoke(&desc->desc, NULL); |
1f1846c6 SH |
641 | } |
642 | ||
502c2ef2 | 643 | static int imxdma_terminate_all(struct dma_chan *chan) |
1f1846c6 SH |
644 | { |
645 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
cd5cf9da | 646 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 647 | unsigned long flags; |
9e15db7c | 648 | |
502c2ef2 | 649 | imxdma_disable_hw(imxdmac); |
1f1846c6 | 650 | |
502c2ef2 MR |
651 | spin_lock_irqsave(&imxdma->lock, flags); |
652 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
653 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
654 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
655 | return 0; | |
656 | } | |
bef2a8d3 | 657 | |
dea7a9fb VK |
658 | static int imxdma_config_write(struct dma_chan *chan, |
659 | struct dma_slave_config *dmaengine_cfg, | |
660 | enum dma_transfer_direction direction) | |
502c2ef2 MR |
661 | { |
662 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
663 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
664 | unsigned int mode = 0; | |
bdc0c753 | 665 | |
dea7a9fb | 666 | if (direction == DMA_DEV_TO_MEM) { |
502c2ef2 MR |
667 | imxdmac->per_address = dmaengine_cfg->src_addr; |
668 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
669 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
670 | } else { | |
671 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
672 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
673 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
674 | } | |
1f1846c6 | 675 | |
502c2ef2 MR |
676 | switch (imxdmac->word_size) { |
677 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
678 | mode = IMX_DMA_MEMSIZE_8; | |
679 | break; | |
680 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
681 | mode = IMX_DMA_MEMSIZE_16; | |
682 | break; | |
1f1846c6 | 683 | default: |
502c2ef2 MR |
684 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
685 | mode = IMX_DMA_MEMSIZE_32; | |
686 | break; | |
1f1846c6 SH |
687 | } |
688 | ||
502c2ef2 MR |
689 | imxdmac->hw_chaining = 0; |
690 | ||
691 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | | |
692 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | | |
693 | CCR_REN; | |
694 | imxdmac->ccr_to_device = | |
695 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | | |
696 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
697 | imx_dmav1_writel(imxdma, imxdmac->dma_request, | |
698 | DMA_RSSR(imxdmac->channel)); | |
699 | ||
700 | /* Set burst length */ | |
701 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * | |
702 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
703 | ||
704 | return 0; | |
1f1846c6 SH |
705 | } |
706 | ||
dea7a9fb VK |
707 | static int imxdma_config(struct dma_chan *chan, |
708 | struct dma_slave_config *dmaengine_cfg) | |
709 | { | |
710 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
711 | ||
712 | memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg)); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
1f1846c6 SH |
717 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, |
718 | dma_cookie_t cookie, | |
719 | struct dma_tx_state *txstate) | |
720 | { | |
96a2af41 | 721 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
722 | } |
723 | ||
724 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
725 | { | |
726 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 727 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 728 | dma_cookie_t cookie; |
9e15db7c | 729 | unsigned long flags; |
1f1846c6 | 730 | |
f606ab89 | 731 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 732 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 733 | cookie = dma_cookie_assign(tx); |
f606ab89 | 734 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
735 | |
736 | return cookie; | |
737 | } | |
738 | ||
739 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
740 | { | |
741 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
742 | struct imx_dma_data *data = chan->private; | |
743 | ||
6c05f091 JM |
744 | if (data != NULL) |
745 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 746 | |
9e15db7c JM |
747 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
748 | struct imxdma_desc *desc; | |
1f1846c6 | 749 | |
9e15db7c JM |
750 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
751 | if (!desc) | |
752 | break; | |
ff5fdafc | 753 | memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor)); |
9e15db7c JM |
754 | dma_async_tx_descriptor_init(&desc->desc, chan); |
755 | desc->desc.tx_submit = imxdma_tx_submit; | |
756 | /* txd.flags will be overwritten in prep funcs */ | |
757 | desc->desc.flags = DMA_CTRL_ACK; | |
3ded1ad1 | 758 | desc->status = DMA_COMPLETE; |
9e15db7c JM |
759 | |
760 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
761 | imxdmac->descs_allocated++; | |
762 | } | |
1f1846c6 | 763 | |
9e15db7c JM |
764 | if (!imxdmac->descs_allocated) |
765 | return -ENOMEM; | |
766 | ||
767 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
768 | } |
769 | ||
770 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
771 | { | |
772 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 773 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
774 | struct imxdma_desc *desc, *_desc; |
775 | unsigned long flags; | |
776 | ||
f606ab89 | 777 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 778 | |
6bd08127 | 779 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
780 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
781 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 782 | |
f606ab89 | 783 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
784 | |
785 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
786 | kfree(desc); | |
787 | imxdmac->descs_allocated--; | |
788 | } | |
789 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 | 790 | |
06f8db4b SK |
791 | kfree(imxdmac->sg_list); |
792 | imxdmac->sg_list = NULL; | |
1f1846c6 SH |
793 | } |
794 | ||
795 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
796 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 797 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 798 | unsigned long flags, void *context) |
1f1846c6 SH |
799 | { |
800 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
801 | struct scatterlist *sg; | |
9e15db7c JM |
802 | int i, dma_length = 0; |
803 | struct imxdma_desc *desc; | |
1f1846c6 | 804 | |
9e15db7c JM |
805 | if (list_empty(&imxdmac->ld_free) || |
806 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
807 | return NULL; |
808 | ||
9e15db7c | 809 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
810 | |
811 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 812 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
813 | } |
814 | ||
7199dded JB |
815 | imxdma_config_write(chan, &imxdmac->config, direction); |
816 | ||
d07102a1 SH |
817 | switch (imxdmac->word_size) { |
818 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 819 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
820 | return NULL; |
821 | break; | |
822 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 823 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
824 | return NULL; |
825 | break; | |
826 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
827 | break; | |
828 | default: | |
829 | return NULL; | |
830 | } | |
831 | ||
9e15db7c JM |
832 | desc->type = IMXDMA_DESC_SLAVE_SG; |
833 | desc->sg = sgl; | |
834 | desc->sgcount = sg_len; | |
835 | desc->len = dma_length; | |
2efc3449 | 836 | desc->direction = direction; |
9e15db7c | 837 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
838 | desc->src = imxdmac->per_address; |
839 | } else { | |
9e15db7c JM |
840 | desc->dest = imxdmac->per_address; |
841 | } | |
842 | desc->desc.callback = NULL; | |
843 | desc->desc.callback_param = NULL; | |
1f1846c6 | 844 | |
9e15db7c | 845 | return &desc->desc; |
1f1846c6 SH |
846 | } |
847 | ||
848 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
849 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 850 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 851 | unsigned long flags) |
1f1846c6 SH |
852 | { |
853 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
854 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
855 | struct imxdma_desc *desc; |
856 | int i; | |
1f1846c6 | 857 | unsigned int periods = buf_len / period_len; |
1f1846c6 | 858 | |
ac806a1c | 859 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n", |
1f1846c6 SH |
860 | __func__, imxdmac->channel, buf_len, period_len); |
861 | ||
9e15db7c JM |
862 | if (list_empty(&imxdmac->ld_free) || |
863 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 864 | return NULL; |
1f1846c6 | 865 | |
9e15db7c | 866 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 | 867 | |
96a3713e | 868 | kfree(imxdmac->sg_list); |
1f1846c6 SH |
869 | |
870 | imxdmac->sg_list = kcalloc(periods + 1, | |
edc530fe | 871 | sizeof(struct scatterlist), GFP_ATOMIC); |
1f1846c6 SH |
872 | if (!imxdmac->sg_list) |
873 | return NULL; | |
874 | ||
875 | sg_init_table(imxdmac->sg_list, periods); | |
876 | ||
877 | for (i = 0; i < periods; i++) { | |
ce818013 | 878 | sg_assign_page(&imxdmac->sg_list[i], NULL); |
1f1846c6 SH |
879 | imxdmac->sg_list[i].offset = 0; |
880 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 881 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
882 | dma_addr += period_len; |
883 | } | |
884 | ||
885 | /* close the loop */ | |
ce818013 | 886 | sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list); |
1f1846c6 | 887 | |
9e15db7c JM |
888 | desc->type = IMXDMA_DESC_CYCLIC; |
889 | desc->sg = imxdmac->sg_list; | |
890 | desc->sgcount = periods; | |
891 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 892 | desc->direction = direction; |
9e15db7c | 893 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
894 | desc->src = imxdmac->per_address; |
895 | } else { | |
9e15db7c JM |
896 | desc->dest = imxdmac->per_address; |
897 | } | |
898 | desc->desc.callback = NULL; | |
899 | desc->desc.callback_param = NULL; | |
1f1846c6 | 900 | |
dea7a9fb VK |
901 | imxdma_config_write(chan, &imxdmac->config, direction); |
902 | ||
9e15db7c | 903 | return &desc->desc; |
1f1846c6 SH |
904 | } |
905 | ||
6c05f091 JM |
906 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
907 | struct dma_chan *chan, dma_addr_t dest, | |
908 | dma_addr_t src, size_t len, unsigned long flags) | |
909 | { | |
910 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
911 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 912 | struct imxdma_desc *desc; |
1f1846c6 | 913 | |
ac806a1c RK |
914 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n", |
915 | __func__, imxdmac->channel, (unsigned long long)src, | |
916 | (unsigned long long)dest, len); | |
6c05f091 | 917 | |
9e15db7c JM |
918 | if (list_empty(&imxdmac->ld_free) || |
919 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
920 | return NULL; |
921 | ||
9e15db7c | 922 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 923 | |
9e15db7c JM |
924 | desc->type = IMXDMA_DESC_MEMCPY; |
925 | desc->src = src; | |
926 | desc->dest = dest; | |
927 | desc->len = len; | |
2efc3449 | 928 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
929 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
930 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
931 | desc->desc.callback = NULL; | |
932 | desc->desc.callback_param = NULL; | |
6c05f091 | 933 | |
9e15db7c | 934 | return &desc->desc; |
6c05f091 JM |
935 | } |
936 | ||
f606ab89 JM |
937 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
938 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
939 | unsigned long flags) | |
940 | { | |
941 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
942 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
943 | struct imxdma_desc *desc; | |
944 | ||
ac806a1c RK |
945 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n" |
946 | " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__, | |
947 | imxdmac->channel, (unsigned long long)xt->src_start, | |
948 | (unsigned long long) xt->dst_start, | |
f606ab89 JM |
949 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", |
950 | xt->numf, xt->frame_size); | |
951 | ||
952 | if (list_empty(&imxdmac->ld_free) || | |
953 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
954 | return NULL; | |
955 | ||
956 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
957 | return NULL; | |
958 | ||
959 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
960 | ||
961 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
962 | desc->src = xt->src_start; | |
963 | desc->dest = xt->dst_start; | |
964 | desc->x = xt->sgl[0].size; | |
965 | desc->y = xt->numf; | |
966 | desc->w = xt->sgl[0].icg + desc->x; | |
967 | desc->len = desc->x * desc->y; | |
968 | desc->direction = DMA_MEM_TO_MEM; | |
969 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
970 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
971 | if (xt->src_sgl) | |
972 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
973 | if (xt->dst_sgl) | |
974 | desc->config_port |= IMX_DMA_TYPE_2D; | |
975 | desc->desc.callback = NULL; | |
976 | desc->desc.callback_param = NULL; | |
977 | ||
978 | return &desc->desc; | |
1f1846c6 SH |
979 | } |
980 | ||
981 | static void imxdma_issue_pending(struct dma_chan *chan) | |
982 | { | |
5b316876 | 983 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
984 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
985 | struct imxdma_desc *desc; | |
986 | unsigned long flags; | |
987 | ||
f606ab89 | 988 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
989 | if (list_empty(&imxdmac->ld_active) && |
990 | !list_empty(&imxdmac->ld_queue)) { | |
991 | desc = list_first_entry(&imxdmac->ld_queue, | |
992 | struct imxdma_desc, node); | |
993 | ||
994 | if (imxdma_xfer_desc(desc) < 0) { | |
995 | dev_warn(imxdma->dev, | |
996 | "%s: channel: %d couldn't issue DMA xfer\n", | |
997 | __func__, imxdmac->channel); | |
998 | } else { | |
999 | list_move_tail(imxdmac->ld_queue.next, | |
1000 | &imxdmac->ld_active); | |
1001 | } | |
1002 | } | |
f606ab89 | 1003 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
1004 | } |
1005 | ||
290ad0f9 MP |
1006 | static bool imxdma_filter_fn(struct dma_chan *chan, void *param) |
1007 | { | |
1008 | struct imxdma_filter_data *fdata = param; | |
1009 | struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); | |
1010 | ||
1011 | if (chan->device->dev != fdata->imxdma->dev) | |
1012 | return false; | |
1013 | ||
1014 | imxdma_chan->dma_request = fdata->request; | |
1015 | chan->private = NULL; | |
1016 | ||
1017 | return true; | |
1018 | } | |
1019 | ||
1020 | static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, | |
1021 | struct of_dma *ofdma) | |
1022 | { | |
1023 | int count = dma_spec->args_count; | |
1024 | struct imxdma_engine *imxdma = ofdma->of_dma_data; | |
1025 | struct imxdma_filter_data fdata = { | |
1026 | .imxdma = imxdma, | |
1027 | }; | |
1028 | ||
1029 | if (count != 1) | |
1030 | return NULL; | |
1031 | ||
1032 | fdata.request = dma_spec->args[0]; | |
1033 | ||
1034 | return dma_request_channel(imxdma->dma_device.cap_mask, | |
1035 | imxdma_filter_fn, &fdata); | |
1036 | } | |
1037 | ||
1f1846c6 | 1038 | static int __init imxdma_probe(struct platform_device *pdev) |
71c6b663 | 1039 | { |
1f1846c6 | 1040 | struct imxdma_engine *imxdma; |
73930eb3 | 1041 | struct resource *res; |
1f1846c6 | 1042 | int ret, i; |
73930eb3 | 1043 | int irq, irq_err; |
cd5cf9da | 1044 | |
04bbd8ef | 1045 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1046 | if (!imxdma) |
1047 | return -ENOMEM; | |
1048 | ||
5c6b3e77 | 1049 | imxdma->dev = &pdev->dev; |
0ab785c8 | 1050 | imxdma->devtype = (enum imx_dma_type)of_device_get_match_data(&pdev->dev); |
e51d0f0a | 1051 | |
73930eb3 | 1052 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1053 | imxdma->base = devm_ioremap_resource(&pdev->dev, res); |
1054 | if (IS_ERR(imxdma->base)) | |
1055 | return PTR_ERR(imxdma->base); | |
73930eb3 SG |
1056 | |
1057 | irq = platform_get_irq(pdev, 0); | |
1058 | if (irq < 0) | |
1059 | return irq; | |
6bd08127 | 1060 | |
a2367db2 | 1061 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1062 | if (IS_ERR(imxdma->dma_ipg)) |
1063 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1064 | |
1065 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1066 | if (IS_ERR(imxdma->dma_ahb)) |
1067 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 | 1068 | |
fce9a74b FE |
1069 | ret = clk_prepare_enable(imxdma->dma_ipg); |
1070 | if (ret) | |
1071 | return ret; | |
1072 | ret = clk_prepare_enable(imxdma->dma_ahb); | |
1073 | if (ret) | |
1074 | goto disable_dma_ipg_clk; | |
6bd08127 JM |
1075 | |
1076 | /* reset DMA module */ | |
cd5cf9da | 1077 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1078 | |
e51d0f0a | 1079 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1080 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1081 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1082 | if (ret) { |
f9b283a6 | 1083 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
fce9a74b | 1084 | goto disable_dma_ahb_clk; |
6bd08127 | 1085 | } |
ea62aa80 | 1086 | imxdma->irq = irq; |
6bd08127 | 1087 | |
73930eb3 SG |
1088 | irq_err = platform_get_irq(pdev, 1); |
1089 | if (irq_err < 0) { | |
1090 | ret = irq_err; | |
fce9a74b | 1091 | goto disable_dma_ahb_clk; |
73930eb3 SG |
1092 | } |
1093 | ||
1094 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1095 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1096 | if (ret) { |
f9b283a6 | 1097 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
fce9a74b | 1098 | goto disable_dma_ahb_clk; |
6bd08127 | 1099 | } |
ea62aa80 | 1100 | imxdma->irq_err = irq_err; |
6bd08127 JM |
1101 | } |
1102 | ||
1103 | /* enable DMA module */ | |
cd5cf9da | 1104 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1105 | |
1106 | /* clear all interrupts */ | |
cd5cf9da | 1107 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1108 | |
1109 | /* disable interrupts */ | |
cd5cf9da | 1110 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1111 | |
1112 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1113 | ||
f8a356ff SH |
1114 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1115 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1116 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1117 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1118 | ||
1119 | /* Initialize 2D global parameters */ | |
1120 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1121 | imxdma->slots_2d[i].count = 0; | |
1122 | ||
1123 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1124 | |
1f1846c6 | 1125 | /* Initialize channel parameters */ |
6bd08127 | 1126 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1127 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1128 | ||
e51d0f0a | 1129 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1130 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1131 | dma_irq_handler, 0, "DMA", imxdma); |
1132 | if (ret) { | |
f9b283a6 JM |
1133 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1134 | "for DMA channel %d\n", | |
73930eb3 | 1135 | irq + i, i); |
fce9a74b | 1136 | goto disable_dma_ahb_clk; |
6bd08127 | 1137 | } |
ea62aa80 VK |
1138 | |
1139 | imxdmac->irq = irq + i; | |
bcdc4bd3 | 1140 | timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0); |
8267f16e | 1141 | } |
1f1846c6 | 1142 | |
1f1846c6 | 1143 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1144 | |
9e15db7c JM |
1145 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1146 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1147 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1148 | ||
cce010a5 | 1149 | tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet); |
1f1846c6 | 1150 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1151 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1152 | imxdmac->channel = i; |
1153 | ||
1154 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1155 | list_add_tail(&imxdmac->chan.device_node, |
1156 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1157 | } |
1158 | ||
1f1846c6 SH |
1159 | imxdma->dma_device.dev = &pdev->dev; |
1160 | ||
1161 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1162 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1163 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1164 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1165 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1166 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1167 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
502c2ef2 MR |
1168 | imxdma->dma_device.device_config = imxdma_config; |
1169 | imxdma->dma_device.device_terminate_all = imxdma_terminate_all; | |
1f1846c6 SH |
1170 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; |
1171 | ||
1172 | platform_set_drvdata(pdev, imxdma); | |
1173 | ||
77a68e56 | 1174 | imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES; |
1e070a60 SH |
1175 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); |
1176 | ||
1f1846c6 SH |
1177 | ret = dma_async_device_register(&imxdma->dma_device); |
1178 | if (ret) { | |
1179 | dev_err(&pdev->dev, "unable to register\n"); | |
fce9a74b | 1180 | goto disable_dma_ahb_clk; |
1f1846c6 SH |
1181 | } |
1182 | ||
290ad0f9 MP |
1183 | if (pdev->dev.of_node) { |
1184 | ret = of_dma_controller_register(pdev->dev.of_node, | |
1185 | imxdma_xlate, imxdma); | |
1186 | if (ret) { | |
1187 | dev_err(&pdev->dev, "unable to register of_dma_controller\n"); | |
1188 | goto err_of_dma_controller; | |
1189 | } | |
1190 | } | |
1191 | ||
1f1846c6 SH |
1192 | return 0; |
1193 | ||
290ad0f9 MP |
1194 | err_of_dma_controller: |
1195 | dma_async_device_unregister(&imxdma->dma_device); | |
fce9a74b | 1196 | disable_dma_ahb_clk: |
a2367db2 | 1197 | clk_disable_unprepare(imxdma->dma_ahb); |
fce9a74b FE |
1198 | disable_dma_ipg_clk: |
1199 | clk_disable_unprepare(imxdma->dma_ipg); | |
1f1846c6 SH |
1200 | return ret; |
1201 | } | |
1202 | ||
ea62aa80 VK |
1203 | static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma) |
1204 | { | |
1205 | int i; | |
1206 | ||
1207 | if (is_imx1_dma(imxdma)) { | |
1208 | disable_irq(imxdma->irq); | |
1209 | disable_irq(imxdma->irq_err); | |
1210 | } | |
1211 | ||
1212 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
1213 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; | |
1214 | ||
1215 | if (!is_imx1_dma(imxdma)) | |
1216 | disable_irq(imxdmac->irq); | |
1217 | ||
1218 | tasklet_kill(&imxdmac->dma_tasklet); | |
1219 | } | |
1220 | } | |
1221 | ||
1d1bbd30 | 1222 | static int imxdma_remove(struct platform_device *pdev) |
1f1846c6 SH |
1223 | { |
1224 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 | 1225 | |
ea62aa80 VK |
1226 | imxdma_free_irq(pdev, imxdma); |
1227 | ||
1f1846c6 SH |
1228 | dma_async_device_unregister(&imxdma->dma_device); |
1229 | ||
290ad0f9 MP |
1230 | if (pdev->dev.of_node) |
1231 | of_dma_controller_free(pdev->dev.of_node); | |
1232 | ||
a2367db2 FE |
1233 | clk_disable_unprepare(imxdma->dma_ipg); |
1234 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1235 | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | static struct platform_driver imxdma_driver = { | |
1240 | .driver = { | |
1241 | .name = "imx-dma", | |
290ad0f9 | 1242 | .of_match_table = imx_dma_of_dev_id, |
1f1846c6 | 1243 | }, |
1d1bbd30 | 1244 | .remove = imxdma_remove, |
1f1846c6 SH |
1245 | }; |
1246 | ||
1247 | static int __init imxdma_module_init(void) | |
1248 | { | |
1249 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1250 | } | |
1251 | subsys_initcall(imxdma_module_init); | |
1252 | ||
1253 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1254 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1255 | MODULE_LICENSE("GPL"); |