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ce9c28ca FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // drivers/dma/imx-dma.c | |
4 | // | |
5 | // This file contains a driver for the Freescale i.MX DMA engine | |
6 | // found on i.MX1/21/27 | |
7 | // | |
8 | // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9 | // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> | |
10 | ||
7331205a | 11 | #include <linux/err.h> |
1f1846c6 SH |
12 | #include <linux/init.h> |
13 | #include <linux/types.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/platform_device.h> | |
6bd08127 | 21 | #include <linux/clk.h> |
1f1846c6 | 22 | #include <linux/dmaengine.h> |
5c45ad77 | 23 | #include <linux/module.h> |
290ad0f9 MP |
24 | #include <linux/of_device.h> |
25 | #include <linux/of_dma.h> | |
1f1846c6 SH |
26 | |
27 | #include <asm/irq.h> | |
82906b13 | 28 | #include <linux/platform_data/dma-imx.h> |
1f1846c6 | 29 | |
d2ebfb33 | 30 | #include "dmaengine.h" |
9e15db7c | 31 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
32 | #define IMX_DMA_CHANNELS 16 |
33 | ||
f606ab89 JM |
34 | #define IMX_DMA_2D_SLOTS 2 |
35 | #define IMX_DMA_2D_SLOT_A 0 | |
36 | #define IMX_DMA_2D_SLOT_B 1 | |
37 | ||
6bd08127 JM |
38 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
39 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
40 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
41 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
42 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
43 | #define IMX_DMA_TYPE_2D (1 << 10) | |
44 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
45 | ||
46 | #define IMX_DMA_ERR_BURST (1 << 0) | |
47 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
48 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
49 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
50 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
51 | ||
52 | #define DMA_DCR 0x00 /* Control Register */ | |
53 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
54 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
55 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
56 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
57 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
58 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
59 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
60 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
61 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
62 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
63 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
64 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
65 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
66 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
67 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
68 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
69 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
70 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
71 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
72 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
73 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
74 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
75 | ||
76 | #define DCR_DRST (1<<1) | |
77 | #define DCR_DEN (1<<0) | |
78 | #define DBTOCR_EN (1<<15) | |
79 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
80 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
81 | #define CCR_ACRPT (1<<14) | |
82 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
83 | #define CCR_DMOD_2D (0x1 << 12) | |
84 | #define CCR_DMOD_FIFO (0x2 << 12) | |
85 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
86 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
87 | #define CCR_SMOD_2D (0x1 << 10) | |
88 | #define CCR_SMOD_FIFO (0x2 << 10) | |
89 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
90 | #define CCR_MDIR_DEC (1<<9) | |
91 | #define CCR_MSEL_B (1<<8) | |
92 | #define CCR_DSIZ_32 (0x0 << 6) | |
93 | #define CCR_DSIZ_8 (0x1 << 6) | |
94 | #define CCR_DSIZ_16 (0x2 << 6) | |
95 | #define CCR_SSIZ_32 (0x0 << 4) | |
96 | #define CCR_SSIZ_8 (0x1 << 4) | |
97 | #define CCR_SSIZ_16 (0x2 << 4) | |
98 | #define CCR_REN (1<<3) | |
99 | #define CCR_RPT (1<<2) | |
100 | #define CCR_FRC (1<<1) | |
101 | #define CCR_CEN (1<<0) | |
102 | #define RTOR_EN (1<<15) | |
103 | #define RTOR_CLK (1<<14) | |
104 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
105 | |
106 | enum imxdma_prep_type { | |
107 | IMXDMA_DESC_MEMCPY, | |
108 | IMXDMA_DESC_INTERLEAVED, | |
109 | IMXDMA_DESC_SLAVE_SG, | |
110 | IMXDMA_DESC_CYCLIC, | |
111 | }; | |
112 | ||
f606ab89 JM |
113 | struct imx_dma_2d_config { |
114 | u16 xsr; | |
115 | u16 ysr; | |
116 | u16 wsr; | |
117 | int count; | |
118 | }; | |
119 | ||
9e15db7c JM |
120 | struct imxdma_desc { |
121 | struct list_head node; | |
122 | struct dma_async_tx_descriptor desc; | |
123 | enum dma_status status; | |
124 | dma_addr_t src; | |
125 | dma_addr_t dest; | |
126 | size_t len; | |
2efc3449 | 127 | enum dma_transfer_direction direction; |
9e15db7c JM |
128 | enum imxdma_prep_type type; |
129 | /* For memcpy and interleaved */ | |
130 | unsigned int config_port; | |
131 | unsigned int config_mem; | |
132 | /* For interleaved transfers */ | |
133 | unsigned int x; | |
134 | unsigned int y; | |
135 | unsigned int w; | |
136 | /* For slave sg and cyclic */ | |
137 | struct scatterlist *sg; | |
138 | unsigned int sgcount; | |
139 | }; | |
140 | ||
1f1846c6 | 141 | struct imxdma_channel { |
2d9c2fc5 JM |
142 | int hw_chaining; |
143 | struct timer_list watchdog; | |
1f1846c6 SH |
144 | struct imxdma_engine *imxdma; |
145 | unsigned int channel; | |
1f1846c6 | 146 | |
9e15db7c JM |
147 | struct tasklet_struct dma_tasklet; |
148 | struct list_head ld_free; | |
149 | struct list_head ld_queue; | |
150 | struct list_head ld_active; | |
151 | int descs_allocated; | |
1f1846c6 SH |
152 | enum dma_slave_buswidth word_size; |
153 | dma_addr_t per_address; | |
154 | u32 watermark_level; | |
155 | struct dma_chan chan; | |
1f1846c6 | 156 | struct dma_async_tx_descriptor desc; |
1f1846c6 SH |
157 | enum dma_status status; |
158 | int dma_request; | |
159 | struct scatterlist *sg_list; | |
359291a1 JM |
160 | u32 ccr_from_device; |
161 | u32 ccr_to_device; | |
f606ab89 JM |
162 | bool enabled_2d; |
163 | int slot_2d; | |
ea62aa80 | 164 | unsigned int irq; |
dea7a9fb | 165 | struct dma_slave_config config; |
1f1846c6 SH |
166 | }; |
167 | ||
e51d0f0a SG |
168 | enum imx_dma_type { |
169 | IMX1_DMA, | |
170 | IMX21_DMA, | |
171 | IMX27_DMA, | |
172 | }; | |
173 | ||
1f1846c6 SH |
174 | struct imxdma_engine { |
175 | struct device *dev; | |
1e070a60 | 176 | struct device_dma_parameters dma_parms; |
1f1846c6 | 177 | struct dma_device dma_device; |
cd5cf9da | 178 | void __iomem *base; |
a2367db2 FE |
179 | struct clk *dma_ahb; |
180 | struct clk *dma_ipg; | |
f606ab89 JM |
181 | spinlock_t lock; |
182 | struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS]; | |
6bd08127 | 183 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
e51d0f0a | 184 | enum imx_dma_type devtype; |
ea62aa80 VK |
185 | unsigned int irq; |
186 | unsigned int irq_err; | |
187 | ||
1f1846c6 SH |
188 | }; |
189 | ||
290ad0f9 MP |
190 | struct imxdma_filter_data { |
191 | struct imxdma_engine *imxdma; | |
192 | int request; | |
193 | }; | |
194 | ||
afe7cded | 195 | static const struct platform_device_id imx_dma_devtype[] = { |
e51d0f0a SG |
196 | { |
197 | .name = "imx1-dma", | |
198 | .driver_data = IMX1_DMA, | |
199 | }, { | |
200 | .name = "imx21-dma", | |
201 | .driver_data = IMX21_DMA, | |
202 | }, { | |
203 | .name = "imx27-dma", | |
204 | .driver_data = IMX27_DMA, | |
205 | }, { | |
206 | /* sentinel */ | |
207 | } | |
208 | }; | |
209 | MODULE_DEVICE_TABLE(platform, imx_dma_devtype); | |
210 | ||
290ad0f9 MP |
211 | static const struct of_device_id imx_dma_of_dev_id[] = { |
212 | { | |
213 | .compatible = "fsl,imx1-dma", | |
214 | .data = &imx_dma_devtype[IMX1_DMA], | |
215 | }, { | |
216 | .compatible = "fsl,imx21-dma", | |
217 | .data = &imx_dma_devtype[IMX21_DMA], | |
218 | }, { | |
219 | .compatible = "fsl,imx27-dma", | |
220 | .data = &imx_dma_devtype[IMX27_DMA], | |
221 | }, { | |
222 | /* sentinel */ | |
223 | } | |
224 | }; | |
225 | MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id); | |
226 | ||
e51d0f0a SG |
227 | static inline int is_imx1_dma(struct imxdma_engine *imxdma) |
228 | { | |
229 | return imxdma->devtype == IMX1_DMA; | |
230 | } | |
231 | ||
e51d0f0a SG |
232 | static inline int is_imx27_dma(struct imxdma_engine *imxdma) |
233 | { | |
234 | return imxdma->devtype == IMX27_DMA; | |
235 | } | |
236 | ||
1f1846c6 SH |
237 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) |
238 | { | |
239 | return container_of(chan, struct imxdma_channel, chan); | |
240 | } | |
241 | ||
9e15db7c | 242 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 243 | { |
9e15db7c JM |
244 | struct imxdma_desc *desc; |
245 | ||
246 | if (!list_empty(&imxdmac->ld_active)) { | |
247 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
248 | node); | |
249 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
250 | return true; | |
251 | } | |
252 | return false; | |
1f1846c6 SH |
253 | } |
254 | ||
6bd08127 | 255 | |
cd5cf9da JM |
256 | |
257 | static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val, | |
258 | unsigned offset) | |
6bd08127 | 259 | { |
cd5cf9da | 260 | __raw_writel(val, imxdma->base + offset); |
6bd08127 JM |
261 | } |
262 | ||
cd5cf9da | 263 | static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset) |
1f1846c6 | 264 | { |
cd5cf9da | 265 | return __raw_readl(imxdma->base + offset); |
6bd08127 | 266 | } |
1f1846c6 | 267 | |
2d9c2fc5 | 268 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 | 269 | { |
e51d0f0a SG |
270 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
271 | ||
272 | if (is_imx27_dma(imxdma)) | |
2d9c2fc5 | 273 | return imxdmac->hw_chaining; |
6bd08127 JM |
274 | else |
275 | return 0; | |
276 | } | |
277 | ||
278 | /* | |
279 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
280 | */ | |
452fd6dc | 281 | static inline void imxdma_sg_next(struct imxdma_desc *d) |
1f1846c6 | 282 | { |
2efc3449 | 283 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 284 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
a6cbb2d8 | 285 | struct scatterlist *sg = d->sg; |
da5035f3 | 286 | size_t now; |
6bd08127 | 287 | |
9227ab56 | 288 | now = min_t(size_t, d->len, sg_dma_len(sg)); |
6b0e2f55 JM |
289 | if (d->len != IMX_DMA_LENGTH_LOOP) |
290 | d->len -= now; | |
6bd08127 | 291 | |
2efc3449 | 292 | if (d->direction == DMA_DEV_TO_MEM) |
cd5cf9da JM |
293 | imx_dmav1_writel(imxdma, sg->dma_address, |
294 | DMA_DAR(imxdmac->channel)); | |
6bd08127 | 295 | else |
cd5cf9da JM |
296 | imx_dmav1_writel(imxdma, sg->dma_address, |
297 | DMA_SAR(imxdmac->channel)); | |
6bd08127 | 298 | |
cd5cf9da | 299 | imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); |
6bd08127 | 300 | |
f9b283a6 JM |
301 | dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " |
302 | "size 0x%08x\n", __func__, imxdmac->channel, | |
cd5cf9da JM |
303 | imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), |
304 | imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), | |
305 | imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); | |
1f1846c6 SH |
306 | } |
307 | ||
2efc3449 | 308 | static void imxdma_enable_hw(struct imxdma_desc *d) |
1f1846c6 | 309 | { |
2efc3449 | 310 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
cd5cf9da | 311 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
312 | int channel = imxdmac->channel; |
313 | unsigned long flags; | |
314 | ||
f9b283a6 | 315 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 316 | |
6bd08127 JM |
317 | local_irq_save(flags); |
318 | ||
cd5cf9da JM |
319 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); |
320 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) & | |
321 | ~(1 << channel), DMA_DIMR); | |
322 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | | |
323 | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); | |
6bd08127 | 324 | |
e51d0f0a | 325 | if (!is_imx1_dma(imxdma) && |
2d9c2fc5 | 326 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
327 | d->sg = sg_next(d->sg); |
328 | if (d->sg) { | |
6bd08127 | 329 | u32 tmp; |
a6cbb2d8 | 330 | imxdma_sg_next(d); |
cd5cf9da JM |
331 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); |
332 | imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT, | |
333 | DMA_CCR(channel)); | |
6bd08127 JM |
334 | } |
335 | } | |
6bd08127 JM |
336 | |
337 | local_irq_restore(flags); | |
338 | } | |
339 | ||
340 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
341 | { | |
cd5cf9da | 342 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 JM |
343 | int channel = imxdmac->channel; |
344 | unsigned long flags; | |
345 | ||
f9b283a6 | 346 | dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel); |
6bd08127 | 347 | |
2d9c2fc5 JM |
348 | if (imxdma_hw_chain(imxdmac)) |
349 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
350 | |
351 | local_irq_save(flags); | |
cd5cf9da JM |
352 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) | |
353 | (1 << channel), DMA_DIMR); | |
354 | imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & | |
355 | ~CCR_CEN, DMA_CCR(channel)); | |
356 | imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR); | |
6bd08127 JM |
357 | local_irq_restore(flags); |
358 | } | |
359 | ||
bcdc4bd3 | 360 | static void imxdma_watchdog(struct timer_list *t) |
1f1846c6 | 361 | { |
bcdc4bd3 | 362 | struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog); |
cd5cf9da | 363 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 364 | int channel = imxdmac->channel; |
1f1846c6 | 365 | |
cd5cf9da | 366 | imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); |
1f1846c6 | 367 | |
6bd08127 | 368 | /* Tasklet watchdog error handler */ |
9e15db7c | 369 | tasklet_schedule(&imxdmac->dma_tasklet); |
f9b283a6 JM |
370 | dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n", |
371 | imxdmac->channel); | |
1f1846c6 SH |
372 | } |
373 | ||
6bd08127 | 374 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) |
1f1846c6 | 375 | { |
6bd08127 | 376 | struct imxdma_engine *imxdma = dev_id; |
6bd08127 JM |
377 | unsigned int err_mask; |
378 | int i, disr; | |
379 | int errcode; | |
380 | ||
cd5cf9da | 381 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 382 | |
cd5cf9da JM |
383 | err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) | |
384 | imx_dmav1_readl(imxdma, DMA_DRTOSR) | | |
385 | imx_dmav1_readl(imxdma, DMA_DSESR) | | |
386 | imx_dmav1_readl(imxdma, DMA_DBOSR); | |
6bd08127 JM |
387 | |
388 | if (!err_mask) | |
389 | return IRQ_HANDLED; | |
390 | ||
cd5cf9da | 391 | imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR); |
6bd08127 JM |
392 | |
393 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
394 | if (!(err_mask & (1 << i))) | |
395 | continue; | |
6bd08127 JM |
396 | errcode = 0; |
397 | ||
cd5cf9da JM |
398 | if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) { |
399 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR); | |
6bd08127 JM |
400 | errcode |= IMX_DMA_ERR_BURST; |
401 | } | |
cd5cf9da JM |
402 | if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) { |
403 | imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR); | |
6bd08127 JM |
404 | errcode |= IMX_DMA_ERR_REQUEST; |
405 | } | |
cd5cf9da JM |
406 | if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) { |
407 | imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR); | |
6bd08127 JM |
408 | errcode |= IMX_DMA_ERR_TRANSFER; |
409 | } | |
cd5cf9da JM |
410 | if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) { |
411 | imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR); | |
6bd08127 JM |
412 | errcode |= IMX_DMA_ERR_BUFFER; |
413 | } | |
414 | /* Tasklet error handler */ | |
415 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
416 | ||
1d94fe06 AS |
417 | dev_warn(imxdma->dev, |
418 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
419 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
420 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
421 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
422 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
6bd08127 JM |
423 | } |
424 | return IRQ_HANDLED; | |
1f1846c6 SH |
425 | } |
426 | ||
6bd08127 | 427 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 428 | { |
cd5cf9da | 429 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
6bd08127 | 430 | int chno = imxdmac->channel; |
2efc3449 | 431 | struct imxdma_desc *desc; |
5a276fa6 | 432 | unsigned long flags; |
6bd08127 | 433 | |
5a276fa6 | 434 | spin_lock_irqsave(&imxdma->lock, flags); |
833bc03b | 435 | if (list_empty(&imxdmac->ld_active)) { |
5a276fa6 | 436 | spin_unlock_irqrestore(&imxdma->lock, flags); |
833bc03b JM |
437 | goto out; |
438 | } | |
2efc3449 | 439 | |
833bc03b JM |
440 | desc = list_first_entry(&imxdmac->ld_active, |
441 | struct imxdma_desc, | |
442 | node); | |
5a276fa6 | 443 | spin_unlock_irqrestore(&imxdma->lock, flags); |
2efc3449 | 444 | |
833bc03b JM |
445 | if (desc->sg) { |
446 | u32 tmp; | |
447 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 448 | |
833bc03b | 449 | if (desc->sg) { |
a6cbb2d8 | 450 | imxdma_sg_next(desc); |
6bd08127 | 451 | |
cd5cf9da | 452 | tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); |
6bd08127 | 453 | |
2d9c2fc5 | 454 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
455 | /* FIXME: The timeout should probably be |
456 | * configurable | |
457 | */ | |
2d9c2fc5 | 458 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
459 | jiffies + msecs_to_jiffies(500)); |
460 | ||
461 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
cd5cf9da | 462 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 | 463 | } else { |
cd5cf9da JM |
464 | imx_dmav1_writel(imxdma, tmp & ~CCR_CEN, |
465 | DMA_CCR(chno)); | |
6bd08127 JM |
466 | tmp |= CCR_CEN; |
467 | } | |
468 | ||
cd5cf9da | 469 | imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); |
6bd08127 JM |
470 | |
471 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
472 | /* Tasklet progression */ | |
473 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 474 | |
6bd08127 JM |
475 | return; |
476 | } | |
477 | ||
2d9c2fc5 JM |
478 | if (imxdma_hw_chain(imxdmac)) { |
479 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
480 | return; |
481 | } | |
482 | } | |
483 | ||
2efc3449 | 484 | out: |
cd5cf9da | 485 | imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); |
6bd08127 | 486 | /* Tasklet irq */ |
9e15db7c JM |
487 | tasklet_schedule(&imxdmac->dma_tasklet); |
488 | } | |
489 | ||
6bd08127 JM |
490 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
491 | { | |
492 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
493 | int i, disr; |
494 | ||
e51d0f0a | 495 | if (!is_imx1_dma(imxdma)) |
6bd08127 JM |
496 | imxdma_err_handler(irq, dev_id); |
497 | ||
cd5cf9da | 498 | disr = imx_dmav1_readl(imxdma, DMA_DISR); |
6bd08127 | 499 | |
f9b283a6 | 500 | dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr); |
6bd08127 | 501 | |
cd5cf9da | 502 | imx_dmav1_writel(imxdma, disr, DMA_DISR); |
6bd08127 | 503 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
2d9c2fc5 | 504 | if (disr & (1 << i)) |
6bd08127 | 505 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
506 | } |
507 | ||
508 | return IRQ_HANDLED; | |
509 | } | |
510 | ||
9e15db7c JM |
511 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
512 | { | |
513 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 514 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
f606ab89 JM |
515 | int slot = -1; |
516 | int i; | |
9e15db7c JM |
517 | |
518 | /* Configure and enable */ | |
519 | switch (d->type) { | |
f606ab89 JM |
520 | case IMXDMA_DESC_INTERLEAVED: |
521 | /* Try to get a free 2D slot */ | |
f606ab89 JM |
522 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) { |
523 | if ((imxdma->slots_2d[i].count > 0) && | |
524 | ((imxdma->slots_2d[i].xsr != d->x) || | |
525 | (imxdma->slots_2d[i].ysr != d->y) || | |
526 | (imxdma->slots_2d[i].wsr != d->w))) | |
527 | continue; | |
528 | slot = i; | |
529 | break; | |
530 | } | |
5a276fa6 | 531 | if (slot < 0) |
f606ab89 JM |
532 | return -EBUSY; |
533 | ||
534 | imxdma->slots_2d[slot].xsr = d->x; | |
535 | imxdma->slots_2d[slot].ysr = d->y; | |
536 | imxdma->slots_2d[slot].wsr = d->w; | |
537 | imxdma->slots_2d[slot].count++; | |
538 | ||
539 | imxdmac->slot_2d = slot; | |
540 | imxdmac->enabled_2d = true; | |
f606ab89 JM |
541 | |
542 | if (slot == IMX_DMA_2D_SLOT_A) { | |
543 | d->config_mem &= ~CCR_MSEL_B; | |
544 | d->config_port &= ~CCR_MSEL_B; | |
545 | imx_dmav1_writel(imxdma, d->x, DMA_XSRA); | |
546 | imx_dmav1_writel(imxdma, d->y, DMA_YSRA); | |
547 | imx_dmav1_writel(imxdma, d->w, DMA_WSRA); | |
548 | } else { | |
549 | d->config_mem |= CCR_MSEL_B; | |
550 | d->config_port |= CCR_MSEL_B; | |
551 | imx_dmav1_writel(imxdma, d->x, DMA_XSRB); | |
552 | imx_dmav1_writel(imxdma, d->y, DMA_YSRB); | |
553 | imx_dmav1_writel(imxdma, d->w, DMA_WSRB); | |
554 | } | |
555 | /* | |
556 | * We fall-through here intentionally, since a 2D transfer is | |
557 | * similar to MEMCPY just adding the 2D slot configuration. | |
558 | */ | |
9e15db7c | 559 | case IMXDMA_DESC_MEMCPY: |
cd5cf9da JM |
560 | imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel)); |
561 | imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel)); | |
562 | imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2), | |
3b4b6dfc | 563 | DMA_CCR(imxdmac->channel)); |
6bd08127 | 564 | |
cd5cf9da | 565 | imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel)); |
3b4b6dfc | 566 | |
ac806a1c RK |
567 | dev_dbg(imxdma->dev, |
568 | "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n", | |
569 | __func__, imxdmac->channel, | |
570 | (unsigned long long)d->dest, | |
571 | (unsigned long long)d->src, d->len); | |
3b4b6dfc JM |
572 | |
573 | break; | |
6bd08127 | 574 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 575 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 576 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 | 577 | if (d->direction == DMA_DEV_TO_MEM) { |
cd5cf9da | 578 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 579 | DMA_SAR(imxdmac->channel)); |
cd5cf9da | 580 | imx_dmav1_writel(imxdma, imxdmac->ccr_from_device, |
359291a1 JM |
581 | DMA_CCR(imxdmac->channel)); |
582 | ||
ac806a1c RK |
583 | dev_dbg(imxdma->dev, |
584 | "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n", | |
585 | __func__, imxdmac->channel, | |
586 | d->sg, d->sgcount, d->len, | |
587 | (unsigned long long)imxdmac->per_address); | |
359291a1 | 588 | } else if (d->direction == DMA_MEM_TO_DEV) { |
cd5cf9da | 589 | imx_dmav1_writel(imxdma, imxdmac->per_address, |
359291a1 | 590 | DMA_DAR(imxdmac->channel)); |
cd5cf9da | 591 | imx_dmav1_writel(imxdma, imxdmac->ccr_to_device, |
359291a1 JM |
592 | DMA_CCR(imxdmac->channel)); |
593 | ||
ac806a1c RK |
594 | dev_dbg(imxdma->dev, |
595 | "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n", | |
596 | __func__, imxdmac->channel, | |
597 | d->sg, d->sgcount, d->len, | |
598 | (unsigned long long)imxdmac->per_address); | |
359291a1 JM |
599 | } else { |
600 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
601 | __func__, imxdmac->channel); | |
602 | return -EINVAL; | |
603 | } | |
604 | ||
a6cbb2d8 | 605 | imxdma_sg_next(d); |
1f1846c6 | 606 | |
9e15db7c JM |
607 | break; |
608 | default: | |
609 | return -EINVAL; | |
610 | } | |
2efc3449 | 611 | imxdma_enable_hw(d); |
9e15db7c | 612 | return 0; |
1f1846c6 SH |
613 | } |
614 | ||
9e15db7c | 615 | static void imxdma_tasklet(unsigned long data) |
1f1846c6 | 616 | { |
9e15db7c JM |
617 | struct imxdma_channel *imxdmac = (void *)data; |
618 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
341198ed | 619 | struct imxdma_desc *desc, *next_desc; |
5a276fa6 | 620 | unsigned long flags; |
1f1846c6 | 621 | |
5a276fa6 | 622 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
623 | |
624 | if (list_empty(&imxdmac->ld_active)) { | |
625 | /* Someone might have called terminate all */ | |
fcaaba6c MG |
626 | spin_unlock_irqrestore(&imxdma->lock, flags); |
627 | return; | |
9e15db7c JM |
628 | } |
629 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
630 | ||
d73111c6 MI |
631 | /* If we are dealing with a cyclic descriptor, keep it on ld_active |
632 | * and dont mark the descriptor as complete. | |
60f2951e VK |
633 | * Only in non-cyclic cases it would be marked as complete |
634 | */ | |
9e15db7c JM |
635 | if (imxdma_chan_is_doing_cyclic(imxdmac)) |
636 | goto out; | |
60f2951e VK |
637 | else |
638 | dma_cookie_complete(&desc->desc); | |
9e15db7c | 639 | |
f606ab89 JM |
640 | /* Free 2D slot if it was an interleaved transfer */ |
641 | if (imxdmac->enabled_2d) { | |
642 | imxdma->slots_2d[imxdmac->slot_2d].count--; | |
643 | imxdmac->enabled_2d = false; | |
644 | } | |
645 | ||
9e15db7c JM |
646 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); |
647 | ||
648 | if (!list_empty(&imxdmac->ld_queue)) { | |
341198ed LI |
649 | next_desc = list_first_entry(&imxdmac->ld_queue, |
650 | struct imxdma_desc, node); | |
9e15db7c | 651 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); |
341198ed | 652 | if (imxdma_xfer_desc(next_desc) < 0) |
9e15db7c JM |
653 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", |
654 | __func__, imxdmac->channel); | |
655 | } | |
656 | out: | |
5a276fa6 | 657 | spin_unlock_irqrestore(&imxdma->lock, flags); |
fcaaba6c | 658 | |
be5af285 | 659 | dmaengine_desc_get_callback_invoke(&desc->desc, NULL); |
1f1846c6 SH |
660 | } |
661 | ||
502c2ef2 | 662 | static int imxdma_terminate_all(struct dma_chan *chan) |
1f1846c6 SH |
663 | { |
664 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
cd5cf9da | 665 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c | 666 | unsigned long flags; |
9e15db7c | 667 | |
502c2ef2 | 668 | imxdma_disable_hw(imxdmac); |
1f1846c6 | 669 | |
502c2ef2 MR |
670 | spin_lock_irqsave(&imxdma->lock, flags); |
671 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
672 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
673 | spin_unlock_irqrestore(&imxdma->lock, flags); | |
674 | return 0; | |
675 | } | |
bef2a8d3 | 676 | |
dea7a9fb VK |
677 | static int imxdma_config_write(struct dma_chan *chan, |
678 | struct dma_slave_config *dmaengine_cfg, | |
679 | enum dma_transfer_direction direction) | |
502c2ef2 MR |
680 | { |
681 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
682 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
683 | unsigned int mode = 0; | |
bdc0c753 | 684 | |
dea7a9fb | 685 | if (direction == DMA_DEV_TO_MEM) { |
502c2ef2 MR |
686 | imxdmac->per_address = dmaengine_cfg->src_addr; |
687 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
688 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
689 | } else { | |
690 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
691 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
692 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
693 | } | |
1f1846c6 | 694 | |
502c2ef2 MR |
695 | switch (imxdmac->word_size) { |
696 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
697 | mode = IMX_DMA_MEMSIZE_8; | |
698 | break; | |
699 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
700 | mode = IMX_DMA_MEMSIZE_16; | |
701 | break; | |
1f1846c6 | 702 | default: |
502c2ef2 MR |
703 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
704 | mode = IMX_DMA_MEMSIZE_32; | |
705 | break; | |
1f1846c6 SH |
706 | } |
707 | ||
502c2ef2 MR |
708 | imxdmac->hw_chaining = 0; |
709 | ||
710 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | | |
711 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | | |
712 | CCR_REN; | |
713 | imxdmac->ccr_to_device = | |
714 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | | |
715 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
716 | imx_dmav1_writel(imxdma, imxdmac->dma_request, | |
717 | DMA_RSSR(imxdmac->channel)); | |
718 | ||
719 | /* Set burst length */ | |
720 | imx_dmav1_writel(imxdma, imxdmac->watermark_level * | |
721 | imxdmac->word_size, DMA_BLR(imxdmac->channel)); | |
722 | ||
723 | return 0; | |
1f1846c6 SH |
724 | } |
725 | ||
dea7a9fb VK |
726 | static int imxdma_config(struct dma_chan *chan, |
727 | struct dma_slave_config *dmaengine_cfg) | |
728 | { | |
729 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
730 | ||
731 | memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg)); | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
1f1846c6 SH |
736 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, |
737 | dma_cookie_t cookie, | |
738 | struct dma_tx_state *txstate) | |
739 | { | |
96a2af41 | 740 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
741 | } |
742 | ||
743 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
744 | { | |
745 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
f606ab89 | 746 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1f1846c6 | 747 | dma_cookie_t cookie; |
9e15db7c | 748 | unsigned long flags; |
1f1846c6 | 749 | |
f606ab89 | 750 | spin_lock_irqsave(&imxdma->lock, flags); |
660cd0dd | 751 | list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue); |
884485e1 | 752 | cookie = dma_cookie_assign(tx); |
f606ab89 | 753 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
754 | |
755 | return cookie; | |
756 | } | |
757 | ||
758 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
759 | { | |
760 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
761 | struct imx_dma_data *data = chan->private; | |
762 | ||
6c05f091 JM |
763 | if (data != NULL) |
764 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 765 | |
9e15db7c JM |
766 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
767 | struct imxdma_desc *desc; | |
1f1846c6 | 768 | |
9e15db7c JM |
769 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
770 | if (!desc) | |
771 | break; | |
ff5fdafc | 772 | memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor)); |
9e15db7c JM |
773 | dma_async_tx_descriptor_init(&desc->desc, chan); |
774 | desc->desc.tx_submit = imxdma_tx_submit; | |
775 | /* txd.flags will be overwritten in prep funcs */ | |
776 | desc->desc.flags = DMA_CTRL_ACK; | |
3ded1ad1 | 777 | desc->status = DMA_COMPLETE; |
9e15db7c JM |
778 | |
779 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
780 | imxdmac->descs_allocated++; | |
781 | } | |
1f1846c6 | 782 | |
9e15db7c JM |
783 | if (!imxdmac->descs_allocated) |
784 | return -ENOMEM; | |
785 | ||
786 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
787 | } |
788 | ||
789 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
790 | { | |
791 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
f606ab89 | 792 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
793 | struct imxdma_desc *desc, *_desc; |
794 | unsigned long flags; | |
795 | ||
f606ab89 | 796 | spin_lock_irqsave(&imxdma->lock, flags); |
1f1846c6 | 797 | |
6bd08127 | 798 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
799 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
800 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
1f1846c6 | 801 | |
f606ab89 | 802 | spin_unlock_irqrestore(&imxdma->lock, flags); |
9e15db7c JM |
803 | |
804 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
805 | kfree(desc); | |
806 | imxdmac->descs_allocated--; | |
807 | } | |
808 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 | 809 | |
06f8db4b SK |
810 | kfree(imxdmac->sg_list); |
811 | imxdmac->sg_list = NULL; | |
1f1846c6 SH |
812 | } |
813 | ||
814 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
815 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 816 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 817 | unsigned long flags, void *context) |
1f1846c6 SH |
818 | { |
819 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
820 | struct scatterlist *sg; | |
9e15db7c JM |
821 | int i, dma_length = 0; |
822 | struct imxdma_desc *desc; | |
1f1846c6 | 823 | |
9e15db7c JM |
824 | if (list_empty(&imxdmac->ld_free) || |
825 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
826 | return NULL; |
827 | ||
9e15db7c | 828 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
829 | |
830 | for_each_sg(sgl, sg, sg_len, i) { | |
fdaf9c4b | 831 | dma_length += sg_dma_len(sg); |
1f1846c6 SH |
832 | } |
833 | ||
d07102a1 SH |
834 | switch (imxdmac->word_size) { |
835 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
fdaf9c4b | 836 | if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3) |
d07102a1 SH |
837 | return NULL; |
838 | break; | |
839 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
fdaf9c4b | 840 | if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1) |
d07102a1 SH |
841 | return NULL; |
842 | break; | |
843 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
844 | break; | |
845 | default: | |
846 | return NULL; | |
847 | } | |
848 | ||
9e15db7c JM |
849 | desc->type = IMXDMA_DESC_SLAVE_SG; |
850 | desc->sg = sgl; | |
851 | desc->sgcount = sg_len; | |
852 | desc->len = dma_length; | |
2efc3449 | 853 | desc->direction = direction; |
9e15db7c | 854 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
855 | desc->src = imxdmac->per_address; |
856 | } else { | |
9e15db7c JM |
857 | desc->dest = imxdmac->per_address; |
858 | } | |
859 | desc->desc.callback = NULL; | |
860 | desc->desc.callback_param = NULL; | |
1f1846c6 | 861 | |
9e15db7c | 862 | return &desc->desc; |
1f1846c6 SH |
863 | } |
864 | ||
865 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
866 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 867 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 868 | unsigned long flags) |
1f1846c6 SH |
869 | { |
870 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
871 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
872 | struct imxdma_desc *desc; |
873 | int i; | |
1f1846c6 | 874 | unsigned int periods = buf_len / period_len; |
1f1846c6 | 875 | |
ac806a1c | 876 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n", |
1f1846c6 SH |
877 | __func__, imxdmac->channel, buf_len, period_len); |
878 | ||
9e15db7c JM |
879 | if (list_empty(&imxdmac->ld_free) || |
880 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 881 | return NULL; |
1f1846c6 | 882 | |
9e15db7c | 883 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 | 884 | |
96a3713e | 885 | kfree(imxdmac->sg_list); |
1f1846c6 SH |
886 | |
887 | imxdmac->sg_list = kcalloc(periods + 1, | |
edc530fe | 888 | sizeof(struct scatterlist), GFP_ATOMIC); |
1f1846c6 SH |
889 | if (!imxdmac->sg_list) |
890 | return NULL; | |
891 | ||
892 | sg_init_table(imxdmac->sg_list, periods); | |
893 | ||
894 | for (i = 0; i < periods; i++) { | |
ce818013 | 895 | sg_assign_page(&imxdmac->sg_list[i], NULL); |
1f1846c6 SH |
896 | imxdmac->sg_list[i].offset = 0; |
897 | imxdmac->sg_list[i].dma_address = dma_addr; | |
fdaf9c4b | 898 | sg_dma_len(&imxdmac->sg_list[i]) = period_len; |
1f1846c6 SH |
899 | dma_addr += period_len; |
900 | } | |
901 | ||
902 | /* close the loop */ | |
ce818013 | 903 | sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list); |
1f1846c6 | 904 | |
9e15db7c JM |
905 | desc->type = IMXDMA_DESC_CYCLIC; |
906 | desc->sg = imxdmac->sg_list; | |
907 | desc->sgcount = periods; | |
908 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 909 | desc->direction = direction; |
9e15db7c | 910 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
911 | desc->src = imxdmac->per_address; |
912 | } else { | |
9e15db7c JM |
913 | desc->dest = imxdmac->per_address; |
914 | } | |
915 | desc->desc.callback = NULL; | |
916 | desc->desc.callback_param = NULL; | |
1f1846c6 | 917 | |
dea7a9fb VK |
918 | imxdma_config_write(chan, &imxdmac->config, direction); |
919 | ||
9e15db7c | 920 | return &desc->desc; |
1f1846c6 SH |
921 | } |
922 | ||
6c05f091 JM |
923 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
924 | struct dma_chan *chan, dma_addr_t dest, | |
925 | dma_addr_t src, size_t len, unsigned long flags) | |
926 | { | |
927 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
928 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 929 | struct imxdma_desc *desc; |
1f1846c6 | 930 | |
ac806a1c RK |
931 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n", |
932 | __func__, imxdmac->channel, (unsigned long long)src, | |
933 | (unsigned long long)dest, len); | |
6c05f091 | 934 | |
9e15db7c JM |
935 | if (list_empty(&imxdmac->ld_free) || |
936 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
937 | return NULL; |
938 | ||
9e15db7c | 939 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 940 | |
9e15db7c JM |
941 | desc->type = IMXDMA_DESC_MEMCPY; |
942 | desc->src = src; | |
943 | desc->dest = dest; | |
944 | desc->len = len; | |
2efc3449 | 945 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
946 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
947 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
948 | desc->desc.callback = NULL; | |
949 | desc->desc.callback_param = NULL; | |
6c05f091 | 950 | |
9e15db7c | 951 | return &desc->desc; |
6c05f091 JM |
952 | } |
953 | ||
f606ab89 JM |
954 | static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved( |
955 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
956 | unsigned long flags) | |
957 | { | |
958 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
959 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
960 | struct imxdma_desc *desc; | |
961 | ||
ac806a1c RK |
962 | dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n" |
963 | " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__, | |
964 | imxdmac->channel, (unsigned long long)xt->src_start, | |
965 | (unsigned long long) xt->dst_start, | |
f606ab89 JM |
966 | xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false", |
967 | xt->numf, xt->frame_size); | |
968 | ||
969 | if (list_empty(&imxdmac->ld_free) || | |
970 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
971 | return NULL; | |
972 | ||
973 | if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM) | |
974 | return NULL; | |
975 | ||
976 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); | |
977 | ||
978 | desc->type = IMXDMA_DESC_INTERLEAVED; | |
979 | desc->src = xt->src_start; | |
980 | desc->dest = xt->dst_start; | |
981 | desc->x = xt->sgl[0].size; | |
982 | desc->y = xt->numf; | |
983 | desc->w = xt->sgl[0].icg + desc->x; | |
984 | desc->len = desc->x * desc->y; | |
985 | desc->direction = DMA_MEM_TO_MEM; | |
986 | desc->config_port = IMX_DMA_MEMSIZE_32; | |
987 | desc->config_mem = IMX_DMA_MEMSIZE_32; | |
988 | if (xt->src_sgl) | |
989 | desc->config_mem |= IMX_DMA_TYPE_2D; | |
990 | if (xt->dst_sgl) | |
991 | desc->config_port |= IMX_DMA_TYPE_2D; | |
992 | desc->desc.callback = NULL; | |
993 | desc->desc.callback_param = NULL; | |
994 | ||
995 | return &desc->desc; | |
1f1846c6 SH |
996 | } |
997 | ||
998 | static void imxdma_issue_pending(struct dma_chan *chan) | |
999 | { | |
5b316876 | 1000 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
1001 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
1002 | struct imxdma_desc *desc; | |
1003 | unsigned long flags; | |
1004 | ||
f606ab89 | 1005 | spin_lock_irqsave(&imxdma->lock, flags); |
9e15db7c JM |
1006 | if (list_empty(&imxdmac->ld_active) && |
1007 | !list_empty(&imxdmac->ld_queue)) { | |
1008 | desc = list_first_entry(&imxdmac->ld_queue, | |
1009 | struct imxdma_desc, node); | |
1010 | ||
1011 | if (imxdma_xfer_desc(desc) < 0) { | |
1012 | dev_warn(imxdma->dev, | |
1013 | "%s: channel: %d couldn't issue DMA xfer\n", | |
1014 | __func__, imxdmac->channel); | |
1015 | } else { | |
1016 | list_move_tail(imxdmac->ld_queue.next, | |
1017 | &imxdmac->ld_active); | |
1018 | } | |
1019 | } | |
f606ab89 | 1020 | spin_unlock_irqrestore(&imxdma->lock, flags); |
1f1846c6 SH |
1021 | } |
1022 | ||
290ad0f9 MP |
1023 | static bool imxdma_filter_fn(struct dma_chan *chan, void *param) |
1024 | { | |
1025 | struct imxdma_filter_data *fdata = param; | |
1026 | struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan); | |
1027 | ||
1028 | if (chan->device->dev != fdata->imxdma->dev) | |
1029 | return false; | |
1030 | ||
1031 | imxdma_chan->dma_request = fdata->request; | |
1032 | chan->private = NULL; | |
1033 | ||
1034 | return true; | |
1035 | } | |
1036 | ||
1037 | static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec, | |
1038 | struct of_dma *ofdma) | |
1039 | { | |
1040 | int count = dma_spec->args_count; | |
1041 | struct imxdma_engine *imxdma = ofdma->of_dma_data; | |
1042 | struct imxdma_filter_data fdata = { | |
1043 | .imxdma = imxdma, | |
1044 | }; | |
1045 | ||
1046 | if (count != 1) | |
1047 | return NULL; | |
1048 | ||
1049 | fdata.request = dma_spec->args[0]; | |
1050 | ||
1051 | return dma_request_channel(imxdma->dma_device.cap_mask, | |
1052 | imxdma_filter_fn, &fdata); | |
1053 | } | |
1054 | ||
1f1846c6 | 1055 | static int __init imxdma_probe(struct platform_device *pdev) |
71c6b663 | 1056 | { |
1f1846c6 | 1057 | struct imxdma_engine *imxdma; |
73930eb3 | 1058 | struct resource *res; |
290ad0f9 | 1059 | const struct of_device_id *of_id; |
1f1846c6 | 1060 | int ret, i; |
73930eb3 | 1061 | int irq, irq_err; |
cd5cf9da | 1062 | |
290ad0f9 MP |
1063 | of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev); |
1064 | if (of_id) | |
1065 | pdev->id_entry = of_id->data; | |
1066 | ||
04bbd8ef | 1067 | imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL); |
1f1846c6 SH |
1068 | if (!imxdma) |
1069 | return -ENOMEM; | |
1070 | ||
5c6b3e77 | 1071 | imxdma->dev = &pdev->dev; |
e51d0f0a SG |
1072 | imxdma->devtype = pdev->id_entry->driver_data; |
1073 | ||
73930eb3 | 1074 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7331205a TR |
1075 | imxdma->base = devm_ioremap_resource(&pdev->dev, res); |
1076 | if (IS_ERR(imxdma->base)) | |
1077 | return PTR_ERR(imxdma->base); | |
73930eb3 SG |
1078 | |
1079 | irq = platform_get_irq(pdev, 0); | |
1080 | if (irq < 0) | |
1081 | return irq; | |
6bd08127 | 1082 | |
a2367db2 | 1083 | imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg"); |
04bbd8ef SG |
1084 | if (IS_ERR(imxdma->dma_ipg)) |
1085 | return PTR_ERR(imxdma->dma_ipg); | |
a2367db2 FE |
1086 | |
1087 | imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
04bbd8ef SG |
1088 | if (IS_ERR(imxdma->dma_ahb)) |
1089 | return PTR_ERR(imxdma->dma_ahb); | |
a2367db2 | 1090 | |
fce9a74b FE |
1091 | ret = clk_prepare_enable(imxdma->dma_ipg); |
1092 | if (ret) | |
1093 | return ret; | |
1094 | ret = clk_prepare_enable(imxdma->dma_ahb); | |
1095 | if (ret) | |
1096 | goto disable_dma_ipg_clk; | |
6bd08127 JM |
1097 | |
1098 | /* reset DMA module */ | |
cd5cf9da | 1099 | imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR); |
6bd08127 | 1100 | |
e51d0f0a | 1101 | if (is_imx1_dma(imxdma)) { |
73930eb3 | 1102 | ret = devm_request_irq(&pdev->dev, irq, |
04bbd8ef | 1103 | dma_irq_handler, 0, "DMA", imxdma); |
6bd08127 | 1104 | if (ret) { |
f9b283a6 | 1105 | dev_warn(imxdma->dev, "Can't register IRQ for DMA\n"); |
fce9a74b | 1106 | goto disable_dma_ahb_clk; |
6bd08127 | 1107 | } |
ea62aa80 | 1108 | imxdma->irq = irq; |
6bd08127 | 1109 | |
73930eb3 SG |
1110 | irq_err = platform_get_irq(pdev, 1); |
1111 | if (irq_err < 0) { | |
1112 | ret = irq_err; | |
fce9a74b | 1113 | goto disable_dma_ahb_clk; |
73930eb3 SG |
1114 | } |
1115 | ||
1116 | ret = devm_request_irq(&pdev->dev, irq_err, | |
04bbd8ef | 1117 | imxdma_err_handler, 0, "DMA", imxdma); |
6bd08127 | 1118 | if (ret) { |
f9b283a6 | 1119 | dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n"); |
fce9a74b | 1120 | goto disable_dma_ahb_clk; |
6bd08127 | 1121 | } |
ea62aa80 | 1122 | imxdma->irq_err = irq_err; |
6bd08127 JM |
1123 | } |
1124 | ||
1125 | /* enable DMA module */ | |
cd5cf9da | 1126 | imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR); |
6bd08127 JM |
1127 | |
1128 | /* clear all interrupts */ | |
cd5cf9da | 1129 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); |
6bd08127 JM |
1130 | |
1131 | /* disable interrupts */ | |
cd5cf9da | 1132 | imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); |
1f1846c6 SH |
1133 | |
1134 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
1135 | ||
f8a356ff SH |
1136 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
1137 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 1138 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f606ab89 JM |
1139 | dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask); |
1140 | ||
1141 | /* Initialize 2D global parameters */ | |
1142 | for (i = 0; i < IMX_DMA_2D_SLOTS; i++) | |
1143 | imxdma->slots_2d[i].count = 0; | |
1144 | ||
1145 | spin_lock_init(&imxdma->lock); | |
f8a356ff | 1146 | |
1f1846c6 | 1147 | /* Initialize channel parameters */ |
6bd08127 | 1148 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 SH |
1149 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
1150 | ||
e51d0f0a | 1151 | if (!is_imx1_dma(imxdma)) { |
73930eb3 | 1152 | ret = devm_request_irq(&pdev->dev, irq + i, |
6bd08127 JM |
1153 | dma_irq_handler, 0, "DMA", imxdma); |
1154 | if (ret) { | |
f9b283a6 JM |
1155 | dev_warn(imxdma->dev, "Can't register IRQ %d " |
1156 | "for DMA channel %d\n", | |
73930eb3 | 1157 | irq + i, i); |
fce9a74b | 1158 | goto disable_dma_ahb_clk; |
6bd08127 | 1159 | } |
ea62aa80 VK |
1160 | |
1161 | imxdmac->irq = irq + i; | |
bcdc4bd3 | 1162 | timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0); |
8267f16e | 1163 | } |
1f1846c6 | 1164 | |
1f1846c6 | 1165 | imxdmac->imxdma = imxdma; |
1f1846c6 | 1166 | |
9e15db7c JM |
1167 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
1168 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1169 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
1170 | ||
1171 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
1172 | (unsigned long)imxdmac); | |
1f1846c6 | 1173 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 1174 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
1175 | imxdmac->channel = i; |
1176 | ||
1177 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
1178 | list_add_tail(&imxdmac->chan.device_node, |
1179 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
1180 | } |
1181 | ||
1f1846c6 SH |
1182 | imxdma->dma_device.dev = &pdev->dev; |
1183 | ||
1184 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
1185 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
1186 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
1187 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
1188 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 1189 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
f606ab89 | 1190 | imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved; |
502c2ef2 MR |
1191 | imxdma->dma_device.device_config = imxdma_config; |
1192 | imxdma->dma_device.device_terminate_all = imxdma_terminate_all; | |
1f1846c6 SH |
1193 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; |
1194 | ||
1195 | platform_set_drvdata(pdev, imxdma); | |
1196 | ||
77a68e56 | 1197 | imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES; |
1e070a60 SH |
1198 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
1199 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
1200 | ||
1f1846c6 SH |
1201 | ret = dma_async_device_register(&imxdma->dma_device); |
1202 | if (ret) { | |
1203 | dev_err(&pdev->dev, "unable to register\n"); | |
fce9a74b | 1204 | goto disable_dma_ahb_clk; |
1f1846c6 SH |
1205 | } |
1206 | ||
290ad0f9 MP |
1207 | if (pdev->dev.of_node) { |
1208 | ret = of_dma_controller_register(pdev->dev.of_node, | |
1209 | imxdma_xlate, imxdma); | |
1210 | if (ret) { | |
1211 | dev_err(&pdev->dev, "unable to register of_dma_controller\n"); | |
1212 | goto err_of_dma_controller; | |
1213 | } | |
1214 | } | |
1215 | ||
1f1846c6 SH |
1216 | return 0; |
1217 | ||
290ad0f9 MP |
1218 | err_of_dma_controller: |
1219 | dma_async_device_unregister(&imxdma->dma_device); | |
fce9a74b | 1220 | disable_dma_ahb_clk: |
a2367db2 | 1221 | clk_disable_unprepare(imxdma->dma_ahb); |
fce9a74b FE |
1222 | disable_dma_ipg_clk: |
1223 | clk_disable_unprepare(imxdma->dma_ipg); | |
1f1846c6 SH |
1224 | return ret; |
1225 | } | |
1226 | ||
ea62aa80 VK |
1227 | static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma) |
1228 | { | |
1229 | int i; | |
1230 | ||
1231 | if (is_imx1_dma(imxdma)) { | |
1232 | disable_irq(imxdma->irq); | |
1233 | disable_irq(imxdma->irq_err); | |
1234 | } | |
1235 | ||
1236 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
1237 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; | |
1238 | ||
1239 | if (!is_imx1_dma(imxdma)) | |
1240 | disable_irq(imxdmac->irq); | |
1241 | ||
1242 | tasklet_kill(&imxdmac->dma_tasklet); | |
1243 | } | |
1244 | } | |
1245 | ||
1d1bbd30 | 1246 | static int imxdma_remove(struct platform_device *pdev) |
1f1846c6 SH |
1247 | { |
1248 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
1f1846c6 | 1249 | |
ea62aa80 VK |
1250 | imxdma_free_irq(pdev, imxdma); |
1251 | ||
1f1846c6 SH |
1252 | dma_async_device_unregister(&imxdma->dma_device); |
1253 | ||
290ad0f9 MP |
1254 | if (pdev->dev.of_node) |
1255 | of_dma_controller_free(pdev->dev.of_node); | |
1256 | ||
a2367db2 FE |
1257 | clk_disable_unprepare(imxdma->dma_ipg); |
1258 | clk_disable_unprepare(imxdma->dma_ahb); | |
1f1846c6 SH |
1259 | |
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | static struct platform_driver imxdma_driver = { | |
1264 | .driver = { | |
1265 | .name = "imx-dma", | |
290ad0f9 | 1266 | .of_match_table = imx_dma_of_dev_id, |
1f1846c6 | 1267 | }, |
e51d0f0a | 1268 | .id_table = imx_dma_devtype, |
1d1bbd30 | 1269 | .remove = imxdma_remove, |
1f1846c6 SH |
1270 | }; |
1271 | ||
1272 | static int __init imxdma_module_init(void) | |
1273 | { | |
1274 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
1275 | } | |
1276 | subsys_initcall(imxdma_module_init); | |
1277 | ||
1278 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1279 | MODULE_DESCRIPTION("i.MX dma driver"); | |
1280 | MODULE_LICENSE("GPL"); |