[linux-2.6-block.git] / drivers / dma / hsu / pci.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * PCI driver for the High Speed UART DMA
 *
 * Copyright (C) 2015 Intel Corporation
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *
 * Partially based on the bits found in drivers/tty/serial/mfd.c.
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "hsu.h"

#define HSU_PCI_DMASR		0x00
#define HSU_PCI_DMAISR		0x04

#define HSU_PCI_CHAN_OFFSET	0x100

#define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA	0x081e
#define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA	0x1192

static irqreturn_t hsu_pci_irq(int irq, void *dev)
{
	struct hsu_dma_chip *chip = dev;
	struct pci_dev *pdev = to_pci_dev(chip->dev);
	u32 dmaisr;
	u32 status;
	unsigned short i;
	int ret = 0;
	int err;

	/*
	 * On Intel Tangier B0 and Anniedale the interrupt line, disregarding
	 * to have different numbers, is shared between HSU DMA and UART IPs.
	 * Thus on such SoCs we are expecting that IRQ handler is called in
	 * UART driver only.
	 */
	if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
		return IRQ_HANDLED;

	dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
	for (i = 0; i < chip->hsu->nr_channels; i++) {
		if (dmaisr & 0x1) {
			err = hsu_dma_get_status(chip, i, &status);
			if (err > 0)
				ret |= 1;
			else if (err == 0)
				ret |= hsu_dma_do_irq(chip, i, status);
		}
		dmaisr >>= 1;
	}

	return IRQ_RETVAL(ret);
}

static int hsu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	struct hsu_dma_chip *chip;
	int ret;

	ret = pcim_enable_device(pdev);
	if (ret)
		return ret;

	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
	if (ret) {
		dev_err(&pdev->dev, "I/O memory remapping failed\n");
		return ret;
	}

	pci_set_master(pdev);
	pci_try_set_mwi(pdev);

	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
	if (ret < 0)
		return ret;

	chip->dev = &pdev->dev;
	chip->regs = pcim_iomap_table(pdev)[0];
	chip->length = pci_resource_len(pdev, 0);
	chip->offset = HSU_PCI_CHAN_OFFSET;
	chip->irq = pci_irq_vector(pdev, 0);

	ret = hsu_dma_probe(chip);
	if (ret)
		return ret;

	ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip);
	if (ret)
		goto err_register_irq;

	pci_set_drvdata(pdev, chip);

	return 0;

err_register_irq:
	hsu_dma_remove(chip);
	return ret;
}

static void hsu_pci_remove(struct pci_dev *pdev)
{
	struct hsu_dma_chip *chip = pci_get_drvdata(pdev);

	free_irq(chip->irq, chip);
	hsu_dma_remove(chip);
}

static const struct pci_device_id hsu_pci_id_table[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
	{ }
};
MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);

static struct pci_driver hsu_pci_driver = {
	.name		= "hsu_dma_pci",
	.id_table	= hsu_pci_id_table,
	.probe		= hsu_pci_probe,
	.remove		= hsu_pci_remove,
};

module_pci_driver(hsu_pci_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
2b49e0c5 AS	2	/*
	3	* PCI driver for the High Speed UART DMA
	4	*
	5	* Copyright (C) 2015 Intel Corporation
	6	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	*
	8	* Partially based on the bits found in drivers/tty/serial/mfd.c.
2b49e0c5 AS	9	*/
	10
	11	#include <linux/bitops.h>
	12	#include <linux/device.h>
	13	#include <linux/module.h>
	14	#include <linux/pci.h>
	15
	16	#include "hsu.h"
	17
	18	#define HSU_PCI_DMASR 0x00
	19	#define HSU_PCI_DMAISR 0x04
	20
	21	#define HSU_PCI_CHAN_OFFSET 0x100
	22
4831e0d9 AS	23	#define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA 0x081e
	24	#define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA 0x1192
	25
2b49e0c5 AS	26	static irqreturn_t hsu_pci_irq(int irq, void *dev)
	27	{
	28	struct hsu_dma_chip *chip = dev;
4831e0d9	29	struct pci_dev *pdev = to_pci_dev(chip->dev);
2b49e0c5	30	u32 dmaisr;
c6f82787	31	u32 status;
2b49e0c5	32	unsigned short i;
d2f5a731	33	int ret = 0;
c6f82787	34	int err;
2b49e0c5	35
4831e0d9 AS	36	/*
	37	* On Intel Tangier B0 and Anniedale the interrupt line, disregarding
	38	* to have different numbers, is shared between HSU DMA and UART IPs.
	39	* Thus on such SoCs we are expecting that IRQ handler is called in
	40	* UART driver only.
	41	*/
	42	if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
	43	return IRQ_HANDLED;
	44
2b49e0c5	45	dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
4c97ad99	46	for (i = 0; i < chip->hsu->nr_channels; i++) {
c6f82787 CKT	47	if (dmaisr & 0x1) {
	48	err = hsu_dma_get_status(chip, i, &status);
	49	if (err > 0)
d2f5a731	50	ret \|= 1;
c6f82787 CKT	51	else if (err == 0)
	52	ret \|= hsu_dma_do_irq(chip, i, status);
	53	}
2b49e0c5 AS	54	dmaisr >>= 1;
	55	}
	56
d2f5a731	57	return IRQ_RETVAL(ret);
2b49e0c5 AS	58	}
	59
	60	static int hsu_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	61	{
	62	struct hsu_dma_chip *chip;
	63	int ret;
	64
	65	ret = pcim_enable_device(pdev);
	66	if (ret)
	67	return ret;
	68
	69	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
	70	if (ret) {
	71	dev_err(&pdev->dev, "I/O memory remapping failed\n");
	72	return ret;
	73	}
	74
	75	pci_set_master(pdev);
	76	pci_try_set_mwi(pdev);
	77
	78	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	79	if (ret)
	80	return ret;
	81
	82	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	83	if (ret)
	84	return ret;
	85
	86	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	87	if (!chip)
	88	return -ENOMEM;
	89
e9bb8a9d AS	90	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
	91	if (ret < 0)
	92	return ret;
	93
2b49e0c5 AS	94	chip->dev = &pdev->dev;
	95	chip->regs = pcim_iomap_table(pdev)[0];
	96	chip->length = pci_resource_len(pdev, 0);
	97	chip->offset = HSU_PCI_CHAN_OFFSET;
e9bb8a9d	98	chip->irq = pci_irq_vector(pdev, 0);
2b49e0c5 AS	99
	100	ret = hsu_dma_probe(chip);
	101	if (ret)
	102	return ret;
	103
	104	ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip);
	105	if (ret)
	106	goto err_register_irq;
	107
	108	pci_set_drvdata(pdev, chip);
	109
	110	return 0;
	111
	112	err_register_irq:
	113	hsu_dma_remove(chip);
	114	return ret;
	115	}
	116
	117	static void hsu_pci_remove(struct pci_dev *pdev)
	118	{
	119	struct hsu_dma_chip *chip = pci_get_drvdata(pdev);
	120
	121	free_irq(chip->irq, chip);
	122	hsu_dma_remove(chip);
	123	}
	124
	125	static const struct pci_device_id hsu_pci_id_table[] = {
4831e0d9 AS	126	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
4831e0d9 AS	127	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
2b49e0c5 AS	128	{ }
	129	};
	130	MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);
	131
	132	static struct pci_driver hsu_pci_driver = {
	133	.name = "hsu_dma_pci",
	134	.id_table = hsu_pci_id_table,
	135	.probe = hsu_pci_probe,
	136	.remove = hsu_pci_remove,
	137	};
	138
	139	module_pci_driver(hsu_pci_driver);
	140
	141	MODULE_LICENSE("GPL v2");
	142	MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
	143	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");