[linux-block.git] / drivers / dma / hsu / hsu.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Core driver for the High Speed UART DMA
 *
 * Copyright (C) 2015 Intel Corporation
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *
 * Partially based on the bits found in drivers/tty/serial/mfd.c.
 */

/*
 * DMA channel allocation:
 * 1. Even number chans are used for DMA Read (UART TX), odd chans for DMA
 *    Write (UART RX).
 * 2. 0/1 channel are assigned to port 0, 2/3 chan to port 1, 4/5 chan to
 *    port 3, and so on.
 */

#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>

#include "hsu.h"

#define HSU_DMA_BUSWIDTHS				\
	BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)	|	\
	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)

static inline void hsu_chan_disable(struct hsu_dma_chan *hsuc)
{
	hsu_chan_writel(hsuc, HSU_CH_CR, 0);
}

static inline void hsu_chan_enable(struct hsu_dma_chan *hsuc)
{
	u32 cr = HSU_CH_CR_CHA;

	if (hsuc->direction == DMA_MEM_TO_DEV)
		cr &= ~HSU_CH_CR_CHD;
	else if (hsuc->direction == DMA_DEV_TO_MEM)
		cr |= HSU_CH_CR_CHD;

	hsu_chan_writel(hsuc, HSU_CH_CR, cr);
}

static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
{
	struct dma_slave_config *config = &hsuc->config;
	struct hsu_dma_desc *desc = hsuc->desc;
	u32 bsr = 0, mtsr = 0;	/* to shut the compiler up */
	u32 dcr = HSU_CH_DCR_CHSOE | HSU_CH_DCR_CHEI;
	unsigned int i, count;

	if (hsuc->direction == DMA_MEM_TO_DEV) {
		bsr = config->dst_maxburst;
		mtsr = config->dst_addr_width;
	} else if (hsuc->direction == DMA_DEV_TO_MEM) {
		bsr = config->src_maxburst;
		mtsr = config->src_addr_width;
	}

	hsu_chan_disable(hsuc);

	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
	hsu_chan_writel(hsuc, HSU_CH_BSR, bsr);
	hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);

	/* Set descriptors */
	count = desc->nents - desc->active;
	for (i = 0; i < count && i < HSU_DMA_CHAN_NR_DESC; i++) {
		hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
		hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);

		/* Prepare value for DCR */
		dcr |= HSU_CH_DCR_DESCA(i);
		dcr |= HSU_CH_DCR_CHTOI(i);	/* timeout bit, see HSU Errata 1 */

		desc->active++;
	}
	/* Only for the last descriptor in the chain */
	dcr |= HSU_CH_DCR_CHSOD(count - 1);
	dcr |= HSU_CH_DCR_CHDI(count - 1);

	hsu_chan_writel(hsuc, HSU_CH_DCR, dcr);

	hsu_chan_enable(hsuc);
}

static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc)
{
	hsu_chan_disable(hsuc);
	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
}

static void hsu_dma_start_channel(struct hsu_dma_chan *hsuc)
{
	hsu_dma_chan_start(hsuc);
}

static void hsu_dma_start_transfer(struct hsu_dma_chan *hsuc)
{
	struct virt_dma_desc *vdesc;

	/* Get the next descriptor */
	vdesc = vchan_next_desc(&hsuc->vchan);
	if (!vdesc) {
		hsuc->desc = NULL;
		return;
	}

	list_del(&vdesc->node);
	hsuc->desc = to_hsu_dma_desc(vdesc);

	/* Start the channel with a new descriptor */
	hsu_dma_start_channel(hsuc);
}

/*
 *      hsu_dma_get_status() - get DMA channel status
 *      @chip: HSUART DMA chip
 *      @nr: DMA channel number
 *      @status: pointer for DMA Channel Status Register value
 *
 *      Description:
 *      The function reads and clears the DMA Channel Status Register, checks
 *      if it was a timeout interrupt and returns a corresponding value.
 *
 *      Caller should provide a valid pointer for the DMA Channel Status
 *      Register value that will be returned in @status.
 *
 *      Return:
 *      1 for DMA timeout status, 0 for other DMA status, or error code for
 *      invalid parameters or no interrupt pending.
 */
int hsu_dma_get_status(struct hsu_dma_chip *chip, unsigned short nr,
		       u32 *status)
{
	struct hsu_dma_chan *hsuc;
	unsigned long flags;
	u32 sr;

	/* Sanity check */
	if (nr >= chip->hsu->nr_channels)
		return -EINVAL;

	hsuc = &chip->hsu->chan[nr];

	/*
	 * No matter what situation, need read clear the IRQ status
	 * There is a bug, see Errata 5, HSD 2900918
	 */
	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	sr = hsu_chan_readl(hsuc, HSU_CH_SR);
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	/* Check if any interrupt is pending */
	sr &= ~(HSU_CH_SR_DESCE_ANY | HSU_CH_SR_CDESC_ANY);
	if (!sr)
		return -EIO;

	/* Timeout IRQ, need wait some time, see Errata 2 */
	if (sr & HSU_CH_SR_DESCTO_ANY)
		udelay(2);

	/*
	 * At this point, at least one of Descriptor Time Out, Channel Error
	 * or Descriptor Done bits must be set. Clear the Descriptor Time Out
	 * bits and if sr is still non-zero, it must be channel error or
	 * descriptor done which are higher priority than timeout and handled
	 * in hsu_dma_do_irq(). Else, it must be a timeout.
	 */
	sr &= ~HSU_CH_SR_DESCTO_ANY;

	*status = sr;

	return sr ? 0 : 1;
}
EXPORT_SYMBOL_GPL(hsu_dma_get_status);

/*
 *      hsu_dma_do_irq() - DMA interrupt handler
 *      @chip: HSUART DMA chip
 *      @nr: DMA channel number
 *      @status: Channel Status Register value
 *
 *      Description:
 *      This function handles Channel Error and Descriptor Done interrupts.
 *      This function should be called after determining that the DMA interrupt
 *      is not a normal timeout interrupt, ie. hsu_dma_get_status() returned 0.
 *
 *      Return:
 *      0 for invalid channel number, 1 otherwise.
 */
int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
{
	struct hsu_dma_chan *hsuc;
	struct hsu_dma_desc *desc;
	unsigned long flags;

	/* Sanity check */
	if (nr >= chip->hsu->nr_channels)
		return 0;

	hsuc = &chip->hsu->chan[nr];

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	desc = hsuc->desc;
	if (desc) {
		if (status & HSU_CH_SR_CHE) {
			desc->status = DMA_ERROR;
		} else if (desc->active < desc->nents) {
			hsu_dma_start_channel(hsuc);
		} else {
			vchan_cookie_complete(&desc->vdesc);
			desc->status = DMA_COMPLETE;
			hsu_dma_start_transfer(hsuc);
		}
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return 1;
}
EXPORT_SYMBOL_GPL(hsu_dma_do_irq);

static struct hsu_dma_desc *hsu_dma_alloc_desc(unsigned int nents)
{
	struct hsu_dma_desc *desc;

	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
	if (!desc)
		return NULL;

	desc->sg = kcalloc(nents, sizeof(*desc->sg), GFP_NOWAIT);
	if (!desc->sg) {
		kfree(desc);
		return NULL;
	}

	return desc;
}

static void hsu_dma_desc_free(struct virt_dma_desc *vdesc)
{
	struct hsu_dma_desc *desc = to_hsu_dma_desc(vdesc);

	kfree(desc->sg);
	kfree(desc);
}

static struct dma_async_tx_descriptor *hsu_dma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags, void *context)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	struct hsu_dma_desc *desc;
	struct scatterlist *sg;
	unsigned int i;

	desc = hsu_dma_alloc_desc(sg_len);
	if (!desc)
		return NULL;

	for_each_sg(sgl, sg, sg_len, i) {
		desc->sg[i].addr = sg_dma_address(sg);
		desc->sg[i].len = sg_dma_len(sg);

		desc->length += sg_dma_len(sg);
	}

	desc->nents = sg_len;
	desc->direction = direction;
	/* desc->active = 0 by kzalloc */
	desc->status = DMA_IN_PROGRESS;

	return vchan_tx_prep(&hsuc->vchan, &desc->vdesc, flags);
}

static void hsu_dma_issue_pending(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	if (vchan_issue_pending(&hsuc->vchan) && !hsuc->desc)
		hsu_dma_start_transfer(hsuc);
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
}

static size_t hsu_dma_active_desc_size(struct hsu_dma_chan *hsuc)
{
	struct hsu_dma_desc *desc = hsuc->desc;
	size_t bytes = 0;
	int i;

	for (i = desc->active; i < desc->nents; i++)
		bytes += desc->sg[i].len;

	i = HSU_DMA_CHAN_NR_DESC - 1;
	do {
		bytes += hsu_chan_readl(hsuc, HSU_CH_DxTSR(i));
	} while (--i >= 0);

	return bytes;
}

static enum dma_status hsu_dma_tx_status(struct dma_chan *chan,
	dma_cookie_t cookie, struct dma_tx_state *state)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	struct virt_dma_desc *vdesc;
	enum dma_status status;
	size_t bytes;
	unsigned long flags;

	status = dma_cookie_status(chan, cookie, state);
	if (status == DMA_COMPLETE)
		return status;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	vdesc = vchan_find_desc(&hsuc->vchan, cookie);
	if (hsuc->desc && cookie == hsuc->desc->vdesc.tx.cookie) {
		bytes = hsu_dma_active_desc_size(hsuc);
		dma_set_residue(state, bytes);
		status = hsuc->desc->status;
	} else if (vdesc) {
		bytes = to_hsu_dma_desc(vdesc)->length;
		dma_set_residue(state, bytes);
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return status;
}

static int hsu_dma_slave_config(struct dma_chan *chan,
				struct dma_slave_config *config)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);

	memcpy(&hsuc->config, config, sizeof(hsuc->config));

	return 0;
}

static int hsu_dma_pause(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	if (hsuc->desc && hsuc->desc->status == DMA_IN_PROGRESS) {
		hsu_chan_disable(hsuc);
		hsuc->desc->status = DMA_PAUSED;
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return 0;
}

static int hsu_dma_resume(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	if (hsuc->desc && hsuc->desc->status == DMA_PAUSED) {
		hsuc->desc->status = DMA_IN_PROGRESS;
		hsu_chan_enable(hsuc);
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return 0;
}

static int hsu_dma_terminate_all(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;
	LIST_HEAD(head);

	spin_lock_irqsave(&hsuc->vchan.lock, flags);

	hsu_dma_stop_channel(hsuc);
	if (hsuc->desc) {
		hsu_dma_desc_free(&hsuc->desc->vdesc);
		hsuc->desc = NULL;
	}

	vchan_get_all_descriptors(&hsuc->vchan, &head);
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	vchan_dma_desc_free_list(&hsuc->vchan, &head);

	return 0;
}

static void hsu_dma_free_chan_resources(struct dma_chan *chan)
{
	vchan_free_chan_resources(to_virt_chan(chan));
}

static void hsu_dma_synchronize(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);

	vchan_synchronize(&hsuc->vchan);
}

int hsu_dma_probe(struct hsu_dma_chip *chip)
{
	struct hsu_dma *hsu;
	void __iomem *addr = chip->regs + chip->offset;
	unsigned short i;
	int ret;

	hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
	if (!hsu)
		return -ENOMEM;

	chip->hsu = hsu;

	/* Calculate nr_channels from the IO space length */
	hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;

	hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
				 sizeof(*hsu->chan), GFP_KERNEL);
	if (!hsu->chan)
		return -ENOMEM;

	INIT_LIST_HEAD(&hsu->dma.channels);
	for (i = 0; i < hsu->nr_channels; i++) {
		struct hsu_dma_chan *hsuc = &hsu->chan[i];

		hsuc->vchan.desc_free = hsu_dma_desc_free;
		vchan_init(&hsuc->vchan, &hsu->dma);

		hsuc->direction = (i & 0x1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
		hsuc->reg = addr + i * HSU_DMA_CHAN_LENGTH;
	}

	dma_cap_set(DMA_SLAVE, hsu->dma.cap_mask);
	dma_cap_set(DMA_PRIVATE, hsu->dma.cap_mask);

	hsu->dma.device_free_chan_resources = hsu_dma_free_chan_resources;

	hsu->dma.device_prep_slave_sg = hsu_dma_prep_slave_sg;

	hsu->dma.device_issue_pending = hsu_dma_issue_pending;
	hsu->dma.device_tx_status = hsu_dma_tx_status;

	hsu->dma.device_config = hsu_dma_slave_config;
	hsu->dma.device_pause = hsu_dma_pause;
	hsu->dma.device_resume = hsu_dma_resume;
	hsu->dma.device_terminate_all = hsu_dma_terminate_all;
	hsu->dma.device_synchronize = hsu_dma_synchronize;

	hsu->dma.src_addr_widths = HSU_DMA_BUSWIDTHS;
	hsu->dma.dst_addr_widths = HSU_DMA_BUSWIDTHS;
	hsu->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
	hsu->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;

	hsu->dma.dev = chip->dev;

	dma_set_max_seg_size(hsu->dma.dev, HSU_CH_DxTSR_MASK);

	ret = dma_async_device_register(&hsu->dma);
	if (ret)
		return ret;

	dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
	return 0;
}
EXPORT_SYMBOL_GPL(hsu_dma_probe);

int hsu_dma_remove(struct hsu_dma_chip *chip)
{
	struct hsu_dma *hsu = chip->hsu;
	unsigned short i;

	dma_async_device_unregister(&hsu->dma);

	for (i = 0; i < hsu->nr_channels; i++) {
		struct hsu_dma_chan *hsuc = &hsu->chan[i];

		tasklet_kill(&hsuc->vchan.task);
	}

	return 0;
}
EXPORT_SYMBOL_GPL(hsu_dma_remove);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("High Speed UART DMA core driver");
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
2b49e0c5 AS	2	/*
	3	* Core driver for the High Speed UART DMA
	4	*
	5	* Copyright (C) 2015 Intel Corporation
	6	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	*
	8	* Partially based on the bits found in drivers/tty/serial/mfd.c.
2b49e0c5 AS	9	*/
	10
	11	/*
	12	* DMA channel allocation:
	13	* 1. Even number chans are used for DMA Read (UART TX), odd chans for DMA
	14	* Write (UART RX).
	15	* 2. 0/1 channel are assigned to port 0, 2/3 chan to port 1, 4/5 chan to
	16	* port 3, and so on.
	17	*/
	18
	19	#include <linux/delay.h>
	20	#include <linux/dmaengine.h>
	21	#include <linux/dma-mapping.h>
	22	#include <linux/init.h>
	23	#include <linux/module.h>
	24	#include <linux/slab.h>
	25
	26	#include "hsu.h"
	27
	28	#define HSU_DMA_BUSWIDTHS \
	29	BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) \| \
	30	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
	31	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
	32	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) \| \
	33	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) \| \
	34	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) \| \
	35	BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)
	36
	37	static inline void hsu_chan_disable(struct hsu_dma_chan *hsuc)
	38	{
	39	hsu_chan_writel(hsuc, HSU_CH_CR, 0);
	40	}
	41
	42	static inline void hsu_chan_enable(struct hsu_dma_chan *hsuc)
	43	{
	44	u32 cr = HSU_CH_CR_CHA;
	45
	46	if (hsuc->direction == DMA_MEM_TO_DEV)
	47	cr &= ~HSU_CH_CR_CHD;
	48	else if (hsuc->direction == DMA_DEV_TO_MEM)
	49	cr \|= HSU_CH_CR_CHD;
	50
	51	hsu_chan_writel(hsuc, HSU_CH_CR, cr);
	52	}
	53
	54	static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
	55	{
	56	struct dma_slave_config *config = &hsuc->config;
	57	struct hsu_dma_desc *desc = hsuc->desc;
4bb82458	58	u32 bsr = 0, mtsr = 0; /* to shut the compiler up */
2b49e0c5 AS	59	u32 dcr = HSU_CH_DCR_CHSOE \| HSU_CH_DCR_CHEI;
	60	unsigned int i, count;
	61
	62	if (hsuc->direction == DMA_MEM_TO_DEV) {
	63	bsr = config->dst_maxburst;
c24a5c73	64	mtsr = config->dst_addr_width;
2b49e0c5 AS	65	} else if (hsuc->direction == DMA_DEV_TO_MEM) {
2b49e0c5 AS	66	bsr = config->src_maxburst;
c24a5c73	67	mtsr = config->src_addr_width;
2b49e0c5 AS	68	}
	69
	70	hsu_chan_disable(hsuc);
	71
	72	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
	73	hsu_chan_writel(hsuc, HSU_CH_BSR, bsr);
	74	hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);
	75
	76	/* Set descriptors */
2d4d689f AS	77	count = desc->nents - desc->active;
2d4d689f AS	78	for (i = 0; i < count && i < HSU_DMA_CHAN_NR_DESC; i++) {
2b49e0c5 AS	79	hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
	80	hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);
	81
	82	/* Prepare value for DCR */
	83	dcr \|= HSU_CH_DCR_DESCA(i);
	84	dcr \|= HSU_CH_DCR_CHTOI(i); /* timeout bit, see HSU Errata 1 */
	85
	86	desc->active++;
	87	}
	88	/* Only for the last descriptor in the chain */
	89	dcr \|= HSU_CH_DCR_CHSOD(count - 1);
	90	dcr \|= HSU_CH_DCR_CHDI(count - 1);
	91
	92	hsu_chan_writel(hsuc, HSU_CH_DCR, dcr);
	93
	94	hsu_chan_enable(hsuc);
	95	}
	96
	97	static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc)
	98	{
2b49e0c5 AS	99	hsu_chan_disable(hsuc);
2b49e0c5 AS	100	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
2b49e0c5 AS	101	}
	102
	103	static void hsu_dma_start_channel(struct hsu_dma_chan *hsuc)
	104	{
2b49e0c5	105	hsu_dma_chan_start(hsuc);
2b49e0c5 AS	106	}
	107
	108	static void hsu_dma_start_transfer(struct hsu_dma_chan *hsuc)
	109	{
	110	struct virt_dma_desc *vdesc;
	111
	112	/* Get the next descriptor */
	113	vdesc = vchan_next_desc(&hsuc->vchan);
	114	if (!vdesc) {
	115	hsuc->desc = NULL;
	116	return;
	117	}
	118
	119	list_del(&vdesc->node);
	120	hsuc->desc = to_hsu_dma_desc(vdesc);
	121
	122	/* Start the channel with a new descriptor */
	123	hsu_dma_start_channel(hsuc);
	124	}
	125
c6f82787 CKT	126	/*
	127	* hsu_dma_get_status() - get DMA channel status
	128	* @chip: HSUART DMA chip
	129	* @nr: DMA channel number
	130	* @status: pointer for DMA Channel Status Register value
	131	*
	132	* Description:
	133	* The function reads and clears the DMA Channel Status Register, checks
	134	* if it was a timeout interrupt and returns a corresponding value.
	135	*
	136	* Caller should provide a valid pointer for the DMA Channel Status
	137	* Register value that will be returned in @status.
	138	*
	139	* Return:
	140	* 1 for DMA timeout status, 0 for other DMA status, or error code for
	141	* invalid parameters or no interrupt pending.
	142	*/
	143	int hsu_dma_get_status(struct hsu_dma_chip *chip, unsigned short nr,
	144	u32 *status)
2b49e0c5 AS	145	{
2b49e0c5 AS	146	struct hsu_dma_chan *hsuc;
2b49e0c5 AS	147	unsigned long flags;
	148	u32 sr;
	149
	150	/* Sanity check */
4c97ad99	151	if (nr >= chip->hsu->nr_channels)
c6f82787	152	return -EINVAL;
2b49e0c5 AS	153
	154	hsuc = &chip->hsu->chan[nr];
	155
	156	/*
	157	* No matter what situation, need read clear the IRQ status
	158	* There is a bug, see Errata 5, HSD 2900918
	159	*/
c6f82787 CKT	160	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	161	sr = hsu_chan_readl(hsuc, HSU_CH_SR);
	162	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	163
	164	/* Check if any interrupt is pending */
	165	sr &= ~(HSU_CH_SR_DESCE_ANY \| HSU_CH_SR_CDESC_ANY);
2b49e0c5	166	if (!sr)
c6f82787	167	return -EIO;
2b49e0c5 AS	168
2b49e0c5 AS	169	/* Timeout IRQ, need wait some time, see Errata 2 */
c36a0176	170	if (sr & HSU_CH_SR_DESCTO_ANY)
2b49e0c5 AS	171	udelay(2);
2b49e0c5 AS	172
c6f82787 CKT	173	/*
	174	* At this point, at least one of Descriptor Time Out, Channel Error
	175	* or Descriptor Done bits must be set. Clear the Descriptor Time Out
	176	* bits and if sr is still non-zero, it must be channel error or
	177	* descriptor done which are higher priority than timeout and handled
	178	* in hsu_dma_do_irq(). Else, it must be a timeout.
	179	*/
2b49e0c5	180	sr &= ~HSU_CH_SR_DESCTO_ANY;
c6f82787 CKT	181
	182	*status = sr;
	183
	184	return sr ? 0 : 1;
	185	}
	186	EXPORT_SYMBOL_GPL(hsu_dma_get_status);
	187
	188	/*
	189	* hsu_dma_do_irq() - DMA interrupt handler
	190	* @chip: HSUART DMA chip
	191	* @nr: DMA channel number
	192	* @status: Channel Status Register value
	193	*
	194	* Description:
	195	* This function handles Channel Error and Descriptor Done interrupts.
	196	* This function should be called after determining that the DMA interrupt
	197	* is not a normal timeout interrupt, ie. hsu_dma_get_status() returned 0.
	198	*
	199	* Return:
d2f5a731	200	* 0 for invalid channel number, 1 otherwise.
c6f82787	201	*/
d2f5a731	202	int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
c6f82787 CKT	203	{
	204	struct hsu_dma_chan *hsuc;
	205	struct hsu_dma_desc *desc;
	206	unsigned long flags;
	207
	208	/* Sanity check */
	209	if (nr >= chip->hsu->nr_channels)
d2f5a731	210	return 0;
c6f82787 CKT	211
c6f82787 CKT	212	hsuc = &chip->hsu->chan[nr];
2b49e0c5 AS	213
	214	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	215	desc = hsuc->desc;
	216	if (desc) {
c6f82787	217	if (status & HSU_CH_SR_CHE) {
2b49e0c5 AS	218	desc->status = DMA_ERROR;
	219	} else if (desc->active < desc->nents) {
	220	hsu_dma_start_channel(hsuc);
	221	} else {
	222	vchan_cookie_complete(&desc->vdesc);
	223	desc->status = DMA_COMPLETE;
	224	hsu_dma_start_transfer(hsuc);
	225	}
	226	}
	227	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	228
d2f5a731	229	return 1;
2b49e0c5	230	}
c6f82787	231	EXPORT_SYMBOL_GPL(hsu_dma_do_irq);
2b49e0c5 AS	232
	233	static struct hsu_dma_desc *hsu_dma_alloc_desc(unsigned int nents)
	234	{
	235	struct hsu_dma_desc *desc;
	236
ad53b26c	237	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
2b49e0c5 AS	238	if (!desc)
	239	return NULL;
	240
ad53b26c	241	desc->sg = kcalloc(nents, sizeof(*desc->sg), GFP_NOWAIT);
2b49e0c5 AS	242	if (!desc->sg) {
	243	kfree(desc);
	244	return NULL;
	245	}
	246
	247	return desc;
	248	}
	249
	250	static void hsu_dma_desc_free(struct virt_dma_desc *vdesc)
	251	{
	252	struct hsu_dma_desc *desc = to_hsu_dma_desc(vdesc);
	253
	254	kfree(desc->sg);
	255	kfree(desc);
	256	}
	257
	258	static struct dma_async_tx_descriptor *hsu_dma_prep_slave_sg(
	259	struct dma_chan chan, struct scatterlist sgl,
	260	unsigned int sg_len, enum dma_transfer_direction direction,
	261	unsigned long flags, void *context)
	262	{
	263	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	264	struct hsu_dma_desc *desc;
	265	struct scatterlist *sg;
	266	unsigned int i;
	267
	268	desc = hsu_dma_alloc_desc(sg_len);
	269	if (!desc)
	270	return NULL;
	271
	272	for_each_sg(sgl, sg, sg_len, i) {
	273	desc->sg[i].addr = sg_dma_address(sg);
	274	desc->sg[i].len = sg_dma_len(sg);
f0579c8c AS	275
f0579c8c AS	276	desc->length += sg_dma_len(sg);
2b49e0c5 AS	277	}
	278
	279	desc->nents = sg_len;
	280	desc->direction = direction;
4bb82458	281	/* desc->active = 0 by kzalloc */
2b49e0c5 AS	282	desc->status = DMA_IN_PROGRESS;
	283
	284	return vchan_tx_prep(&hsuc->vchan, &desc->vdesc, flags);
	285	}
	286
	287	static void hsu_dma_issue_pending(struct dma_chan *chan)
	288	{
	289	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	290	unsigned long flags;
	291
	292	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	293	if (vchan_issue_pending(&hsuc->vchan) && !hsuc->desc)
	294	hsu_dma_start_transfer(hsuc);
	295	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	296	}
	297
2b49e0c5 AS	298	static size_t hsu_dma_active_desc_size(struct hsu_dma_chan *hsuc)
	299	{
	300	struct hsu_dma_desc *desc = hsuc->desc;
a197f3c7	301	size_t bytes = 0;
2b49e0c5	302	int i;
2b49e0c5	303
a197f3c7 AS	304	for (i = desc->active; i < desc->nents; i++)
	305	bytes += desc->sg[i].len;
	306
	307	i = HSU_DMA_CHAN_NR_DESC - 1;
2b49e0c5 AS	308	do {
	309	bytes += hsu_chan_readl(hsuc, HSU_CH_DxTSR(i));
	310	} while (--i >= 0);
2b49e0c5 AS	311
	312	return bytes;
	313	}
	314
	315	static enum dma_status hsu_dma_tx_status(struct dma_chan *chan,
	316	dma_cookie_t cookie, struct dma_tx_state *state)
	317	{
	318	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	319	struct virt_dma_desc *vdesc;
	320	enum dma_status status;
	321	size_t bytes;
	322	unsigned long flags;
	323
	324	status = dma_cookie_status(chan, cookie, state);
	325	if (status == DMA_COMPLETE)
	326	return status;
	327
	328	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	329	vdesc = vchan_find_desc(&hsuc->vchan, cookie);
	330	if (hsuc->desc && cookie == hsuc->desc->vdesc.tx.cookie) {
	331	bytes = hsu_dma_active_desc_size(hsuc);
	332	dma_set_residue(state, bytes);
	333	status = hsuc->desc->status;
	334	} else if (vdesc) {
f0579c8c	335	bytes = to_hsu_dma_desc(vdesc)->length;
2b49e0c5 AS	336	dma_set_residue(state, bytes);
	337	}
	338	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	339
	340	return status;
	341	}
	342
	343	static int hsu_dma_slave_config(struct dma_chan *chan,
	344	struct dma_slave_config *config)
	345	{
	346	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	347
2b49e0c5 AS	348	memcpy(&hsuc->config, config, sizeof(hsuc->config));
	349
	350	return 0;
	351	}
	352
2b49e0c5 AS	353	static int hsu_dma_pause(struct dma_chan *chan)
	354	{
	355	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	356	unsigned long flags;
	357
	358	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	359	if (hsuc->desc && hsuc->desc->status == DMA_IN_PROGRESS) {
03734485	360	hsu_chan_disable(hsuc);
2b49e0c5 AS	361	hsuc->desc->status = DMA_PAUSED;
	362	}
	363	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	364
	365	return 0;
	366	}
	367
	368	static int hsu_dma_resume(struct dma_chan *chan)
	369	{
	370	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	371	unsigned long flags;
	372
	373	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	374	if (hsuc->desc && hsuc->desc->status == DMA_PAUSED) {
	375	hsuc->desc->status = DMA_IN_PROGRESS;
03734485	376	hsu_chan_enable(hsuc);
2b49e0c5 AS	377	}
	378	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	379
	380	return 0;
	381	}
	382
	383	static int hsu_dma_terminate_all(struct dma_chan *chan)
	384	{
	385	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	386	unsigned long flags;
	387	LIST_HEAD(head);
	388
	389	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	390
	391	hsu_dma_stop_channel(hsuc);
42977082 PU	392	if (hsuc->desc) {
	393	hsu_dma_desc_free(&hsuc->desc->vdesc);
	394	hsuc->desc = NULL;
	395	}
2b49e0c5 AS	396
	397	vchan_get_all_descriptors(&hsuc->vchan, &head);
	398	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	399	vchan_dma_desc_free_list(&hsuc->vchan, &head);
	400
	401	return 0;
	402	}
	403
2b49e0c5 AS	404	static void hsu_dma_free_chan_resources(struct dma_chan *chan)
	405	{
	406	vchan_free_chan_resources(to_virt_chan(chan));
	407	}
	408
2abc66cd AS	409	static void hsu_dma_synchronize(struct dma_chan *chan)
	410	{
	411	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	412
	413	vchan_synchronize(&hsuc->vchan);
	414	}
	415
2b49e0c5 AS	416	int hsu_dma_probe(struct hsu_dma_chip *chip)
	417	{
	418	struct hsu_dma *hsu;
2b49e0c5 AS	419	void __iomem *addr = chip->regs + chip->offset;
	420	unsigned short i;
	421	int ret;
	422
	423	hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
	424	if (!hsu)
	425	return -ENOMEM;
	426
	427	chip->hsu = hsu;
	428
4c97ad99 HK	429	/* Calculate nr_channels from the IO space length */
4c97ad99 HK	430	hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;
2b49e0c5	431
4c97ad99	432	hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
2b49e0c5 AS	433	sizeof(*hsu->chan), GFP_KERNEL);
	434	if (!hsu->chan)
	435	return -ENOMEM;
	436
	437	INIT_LIST_HEAD(&hsu->dma.channels);
4c97ad99	438	for (i = 0; i < hsu->nr_channels; i++) {
2b49e0c5 AS	439	struct hsu_dma_chan *hsuc = &hsu->chan[i];
	440
	441	hsuc->vchan.desc_free = hsu_dma_desc_free;
	442	vchan_init(&hsuc->vchan, &hsu->dma);
	443
	444	hsuc->direction = (i & 0x1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
	445	hsuc->reg = addr + i * HSU_DMA_CHAN_LENGTH;
2b49e0c5 AS	446	}
	447
	448	dma_cap_set(DMA_SLAVE, hsu->dma.cap_mask);
	449	dma_cap_set(DMA_PRIVATE, hsu->dma.cap_mask);
	450
2b49e0c5 AS	451	hsu->dma.device_free_chan_resources = hsu_dma_free_chan_resources;
	452
	453	hsu->dma.device_prep_slave_sg = hsu_dma_prep_slave_sg;
	454
	455	hsu->dma.device_issue_pending = hsu_dma_issue_pending;
	456	hsu->dma.device_tx_status = hsu_dma_tx_status;
	457
	458	hsu->dma.device_config = hsu_dma_slave_config;
	459	hsu->dma.device_pause = hsu_dma_pause;
	460	hsu->dma.device_resume = hsu_dma_resume;
	461	hsu->dma.device_terminate_all = hsu_dma_terminate_all;
2abc66cd	462	hsu->dma.device_synchronize = hsu_dma_synchronize;
2b49e0c5 AS	463
	464	hsu->dma.src_addr_widths = HSU_DMA_BUSWIDTHS;
	465	hsu->dma.dst_addr_widths = HSU_DMA_BUSWIDTHS;
	466	hsu->dma.directions = BIT(DMA_DEV_TO_MEM) \| BIT(DMA_MEM_TO_DEV);
	467	hsu->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
	468
	469	hsu->dma.dev = chip->dev;
	470
17b3cf42 AS	471	dma_set_max_seg_size(hsu->dma.dev, HSU_CH_DxTSR_MASK);
17b3cf42 AS	472
2b49e0c5 AS	473	ret = dma_async_device_register(&hsu->dma);
	474	if (ret)
	475	return ret;
	476
4c97ad99	477	dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
2b49e0c5 AS	478	return 0;
	479	}
	480	EXPORT_SYMBOL_GPL(hsu_dma_probe);
	481
	482	int hsu_dma_remove(struct hsu_dma_chip *chip)
	483	{
	484	struct hsu_dma *hsu = chip->hsu;
	485	unsigned short i;
	486
	487	dma_async_device_unregister(&hsu->dma);
	488
4c97ad99	489	for (i = 0; i < hsu->nr_channels; i++) {
2b49e0c5 AS	490	struct hsu_dma_chan *hsuc = &hsu->chan[i];
	491
	492	tasklet_kill(&hsuc->vchan.task);
	493	}
	494
	495	return 0;
	496	}
	497	EXPORT_SYMBOL_GPL(hsu_dma_remove);
	498
	499	MODULE_LICENSE("GPL v2");
	500	MODULE_DESCRIPTION("High Speed UART DMA core driver");
	501	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");