[linux-2.6-block.git] / drivers / dma / fsldma.h

/*
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author:
 *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
 *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */
#ifndef __DMA_FSLDMA_H
#define __DMA_FSLDMA_H

#include <linux/device.h>
#include <linux/dmapool.h>
#include <linux/dmaengine.h>

/* Define data structures needed by Freescale
 * MPC8540 and MPC8349 DMA controller.
 */
#define FSL_DMA_MR_CS		0x00000001
#define FSL_DMA_MR_CC		0x00000002
#define FSL_DMA_MR_CA		0x00000008
#define FSL_DMA_MR_EIE		0x00000040
#define FSL_DMA_MR_XFE		0x00000020
#define FSL_DMA_MR_EOLNIE	0x00000100
#define FSL_DMA_MR_EOLSIE	0x00000080
#define FSL_DMA_MR_EOSIE	0x00000200
#define FSL_DMA_MR_CDSM		0x00000010
#define FSL_DMA_MR_CTM		0x00000004
#define FSL_DMA_MR_EMP_EN	0x00200000
#define FSL_DMA_MR_EMS_EN	0x00040000
#define FSL_DMA_MR_DAHE		0x00002000
#define FSL_DMA_MR_SAHE		0x00001000

/*
 * Bandwidth/pause control determines how many bytes a given
 * channel is allowed to transfer before the DMA engine pauses
 * the current channel and switches to the next channel
 */
#define FSL_DMA_MR_BWC         0x0A000000

/* Special MR definition for MPC8349 */
#define FSL_DMA_MR_EOTIE	0x00000080
#define FSL_DMA_MR_PRC_RM	0x00000800

#define FSL_DMA_SR_CH		0x00000020
#define FSL_DMA_SR_PE		0x00000010
#define FSL_DMA_SR_CB		0x00000004
#define FSL_DMA_SR_TE		0x00000080
#define FSL_DMA_SR_EOSI		0x00000002
#define FSL_DMA_SR_EOLSI	0x00000001
#define FSL_DMA_SR_EOCDI	0x00000001
#define FSL_DMA_SR_EOLNI	0x00000008

#define FSL_DMA_SATR_SBPATMU			0x20000000
#define FSL_DMA_SATR_STRANSINT_RIO		0x00c00000
#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ	0x00050000
#define FSL_DMA_SATR_SREADTYPE_BP_IORH		0x00020000
#define FSL_DMA_SATR_SREADTYPE_BP_NREAD		0x00040000
#define FSL_DMA_SATR_SREADTYPE_BP_MREAD		0x00070000

#define FSL_DMA_DATR_DBPATMU			0x20000000
#define FSL_DMA_DATR_DTRANSINT_RIO		0x00c00000
#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE	0x00050000
#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH	0x00010000

#define FSL_DMA_EOL		((u64)0x1)
#define FSL_DMA_SNEN		((u64)0x10)
#define FSL_DMA_EOSIE		0x8
#define FSL_DMA_NLDA_MASK	(~(u64)0x1f)

#define FSL_DMA_BCR_MAX_CNT	0x03ffffffu

#define FSL_DMA_DGSR_TE		0x80
#define FSL_DMA_DGSR_CH		0x20
#define FSL_DMA_DGSR_PE		0x10
#define FSL_DMA_DGSR_EOLNI	0x08
#define FSL_DMA_DGSR_CB		0x04
#define FSL_DMA_DGSR_EOSI	0x02
#define FSL_DMA_DGSR_EOLSI	0x01

typedef u64 __bitwise v64;
typedef u32 __bitwise v32;

struct fsl_dma_ld_hw {
	v64 src_addr;
	v64 dst_addr;
	v64 next_ln_addr;
	v32 count;
	v32 reserve;
} __attribute__((aligned(32)));

struct fsl_desc_sw {
	struct fsl_dma_ld_hw hw;
	struct list_head node;
	struct list_head tx_list;
	struct dma_async_tx_descriptor async_tx;
} __attribute__((aligned(32)));

struct fsldma_chan_regs {
	u32 mr;		/* 0x00 - Mode Register */
	u32 sr;		/* 0x04 - Status Register */
	u64 cdar;	/* 0x08 - Current descriptor address register */
	u64 sar;	/* 0x10 - Source Address Register */
	u64 dar;	/* 0x18 - Destination Address Register */
	u32 bcr;	/* 0x20 - Byte Count Register */
	u64 ndar;	/* 0x24 - Next Descriptor Address Register */
};

struct fsldma_chan;
#define FSL_DMA_MAX_CHANS_PER_DEVICE 8

struct fsldma_device {
	void __iomem *regs;	/* DGSR register base */
	struct device *dev;
	struct dma_device common;
	struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
	u32 feature;		/* The same as DMA channels */
	int irq;		/* Channel IRQ */
};

/* Define macros for fsldma_chan->feature property */
#define FSL_DMA_LITTLE_ENDIAN	0x00000000
#define FSL_DMA_BIG_ENDIAN	0x00000001

#define FSL_DMA_IP_MASK		0x00000ff0
#define FSL_DMA_IP_85XX		0x00000010
#define FSL_DMA_IP_83XX		0x00000020

#define FSL_DMA_CHAN_PAUSE_EXT	0x00001000
#define FSL_DMA_CHAN_START_EXT	0x00002000

#ifdef CONFIG_PM
struct fsldma_chan_regs_save {
	u32 mr;
};

enum fsldma_pm_state {
	RUNNING = 0,
	SUSPENDED,
};
#endif

struct fsldma_chan {
	char name[8];			/* Channel name */
	struct fsldma_chan_regs __iomem *regs;
	spinlock_t desc_lock;		/* Descriptor operation lock */
	/*
	 * Descriptors which are queued to run, but have not yet been
	 * submitted to the hardware for execution
	 */
	struct list_head ld_pending;
	/*
	 * Descriptors which are currently being executed by the hardware
	 */
	struct list_head ld_running;
	/*
	 * Descriptors which have finished execution by the hardware. These
	 * descriptors have already had their cleanup actions run. They are
	 * waiting for the ACK bit to be set by the async_tx API.
	 */
	struct list_head ld_completed;	/* Link descriptors queue */
	struct dma_chan common;		/* DMA common channel */
	struct dma_pool *desc_pool;	/* Descriptors pool */
	struct device *dev;		/* Channel device */
	int irq;			/* Channel IRQ */
	int id;				/* Raw id of this channel */
	struct tasklet_struct tasklet;
	u32 feature;
	bool idle;			/* DMA controller is idle */
#ifdef CONFIG_PM
	struct fsldma_chan_regs_save regs_save;
	enum fsldma_pm_state pm_state;
#endif

	void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
	void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
	void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
	void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
	void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
};

#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)

#ifndef __powerpc64__
static u64 in_be64(const u64 __iomem *addr)
{
	return ((u64)in_be32((u32 __iomem *)addr) << 32) |
		(in_be32((u32 __iomem *)addr + 1));
}

static void out_be64(u64 __iomem *addr, u64 val)
{
	out_be32((u32 __iomem *)addr, val >> 32);
	out_be32((u32 __iomem *)addr + 1, (u32)val);
}

/* There is no asm instructions for 64 bits reverse loads and stores */
static u64 in_le64(const u64 __iomem *addr)
{
	return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
		(in_le32((u32 __iomem *)addr));
}

static void out_le64(u64 __iomem *addr, u64 val)
{
	out_le32((u32 __iomem *)addr + 1, val >> 32);
	out_le32((u32 __iomem *)addr, (u32)val);
}
#endif

#define DMA_IN(fsl_chan, addr, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			in_be##width(addr) : in_le##width(addr))
#define DMA_OUT(fsl_chan, addr, val, width)				\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			out_be##width(addr, val) : out_le##width(addr, val))

#define DMA_TO_CPU(fsl_chan, d, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			be##width##_to_cpu((__force __be##width)(v##width)d) : \
			le##width##_to_cpu((__force __le##width)(v##width)d))
#define CPU_TO_DMA(fsl_chan, c, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			(__force v##width)cpu_to_be##width(c) :		\
			(__force v##width)cpu_to_le##width(c))

#endif	/* __DMA_FSLDMA_H */
Commit	Line	Data
173acc7c	1	/*
f3c677b9	2	* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
173acc7c ZW	3	*
	4	* Author:
	5	* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
	6	* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
	7	*
	8	* This is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14	#ifndef __DMA_FSLDMA_H
	15	#define __DMA_FSLDMA_H
	16
	17	#include <linux/device.h>
	18	#include <linux/dmapool.h>
	19	#include <linux/dmaengine.h>
	20
	21	/* Define data structures needed by Freescale
	22	* MPC8540 and MPC8349 DMA controller.
	23	*/
	24	#define FSL_DMA_MR_CS 0x00000001
	25	#define FSL_DMA_MR_CC 0x00000002
	26	#define FSL_DMA_MR_CA 0x00000008
	27	#define FSL_DMA_MR_EIE 0x00000040
	28	#define FSL_DMA_MR_XFE 0x00000020
	29	#define FSL_DMA_MR_EOLNIE 0x00000100
	30	#define FSL_DMA_MR_EOLSIE 0x00000080
	31	#define FSL_DMA_MR_EOSIE 0x00000200
	32	#define FSL_DMA_MR_CDSM 0x00000010
	33	#define FSL_DMA_MR_CTM 0x00000004
	34	#define FSL_DMA_MR_EMP_EN 0x00200000
	35	#define FSL_DMA_MR_EMS_EN 0x00040000
	36	#define FSL_DMA_MR_DAHE 0x00002000
	37	#define FSL_DMA_MR_SAHE 0x00001000
	38
f3c677b9 FS	39	/*
	40	* Bandwidth/pause control determines how many bytes a given
	41	* channel is allowed to transfer before the DMA engine pauses
	42	* the current channel and switches to the next channel
	43	*/
0ca583a2	44	#define FSL_DMA_MR_BWC 0x0A000000
f3c677b9	45
173acc7c ZW	46	/* Special MR definition for MPC8349 */
173acc7c ZW	47	#define FSL_DMA_MR_EOTIE 0x00000080
a7aea373	48	#define FSL_DMA_MR_PRC_RM 0x00000800
173acc7c ZW	49
173acc7c ZW	50	#define FSL_DMA_SR_CH 0x00000020
f79abb62	51	#define FSL_DMA_SR_PE 0x00000010
173acc7c ZW	52	#define FSL_DMA_SR_CB 0x00000004
	53	#define FSL_DMA_SR_TE 0x00000080
	54	#define FSL_DMA_SR_EOSI 0x00000002
	55	#define FSL_DMA_SR_EOLSI 0x00000001
	56	#define FSL_DMA_SR_EOCDI 0x00000001
	57	#define FSL_DMA_SR_EOLNI 0x00000008
	58
	59	#define FSL_DMA_SATR_SBPATMU 0x20000000
	60	#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
	61	#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
	62	#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
	63	#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
	64	#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
	65
	66	#define FSL_DMA_DATR_DBPATMU 0x20000000
	67	#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
	68	#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
	69	#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
	70
	71	#define FSL_DMA_EOL ((u64)0x1)
	72	#define FSL_DMA_SNEN ((u64)0x10)
	73	#define FSL_DMA_EOSIE 0x8
	74	#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
	75
	76	#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
	77
	78	#define FSL_DMA_DGSR_TE 0x80
	79	#define FSL_DMA_DGSR_CH 0x20
	80	#define FSL_DMA_DGSR_PE 0x10
	81	#define FSL_DMA_DGSR_EOLNI 0x08
	82	#define FSL_DMA_DGSR_CB 0x04
	83	#define FSL_DMA_DGSR_EOSI 0x02
	84	#define FSL_DMA_DGSR_EOLSI 0x01
	85
a4e6d5d3 AV	86	typedef u64 __bitwise v64;
	87	typedef u32 __bitwise v32;
	88
173acc7c	89	struct fsl_dma_ld_hw {
a4e6d5d3 AV	90	v64 src_addr;
	91	v64 dst_addr;
	92	v64 next_ln_addr;
	93	v32 count;
	94	v32 reserve;
173acc7c ZW	95	} __attribute__((aligned(32)));
	96
	97	struct fsl_desc_sw {
	98	struct fsl_dma_ld_hw hw;
	99	struct list_head node;
eda34234	100	struct list_head tx_list;
173acc7c	101	struct dma_async_tx_descriptor async_tx;
173acc7c ZW	102	} __attribute__((aligned(32)));
173acc7c ZW	103
a4f56d4b	104	struct fsldma_chan_regs {
31f4306c IS	105	u32 mr; /* 0x00 - Mode Register */
31f4306c IS	106	u32 sr; /* 0x04 - Status Register */
a4e6d5d3 AV	107	u64 cdar; /* 0x08 - Current descriptor address register */
	108	u64 sar; /* 0x10 - Source Address Register */
	109	u64 dar; /* 0x18 - Destination Address Register */
	110	u32 bcr; /* 0x20 - Byte Count Register */
	111	u64 ndar; /* 0x24 - Next Descriptor Address Register */
173acc7c ZW	112	};
173acc7c ZW	113
a4f56d4b	114	struct fsldma_chan;
8de7a7d9	115	#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
173acc7c	116
a4f56d4b	117	struct fsldma_device {
e7a29151	118	void __iomem regs; / DGSR register base */
173acc7c ZW	119	struct device *dev;
173acc7c ZW	120	struct dma_device common;
a4f56d4b	121	struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
173acc7c	122	u32 feature; /* The same as DMA channels */
77cd62e8	123	int irq; /* Channel IRQ */
173acc7c ZW	124	};
173acc7c ZW	125
a4f56d4b	126	/* Define macros for fsldma_chan->feature property */
173acc7c ZW	127	#define FSL_DMA_LITTLE_ENDIAN 0x00000000
	128	#define FSL_DMA_BIG_ENDIAN 0x00000001
	129
	130	#define FSL_DMA_IP_MASK 0x00000ff0
	131	#define FSL_DMA_IP_85XX 0x00000010
	132	#define FSL_DMA_IP_83XX 0x00000020
	133
	134	#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
	135	#define FSL_DMA_CHAN_START_EXT 0x00002000
	136
14c6a333 HZ	137	#ifdef CONFIG_PM
	138	struct fsldma_chan_regs_save {
	139	u32 mr;
	140	};
	141
	142	enum fsldma_pm_state {
	143	RUNNING = 0,
	144	SUSPENDED,
	145	};
	146	#endif
	147
a4f56d4b	148	struct fsldma_chan {
b158471e	149	char name[8]; /* Channel name */
e7a29151	150	struct fsldma_chan_regs __iomem *regs;
173acc7c	151	spinlock_t desc_lock; /* Descriptor operation lock */
43452fad HZ	152	/*
	153	* Descriptors which are queued to run, but have not yet been
	154	* submitted to the hardware for execution
	155	*/
	156	struct list_head ld_pending;
	157	/*
	158	* Descriptors which are currently being executed by the hardware
	159	*/
	160	struct list_head ld_running;
	161	/*
	162	* Descriptors which have finished execution by the hardware. These
	163	* descriptors have already had their cleanup actions run. They are
	164	* waiting for the ACK bit to be set by the async_tx API.
	165	*/
	166	struct list_head ld_completed; /* Link descriptors queue */
173acc7c ZW	167	struct dma_chan common; /* DMA common channel */
	168	struct dma_pool desc_pool; / Descriptors pool */
	169	struct device dev; / Channel device */
173acc7c ZW	170	int irq; /* Channel IRQ */
	171	int id; /* Raw id of this channel */
	172	struct tasklet_struct tasklet;
	173	u32 feature;
f04cd407	174	bool idle; /* DMA controller is idle */
14c6a333 HZ	175	#ifdef CONFIG_PM
	176	struct fsldma_chan_regs_save regs_save;
	177	enum fsldma_pm_state pm_state;
	178	#endif
173acc7c	179
a4f56d4b IS	180	void (toggle_ext_pause)(struct fsldma_chan fsl_chan, int enable);
	181	void (toggle_ext_start)(struct fsldma_chan fsl_chan, int enable);
	182	void (set_src_loop_size)(struct fsldma_chan fsl_chan, int size);
738f5f7e	183	void (set_dst_loop_size)(struct fsldma_chan fsl_chan, int size);
a4f56d4b	184	void (set_request_count)(struct fsldma_chan fsl_chan, int size);
173acc7c ZW	185	};
173acc7c ZW	186
a4f56d4b	187	#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
173acc7c ZW	188	#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
	189	#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
	190
	191	#ifndef __powerpc64__
	192	static u64 in_be64(const u64 __iomem *addr)
	193	{
a4e6d5d3 AV	194	return ((u64)in_be32((u32 __iomem *)addr) << 32) \|
a4e6d5d3 AV	195	(in_be32((u32 __iomem *)addr + 1));
173acc7c ZW	196	}
	197
	198	static void out_be64(u64 __iomem *addr, u64 val)
	199	{
a4e6d5d3 AV	200	out_be32((u32 __iomem *)addr, val >> 32);
a4e6d5d3 AV	201	out_be32((u32 __iomem *)addr + 1, (u32)val);
173acc7c ZW	202	}
	203
	204	/* There is no asm instructions for 64 bits reverse loads and stores */
	205	static u64 in_le64(const u64 __iomem *addr)
	206	{
a4e6d5d3 AV	207	return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) \|
a4e6d5d3 AV	208	(in_le32((u32 __iomem *)addr));
173acc7c ZW	209	}
	210
	211	static void out_le64(u64 __iomem *addr, u64 val)
	212	{
a4e6d5d3 AV	213	out_le32((u32 __iomem *)addr + 1, val >> 32);
a4e6d5d3 AV	214	out_le32((u32 __iomem *)addr, (u32)val);
173acc7c ZW	215	}
	216	#endif
	217
	218	#define DMA_IN(fsl_chan, addr, width) \
	219	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
	220	in_be##width(addr) : in_le##width(addr))
	221	#define DMA_OUT(fsl_chan, addr, val, width) \
	222	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
	223	out_be##width(addr, val) : out_le##width(addr, val))
	224
	225	#define DMA_TO_CPU(fsl_chan, d, width) \
	226	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
a4e6d5d3 AV	227	be##width##_to_cpu((__force __be##width)(v##width)d) : \
a4e6d5d3 AV	228	le##width##_to_cpu((__force __le##width)(v##width)d))
173acc7c ZW	229	#define CPU_TO_DMA(fsl_chan, c, width) \
173acc7c ZW	230	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
a4e6d5d3 AV	231	(__force v##width)cpu_to_be##width(c) : \
a4e6d5d3 AV	232	(__force v##width)cpu_to_le##width(c))
173acc7c ZW	233
173acc7c ZW	234	#endif /* __DMA_FSLDMA_H */