Commit | Line | Data |
---|---|---|
173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
36 | #include <linux/of_platform.h> | |
37 | ||
38 | #include "fsldma.h" | |
39 | ||
b158471e IS |
40 | #define chan_dbg(chan, fmt, arg...) \ |
41 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
42 | #define chan_err(chan, fmt, arg...) \ | |
43 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
c1433041 | 44 | |
b158471e | 45 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
173acc7c | 46 | |
e8bd84df IS |
47 | /* |
48 | * Register Helpers | |
49 | */ | |
173acc7c | 50 | |
a1c03319 | 51 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 52 | { |
a1c03319 | 53 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
54 | } |
55 | ||
a1c03319 | 56 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 57 | { |
a1c03319 | 58 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
59 | } |
60 | ||
e8bd84df IS |
61 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
62 | { | |
63 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
64 | } | |
65 | ||
66 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
67 | { | |
68 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
69 | } | |
70 | ||
e8bd84df IS |
71 | static u32 get_bcr(struct fsldma_chan *chan) |
72 | { | |
73 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
74 | } | |
75 | ||
76 | /* | |
77 | * Descriptor Helpers | |
78 | */ | |
79 | ||
a1c03319 | 80 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
81 | struct fsl_dma_ld_hw *hw, u32 count) |
82 | { | |
a1c03319 | 83 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
84 | } |
85 | ||
9c4d1e7b IS |
86 | static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
87 | { | |
88 | return DMA_TO_CPU(chan, desc->hw.count, 32); | |
89 | } | |
90 | ||
a1c03319 | 91 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 92 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
93 | { |
94 | u64 snoop_bits; | |
95 | ||
a1c03319 | 96 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 97 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 98 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
99 | } |
100 | ||
9c4d1e7b IS |
101 | static dma_addr_t get_desc_src(struct fsldma_chan *chan, |
102 | struct fsl_desc_sw *desc) | |
103 | { | |
104 | u64 snoop_bits; | |
105 | ||
106 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) | |
107 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; | |
108 | return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits; | |
109 | } | |
110 | ||
a1c03319 | 111 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 112 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
113 | { |
114 | u64 snoop_bits; | |
115 | ||
a1c03319 | 116 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 117 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 118 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
119 | } |
120 | ||
9c4d1e7b IS |
121 | static dma_addr_t get_desc_dst(struct fsldma_chan *chan, |
122 | struct fsl_desc_sw *desc) | |
123 | { | |
124 | u64 snoop_bits; | |
125 | ||
126 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) | |
127 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; | |
128 | return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits; | |
129 | } | |
130 | ||
a1c03319 | 131 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 132 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
133 | { |
134 | u64 snoop_bits; | |
135 | ||
a1c03319 | 136 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 137 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 138 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
139 | } |
140 | ||
31f4306c | 141 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 142 | { |
e8bd84df | 143 | u64 snoop_bits; |
173acc7c | 144 | |
e8bd84df IS |
145 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
146 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 147 | |
e8bd84df IS |
148 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
149 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
150 | | snoop_bits, 64); | |
173acc7c ZW |
151 | } |
152 | ||
e8bd84df IS |
153 | /* |
154 | * DMA Engine Hardware Control Helpers | |
155 | */ | |
156 | ||
157 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 158 | { |
e8bd84df IS |
159 | /* Reset the channel */ |
160 | DMA_OUT(chan, &chan->regs->mr, 0, 32); | |
161 | ||
162 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
163 | case FSL_DMA_IP_85XX: | |
164 | /* Set the channel to below modes: | |
165 | * EIE - Error interrupt enable | |
e8bd84df IS |
166 | * EOLNIE - End of links interrupt enable |
167 | * BWC - Bandwidth sharing among channels | |
168 | */ | |
169 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC | |
f04cd407 | 170 | | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32); |
e8bd84df IS |
171 | break; |
172 | case FSL_DMA_IP_83XX: | |
173 | /* Set the channel to below modes: | |
174 | * EOTIE - End-of-transfer interrupt enable | |
175 | * PRC_RM - PCI read multiple | |
176 | */ | |
177 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE | |
178 | | FSL_DMA_MR_PRC_RM, 32); | |
179 | break; | |
180 | } | |
f79abb62 ZW |
181 | } |
182 | ||
a1c03319 | 183 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 184 | { |
a1c03319 | 185 | u32 sr = get_sr(chan); |
173acc7c ZW |
186 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
187 | } | |
188 | ||
f04cd407 IS |
189 | /* |
190 | * Start the DMA controller | |
191 | * | |
192 | * Preconditions: | |
193 | * - the CDAR register must point to the start descriptor | |
194 | * - the MRn[CS] bit must be cleared | |
195 | */ | |
a1c03319 | 196 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 197 | { |
272ca655 IS |
198 | u32 mode; |
199 | ||
a1c03319 | 200 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 201 | |
f04cd407 IS |
202 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
203 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
204 | mode |= FSL_DMA_MR_EMP_EN; | |
205 | } else { | |
206 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 207 | } |
173acc7c | 208 | |
f04cd407 | 209 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 210 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
211 | } else { |
212 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 213 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 214 | } |
173acc7c | 215 | |
a1c03319 | 216 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
217 | } |
218 | ||
a1c03319 | 219 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 220 | { |
272ca655 | 221 | u32 mode; |
900325a6 DW |
222 | int i; |
223 | ||
a00ae34a | 224 | /* read the mode register */ |
a1c03319 | 225 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 226 | |
a00ae34a IS |
227 | /* |
228 | * The 85xx controller supports channel abort, which will stop | |
229 | * the current transfer. On 83xx, this bit is the transfer error | |
230 | * mask bit, which should not be changed. | |
231 | */ | |
232 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
233 | mode |= FSL_DMA_MR_CA; | |
234 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
235 | ||
236 | mode &= ~FSL_DMA_MR_CA; | |
237 | } | |
238 | ||
239 | /* stop the DMA controller */ | |
240 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); | |
a1c03319 | 241 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 242 | |
a00ae34a | 243 | /* wait for the DMA controller to become idle */ |
900325a6 | 244 | for (i = 0; i < 100; i++) { |
a1c03319 | 245 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
246 | return; |
247 | ||
173acc7c | 248 | udelay(10); |
900325a6 | 249 | } |
272ca655 | 250 | |
9c3a50b7 | 251 | if (!dma_is_idle(chan)) |
b158471e | 252 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
253 | } |
254 | ||
173acc7c ZW |
255 | /** |
256 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 257 | * @chan : Freescale DMA channel |
173acc7c ZW |
258 | * @size : Address loop size, 0 for disable loop |
259 | * | |
260 | * The set source address hold transfer size. The source | |
261 | * address hold or loop transfer size is when the DMA transfer | |
262 | * data from source address (SA), if the loop size is 4, the DMA will | |
263 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
264 | * SA + 1 ... and so on. | |
265 | */ | |
a1c03319 | 266 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 267 | { |
272ca655 IS |
268 | u32 mode; |
269 | ||
a1c03319 | 270 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 271 | |
173acc7c ZW |
272 | switch (size) { |
273 | case 0: | |
272ca655 | 274 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
275 | break; |
276 | case 1: | |
277 | case 2: | |
278 | case 4: | |
279 | case 8: | |
272ca655 | 280 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
281 | break; |
282 | } | |
272ca655 | 283 | |
a1c03319 | 284 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
285 | } |
286 | ||
287 | /** | |
738f5f7e | 288 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 289 | * @chan : Freescale DMA channel |
173acc7c ZW |
290 | * @size : Address loop size, 0 for disable loop |
291 | * | |
292 | * The set destination address hold transfer size. The destination | |
293 | * address hold or loop transfer size is when the DMA transfer | |
294 | * data to destination address (TA), if the loop size is 4, the DMA will | |
295 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
296 | * TA + 1 ... and so on. | |
297 | */ | |
a1c03319 | 298 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 299 | { |
272ca655 IS |
300 | u32 mode; |
301 | ||
a1c03319 | 302 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 303 | |
173acc7c ZW |
304 | switch (size) { |
305 | case 0: | |
272ca655 | 306 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
307 | break; |
308 | case 1: | |
309 | case 2: | |
310 | case 4: | |
311 | case 8: | |
272ca655 | 312 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
313 | break; |
314 | } | |
272ca655 | 315 | |
a1c03319 | 316 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
317 | } |
318 | ||
319 | /** | |
e6c7ecb6 | 320 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 321 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
322 | * @size : Number of bytes to transfer in a single request |
323 | * | |
324 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
325 | * The DMA request count is how many bytes are allowed to transfer before | |
326 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
327 | * operation. | |
173acc7c | 328 | * |
e6c7ecb6 | 329 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 330 | */ |
a1c03319 | 331 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 332 | { |
272ca655 IS |
333 | u32 mode; |
334 | ||
e6c7ecb6 | 335 | BUG_ON(size > 1024); |
272ca655 | 336 | |
a1c03319 | 337 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
338 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
339 | ||
a1c03319 | 340 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 341 | } |
173acc7c | 342 | |
e6c7ecb6 IS |
343 | /** |
344 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 345 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
346 | * @enable : 0 is disabled, 1 is enabled. |
347 | * | |
348 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
349 | * The DMA Request Count feature should be used in addition to this feature | |
350 | * to set the number of bytes to transfer before pausing the channel. | |
351 | */ | |
a1c03319 | 352 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
353 | { |
354 | if (enable) | |
a1c03319 | 355 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 356 | else |
a1c03319 | 357 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
358 | } |
359 | ||
360 | /** | |
361 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 362 | * @chan : Freescale DMA channel |
173acc7c ZW |
363 | * @enable : 0 is disabled, 1 is enabled. |
364 | * | |
365 | * If enable the external start, the channel can be started by an | |
366 | * external DMA start pin. So the dma_start() does not start the | |
367 | * transfer immediately. The DMA channel will wait for the | |
368 | * control pin asserted. | |
369 | */ | |
a1c03319 | 370 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
371 | { |
372 | if (enable) | |
a1c03319 | 373 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 374 | else |
a1c03319 | 375 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
376 | } |
377 | ||
31f4306c | 378 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
379 | { |
380 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
381 | ||
382 | if (list_empty(&chan->ld_pending)) | |
383 | goto out_splice; | |
384 | ||
385 | /* | |
386 | * Add the hardware descriptor to the chain of hardware descriptors | |
387 | * that already exists in memory. | |
388 | * | |
389 | * This will un-set the EOL bit of the existing transaction, and the | |
390 | * last link in this transaction will become the EOL descriptor. | |
391 | */ | |
392 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
393 | ||
394 | /* | |
395 | * Add the software descriptor and all children to the list | |
396 | * of pending transactions | |
397 | */ | |
398 | out_splice: | |
399 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
400 | } | |
401 | ||
173acc7c ZW |
402 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
403 | { | |
a1c03319 | 404 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
405 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
406 | struct fsl_desc_sw *child; | |
173acc7c ZW |
407 | unsigned long flags; |
408 | dma_cookie_t cookie; | |
409 | ||
a1c03319 | 410 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 411 | |
9c3a50b7 IS |
412 | /* |
413 | * assign cookies to all of the software descriptors | |
414 | * that make up this transaction | |
415 | */ | |
a1c03319 | 416 | cookie = chan->common.cookie; |
eda34234 | 417 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 | 418 | cookie++; |
31f4306c IS |
419 | if (cookie < DMA_MIN_COOKIE) |
420 | cookie = DMA_MIN_COOKIE; | |
bcfb7465 | 421 | |
6ca3a7a9 | 422 | child->async_tx.cookie = cookie; |
bcfb7465 IS |
423 | } |
424 | ||
a1c03319 | 425 | chan->common.cookie = cookie; |
9c3a50b7 IS |
426 | |
427 | /* put this transaction onto the tail of the pending queue */ | |
a1c03319 | 428 | append_ld_queue(chan, desc); |
173acc7c | 429 | |
a1c03319 | 430 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
431 | |
432 | return cookie; | |
433 | } | |
434 | ||
435 | /** | |
436 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 437 | * @chan : Freescale DMA channel |
173acc7c ZW |
438 | * |
439 | * Return - The descriptor allocated. NULL for failed. | |
440 | */ | |
31f4306c | 441 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 442 | { |
9c3a50b7 | 443 | struct fsl_desc_sw *desc; |
173acc7c | 444 | dma_addr_t pdesc; |
9c3a50b7 IS |
445 | |
446 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
447 | if (!desc) { | |
b158471e | 448 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 449 | return NULL; |
173acc7c ZW |
450 | } |
451 | ||
9c3a50b7 IS |
452 | memset(desc, 0, sizeof(*desc)); |
453 | INIT_LIST_HEAD(&desc->tx_list); | |
454 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
455 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
456 | desc->async_tx.phys = pdesc; | |
457 | ||
0ab09c36 IS |
458 | #ifdef FSL_DMA_LD_DEBUG |
459 | chan_dbg(chan, "LD %p allocated\n", desc); | |
460 | #endif | |
461 | ||
9c3a50b7 | 462 | return desc; |
173acc7c ZW |
463 | } |
464 | ||
173acc7c ZW |
465 | /** |
466 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 467 | * @chan : Freescale DMA channel |
173acc7c ZW |
468 | * |
469 | * This function will create a dma pool for descriptor allocation. | |
470 | * | |
471 | * Return - The number of descriptors allocated. | |
472 | */ | |
a1c03319 | 473 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 474 | { |
a1c03319 | 475 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
476 | |
477 | /* Has this channel already been allocated? */ | |
a1c03319 | 478 | if (chan->desc_pool) |
77cd62e8 | 479 | return 1; |
173acc7c | 480 | |
9c3a50b7 IS |
481 | /* |
482 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
483 | * for meeting FSL DMA specification requirement. |
484 | */ | |
b158471e | 485 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
486 | sizeof(struct fsl_desc_sw), |
487 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 488 | if (!chan->desc_pool) { |
b158471e | 489 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 490 | return -ENOMEM; |
173acc7c ZW |
491 | } |
492 | ||
9c3a50b7 | 493 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
494 | return 1; |
495 | } | |
496 | ||
9c3a50b7 IS |
497 | /** |
498 | * fsldma_free_desc_list - Free all descriptors in a queue | |
499 | * @chan: Freescae DMA channel | |
500 | * @list: the list to free | |
501 | * | |
502 | * LOCKING: must hold chan->desc_lock | |
503 | */ | |
504 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
505 | struct list_head *list) | |
506 | { | |
507 | struct fsl_desc_sw *desc, *_desc; | |
508 | ||
509 | list_for_each_entry_safe(desc, _desc, list, node) { | |
510 | list_del(&desc->node); | |
0ab09c36 IS |
511 | #ifdef FSL_DMA_LD_DEBUG |
512 | chan_dbg(chan, "LD %p free\n", desc); | |
513 | #endif | |
9c3a50b7 IS |
514 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
515 | } | |
516 | } | |
517 | ||
518 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
519 | struct list_head *list) | |
520 | { | |
521 | struct fsl_desc_sw *desc, *_desc; | |
522 | ||
523 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
524 | list_del(&desc->node); | |
0ab09c36 IS |
525 | #ifdef FSL_DMA_LD_DEBUG |
526 | chan_dbg(chan, "LD %p free\n", desc); | |
527 | #endif | |
9c3a50b7 IS |
528 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
529 | } | |
530 | } | |
531 | ||
173acc7c ZW |
532 | /** |
533 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 534 | * @chan : Freescale DMA channel |
173acc7c | 535 | */ |
a1c03319 | 536 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 537 | { |
a1c03319 | 538 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
539 | unsigned long flags; |
540 | ||
b158471e | 541 | chan_dbg(chan, "free all channel resources\n"); |
a1c03319 | 542 | spin_lock_irqsave(&chan->desc_lock, flags); |
9c3a50b7 IS |
543 | fsldma_free_desc_list(chan, &chan->ld_pending); |
544 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 545 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 546 | |
9c3a50b7 | 547 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 548 | chan->desc_pool = NULL; |
173acc7c ZW |
549 | } |
550 | ||
2187c269 | 551 | static struct dma_async_tx_descriptor * |
a1c03319 | 552 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 553 | { |
a1c03319 | 554 | struct fsldma_chan *chan; |
2187c269 ZW |
555 | struct fsl_desc_sw *new; |
556 | ||
a1c03319 | 557 | if (!dchan) |
2187c269 ZW |
558 | return NULL; |
559 | ||
a1c03319 | 560 | chan = to_fsl_chan(dchan); |
2187c269 | 561 | |
a1c03319 | 562 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 563 | if (!new) { |
b158471e | 564 | chan_err(chan, "%s\n", msg_ld_oom); |
2187c269 ZW |
565 | return NULL; |
566 | } | |
567 | ||
568 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 569 | new->async_tx.flags = flags; |
2187c269 | 570 | |
f79abb62 | 571 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 572 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 573 | |
31f4306c | 574 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 575 | set_ld_eol(chan, new); |
2187c269 ZW |
576 | |
577 | return &new->async_tx; | |
578 | } | |
579 | ||
31f4306c IS |
580 | static struct dma_async_tx_descriptor * |
581 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
582 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
583 | size_t len, unsigned long flags) |
584 | { | |
a1c03319 | 585 | struct fsldma_chan *chan; |
173acc7c ZW |
586 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
587 | size_t copy; | |
173acc7c | 588 | |
a1c03319 | 589 | if (!dchan) |
173acc7c ZW |
590 | return NULL; |
591 | ||
592 | if (!len) | |
593 | return NULL; | |
594 | ||
a1c03319 | 595 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
596 | |
597 | do { | |
598 | ||
599 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 600 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 601 | if (!new) { |
b158471e | 602 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 603 | goto fail; |
173acc7c | 604 | } |
173acc7c | 605 | |
56822843 | 606 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 607 | |
a1c03319 IS |
608 | set_desc_cnt(chan, &new->hw, copy); |
609 | set_desc_src(chan, &new->hw, dma_src); | |
610 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
611 | |
612 | if (!first) | |
613 | first = new; | |
614 | else | |
a1c03319 | 615 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
616 | |
617 | new->async_tx.cookie = 0; | |
636bdeaa | 618 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
619 | |
620 | prev = new; | |
621 | len -= copy; | |
622 | dma_src += copy; | |
738f5f7e | 623 | dma_dst += copy; |
173acc7c ZW |
624 | |
625 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 626 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
627 | } while (len); |
628 | ||
636bdeaa | 629 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
630 | new->async_tx.cookie = -EBUSY; |
631 | ||
31f4306c | 632 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 633 | set_ld_eol(chan, new); |
173acc7c | 634 | |
2e077f8e IS |
635 | return &first->async_tx; |
636 | ||
637 | fail: | |
638 | if (!first) | |
639 | return NULL; | |
640 | ||
9c3a50b7 | 641 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 642 | return NULL; |
173acc7c ZW |
643 | } |
644 | ||
c1433041 IS |
645 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
646 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
647 | struct scatterlist *src_sg, unsigned int src_nents, | |
648 | unsigned long flags) | |
649 | { | |
650 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
651 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
652 | size_t dst_avail, src_avail; | |
653 | dma_addr_t dst, src; | |
654 | size_t len; | |
655 | ||
656 | /* basic sanity checks */ | |
657 | if (dst_nents == 0 || src_nents == 0) | |
658 | return NULL; | |
659 | ||
660 | if (dst_sg == NULL || src_sg == NULL) | |
661 | return NULL; | |
662 | ||
663 | /* | |
664 | * TODO: should we check that both scatterlists have the same | |
665 | * TODO: number of bytes in total? Is that really an error? | |
666 | */ | |
667 | ||
668 | /* get prepared for the loop */ | |
669 | dst_avail = sg_dma_len(dst_sg); | |
670 | src_avail = sg_dma_len(src_sg); | |
671 | ||
672 | /* run until we are out of scatterlist entries */ | |
673 | while (true) { | |
674 | ||
675 | /* create the largest transaction possible */ | |
676 | len = min_t(size_t, src_avail, dst_avail); | |
677 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
678 | if (len == 0) | |
679 | goto fetch; | |
680 | ||
681 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
682 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
683 | ||
684 | /* allocate and populate the descriptor */ | |
685 | new = fsl_dma_alloc_descriptor(chan); | |
686 | if (!new) { | |
b158471e | 687 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
688 | goto fail; |
689 | } | |
c1433041 IS |
690 | |
691 | set_desc_cnt(chan, &new->hw, len); | |
692 | set_desc_src(chan, &new->hw, src); | |
693 | set_desc_dst(chan, &new->hw, dst); | |
694 | ||
695 | if (!first) | |
696 | first = new; | |
697 | else | |
698 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
699 | ||
700 | new->async_tx.cookie = 0; | |
701 | async_tx_ack(&new->async_tx); | |
702 | prev = new; | |
703 | ||
704 | /* Insert the link descriptor to the LD ring */ | |
705 | list_add_tail(&new->node, &first->tx_list); | |
706 | ||
707 | /* update metadata */ | |
708 | dst_avail -= len; | |
709 | src_avail -= len; | |
710 | ||
711 | fetch: | |
712 | /* fetch the next dst scatterlist entry */ | |
713 | if (dst_avail == 0) { | |
714 | ||
715 | /* no more entries: we're done */ | |
716 | if (dst_nents == 0) | |
717 | break; | |
718 | ||
719 | /* fetch the next entry: if there are no more: done */ | |
720 | dst_sg = sg_next(dst_sg); | |
721 | if (dst_sg == NULL) | |
722 | break; | |
723 | ||
724 | dst_nents--; | |
725 | dst_avail = sg_dma_len(dst_sg); | |
726 | } | |
727 | ||
728 | /* fetch the next src scatterlist entry */ | |
729 | if (src_avail == 0) { | |
730 | ||
731 | /* no more entries: we're done */ | |
732 | if (src_nents == 0) | |
733 | break; | |
734 | ||
735 | /* fetch the next entry: if there are no more: done */ | |
736 | src_sg = sg_next(src_sg); | |
737 | if (src_sg == NULL) | |
738 | break; | |
739 | ||
740 | src_nents--; | |
741 | src_avail = sg_dma_len(src_sg); | |
742 | } | |
743 | } | |
744 | ||
745 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
746 | new->async_tx.cookie = -EBUSY; | |
747 | ||
748 | /* Set End-of-link to the last link descriptor of new list */ | |
749 | set_ld_eol(chan, new); | |
750 | ||
751 | return &first->async_tx; | |
752 | ||
753 | fail: | |
754 | if (!first) | |
755 | return NULL; | |
756 | ||
757 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
758 | return NULL; | |
759 | } | |
760 | ||
bbea0b6e IS |
761 | /** |
762 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
763 | * @chan: DMA channel | |
764 | * @sgl: scatterlist to transfer to/from | |
765 | * @sg_len: number of entries in @scatterlist | |
766 | * @direction: DMA direction | |
767 | * @flags: DMAEngine flags | |
768 | * | |
769 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
770 | * DMA_SLAVE API, this gets the device-specific information from the | |
771 | * chan->private variable. | |
772 | */ | |
773 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 774 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
775 | enum dma_data_direction direction, unsigned long flags) |
776 | { | |
bbea0b6e | 777 | /* |
968f19ae | 778 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 779 | * |
968f19ae IS |
780 | * However, we need to provide the function pointer to allow the |
781 | * device_control() method to work. | |
bbea0b6e | 782 | */ |
bbea0b6e IS |
783 | return NULL; |
784 | } | |
785 | ||
c3635c78 | 786 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 787 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 788 | { |
968f19ae | 789 | struct dma_slave_config *config; |
a1c03319 | 790 | struct fsldma_chan *chan; |
bbea0b6e | 791 | unsigned long flags; |
968f19ae | 792 | int size; |
c3635c78 | 793 | |
a1c03319 | 794 | if (!dchan) |
c3635c78 | 795 | return -EINVAL; |
bbea0b6e | 796 | |
a1c03319 | 797 | chan = to_fsl_chan(dchan); |
bbea0b6e | 798 | |
968f19ae IS |
799 | switch (cmd) { |
800 | case DMA_TERMINATE_ALL: | |
f04cd407 IS |
801 | spin_lock_irqsave(&chan->desc_lock, flags); |
802 | ||
968f19ae IS |
803 | /* Halt the DMA engine */ |
804 | dma_halt(chan); | |
bbea0b6e | 805 | |
968f19ae IS |
806 | /* Remove and free all of the descriptors in the LD queue */ |
807 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
808 | fsldma_free_desc_list(chan, &chan->ld_running); | |
f04cd407 | 809 | chan->idle = true; |
bbea0b6e | 810 | |
968f19ae IS |
811 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
812 | return 0; | |
813 | ||
814 | case DMA_SLAVE_CONFIG: | |
815 | config = (struct dma_slave_config *)arg; | |
816 | ||
817 | /* make sure the channel supports setting burst size */ | |
818 | if (!chan->set_request_count) | |
819 | return -ENXIO; | |
820 | ||
821 | /* we set the controller burst size depending on direction */ | |
822 | if (config->direction == DMA_TO_DEVICE) | |
823 | size = config->dst_addr_width * config->dst_maxburst; | |
824 | else | |
825 | size = config->src_addr_width * config->src_maxburst; | |
826 | ||
827 | chan->set_request_count(chan, size); | |
828 | return 0; | |
829 | ||
830 | case FSLDMA_EXTERNAL_START: | |
831 | ||
832 | /* make sure the channel supports external start */ | |
833 | if (!chan->toggle_ext_start) | |
834 | return -ENXIO; | |
835 | ||
836 | chan->toggle_ext_start(chan, arg); | |
837 | return 0; | |
838 | ||
839 | default: | |
840 | return -ENXIO; | |
841 | } | |
c3635c78 LW |
842 | |
843 | return 0; | |
bbea0b6e IS |
844 | } |
845 | ||
173acc7c | 846 | /** |
9c4d1e7b | 847 | * fsldma_cleanup_descriptor - cleanup and free a single link descriptor |
9c3a50b7 | 848 | * @chan: Freescale DMA channel |
9c4d1e7b | 849 | * @desc: descriptor to cleanup and free |
173acc7c | 850 | * |
9c4d1e7b IS |
851 | * This function is used on a descriptor which has been executed by the DMA |
852 | * controller. It will run any callbacks, submit any dependencies, and then | |
853 | * free the descriptor. | |
173acc7c | 854 | */ |
9c4d1e7b IS |
855 | static void fsldma_cleanup_descriptor(struct fsldma_chan *chan, |
856 | struct fsl_desc_sw *desc) | |
173acc7c | 857 | { |
9c4d1e7b IS |
858 | struct dma_async_tx_descriptor *txd = &desc->async_tx; |
859 | struct device *dev = chan->common.device->dev; | |
860 | dma_addr_t src = get_desc_src(chan, desc); | |
861 | dma_addr_t dst = get_desc_dst(chan, desc); | |
862 | u32 len = get_desc_cnt(chan, desc); | |
863 | ||
864 | /* Run the link descriptor callback function */ | |
865 | if (txd->callback) { | |
866 | #ifdef FSL_DMA_LD_DEBUG | |
867 | chan_dbg(chan, "LD %p callback\n", desc); | |
868 | #endif | |
869 | txd->callback(txd->callback_param); | |
870 | } | |
173acc7c | 871 | |
9c4d1e7b IS |
872 | /* Run any dependencies */ |
873 | dma_run_dependencies(txd); | |
173acc7c | 874 | |
9c4d1e7b IS |
875 | /* Unmap the dst buffer, if requested */ |
876 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
877 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
878 | dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE); | |
879 | else | |
880 | dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE); | |
881 | } | |
9c3a50b7 | 882 | |
9c4d1e7b IS |
883 | /* Unmap the src buffer, if requested */ |
884 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
885 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
886 | dma_unmap_single(dev, src, len, DMA_TO_DEVICE); | |
887 | else | |
888 | dma_unmap_page(dev, src, len, DMA_TO_DEVICE); | |
173acc7c | 889 | } |
9c3a50b7 | 890 | |
9c4d1e7b IS |
891 | #ifdef FSL_DMA_LD_DEBUG |
892 | chan_dbg(chan, "LD %p free\n", desc); | |
893 | #endif | |
894 | dma_pool_free(chan->desc_pool, desc, txd->phys); | |
173acc7c ZW |
895 | } |
896 | ||
897 | /** | |
9c3a50b7 | 898 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 899 | * @chan : Freescale DMA channel |
9c3a50b7 | 900 | * |
f04cd407 | 901 | * HARDWARE STATE: idle |
dc8d4091 | 902 | * LOCKING: must hold chan->desc_lock |
173acc7c | 903 | */ |
a1c03319 | 904 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 905 | { |
9c3a50b7 | 906 | struct fsl_desc_sw *desc; |
138ef018 | 907 | |
9c3a50b7 IS |
908 | /* |
909 | * If the list of pending descriptors is empty, then we | |
910 | * don't need to do any work at all | |
911 | */ | |
912 | if (list_empty(&chan->ld_pending)) { | |
b158471e | 913 | chan_dbg(chan, "no pending LDs\n"); |
dc8d4091 | 914 | return; |
9c3a50b7 | 915 | } |
173acc7c | 916 | |
9c3a50b7 | 917 | /* |
f04cd407 IS |
918 | * The DMA controller is not idle, which means that the interrupt |
919 | * handler will start any queued transactions when it runs after | |
920 | * this transaction finishes | |
9c3a50b7 | 921 | */ |
f04cd407 | 922 | if (!chan->idle) { |
b158471e | 923 | chan_dbg(chan, "DMA controller still busy\n"); |
dc8d4091 | 924 | return; |
9c3a50b7 IS |
925 | } |
926 | ||
9c3a50b7 IS |
927 | /* |
928 | * If there are some link descriptors which have not been | |
929 | * transferred, we need to start the controller | |
173acc7c | 930 | */ |
173acc7c | 931 | |
9c3a50b7 IS |
932 | /* |
933 | * Move all elements from the queue of pending transactions | |
934 | * onto the list of running transactions | |
935 | */ | |
f04cd407 | 936 | chan_dbg(chan, "idle, starting controller\n"); |
9c3a50b7 IS |
937 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); |
938 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
939 | ||
f04cd407 IS |
940 | /* |
941 | * The 85xx DMA controller doesn't clear the channel start bit | |
942 | * automatically at the end of a transfer. Therefore we must clear | |
943 | * it in software before starting the transfer. | |
944 | */ | |
945 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
946 | u32 mode; | |
947 | ||
948 | mode = DMA_IN(chan, &chan->regs->mr, 32); | |
949 | mode &= ~FSL_DMA_MR_CS; | |
950 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
951 | } | |
952 | ||
9c3a50b7 IS |
953 | /* |
954 | * Program the descriptor's address into the DMA controller, | |
955 | * then start the DMA transaction | |
956 | */ | |
957 | set_cdar(chan, desc->async_tx.phys); | |
f04cd407 | 958 | get_cdar(chan); |
138ef018 | 959 | |
9c3a50b7 | 960 | dma_start(chan); |
f04cd407 | 961 | chan->idle = false; |
173acc7c ZW |
962 | } |
963 | ||
964 | /** | |
965 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 966 | * @chan : Freescale DMA channel |
173acc7c | 967 | */ |
a1c03319 | 968 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 969 | { |
a1c03319 | 970 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
dc8d4091 IS |
971 | unsigned long flags; |
972 | ||
973 | spin_lock_irqsave(&chan->desc_lock, flags); | |
a1c03319 | 974 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 | 975 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
976 | } |
977 | ||
173acc7c | 978 | /** |
07934481 | 979 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 980 | * @chan : Freescale DMA channel |
173acc7c | 981 | */ |
07934481 | 982 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 983 | dma_cookie_t cookie, |
07934481 | 984 | struct dma_tx_state *txstate) |
173acc7c | 985 | { |
a1c03319 | 986 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c | 987 | dma_cookie_t last_complete; |
f04cd407 IS |
988 | dma_cookie_t last_used; |
989 | unsigned long flags; | |
173acc7c | 990 | |
f04cd407 | 991 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 992 | |
a1c03319 | 993 | last_complete = chan->completed_cookie; |
f04cd407 | 994 | last_used = dchan->cookie; |
173acc7c | 995 | |
f04cd407 | 996 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c | 997 | |
f04cd407 | 998 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
173acc7c ZW |
999 | return dma_async_is_complete(cookie, last_complete, last_used); |
1000 | } | |
1001 | ||
d3f620b2 IS |
1002 | /*----------------------------------------------------------------------------*/ |
1003 | /* Interrupt Handling */ | |
1004 | /*----------------------------------------------------------------------------*/ | |
1005 | ||
e7a29151 | 1006 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 1007 | { |
a1c03319 | 1008 | struct fsldma_chan *chan = data; |
a1c03319 | 1009 | u32 stat; |
173acc7c | 1010 | |
9c3a50b7 | 1011 | /* save and clear the status register */ |
a1c03319 | 1012 | stat = get_sr(chan); |
9c3a50b7 | 1013 | set_sr(chan, stat); |
b158471e | 1014 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 1015 | |
f04cd407 | 1016 | /* check that this was really our device */ |
173acc7c ZW |
1017 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
1018 | if (!stat) | |
1019 | return IRQ_NONE; | |
1020 | ||
1021 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 1022 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 1023 | |
9c3a50b7 IS |
1024 | /* |
1025 | * Programming Error | |
f79abb62 ZW |
1026 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1027 | * triger a PE interrupt. | |
1028 | */ | |
1029 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 1030 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 1031 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
1032 | if (get_bcr(chan) != 0) |
1033 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
1034 | } |
1035 | ||
9c3a50b7 IS |
1036 | /* |
1037 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1038 | * and start the next transfer if it exist. |
1039 | */ | |
1040 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 1041 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 1042 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
1043 | } |
1044 | ||
9c3a50b7 IS |
1045 | /* |
1046 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1047 | * we should clear the Channel Start bit for |
1048 | * prepare next transfer. | |
1049 | */ | |
1c62979e | 1050 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 1051 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 1052 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
1053 | } |
1054 | ||
f04cd407 IS |
1055 | /* check that the DMA controller is really idle */ |
1056 | if (!dma_is_idle(chan)) | |
1057 | chan_err(chan, "irq: controller not idle!\n"); | |
1058 | ||
1059 | /* check that we handled all of the bits */ | |
173acc7c | 1060 | if (stat) |
f04cd407 | 1061 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 1062 | |
f04cd407 IS |
1063 | /* |
1064 | * Schedule the tasklet to handle all cleanup of the current | |
1065 | * transaction. It will start a new transaction if there is | |
1066 | * one pending. | |
1067 | */ | |
a1c03319 | 1068 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 1069 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
1070 | return IRQ_HANDLED; |
1071 | } | |
1072 | ||
d3f620b2 IS |
1073 | static void dma_do_tasklet(unsigned long data) |
1074 | { | |
a1c03319 | 1075 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
dc8d4091 IS |
1076 | struct fsl_desc_sw *desc, *_desc; |
1077 | LIST_HEAD(ld_cleanup); | |
f04cd407 IS |
1078 | unsigned long flags; |
1079 | ||
1080 | chan_dbg(chan, "tasklet entry\n"); | |
1081 | ||
f04cd407 | 1082 | spin_lock_irqsave(&chan->desc_lock, flags); |
dc8d4091 IS |
1083 | |
1084 | /* update the cookie if we have some descriptors to cleanup */ | |
1085 | if (!list_empty(&chan->ld_running)) { | |
1086 | dma_cookie_t cookie; | |
1087 | ||
1088 | desc = to_fsl_desc(chan->ld_running.prev); | |
1089 | cookie = desc->async_tx.cookie; | |
1090 | ||
1091 | chan->completed_cookie = cookie; | |
1092 | chan_dbg(chan, "completed_cookie=%d\n", cookie); | |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * move the descriptors to a temporary list so we can drop the lock | |
1097 | * during the entire cleanup operation | |
1098 | */ | |
1099 | list_splice_tail_init(&chan->ld_running, &ld_cleanup); | |
1100 | ||
1101 | /* the hardware is now idle and ready for more */ | |
f04cd407 | 1102 | chan->idle = true; |
f04cd407 | 1103 | |
dc8d4091 IS |
1104 | /* |
1105 | * Start any pending transactions automatically | |
1106 | * | |
1107 | * In the ideal case, we keep the DMA controller busy while we go | |
1108 | * ahead and free the descriptors below. | |
1109 | */ | |
f04cd407 | 1110 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 IS |
1111 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
1112 | ||
1113 | /* Run the callback for each descriptor, in order */ | |
1114 | list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) { | |
1115 | ||
1116 | /* Remove from the list of transactions */ | |
1117 | list_del(&desc->node); | |
1118 | ||
1119 | /* Run all cleanup for this descriptor */ | |
1120 | fsldma_cleanup_descriptor(chan, desc); | |
1121 | } | |
1122 | ||
f04cd407 | 1123 | chan_dbg(chan, "tasklet exit\n"); |
d3f620b2 IS |
1124 | } |
1125 | ||
1126 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1127 | { |
a4f56d4b | 1128 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1129 | struct fsldma_chan *chan; |
1130 | unsigned int handled = 0; | |
1131 | u32 gsr, mask; | |
1132 | int i; | |
173acc7c | 1133 | |
e7a29151 | 1134 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1135 | : in_le32(fdev->regs); |
1136 | mask = 0xff000000; | |
1137 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1138 | |
d3f620b2 IS |
1139 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1140 | chan = fdev->chan[i]; | |
1141 | if (!chan) | |
1142 | continue; | |
1143 | ||
1144 | if (gsr & mask) { | |
1145 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1146 | fsldma_chan_irq(irq, chan); | |
1147 | handled++; | |
1148 | } | |
1149 | ||
1150 | gsr &= ~mask; | |
1151 | mask >>= 8; | |
1152 | } | |
1153 | ||
1154 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1155 | } |
1156 | ||
d3f620b2 | 1157 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1158 | { |
d3f620b2 IS |
1159 | struct fsldma_chan *chan; |
1160 | int i; | |
1161 | ||
1162 | if (fdev->irq != NO_IRQ) { | |
1163 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1164 | free_irq(fdev->irq, fdev); | |
1165 | return; | |
1166 | } | |
1167 | ||
1168 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1169 | chan = fdev->chan[i]; | |
1170 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1171 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1172 | free_irq(chan->irq, chan); |
1173 | } | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1178 | { | |
1179 | struct fsldma_chan *chan; | |
1180 | int ret; | |
1181 | int i; | |
1182 | ||
1183 | /* if we have a per-controller IRQ, use that */ | |
1184 | if (fdev->irq != NO_IRQ) { | |
1185 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1186 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1187 | "fsldma-controller", fdev); | |
1188 | return ret; | |
1189 | } | |
1190 | ||
1191 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1192 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1193 | chan = fdev->chan[i]; | |
1194 | if (!chan) | |
1195 | continue; | |
1196 | ||
1197 | if (chan->irq == NO_IRQ) { | |
b158471e | 1198 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1199 | ret = -ENODEV; |
1200 | goto out_unwind; | |
1201 | } | |
1202 | ||
b158471e | 1203 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1204 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1205 | "fsldma-chan", chan); | |
1206 | if (ret) { | |
b158471e | 1207 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1208 | goto out_unwind; |
1209 | } | |
1210 | } | |
1211 | ||
1212 | return 0; | |
1213 | ||
1214 | out_unwind: | |
1215 | for (/* none */; i >= 0; i--) { | |
1216 | chan = fdev->chan[i]; | |
1217 | if (!chan) | |
1218 | continue; | |
1219 | ||
1220 | if (chan->irq == NO_IRQ) | |
1221 | continue; | |
1222 | ||
1223 | free_irq(chan->irq, chan); | |
1224 | } | |
1225 | ||
1226 | return ret; | |
173acc7c ZW |
1227 | } |
1228 | ||
a4f56d4b IS |
1229 | /*----------------------------------------------------------------------------*/ |
1230 | /* OpenFirmware Subsystem */ | |
1231 | /*----------------------------------------------------------------------------*/ | |
1232 | ||
1233 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1234 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1235 | { |
a1c03319 | 1236 | struct fsldma_chan *chan; |
4ce0e953 | 1237 | struct resource res; |
173acc7c ZW |
1238 | int err; |
1239 | ||
173acc7c | 1240 | /* alloc channel */ |
a1c03319 IS |
1241 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1242 | if (!chan) { | |
e7a29151 IS |
1243 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1244 | err = -ENOMEM; | |
1245 | goto out_return; | |
1246 | } | |
1247 | ||
1248 | /* ioremap registers for use */ | |
a1c03319 IS |
1249 | chan->regs = of_iomap(node, 0); |
1250 | if (!chan->regs) { | |
e7a29151 IS |
1251 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1252 | err = -ENOMEM; | |
a1c03319 | 1253 | goto out_free_chan; |
173acc7c ZW |
1254 | } |
1255 | ||
4ce0e953 | 1256 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1257 | if (err) { |
e7a29151 IS |
1258 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1259 | goto out_iounmap_regs; | |
173acc7c ZW |
1260 | } |
1261 | ||
a1c03319 | 1262 | chan->feature = feature; |
173acc7c | 1263 | if (!fdev->feature) |
a1c03319 | 1264 | fdev->feature = chan->feature; |
173acc7c | 1265 | |
e7a29151 IS |
1266 | /* |
1267 | * If the DMA device's feature is different than the feature | |
1268 | * of its channels, report the bug | |
173acc7c | 1269 | */ |
a1c03319 | 1270 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1271 | |
a1c03319 IS |
1272 | chan->dev = fdev->dev; |
1273 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1274 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1275 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1276 | err = -EINVAL; |
e7a29151 | 1277 | goto out_iounmap_regs; |
173acc7c | 1278 | } |
173acc7c | 1279 | |
a1c03319 IS |
1280 | fdev->chan[chan->id] = chan; |
1281 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1282 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1283 | |
1284 | /* Initialize the channel */ | |
a1c03319 | 1285 | dma_init(chan); |
173acc7c ZW |
1286 | |
1287 | /* Clear cdar registers */ | |
a1c03319 | 1288 | set_cdar(chan, 0); |
173acc7c | 1289 | |
a1c03319 | 1290 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1291 | case FSL_DMA_IP_85XX: |
a1c03319 | 1292 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1293 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1294 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1295 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1296 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1297 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1298 | } |
1299 | ||
a1c03319 | 1300 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1301 | INIT_LIST_HEAD(&chan->ld_pending); |
1302 | INIT_LIST_HEAD(&chan->ld_running); | |
f04cd407 | 1303 | chan->idle = true; |
173acc7c | 1304 | |
a1c03319 | 1305 | chan->common.device = &fdev->common; |
173acc7c | 1306 | |
d3f620b2 | 1307 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1308 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1309 | |
173acc7c | 1310 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1311 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1312 | fdev->common.chancnt++; |
1313 | ||
a1c03319 IS |
1314 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1315 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1316 | |
1317 | return 0; | |
51ee87f2 | 1318 | |
e7a29151 | 1319 | out_iounmap_regs: |
a1c03319 IS |
1320 | iounmap(chan->regs); |
1321 | out_free_chan: | |
1322 | kfree(chan); | |
e7a29151 | 1323 | out_return: |
173acc7c ZW |
1324 | return err; |
1325 | } | |
1326 | ||
a1c03319 | 1327 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1328 | { |
a1c03319 IS |
1329 | irq_dispose_mapping(chan->irq); |
1330 | list_del(&chan->common.device_node); | |
1331 | iounmap(chan->regs); | |
1332 | kfree(chan); | |
173acc7c ZW |
1333 | } |
1334 | ||
00006124 | 1335 | static int __devinit fsldma_of_probe(struct platform_device *op) |
173acc7c | 1336 | { |
a4f56d4b | 1337 | struct fsldma_device *fdev; |
77cd62e8 | 1338 | struct device_node *child; |
e7a29151 | 1339 | int err; |
173acc7c | 1340 | |
a4f56d4b | 1341 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1342 | if (!fdev) { |
e7a29151 IS |
1343 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1344 | err = -ENOMEM; | |
1345 | goto out_return; | |
173acc7c | 1346 | } |
e7a29151 IS |
1347 | |
1348 | fdev->dev = &op->dev; | |
173acc7c ZW |
1349 | INIT_LIST_HEAD(&fdev->common.channels); |
1350 | ||
e7a29151 | 1351 | /* ioremap the registers for use */ |
61c7a080 | 1352 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1353 | if (!fdev->regs) { |
1354 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1355 | err = -ENOMEM; | |
1356 | goto out_free_fdev; | |
173acc7c ZW |
1357 | } |
1358 | ||
d3f620b2 | 1359 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1360 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1361 | |
173acc7c ZW |
1362 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1363 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1364 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1365 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1366 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1367 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1368 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1369 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1370 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1371 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1372 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1373 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1374 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1375 | fdev->common.dev = &op->dev; |
173acc7c | 1376 | |
e2c8e425 LY |
1377 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1378 | ||
e7a29151 | 1379 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1380 | |
e7a29151 IS |
1381 | /* |
1382 | * We cannot use of_platform_bus_probe() because there is no | |
1383 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1384 | * channel object. |
1385 | */ | |
61c7a080 | 1386 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1387 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1388 | fsl_dma_chan_probe(fdev, child, |
1389 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1390 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1391 | } |
1392 | ||
1393 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1394 | fsl_dma_chan_probe(fdev, child, |
1395 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1396 | "fsl,elo-dma-channel"); | |
e7a29151 | 1397 | } |
77cd62e8 | 1398 | } |
173acc7c | 1399 | |
d3f620b2 IS |
1400 | /* |
1401 | * Hookup the IRQ handler(s) | |
1402 | * | |
1403 | * If we have a per-controller interrupt, we prefer that to the | |
1404 | * per-channel interrupts to reduce the number of shared interrupt | |
1405 | * handlers on the same IRQ line | |
1406 | */ | |
1407 | err = fsldma_request_irqs(fdev); | |
1408 | if (err) { | |
1409 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1410 | goto out_free_fdev; | |
1411 | } | |
1412 | ||
173acc7c ZW |
1413 | dma_async_device_register(&fdev->common); |
1414 | return 0; | |
1415 | ||
e7a29151 | 1416 | out_free_fdev: |
d3f620b2 | 1417 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1418 | kfree(fdev); |
e7a29151 | 1419 | out_return: |
173acc7c ZW |
1420 | return err; |
1421 | } | |
1422 | ||
2dc11581 | 1423 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1424 | { |
a4f56d4b | 1425 | struct fsldma_device *fdev; |
77cd62e8 TT |
1426 | unsigned int i; |
1427 | ||
e7a29151 | 1428 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1429 | dma_async_device_unregister(&fdev->common); |
1430 | ||
d3f620b2 IS |
1431 | fsldma_free_irqs(fdev); |
1432 | ||
e7a29151 | 1433 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1434 | if (fdev->chan[i]) |
1435 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1436 | } |
77cd62e8 | 1437 | |
e7a29151 IS |
1438 | iounmap(fdev->regs); |
1439 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1440 | kfree(fdev); |
77cd62e8 TT |
1441 | |
1442 | return 0; | |
1443 | } | |
1444 | ||
4b1cf1fa | 1445 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1446 | { .compatible = "fsl,eloplus-dma", }, |
1447 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1448 | {} |
1449 | }; | |
1450 | ||
8faa7cf8 | 1451 | static struct platform_driver fsldma_of_driver = { |
4018294b GL |
1452 | .driver = { |
1453 | .name = "fsl-elo-dma", | |
1454 | .owner = THIS_MODULE, | |
1455 | .of_match_table = fsldma_of_ids, | |
1456 | }, | |
1457 | .probe = fsldma_of_probe, | |
1458 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1459 | }; |
1460 | ||
a4f56d4b IS |
1461 | /*----------------------------------------------------------------------------*/ |
1462 | /* Module Init / Exit */ | |
1463 | /*----------------------------------------------------------------------------*/ | |
1464 | ||
1465 | static __init int fsldma_init(void) | |
173acc7c | 1466 | { |
77cd62e8 | 1467 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); |
00006124 | 1468 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1469 | } |
1470 | ||
a4f56d4b | 1471 | static void __exit fsldma_exit(void) |
77cd62e8 | 1472 | { |
00006124 | 1473 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1474 | } |
1475 | ||
a4f56d4b IS |
1476 | subsys_initcall(fsldma_init); |
1477 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1478 | |
1479 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1480 | MODULE_LICENSE("GPL"); |