Commit | Line | Data |
---|---|---|
173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
5af50730 RH |
36 | #include <linux/of_address.h> |
37 | #include <linux/of_irq.h> | |
173acc7c | 38 | #include <linux/of_platform.h> |
0a5642be | 39 | #include <linux/fsldma.h> |
d2ebfb33 | 40 | #include "dmaengine.h" |
173acc7c ZW |
41 | #include "fsldma.h" |
42 | ||
b158471e IS |
43 | #define chan_dbg(chan, fmt, arg...) \ |
44 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
45 | #define chan_err(chan, fmt, arg...) \ | |
46 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
c1433041 | 47 | |
b158471e | 48 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
173acc7c | 49 | |
e8bd84df IS |
50 | /* |
51 | * Register Helpers | |
52 | */ | |
173acc7c | 53 | |
a1c03319 | 54 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 55 | { |
a1c03319 | 56 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
57 | } |
58 | ||
a1c03319 | 59 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 60 | { |
a1c03319 | 61 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
62 | } |
63 | ||
ccdce9a0 HZ |
64 | static void set_mr(struct fsldma_chan *chan, u32 val) |
65 | { | |
66 | DMA_OUT(chan, &chan->regs->mr, val, 32); | |
67 | } | |
68 | ||
69 | static u32 get_mr(struct fsldma_chan *chan) | |
70 | { | |
71 | return DMA_IN(chan, &chan->regs->mr, 32); | |
72 | } | |
73 | ||
e8bd84df IS |
74 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
75 | { | |
76 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
77 | } | |
78 | ||
79 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
80 | { | |
81 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
82 | } | |
83 | ||
ccdce9a0 HZ |
84 | static void set_bcr(struct fsldma_chan *chan, u32 val) |
85 | { | |
86 | DMA_OUT(chan, &chan->regs->bcr, val, 32); | |
87 | } | |
88 | ||
e8bd84df IS |
89 | static u32 get_bcr(struct fsldma_chan *chan) |
90 | { | |
91 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
92 | } | |
93 | ||
94 | /* | |
95 | * Descriptor Helpers | |
96 | */ | |
97 | ||
a1c03319 | 98 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
99 | struct fsl_dma_ld_hw *hw, u32 count) |
100 | { | |
a1c03319 | 101 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
102 | } |
103 | ||
a1c03319 | 104 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 105 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
106 | { |
107 | u64 snoop_bits; | |
108 | ||
a1c03319 | 109 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 110 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 111 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
112 | } |
113 | ||
a1c03319 | 114 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 115 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
116 | { |
117 | u64 snoop_bits; | |
118 | ||
a1c03319 | 119 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 120 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 121 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
122 | } |
123 | ||
a1c03319 | 124 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 125 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
126 | { |
127 | u64 snoop_bits; | |
128 | ||
a1c03319 | 129 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 130 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 131 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
132 | } |
133 | ||
31f4306c | 134 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 135 | { |
e8bd84df | 136 | u64 snoop_bits; |
173acc7c | 137 | |
e8bd84df IS |
138 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
139 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 140 | |
e8bd84df IS |
141 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
142 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
143 | | snoop_bits, 64); | |
173acc7c ZW |
144 | } |
145 | ||
e8bd84df IS |
146 | /* |
147 | * DMA Engine Hardware Control Helpers | |
148 | */ | |
149 | ||
150 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 151 | { |
e8bd84df | 152 | /* Reset the channel */ |
ccdce9a0 | 153 | set_mr(chan, 0); |
e8bd84df IS |
154 | |
155 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
156 | case FSL_DMA_IP_85XX: | |
157 | /* Set the channel to below modes: | |
158 | * EIE - Error interrupt enable | |
e8bd84df IS |
159 | * EOLNIE - End of links interrupt enable |
160 | * BWC - Bandwidth sharing among channels | |
161 | */ | |
ccdce9a0 HZ |
162 | set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE |
163 | | FSL_DMA_MR_EOLNIE); | |
e8bd84df IS |
164 | break; |
165 | case FSL_DMA_IP_83XX: | |
166 | /* Set the channel to below modes: | |
167 | * EOTIE - End-of-transfer interrupt enable | |
168 | * PRC_RM - PCI read multiple | |
169 | */ | |
ccdce9a0 | 170 | set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM); |
e8bd84df IS |
171 | break; |
172 | } | |
f79abb62 ZW |
173 | } |
174 | ||
a1c03319 | 175 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 176 | { |
a1c03319 | 177 | u32 sr = get_sr(chan); |
173acc7c ZW |
178 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
179 | } | |
180 | ||
f04cd407 IS |
181 | /* |
182 | * Start the DMA controller | |
183 | * | |
184 | * Preconditions: | |
185 | * - the CDAR register must point to the start descriptor | |
186 | * - the MRn[CS] bit must be cleared | |
187 | */ | |
a1c03319 | 188 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 189 | { |
272ca655 IS |
190 | u32 mode; |
191 | ||
ccdce9a0 | 192 | mode = get_mr(chan); |
272ca655 | 193 | |
f04cd407 | 194 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
ccdce9a0 | 195 | set_bcr(chan, 0); |
f04cd407 IS |
196 | mode |= FSL_DMA_MR_EMP_EN; |
197 | } else { | |
198 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 199 | } |
173acc7c | 200 | |
f04cd407 | 201 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 202 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
203 | } else { |
204 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 205 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 206 | } |
173acc7c | 207 | |
ccdce9a0 | 208 | set_mr(chan, mode); |
173acc7c ZW |
209 | } |
210 | ||
a1c03319 | 211 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 212 | { |
272ca655 | 213 | u32 mode; |
900325a6 DW |
214 | int i; |
215 | ||
a00ae34a | 216 | /* read the mode register */ |
ccdce9a0 | 217 | mode = get_mr(chan); |
272ca655 | 218 | |
a00ae34a IS |
219 | /* |
220 | * The 85xx controller supports channel abort, which will stop | |
221 | * the current transfer. On 83xx, this bit is the transfer error | |
222 | * mask bit, which should not be changed. | |
223 | */ | |
224 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
225 | mode |= FSL_DMA_MR_CA; | |
ccdce9a0 | 226 | set_mr(chan, mode); |
a00ae34a IS |
227 | |
228 | mode &= ~FSL_DMA_MR_CA; | |
229 | } | |
230 | ||
231 | /* stop the DMA controller */ | |
232 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); | |
ccdce9a0 | 233 | set_mr(chan, mode); |
173acc7c | 234 | |
a00ae34a | 235 | /* wait for the DMA controller to become idle */ |
900325a6 | 236 | for (i = 0; i < 100; i++) { |
a1c03319 | 237 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
238 | return; |
239 | ||
173acc7c | 240 | udelay(10); |
900325a6 | 241 | } |
272ca655 | 242 | |
9c3a50b7 | 243 | if (!dma_is_idle(chan)) |
b158471e | 244 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
245 | } |
246 | ||
173acc7c ZW |
247 | /** |
248 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 249 | * @chan : Freescale DMA channel |
173acc7c ZW |
250 | * @size : Address loop size, 0 for disable loop |
251 | * | |
252 | * The set source address hold transfer size. The source | |
253 | * address hold or loop transfer size is when the DMA transfer | |
254 | * data from source address (SA), if the loop size is 4, the DMA will | |
255 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
256 | * SA + 1 ... and so on. | |
257 | */ | |
a1c03319 | 258 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 259 | { |
272ca655 IS |
260 | u32 mode; |
261 | ||
ccdce9a0 | 262 | mode = get_mr(chan); |
272ca655 | 263 | |
173acc7c ZW |
264 | switch (size) { |
265 | case 0: | |
272ca655 | 266 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
267 | break; |
268 | case 1: | |
269 | case 2: | |
270 | case 4: | |
271 | case 8: | |
ccc07729 | 272 | mode &= ~FSL_DMA_MR_SAHTS_MASK; |
272ca655 | 273 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
274 | break; |
275 | } | |
272ca655 | 276 | |
ccdce9a0 | 277 | set_mr(chan, mode); |
173acc7c ZW |
278 | } |
279 | ||
280 | /** | |
738f5f7e | 281 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 282 | * @chan : Freescale DMA channel |
173acc7c ZW |
283 | * @size : Address loop size, 0 for disable loop |
284 | * | |
285 | * The set destination address hold transfer size. The destination | |
286 | * address hold or loop transfer size is when the DMA transfer | |
287 | * data to destination address (TA), if the loop size is 4, the DMA will | |
288 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
289 | * TA + 1 ... and so on. | |
290 | */ | |
a1c03319 | 291 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 292 | { |
272ca655 IS |
293 | u32 mode; |
294 | ||
ccdce9a0 | 295 | mode = get_mr(chan); |
272ca655 | 296 | |
173acc7c ZW |
297 | switch (size) { |
298 | case 0: | |
272ca655 | 299 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
300 | break; |
301 | case 1: | |
302 | case 2: | |
303 | case 4: | |
304 | case 8: | |
ccc07729 | 305 | mode &= ~FSL_DMA_MR_DAHTS_MASK; |
272ca655 | 306 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
307 | break; |
308 | } | |
272ca655 | 309 | |
ccdce9a0 | 310 | set_mr(chan, mode); |
173acc7c ZW |
311 | } |
312 | ||
313 | /** | |
e6c7ecb6 | 314 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 315 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
316 | * @size : Number of bytes to transfer in a single request |
317 | * | |
318 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
319 | * The DMA request count is how many bytes are allowed to transfer before | |
320 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
321 | * operation. | |
173acc7c | 322 | * |
e6c7ecb6 | 323 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 324 | */ |
a1c03319 | 325 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 326 | { |
272ca655 IS |
327 | u32 mode; |
328 | ||
e6c7ecb6 | 329 | BUG_ON(size > 1024); |
272ca655 | 330 | |
ccdce9a0 | 331 | mode = get_mr(chan); |
ccc07729 TB |
332 | mode &= ~FSL_DMA_MR_BWC_MASK; |
333 | mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK; | |
272ca655 | 334 | |
ccdce9a0 | 335 | set_mr(chan, mode); |
e6c7ecb6 | 336 | } |
173acc7c | 337 | |
e6c7ecb6 IS |
338 | /** |
339 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 340 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
341 | * @enable : 0 is disabled, 1 is enabled. |
342 | * | |
343 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
344 | * The DMA Request Count feature should be used in addition to this feature | |
345 | * to set the number of bytes to transfer before pausing the channel. | |
346 | */ | |
a1c03319 | 347 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
348 | { |
349 | if (enable) | |
a1c03319 | 350 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 351 | else |
a1c03319 | 352 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
353 | } |
354 | ||
355 | /** | |
356 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 357 | * @chan : Freescale DMA channel |
173acc7c ZW |
358 | * @enable : 0 is disabled, 1 is enabled. |
359 | * | |
360 | * If enable the external start, the channel can be started by an | |
361 | * external DMA start pin. So the dma_start() does not start the | |
362 | * transfer immediately. The DMA channel will wait for the | |
363 | * control pin asserted. | |
364 | */ | |
a1c03319 | 365 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
366 | { |
367 | if (enable) | |
a1c03319 | 368 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 369 | else |
a1c03319 | 370 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
371 | } |
372 | ||
0a5642be VK |
373 | int fsl_dma_external_start(struct dma_chan *dchan, int enable) |
374 | { | |
375 | struct fsldma_chan *chan; | |
376 | ||
377 | if (!dchan) | |
378 | return -EINVAL; | |
379 | ||
380 | chan = to_fsl_chan(dchan); | |
381 | ||
382 | fsl_chan_toggle_ext_start(chan, enable); | |
383 | return 0; | |
384 | } | |
385 | EXPORT_SYMBOL_GPL(fsl_dma_external_start); | |
386 | ||
31f4306c | 387 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
388 | { |
389 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
390 | ||
391 | if (list_empty(&chan->ld_pending)) | |
392 | goto out_splice; | |
393 | ||
394 | /* | |
395 | * Add the hardware descriptor to the chain of hardware descriptors | |
396 | * that already exists in memory. | |
397 | * | |
398 | * This will un-set the EOL bit of the existing transaction, and the | |
399 | * last link in this transaction will become the EOL descriptor. | |
400 | */ | |
401 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
402 | ||
403 | /* | |
404 | * Add the software descriptor and all children to the list | |
405 | * of pending transactions | |
406 | */ | |
407 | out_splice: | |
408 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
409 | } | |
410 | ||
173acc7c ZW |
411 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
412 | { | |
a1c03319 | 413 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
414 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
415 | struct fsl_desc_sw *child; | |
bbc76560 | 416 | dma_cookie_t cookie = -EINVAL; |
173acc7c | 417 | |
2baff570 | 418 | spin_lock_bh(&chan->desc_lock); |
173acc7c | 419 | |
14c6a333 HZ |
420 | #ifdef CONFIG_PM |
421 | if (unlikely(chan->pm_state != RUNNING)) { | |
422 | chan_dbg(chan, "cannot submit due to suspend\n"); | |
423 | spin_unlock_bh(&chan->desc_lock); | |
424 | return -1; | |
425 | } | |
426 | #endif | |
427 | ||
9c3a50b7 IS |
428 | /* |
429 | * assign cookies to all of the software descriptors | |
430 | * that make up this transaction | |
431 | */ | |
eda34234 | 432 | list_for_each_entry(child, &desc->tx_list, node) { |
884485e1 | 433 | cookie = dma_cookie_assign(&child->async_tx); |
bcfb7465 IS |
434 | } |
435 | ||
9c3a50b7 | 436 | /* put this transaction onto the tail of the pending queue */ |
a1c03319 | 437 | append_ld_queue(chan, desc); |
173acc7c | 438 | |
2baff570 | 439 | spin_unlock_bh(&chan->desc_lock); |
173acc7c ZW |
440 | |
441 | return cookie; | |
442 | } | |
443 | ||
86d19a54 HZ |
444 | /** |
445 | * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool. | |
446 | * @chan : Freescale DMA channel | |
447 | * @desc: descriptor to be freed | |
448 | */ | |
449 | static void fsl_dma_free_descriptor(struct fsldma_chan *chan, | |
450 | struct fsl_desc_sw *desc) | |
451 | { | |
452 | list_del(&desc->node); | |
453 | chan_dbg(chan, "LD %p free\n", desc); | |
454 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
455 | } | |
456 | ||
173acc7c ZW |
457 | /** |
458 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 459 | * @chan : Freescale DMA channel |
173acc7c ZW |
460 | * |
461 | * Return - The descriptor allocated. NULL for failed. | |
462 | */ | |
31f4306c | 463 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 464 | { |
9c3a50b7 | 465 | struct fsl_desc_sw *desc; |
173acc7c | 466 | dma_addr_t pdesc; |
9c3a50b7 | 467 | |
43764557 | 468 | desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc); |
9c3a50b7 | 469 | if (!desc) { |
b158471e | 470 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 471 | return NULL; |
173acc7c ZW |
472 | } |
473 | ||
9c3a50b7 IS |
474 | INIT_LIST_HEAD(&desc->tx_list); |
475 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
476 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
477 | desc->async_tx.phys = pdesc; | |
478 | ||
0ab09c36 | 479 | chan_dbg(chan, "LD %p allocated\n", desc); |
0ab09c36 | 480 | |
9c3a50b7 | 481 | return desc; |
173acc7c ZW |
482 | } |
483 | ||
43452fad HZ |
484 | /** |
485 | * fsldma_clean_completed_descriptor - free all descriptors which | |
486 | * has been completed and acked | |
487 | * @chan: Freescale DMA channel | |
488 | * | |
489 | * This function is used on all completed and acked descriptors. | |
490 | * All descriptors should only be freed in this function. | |
491 | */ | |
492 | static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan) | |
493 | { | |
494 | struct fsl_desc_sw *desc, *_desc; | |
495 | ||
496 | /* Run the callback for each descriptor, in order */ | |
497 | list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) | |
498 | if (async_tx_test_ack(&desc->async_tx)) | |
499 | fsl_dma_free_descriptor(chan, desc); | |
500 | } | |
501 | ||
502 | /** | |
503 | * fsldma_run_tx_complete_actions - cleanup a single link descriptor | |
504 | * @chan: Freescale DMA channel | |
505 | * @desc: descriptor to cleanup and free | |
506 | * @cookie: Freescale DMA transaction identifier | |
507 | * | |
508 | * This function is used on a descriptor which has been executed by the DMA | |
509 | * controller. It will run any callbacks, submit any dependencies. | |
510 | */ | |
511 | static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan, | |
512 | struct fsl_desc_sw *desc, dma_cookie_t cookie) | |
513 | { | |
514 | struct dma_async_tx_descriptor *txd = &desc->async_tx; | |
515 | dma_cookie_t ret = cookie; | |
516 | ||
517 | BUG_ON(txd->cookie < 0); | |
518 | ||
519 | if (txd->cookie > 0) { | |
520 | ret = txd->cookie; | |
521 | ||
9b335978 | 522 | dma_descriptor_unmap(txd); |
43452fad | 523 | /* Run the link descriptor callback function */ |
af1a5a51 | 524 | dmaengine_desc_get_callback_invoke(txd, NULL); |
43452fad HZ |
525 | } |
526 | ||
527 | /* Run any dependencies */ | |
528 | dma_run_dependencies(txd); | |
529 | ||
530 | return ret; | |
531 | } | |
532 | ||
533 | /** | |
534 | * fsldma_clean_running_descriptor - move the completed descriptor from | |
535 | * ld_running to ld_completed | |
536 | * @chan: Freescale DMA channel | |
537 | * @desc: the descriptor which is completed | |
538 | * | |
539 | * Free the descriptor directly if acked by async_tx api, or move it to | |
540 | * queue ld_completed. | |
541 | */ | |
542 | static void fsldma_clean_running_descriptor(struct fsldma_chan *chan, | |
543 | struct fsl_desc_sw *desc) | |
544 | { | |
545 | /* Remove from the list of transactions */ | |
546 | list_del(&desc->node); | |
547 | ||
548 | /* | |
549 | * the client is allowed to attach dependent operations | |
550 | * until 'ack' is set | |
551 | */ | |
552 | if (!async_tx_test_ack(&desc->async_tx)) { | |
553 | /* | |
554 | * Move this descriptor to the list of descriptors which is | |
555 | * completed, but still awaiting the 'ack' bit to be set. | |
556 | */ | |
557 | list_add_tail(&desc->node, &chan->ld_completed); | |
558 | return; | |
559 | } | |
560 | ||
561 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
562 | } | |
563 | ||
2a5ecb79 HZ |
564 | /** |
565 | * fsl_chan_xfer_ld_queue - transfer any pending transactions | |
566 | * @chan : Freescale DMA channel | |
567 | * | |
568 | * HARDWARE STATE: idle | |
569 | * LOCKING: must hold chan->desc_lock | |
570 | */ | |
571 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) | |
572 | { | |
573 | struct fsl_desc_sw *desc; | |
574 | ||
575 | /* | |
576 | * If the list of pending descriptors is empty, then we | |
577 | * don't need to do any work at all | |
578 | */ | |
579 | if (list_empty(&chan->ld_pending)) { | |
580 | chan_dbg(chan, "no pending LDs\n"); | |
581 | return; | |
582 | } | |
583 | ||
584 | /* | |
585 | * The DMA controller is not idle, which means that the interrupt | |
586 | * handler will start any queued transactions when it runs after | |
587 | * this transaction finishes | |
588 | */ | |
589 | if (!chan->idle) { | |
590 | chan_dbg(chan, "DMA controller still busy\n"); | |
591 | return; | |
592 | } | |
593 | ||
594 | /* | |
595 | * If there are some link descriptors which have not been | |
596 | * transferred, we need to start the controller | |
597 | */ | |
598 | ||
599 | /* | |
600 | * Move all elements from the queue of pending transactions | |
601 | * onto the list of running transactions | |
602 | */ | |
603 | chan_dbg(chan, "idle, starting controller\n"); | |
604 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
605 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
606 | ||
607 | /* | |
608 | * The 85xx DMA controller doesn't clear the channel start bit | |
609 | * automatically at the end of a transfer. Therefore we must clear | |
610 | * it in software before starting the transfer. | |
611 | */ | |
612 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
613 | u32 mode; | |
614 | ||
615 | mode = get_mr(chan); | |
616 | mode &= ~FSL_DMA_MR_CS; | |
617 | set_mr(chan, mode); | |
618 | } | |
619 | ||
620 | /* | |
621 | * Program the descriptor's address into the DMA controller, | |
622 | * then start the DMA transaction | |
623 | */ | |
624 | set_cdar(chan, desc->async_tx.phys); | |
625 | get_cdar(chan); | |
626 | ||
627 | dma_start(chan); | |
628 | chan->idle = false; | |
629 | } | |
630 | ||
631 | /** | |
43452fad HZ |
632 | * fsldma_cleanup_descriptors - cleanup link descriptors which are completed |
633 | * and move them to ld_completed to free until flag 'ack' is set | |
2a5ecb79 | 634 | * @chan: Freescale DMA channel |
2a5ecb79 | 635 | * |
43452fad HZ |
636 | * This function is used on descriptors which have been executed by the DMA |
637 | * controller. It will run any callbacks, submit any dependencies, then | |
638 | * free these descriptors if flag 'ack' is set. | |
2a5ecb79 | 639 | */ |
43452fad | 640 | static void fsldma_cleanup_descriptors(struct fsldma_chan *chan) |
2a5ecb79 | 641 | { |
43452fad HZ |
642 | struct fsl_desc_sw *desc, *_desc; |
643 | dma_cookie_t cookie = 0; | |
644 | dma_addr_t curr_phys = get_cdar(chan); | |
645 | int seen_current = 0; | |
2a5ecb79 | 646 | |
43452fad HZ |
647 | fsldma_clean_completed_descriptor(chan); |
648 | ||
649 | /* Run the callback for each descriptor, in order */ | |
650 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { | |
651 | /* | |
652 | * do not advance past the current descriptor loaded into the | |
653 | * hardware channel, subsequent descriptors are either in | |
654 | * process or have not been submitted | |
655 | */ | |
656 | if (seen_current) | |
657 | break; | |
658 | ||
659 | /* | |
660 | * stop the search if we reach the current descriptor and the | |
661 | * channel is busy | |
662 | */ | |
663 | if (desc->async_tx.phys == curr_phys) { | |
664 | seen_current = 1; | |
665 | if (!dma_is_idle(chan)) | |
666 | break; | |
667 | } | |
668 | ||
669 | cookie = fsldma_run_tx_complete_actions(chan, desc, cookie); | |
670 | ||
671 | fsldma_clean_running_descriptor(chan, desc); | |
2a5ecb79 HZ |
672 | } |
673 | ||
43452fad HZ |
674 | /* |
675 | * Start any pending transactions automatically | |
676 | * | |
677 | * In the ideal case, we keep the DMA controller busy while we go | |
678 | * ahead and free the descriptors below. | |
679 | */ | |
680 | fsl_chan_xfer_ld_queue(chan); | |
2a5ecb79 | 681 | |
43452fad HZ |
682 | if (cookie > 0) |
683 | chan->common.completed_cookie = cookie; | |
2a5ecb79 HZ |
684 | } |
685 | ||
173acc7c ZW |
686 | /** |
687 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 688 | * @chan : Freescale DMA channel |
173acc7c ZW |
689 | * |
690 | * This function will create a dma pool for descriptor allocation. | |
691 | * | |
692 | * Return - The number of descriptors allocated. | |
693 | */ | |
a1c03319 | 694 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 695 | { |
a1c03319 | 696 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
697 | |
698 | /* Has this channel already been allocated? */ | |
a1c03319 | 699 | if (chan->desc_pool) |
77cd62e8 | 700 | return 1; |
173acc7c | 701 | |
9c3a50b7 IS |
702 | /* |
703 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
704 | * for meeting FSL DMA specification requirement. |
705 | */ | |
b158471e | 706 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
707 | sizeof(struct fsl_desc_sw), |
708 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 709 | if (!chan->desc_pool) { |
b158471e | 710 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 711 | return -ENOMEM; |
173acc7c ZW |
712 | } |
713 | ||
9c3a50b7 | 714 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
715 | return 1; |
716 | } | |
717 | ||
9c3a50b7 IS |
718 | /** |
719 | * fsldma_free_desc_list - Free all descriptors in a queue | |
720 | * @chan: Freescae DMA channel | |
721 | * @list: the list to free | |
722 | * | |
723 | * LOCKING: must hold chan->desc_lock | |
724 | */ | |
725 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
726 | struct list_head *list) | |
727 | { | |
728 | struct fsl_desc_sw *desc, *_desc; | |
729 | ||
86d19a54 HZ |
730 | list_for_each_entry_safe(desc, _desc, list, node) |
731 | fsl_dma_free_descriptor(chan, desc); | |
9c3a50b7 IS |
732 | } |
733 | ||
734 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
735 | struct list_head *list) | |
736 | { | |
737 | struct fsl_desc_sw *desc, *_desc; | |
738 | ||
86d19a54 HZ |
739 | list_for_each_entry_safe_reverse(desc, _desc, list, node) |
740 | fsl_dma_free_descriptor(chan, desc); | |
9c3a50b7 IS |
741 | } |
742 | ||
173acc7c ZW |
743 | /** |
744 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 745 | * @chan : Freescale DMA channel |
173acc7c | 746 | */ |
a1c03319 | 747 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 748 | { |
a1c03319 | 749 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c | 750 | |
b158471e | 751 | chan_dbg(chan, "free all channel resources\n"); |
2baff570 | 752 | spin_lock_bh(&chan->desc_lock); |
43452fad | 753 | fsldma_cleanup_descriptors(chan); |
9c3a50b7 IS |
754 | fsldma_free_desc_list(chan, &chan->ld_pending); |
755 | fsldma_free_desc_list(chan, &chan->ld_running); | |
43452fad | 756 | fsldma_free_desc_list(chan, &chan->ld_completed); |
2baff570 | 757 | spin_unlock_bh(&chan->desc_lock); |
77cd62e8 | 758 | |
9c3a50b7 | 759 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 760 | chan->desc_pool = NULL; |
173acc7c ZW |
761 | } |
762 | ||
31f4306c IS |
763 | static struct dma_async_tx_descriptor * |
764 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
765 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
766 | size_t len, unsigned long flags) |
767 | { | |
a1c03319 | 768 | struct fsldma_chan *chan; |
173acc7c ZW |
769 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
770 | size_t copy; | |
173acc7c | 771 | |
a1c03319 | 772 | if (!dchan) |
173acc7c ZW |
773 | return NULL; |
774 | ||
775 | if (!len) | |
776 | return NULL; | |
777 | ||
a1c03319 | 778 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
779 | |
780 | do { | |
781 | ||
782 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 783 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 784 | if (!new) { |
b158471e | 785 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 786 | goto fail; |
173acc7c | 787 | } |
173acc7c | 788 | |
56822843 | 789 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 790 | |
a1c03319 IS |
791 | set_desc_cnt(chan, &new->hw, copy); |
792 | set_desc_src(chan, &new->hw, dma_src); | |
793 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
794 | |
795 | if (!first) | |
796 | first = new; | |
797 | else | |
a1c03319 | 798 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
799 | |
800 | new->async_tx.cookie = 0; | |
636bdeaa | 801 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
802 | |
803 | prev = new; | |
804 | len -= copy; | |
805 | dma_src += copy; | |
738f5f7e | 806 | dma_dst += copy; |
173acc7c ZW |
807 | |
808 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 809 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
810 | } while (len); |
811 | ||
636bdeaa | 812 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
813 | new->async_tx.cookie = -EBUSY; |
814 | ||
31f4306c | 815 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 816 | set_ld_eol(chan, new); |
173acc7c | 817 | |
2e077f8e IS |
818 | return &first->async_tx; |
819 | ||
820 | fail: | |
821 | if (!first) | |
822 | return NULL; | |
823 | ||
9c3a50b7 | 824 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 825 | return NULL; |
173acc7c ZW |
826 | } |
827 | ||
b7f7552b | 828 | static int fsl_dma_device_terminate_all(struct dma_chan *dchan) |
bbea0b6e | 829 | { |
a1c03319 | 830 | struct fsldma_chan *chan; |
c3635c78 | 831 | |
a1c03319 | 832 | if (!dchan) |
c3635c78 | 833 | return -EINVAL; |
bbea0b6e | 834 | |
a1c03319 | 835 | chan = to_fsl_chan(dchan); |
bbea0b6e | 836 | |
b7f7552b | 837 | spin_lock_bh(&chan->desc_lock); |
bbea0b6e | 838 | |
b7f7552b MR |
839 | /* Halt the DMA engine */ |
840 | dma_halt(chan); | |
bbea0b6e | 841 | |
b7f7552b MR |
842 | /* Remove and free all of the descriptors in the LD queue */ |
843 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
844 | fsldma_free_desc_list(chan, &chan->ld_running); | |
845 | fsldma_free_desc_list(chan, &chan->ld_completed); | |
846 | chan->idle = true; | |
968f19ae | 847 | |
b7f7552b MR |
848 | spin_unlock_bh(&chan->desc_lock); |
849 | return 0; | |
850 | } | |
968f19ae | 851 | |
b7f7552b MR |
852 | static int fsl_dma_device_config(struct dma_chan *dchan, |
853 | struct dma_slave_config *config) | |
854 | { | |
855 | struct fsldma_chan *chan; | |
856 | int size; | |
968f19ae | 857 | |
b7f7552b MR |
858 | if (!dchan) |
859 | return -EINVAL; | |
968f19ae | 860 | |
b7f7552b | 861 | chan = to_fsl_chan(dchan); |
968f19ae | 862 | |
b7f7552b MR |
863 | /* make sure the channel supports setting burst size */ |
864 | if (!chan->set_request_count) | |
968f19ae | 865 | return -ENXIO; |
c3635c78 | 866 | |
b7f7552b MR |
867 | /* we set the controller burst size depending on direction */ |
868 | if (config->direction == DMA_MEM_TO_DEV) | |
869 | size = config->dst_addr_width * config->dst_maxburst; | |
870 | else | |
871 | size = config->src_addr_width * config->src_maxburst; | |
872 | ||
873 | chan->set_request_count(chan, size); | |
c3635c78 | 874 | return 0; |
bbea0b6e IS |
875 | } |
876 | ||
b7f7552b | 877 | |
173acc7c ZW |
878 | /** |
879 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 880 | * @chan : Freescale DMA channel |
173acc7c | 881 | */ |
a1c03319 | 882 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 883 | { |
a1c03319 | 884 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
dc8d4091 | 885 | |
2baff570 | 886 | spin_lock_bh(&chan->desc_lock); |
a1c03319 | 887 | fsl_chan_xfer_ld_queue(chan); |
2baff570 | 888 | spin_unlock_bh(&chan->desc_lock); |
173acc7c ZW |
889 | } |
890 | ||
173acc7c | 891 | /** |
07934481 | 892 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 893 | * @chan : Freescale DMA channel |
173acc7c | 894 | */ |
07934481 | 895 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 896 | dma_cookie_t cookie, |
07934481 | 897 | struct dma_tx_state *txstate) |
173acc7c | 898 | { |
43452fad HZ |
899 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
900 | enum dma_status ret; | |
901 | ||
902 | ret = dma_cookie_status(dchan, cookie, txstate); | |
903 | if (ret == DMA_COMPLETE) | |
904 | return ret; | |
905 | ||
906 | spin_lock_bh(&chan->desc_lock); | |
907 | fsldma_cleanup_descriptors(chan); | |
908 | spin_unlock_bh(&chan->desc_lock); | |
909 | ||
9b0b0bdc | 910 | return dma_cookie_status(dchan, cookie, txstate); |
173acc7c ZW |
911 | } |
912 | ||
d3f620b2 IS |
913 | /*----------------------------------------------------------------------------*/ |
914 | /* Interrupt Handling */ | |
915 | /*----------------------------------------------------------------------------*/ | |
916 | ||
e7a29151 | 917 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 918 | { |
a1c03319 | 919 | struct fsldma_chan *chan = data; |
a1c03319 | 920 | u32 stat; |
173acc7c | 921 | |
9c3a50b7 | 922 | /* save and clear the status register */ |
a1c03319 | 923 | stat = get_sr(chan); |
9c3a50b7 | 924 | set_sr(chan, stat); |
b158471e | 925 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 926 | |
f04cd407 | 927 | /* check that this was really our device */ |
173acc7c ZW |
928 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
929 | if (!stat) | |
930 | return IRQ_NONE; | |
931 | ||
932 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 933 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 934 | |
9c3a50b7 IS |
935 | /* |
936 | * Programming Error | |
f79abb62 | 937 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
d73111c6 | 938 | * trigger a PE interrupt. |
f79abb62 ZW |
939 | */ |
940 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 941 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 942 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
943 | if (get_bcr(chan) != 0) |
944 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
945 | } |
946 | ||
9c3a50b7 IS |
947 | /* |
948 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
949 | * and start the next transfer if it exist. |
950 | */ | |
951 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 952 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 953 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
954 | } |
955 | ||
9c3a50b7 IS |
956 | /* |
957 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
958 | * we should clear the Channel Start bit for |
959 | * prepare next transfer. | |
960 | */ | |
1c62979e | 961 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 962 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 963 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
964 | } |
965 | ||
f04cd407 IS |
966 | /* check that the DMA controller is really idle */ |
967 | if (!dma_is_idle(chan)) | |
968 | chan_err(chan, "irq: controller not idle!\n"); | |
969 | ||
970 | /* check that we handled all of the bits */ | |
173acc7c | 971 | if (stat) |
f04cd407 | 972 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 973 | |
f04cd407 IS |
974 | /* |
975 | * Schedule the tasklet to handle all cleanup of the current | |
976 | * transaction. It will start a new transaction if there is | |
977 | * one pending. | |
978 | */ | |
a1c03319 | 979 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 980 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
981 | return IRQ_HANDLED; |
982 | } | |
983 | ||
d3f620b2 IS |
984 | static void dma_do_tasklet(unsigned long data) |
985 | { | |
a1c03319 | 986 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
f04cd407 IS |
987 | |
988 | chan_dbg(chan, "tasklet entry\n"); | |
989 | ||
2baff570 | 990 | spin_lock_bh(&chan->desc_lock); |
dc8d4091 | 991 | |
dc8d4091 | 992 | /* the hardware is now idle and ready for more */ |
f04cd407 | 993 | chan->idle = true; |
f04cd407 | 994 | |
43452fad HZ |
995 | /* Run all cleanup for descriptors which have been completed */ |
996 | fsldma_cleanup_descriptors(chan); | |
dc8d4091 | 997 | |
43452fad | 998 | spin_unlock_bh(&chan->desc_lock); |
dc8d4091 | 999 | |
f04cd407 | 1000 | chan_dbg(chan, "tasklet exit\n"); |
d3f620b2 IS |
1001 | } |
1002 | ||
1003 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1004 | { |
a4f56d4b | 1005 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1006 | struct fsldma_chan *chan; |
1007 | unsigned int handled = 0; | |
1008 | u32 gsr, mask; | |
1009 | int i; | |
173acc7c | 1010 | |
e7a29151 | 1011 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1012 | : in_le32(fdev->regs); |
1013 | mask = 0xff000000; | |
1014 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1015 | |
d3f620b2 IS |
1016 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1017 | chan = fdev->chan[i]; | |
1018 | if (!chan) | |
1019 | continue; | |
1020 | ||
1021 | if (gsr & mask) { | |
1022 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1023 | fsldma_chan_irq(irq, chan); | |
1024 | handled++; | |
1025 | } | |
1026 | ||
1027 | gsr &= ~mask; | |
1028 | mask >>= 8; | |
1029 | } | |
1030 | ||
1031 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1032 | } |
1033 | ||
d3f620b2 | 1034 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1035 | { |
d3f620b2 IS |
1036 | struct fsldma_chan *chan; |
1037 | int i; | |
1038 | ||
aa570be6 | 1039 | if (fdev->irq) { |
d3f620b2 IS |
1040 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); |
1041 | free_irq(fdev->irq, fdev); | |
1042 | return; | |
1043 | } | |
1044 | ||
1045 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1046 | chan = fdev->chan[i]; | |
aa570be6 | 1047 | if (chan && chan->irq) { |
b158471e | 1048 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1049 | free_irq(chan->irq, chan); |
1050 | } | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1055 | { | |
1056 | struct fsldma_chan *chan; | |
1057 | int ret; | |
1058 | int i; | |
1059 | ||
1060 | /* if we have a per-controller IRQ, use that */ | |
aa570be6 | 1061 | if (fdev->irq) { |
d3f620b2 IS |
1062 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); |
1063 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1064 | "fsldma-controller", fdev); | |
1065 | return ret; | |
1066 | } | |
1067 | ||
1068 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1069 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1070 | chan = fdev->chan[i]; | |
1071 | if (!chan) | |
1072 | continue; | |
1073 | ||
aa570be6 | 1074 | if (!chan->irq) { |
b158471e | 1075 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1076 | ret = -ENODEV; |
1077 | goto out_unwind; | |
1078 | } | |
1079 | ||
b158471e | 1080 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1081 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1082 | "fsldma-chan", chan); | |
1083 | if (ret) { | |
b158471e | 1084 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1085 | goto out_unwind; |
1086 | } | |
1087 | } | |
1088 | ||
1089 | return 0; | |
1090 | ||
1091 | out_unwind: | |
1092 | for (/* none */; i >= 0; i--) { | |
1093 | chan = fdev->chan[i]; | |
1094 | if (!chan) | |
1095 | continue; | |
1096 | ||
aa570be6 | 1097 | if (!chan->irq) |
d3f620b2 IS |
1098 | continue; |
1099 | ||
1100 | free_irq(chan->irq, chan); | |
1101 | } | |
1102 | ||
1103 | return ret; | |
173acc7c ZW |
1104 | } |
1105 | ||
a4f56d4b IS |
1106 | /*----------------------------------------------------------------------------*/ |
1107 | /* OpenFirmware Subsystem */ | |
1108 | /*----------------------------------------------------------------------------*/ | |
1109 | ||
463a1f8b | 1110 | static int fsl_dma_chan_probe(struct fsldma_device *fdev, |
77cd62e8 | 1111 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1112 | { |
a1c03319 | 1113 | struct fsldma_chan *chan; |
4ce0e953 | 1114 | struct resource res; |
173acc7c ZW |
1115 | int err; |
1116 | ||
173acc7c | 1117 | /* alloc channel */ |
a1c03319 IS |
1118 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1119 | if (!chan) { | |
e7a29151 IS |
1120 | err = -ENOMEM; |
1121 | goto out_return; | |
1122 | } | |
1123 | ||
1124 | /* ioremap registers for use */ | |
a1c03319 IS |
1125 | chan->regs = of_iomap(node, 0); |
1126 | if (!chan->regs) { | |
e7a29151 IS |
1127 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1128 | err = -ENOMEM; | |
a1c03319 | 1129 | goto out_free_chan; |
173acc7c ZW |
1130 | } |
1131 | ||
4ce0e953 | 1132 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1133 | if (err) { |
e7a29151 IS |
1134 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1135 | goto out_iounmap_regs; | |
173acc7c ZW |
1136 | } |
1137 | ||
a1c03319 | 1138 | chan->feature = feature; |
173acc7c | 1139 | if (!fdev->feature) |
a1c03319 | 1140 | fdev->feature = chan->feature; |
173acc7c | 1141 | |
e7a29151 IS |
1142 | /* |
1143 | * If the DMA device's feature is different than the feature | |
1144 | * of its channels, report the bug | |
173acc7c | 1145 | */ |
a1c03319 | 1146 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1147 | |
a1c03319 | 1148 | chan->dev = fdev->dev; |
8de7a7d9 HZ |
1149 | chan->id = (res.start & 0xfff) < 0x300 ? |
1150 | ((res.start - 0x100) & 0xfff) >> 7 : | |
1151 | ((res.start - 0x200) & 0xfff) >> 7; | |
a1c03319 | 1152 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { |
e7a29151 | 1153 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1154 | err = -EINVAL; |
e7a29151 | 1155 | goto out_iounmap_regs; |
173acc7c | 1156 | } |
173acc7c | 1157 | |
a1c03319 IS |
1158 | fdev->chan[chan->id] = chan; |
1159 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1160 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1161 | |
1162 | /* Initialize the channel */ | |
a1c03319 | 1163 | dma_init(chan); |
173acc7c ZW |
1164 | |
1165 | /* Clear cdar registers */ | |
a1c03319 | 1166 | set_cdar(chan, 0); |
173acc7c | 1167 | |
a1c03319 | 1168 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1169 | case FSL_DMA_IP_85XX: |
a1c03319 | 1170 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1171 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1172 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1173 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1174 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1175 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1176 | } |
1177 | ||
a1c03319 | 1178 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1179 | INIT_LIST_HEAD(&chan->ld_pending); |
1180 | INIT_LIST_HEAD(&chan->ld_running); | |
43452fad | 1181 | INIT_LIST_HEAD(&chan->ld_completed); |
f04cd407 | 1182 | chan->idle = true; |
14c6a333 HZ |
1183 | #ifdef CONFIG_PM |
1184 | chan->pm_state = RUNNING; | |
1185 | #endif | |
173acc7c | 1186 | |
a1c03319 | 1187 | chan->common.device = &fdev->common; |
8ac69546 | 1188 | dma_cookie_init(&chan->common); |
173acc7c | 1189 | |
d3f620b2 | 1190 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1191 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1192 | |
173acc7c | 1193 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1194 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c | 1195 | |
a1c03319 | 1196 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
aa570be6 | 1197 | chan->irq ? chan->irq : fdev->irq); |
173acc7c ZW |
1198 | |
1199 | return 0; | |
51ee87f2 | 1200 | |
e7a29151 | 1201 | out_iounmap_regs: |
a1c03319 IS |
1202 | iounmap(chan->regs); |
1203 | out_free_chan: | |
1204 | kfree(chan); | |
e7a29151 | 1205 | out_return: |
173acc7c ZW |
1206 | return err; |
1207 | } | |
1208 | ||
a1c03319 | 1209 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1210 | { |
a1c03319 IS |
1211 | irq_dispose_mapping(chan->irq); |
1212 | list_del(&chan->common.device_node); | |
1213 | iounmap(chan->regs); | |
1214 | kfree(chan); | |
173acc7c ZW |
1215 | } |
1216 | ||
463a1f8b | 1217 | static int fsldma_of_probe(struct platform_device *op) |
173acc7c | 1218 | { |
a4f56d4b | 1219 | struct fsldma_device *fdev; |
77cd62e8 | 1220 | struct device_node *child; |
e7a29151 | 1221 | int err; |
173acc7c | 1222 | |
a4f56d4b | 1223 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1224 | if (!fdev) { |
e7a29151 IS |
1225 | err = -ENOMEM; |
1226 | goto out_return; | |
173acc7c | 1227 | } |
e7a29151 IS |
1228 | |
1229 | fdev->dev = &op->dev; | |
173acc7c ZW |
1230 | INIT_LIST_HEAD(&fdev->common.channels); |
1231 | ||
e7a29151 | 1232 | /* ioremap the registers for use */ |
61c7a080 | 1233 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1234 | if (!fdev->regs) { |
1235 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1236 | err = -ENOMEM; | |
585a1db1 | 1237 | goto out_free; |
173acc7c ZW |
1238 | } |
1239 | ||
d3f620b2 | 1240 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1241 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1242 | |
173acc7c | 1243 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
bbea0b6e | 1244 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1245 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1246 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
1247 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; | |
07934481 | 1248 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1249 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
b7f7552b MR |
1250 | fdev->common.device_config = fsl_dma_device_config; |
1251 | fdev->common.device_terminate_all = fsl_dma_device_terminate_all; | |
e7a29151 | 1252 | fdev->common.dev = &op->dev; |
173acc7c | 1253 | |
75dc1775 KH |
1254 | fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS; |
1255 | fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS; | |
1256 | fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1257 | fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; | |
1258 | ||
e2c8e425 LY |
1259 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1260 | ||
dd3daca1 | 1261 | platform_set_drvdata(op, fdev); |
77cd62e8 | 1262 | |
e7a29151 IS |
1263 | /* |
1264 | * We cannot use of_platform_bus_probe() because there is no | |
1265 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1266 | * channel object. |
1267 | */ | |
61c7a080 | 1268 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1269 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1270 | fsl_dma_chan_probe(fdev, child, |
1271 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1272 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1273 | } |
1274 | ||
1275 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1276 | fsl_dma_chan_probe(fdev, child, |
1277 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1278 | "fsl,elo-dma-channel"); | |
e7a29151 | 1279 | } |
77cd62e8 | 1280 | } |
173acc7c | 1281 | |
d3f620b2 IS |
1282 | /* |
1283 | * Hookup the IRQ handler(s) | |
1284 | * | |
1285 | * If we have a per-controller interrupt, we prefer that to the | |
1286 | * per-channel interrupts to reduce the number of shared interrupt | |
1287 | * handlers on the same IRQ line | |
1288 | */ | |
1289 | err = fsldma_request_irqs(fdev); | |
1290 | if (err) { | |
1291 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1292 | goto out_free_fdev; | |
1293 | } | |
1294 | ||
173acc7c ZW |
1295 | dma_async_device_register(&fdev->common); |
1296 | return 0; | |
1297 | ||
e7a29151 | 1298 | out_free_fdev: |
d3f620b2 | 1299 | irq_dispose_mapping(fdev->irq); |
585a1db1 AY |
1300 | iounmap(fdev->regs); |
1301 | out_free: | |
173acc7c | 1302 | kfree(fdev); |
e7a29151 | 1303 | out_return: |
173acc7c ZW |
1304 | return err; |
1305 | } | |
1306 | ||
2dc11581 | 1307 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1308 | { |
a4f56d4b | 1309 | struct fsldma_device *fdev; |
77cd62e8 TT |
1310 | unsigned int i; |
1311 | ||
dd3daca1 | 1312 | fdev = platform_get_drvdata(op); |
77cd62e8 TT |
1313 | dma_async_device_unregister(&fdev->common); |
1314 | ||
d3f620b2 IS |
1315 | fsldma_free_irqs(fdev); |
1316 | ||
e7a29151 | 1317 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1318 | if (fdev->chan[i]) |
1319 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1320 | } |
77cd62e8 | 1321 | |
e7a29151 | 1322 | iounmap(fdev->regs); |
77cd62e8 | 1323 | kfree(fdev); |
77cd62e8 TT |
1324 | |
1325 | return 0; | |
1326 | } | |
1327 | ||
14c6a333 HZ |
1328 | #ifdef CONFIG_PM |
1329 | static int fsldma_suspend_late(struct device *dev) | |
1330 | { | |
1331 | struct platform_device *pdev = to_platform_device(dev); | |
1332 | struct fsldma_device *fdev = platform_get_drvdata(pdev); | |
1333 | struct fsldma_chan *chan; | |
1334 | int i; | |
1335 | ||
1336 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1337 | chan = fdev->chan[i]; | |
1338 | if (!chan) | |
1339 | continue; | |
1340 | ||
1341 | spin_lock_bh(&chan->desc_lock); | |
1342 | if (unlikely(!chan->idle)) | |
1343 | goto out; | |
1344 | chan->regs_save.mr = get_mr(chan); | |
1345 | chan->pm_state = SUSPENDED; | |
1346 | spin_unlock_bh(&chan->desc_lock); | |
1347 | } | |
1348 | return 0; | |
1349 | ||
1350 | out: | |
1351 | for (; i >= 0; i--) { | |
1352 | chan = fdev->chan[i]; | |
1353 | if (!chan) | |
1354 | continue; | |
1355 | chan->pm_state = RUNNING; | |
1356 | spin_unlock_bh(&chan->desc_lock); | |
1357 | } | |
1358 | return -EBUSY; | |
1359 | } | |
1360 | ||
1361 | static int fsldma_resume_early(struct device *dev) | |
1362 | { | |
1363 | struct platform_device *pdev = to_platform_device(dev); | |
1364 | struct fsldma_device *fdev = platform_get_drvdata(pdev); | |
1365 | struct fsldma_chan *chan; | |
1366 | u32 mode; | |
1367 | int i; | |
1368 | ||
1369 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1370 | chan = fdev->chan[i]; | |
1371 | if (!chan) | |
1372 | continue; | |
1373 | ||
1374 | spin_lock_bh(&chan->desc_lock); | |
1375 | mode = chan->regs_save.mr | |
1376 | & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA; | |
1377 | set_mr(chan, mode); | |
1378 | chan->pm_state = RUNNING; | |
1379 | spin_unlock_bh(&chan->desc_lock); | |
1380 | } | |
1381 | ||
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | static const struct dev_pm_ops fsldma_pm_ops = { | |
1386 | .suspend_late = fsldma_suspend_late, | |
1387 | .resume_early = fsldma_resume_early, | |
1388 | }; | |
1389 | #endif | |
1390 | ||
4b1cf1fa | 1391 | static const struct of_device_id fsldma_of_ids[] = { |
8de7a7d9 | 1392 | { .compatible = "fsl,elo3-dma", }, |
049c9d45 KG |
1393 | { .compatible = "fsl,eloplus-dma", }, |
1394 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1395 | {} |
1396 | }; | |
7522c240 | 1397 | MODULE_DEVICE_TABLE(of, fsldma_of_ids); |
173acc7c | 1398 | |
8faa7cf8 | 1399 | static struct platform_driver fsldma_of_driver = { |
4018294b GL |
1400 | .driver = { |
1401 | .name = "fsl-elo-dma", | |
4018294b | 1402 | .of_match_table = fsldma_of_ids, |
14c6a333 HZ |
1403 | #ifdef CONFIG_PM |
1404 | .pm = &fsldma_pm_ops, | |
1405 | #endif | |
4018294b GL |
1406 | }, |
1407 | .probe = fsldma_of_probe, | |
1408 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1409 | }; |
1410 | ||
a4f56d4b IS |
1411 | /*----------------------------------------------------------------------------*/ |
1412 | /* Module Init / Exit */ | |
1413 | /*----------------------------------------------------------------------------*/ | |
1414 | ||
1415 | static __init int fsldma_init(void) | |
173acc7c | 1416 | { |
8de7a7d9 | 1417 | pr_info("Freescale Elo series DMA driver\n"); |
00006124 | 1418 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1419 | } |
1420 | ||
a4f56d4b | 1421 | static void __exit fsldma_exit(void) |
77cd62e8 | 1422 | { |
00006124 | 1423 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1424 | } |
1425 | ||
a4f56d4b IS |
1426 | subsys_initcall(fsldma_init); |
1427 | module_exit(fsldma_exit); | |
77cd62e8 | 1428 | |
8de7a7d9 | 1429 | MODULE_DESCRIPTION("Freescale Elo series DMA driver"); |
77cd62e8 | 1430 | MODULE_LICENSE("GPL"); |