[linux-2.6-block.git] / drivers / dma / fsl-edma-common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
 */
#ifndef _FSL_EDMA_COMMON_H_
#define _FSL_EDMA_COMMON_H_

#include <linux/dma-direction.h>
#include <linux/platform_device.h>
#include "virt-dma.h"

#define EDMA_CR_EDBG		BIT(1)
#define EDMA_CR_ERCA		BIT(2)
#define EDMA_CR_ERGA		BIT(3)
#define EDMA_CR_HOE		BIT(4)
#define EDMA_CR_HALT		BIT(5)
#define EDMA_CR_CLM		BIT(6)
#define EDMA_CR_EMLM		BIT(7)
#define EDMA_CR_ECX		BIT(16)
#define EDMA_CR_CX		BIT(17)

#define EDMA_SEEI_SEEI(x)	((x) & GENMASK(4, 0))
#define EDMA_CEEI_CEEI(x)	((x) & GENMASK(4, 0))
#define EDMA_CINT_CINT(x)	((x) & GENMASK(4, 0))
#define EDMA_CERR_CERR(x)	((x) & GENMASK(4, 0))

#define EDMA_TCD_ATTR_DSIZE(x)		(((x) & GENMASK(2, 0)))
#define EDMA_TCD_ATTR_DMOD(x)		(((x) & GENMASK(4, 0)) << 3)
#define EDMA_TCD_ATTR_SSIZE(x)		(((x) & GENMASK(2, 0)) << 8)
#define EDMA_TCD_ATTR_SMOD(x)		(((x) & GENMASK(4, 0)) << 11)

#define EDMA_TCD_ITER_MASK		GENMASK(14, 0)
#define EDMA_TCD_CITER_CITER(x)		((x) & EDMA_TCD_ITER_MASK)
#define EDMA_TCD_BITER_BITER(x)		((x) & EDMA_TCD_ITER_MASK)

#define EDMA_TCD_CSR_START		BIT(0)
#define EDMA_TCD_CSR_INT_MAJOR		BIT(1)
#define EDMA_TCD_CSR_INT_HALF		BIT(2)
#define EDMA_TCD_CSR_D_REQ		BIT(3)
#define EDMA_TCD_CSR_E_SG		BIT(4)
#define EDMA_TCD_CSR_E_LINK		BIT(5)
#define EDMA_TCD_CSR_ACTIVE		BIT(6)
#define EDMA_TCD_CSR_DONE		BIT(7)

#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
#define EDMA_V3_TCD_NBYTES_MLOFF(x)        (x << 10)
#define EDMA_V3_TCD_NBYTES_DMLOE           (1 << 30)
#define EDMA_V3_TCD_NBYTES_SMLOE           (1 << 31)

#define EDMAMUX_CHCFG_DIS		0x0
#define EDMAMUX_CHCFG_ENBL		0x80
#define EDMAMUX_CHCFG_SOURCE(n)		((n) & 0x3F)

#define DMAMUX_NR	2

#define EDMA_TCD                0x1000

#define FSL_EDMA_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
				 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))

#define EDMA_V3_CH_SBR_RD          BIT(22)
#define EDMA_V3_CH_SBR_WR          BIT(21)
#define EDMA_V3_CH_CSR_ERQ         BIT(0)
#define EDMA_V3_CH_CSR_EARQ        BIT(1)
#define EDMA_V3_CH_CSR_EEI         BIT(2)
#define EDMA_V3_CH_CSR_DONE        BIT(30)
#define EDMA_V3_CH_CSR_ACTIVE      BIT(31)

enum fsl_edma_pm_state {
	RUNNING = 0,
	SUSPENDED,
};

struct fsl_edma_hw_tcd {
	__le32	saddr;
	__le16	soff;
	__le16	attr;
	__le32	nbytes;
	__le32	slast;
	__le32	daddr;
	__le16	doff;
	__le16	citer;
	__le32	dlast_sga;
	__le16	csr;
	__le16	biter;
};

struct fsl_edma3_ch_reg {
	__le32	ch_csr;
	__le32	ch_es;
	__le32	ch_int;
	__le32	ch_sbr;
	__le32	ch_pri;
	__le32	ch_mux;
	__le32  ch_mattr; /* edma4, reserved for edma3 */
	__le32  ch_reserved;
	struct fsl_edma_hw_tcd tcd;
} __packed;

/*
 * These are iomem pointers, for both v32 and v64.
 */
struct edma_regs {
	void __iomem *cr;
	void __iomem *es;
	void __iomem *erqh;
	void __iomem *erql;	/* aka erq on v32 */
	void __iomem *eeih;
	void __iomem *eeil;	/* aka eei on v32 */
	void __iomem *seei;
	void __iomem *ceei;
	void __iomem *serq;
	void __iomem *cerq;
	void __iomem *cint;
	void __iomem *cerr;
	void __iomem *ssrt;
	void __iomem *cdne;
	void __iomem *inth;
	void __iomem *intl;
	void __iomem *errh;
	void __iomem *errl;
};

struct fsl_edma_sw_tcd {
	dma_addr_t			ptcd;
	struct fsl_edma_hw_tcd		*vtcd;
};

struct fsl_edma_chan {
	struct virt_dma_chan		vchan;
	enum dma_status			status;
	enum fsl_edma_pm_state		pm_state;
	bool				idle;
	u32				slave_id;
	struct fsl_edma_engine		*edma;
	struct fsl_edma_desc		*edesc;
	struct dma_slave_config		cfg;
	u32				attr;
	bool                            is_sw;
	struct dma_pool			*tcd_pool;
	dma_addr_t			dma_dev_addr;
	u32				dma_dev_size;
	enum dma_data_direction		dma_dir;
	char				chan_name[32];
	struct fsl_edma_hw_tcd __iomem *tcd;
	u32				real_count;
	struct work_struct		issue_worker;
	struct platform_device		*pdev;
	struct device			*pd_dev;
	u32				srcid;
	struct clk			*clk;
	int                             priority;
	int				hw_chanid;
	int				txirq;
	bool				is_rxchan;
	bool				is_remote;
	bool				is_multi_fifo;
};

struct fsl_edma_desc {
	struct virt_dma_desc		vdesc;
	struct fsl_edma_chan		*echan;
	bool				iscyclic;
	enum dma_transfer_direction	dirn;
	unsigned int			n_tcds;
	struct fsl_edma_sw_tcd		tcd[];
};

#define FSL_EDMA_DRV_HAS_DMACLK		BIT(0)
#define FSL_EDMA_DRV_MUX_SWAP		BIT(1)
#define FSL_EDMA_DRV_CONFIG32		BIT(2)
#define FSL_EDMA_DRV_WRAP_IO		BIT(3)
#define FSL_EDMA_DRV_EDMA64		BIT(4)
#define FSL_EDMA_DRV_HAS_PD		BIT(5)
#define FSL_EDMA_DRV_HAS_CHCLK		BIT(6)
#define FSL_EDMA_DRV_HAS_CHMUX		BIT(7)
/* imx8 QM audio edma remote local swapped */
#define FSL_EDMA_DRV_QUIRK_SWAPPED	BIT(8)
/* control and status register is in tcd address space, edma3 reg layout */
#define FSL_EDMA_DRV_SPLIT_REG		BIT(9)
#define FSL_EDMA_DRV_BUS_8BYTE		BIT(10)
#define FSL_EDMA_DRV_DEV_TO_DEV		BIT(11)
#define FSL_EDMA_DRV_ALIGN_64BYTE	BIT(12)
/* Need clean CHn_CSR DONE before enable TCD's ESG */
#define FSL_EDMA_DRV_CLEAR_DONE_E_SG	BIT(13)
/* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
#define FSL_EDMA_DRV_CLEAR_DONE_E_LINK	BIT(14)

#define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
				 FSL_EDMA_DRV_BUS_8BYTE |	\
				 FSL_EDMA_DRV_DEV_TO_DEV |	\
				 FSL_EDMA_DRV_ALIGN_64BYTE |	\
				 FSL_EDMA_DRV_CLEAR_DONE_E_SG |	\
				 FSL_EDMA_DRV_CLEAR_DONE_E_LINK)

#define FSL_EDMA_DRV_EDMA4	(FSL_EDMA_DRV_SPLIT_REG |	\
				 FSL_EDMA_DRV_BUS_8BYTE |	\
				 FSL_EDMA_DRV_DEV_TO_DEV |	\
				 FSL_EDMA_DRV_ALIGN_64BYTE |	\
				 FSL_EDMA_DRV_CLEAR_DONE_E_LINK)

struct fsl_edma_drvdata {
	u32			dmamuxs; /* only used before v3 */
	u32			chreg_off;
	u32			chreg_space_sz;
	u32			flags;
	int			(*setup_irq)(struct platform_device *pdev,
					     struct fsl_edma_engine *fsl_edma);
};

struct fsl_edma_engine {
	struct dma_device	dma_dev;
	void __iomem		*membase;
	void __iomem		*muxbase[DMAMUX_NR];
	struct clk		*muxclk[DMAMUX_NR];
	struct clk		*dmaclk;
	struct clk		*chclk;
	struct mutex		fsl_edma_mutex;
	const struct fsl_edma_drvdata *drvdata;
	u32			n_chans;
	int			txirq;
	int			errirq;
	bool			big_endian;
	struct edma_regs	regs;
	u64			chan_masked;
	struct fsl_edma_chan	chans[] __counted_by(n_chans);
};

#define edma_read_tcdreg(chan, __name)				\
(sizeof(chan->tcd->__name) == sizeof(u32) ?			\
	edma_readl(chan->edma, &chan->tcd->__name) :		\
	edma_readw(chan->edma, &chan->tcd->__name))

#define edma_write_tcdreg(chan, val, __name)			\
(sizeof(chan->tcd->__name) == sizeof(u32) ?			\
	edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) :	\
	edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))

#define edma_readl_chreg(chan, __name)				\
	edma_readl(chan->edma,					\
		   (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))

#define edma_writel_chreg(chan, val,  __name)			\
	edma_writel(chan->edma, val,				\
		   (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))

/*
 * R/W functions for big- or little-endian registers:
 * The eDMA controller's endian is independent of the CPU core's endian.
 * For the big-endian IP module, the offset for 8-bit or 16-bit registers
 * should also be swapped opposite to that in little-endian IP.
 */
static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
{
	if (edma->big_endian)
		return ioread32be(addr);
	else
		return ioread32(addr);
}

static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
{
	if (edma->big_endian)
		return ioread16be(addr);
	else
		return ioread16(addr);
}

static inline void edma_writeb(struct fsl_edma_engine *edma,
			       u8 val, void __iomem *addr)
{
	/* swap the reg offset for these in big-endian mode */
	if (edma->big_endian)
		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
	else
		iowrite8(val, addr);
}

static inline void edma_writew(struct fsl_edma_engine *edma,
			       u16 val, void __iomem *addr)
{
	/* swap the reg offset for these in big-endian mode */
	if (edma->big_endian)
		iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
	else
		iowrite16(val, addr);
}

static inline void edma_writel(struct fsl_edma_engine *edma,
			       u32 val, void __iomem *addr)
{
	if (edma->big_endian)
		iowrite32be(val, addr);
	else
		iowrite32(val, addr);
}

static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct fsl_edma_chan, vchan.chan);
}

static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
{
	return fsl_chan->edma->drvdata->flags;
}

static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
{
	return container_of(vd, struct fsl_edma_desc, vdesc);
}

static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
{
	fsl_chan->status = DMA_ERROR;
	fsl_chan->idle = true;
}

void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
			unsigned int slot, bool enable);
void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
int fsl_edma_terminate_all(struct dma_chan *chan);
int fsl_edma_pause(struct dma_chan *chan);
int fsl_edma_resume(struct dma_chan *chan);
int fsl_edma_slave_config(struct dma_chan *chan,
				 struct dma_slave_config *cfg);
enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
		dma_cookie_t cookie, struct dma_tx_state *txstate);
struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction,
		unsigned long flags);
struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags, void *context);
struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
		struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
		size_t len, unsigned long flags);
void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
void fsl_edma_issue_pending(struct dma_chan *chan);
int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
void fsl_edma_free_chan_resources(struct dma_chan *chan);
void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
void fsl_edma_setup_regs(struct fsl_edma_engine *edma);

#endif /* _FSL_EDMA_COMMON_H_ */
Commit	Line	Data
9d831528 AD	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright 2013-2014 Freescale Semiconductor, Inc.
	4	* Copyright 2018 Angelo Dureghello <angelo@sysam.it>
	5	*/
	6	#ifndef _FSL_EDMA_COMMON_H_
	7	#define _FSL_EDMA_COMMON_H_
	8
0fa89f97	9	#include <linux/dma-direction.h>
af802728	10	#include <linux/platform_device.h>
9d831528 AD	11	#include "virt-dma.h"
9d831528 AD	12
9d831528 AD	13	#define EDMA_CR_EDBG BIT(1)
	14	#define EDMA_CR_ERCA BIT(2)
	15	#define EDMA_CR_ERGA BIT(3)
	16	#define EDMA_CR_HOE BIT(4)
	17	#define EDMA_CR_HALT BIT(5)
	18	#define EDMA_CR_CLM BIT(6)
	19	#define EDMA_CR_EMLM BIT(7)
	20	#define EDMA_CR_ECX BIT(16)
	21	#define EDMA_CR_CX BIT(17)
	22
4d6d3a90 AD	23	#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
	24	#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
	25	#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
	26	#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
9d831528	27
4d6d3a90 AD	28	#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
	29	#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
	30	#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
	31	#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
9d831528	32
a79f949a FL	33	#define EDMA_TCD_ITER_MASK GENMASK(14, 0)
	34	#define EDMA_TCD_CITER_CITER(x) ((x) & EDMA_TCD_ITER_MASK)
	35	#define EDMA_TCD_BITER_BITER(x) ((x) & EDMA_TCD_ITER_MASK)
9d831528 AD	36
	37	#define EDMA_TCD_CSR_START BIT(0)
	38	#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
	39	#define EDMA_TCD_CSR_INT_HALF BIT(2)
	40	#define EDMA_TCD_CSR_D_REQ BIT(3)
	41	#define EDMA_TCD_CSR_E_SG BIT(4)
	42	#define EDMA_TCD_CSR_E_LINK BIT(5)
	43	#define EDMA_TCD_CSR_ACTIVE BIT(6)
	44	#define EDMA_TCD_CSR_DONE BIT(7)
	45
72f5801a FL	46	#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
	47	#define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10)
	48	#define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
	49	#define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
	50
9d831528 AD	51	#define EDMAMUX_CHCFG_DIS 0x0
	52	#define EDMAMUX_CHCFG_ENBL 0x80
	53	#define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
	54
	55	#define DMAMUX_NR 2
	56
7536f8b3 FL	57	#define EDMA_TCD 0x1000
7536f8b3 FL	58
9d831528 AD	59	#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
	60	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
	61	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) \| \
	62	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
72f5801a FL	63
	64	#define EDMA_V3_CH_SBR_RD BIT(22)
	65	#define EDMA_V3_CH_SBR_WR BIT(21)
	66	#define EDMA_V3_CH_CSR_ERQ BIT(0)
	67	#define EDMA_V3_CH_CSR_EARQ BIT(1)
	68	#define EDMA_V3_CH_CSR_EEI BIT(2)
	69	#define EDMA_V3_CH_CSR_DONE BIT(30)
	70	#define EDMA_V3_CH_CSR_ACTIVE BIT(31)
	71
9d831528 AD	72	enum fsl_edma_pm_state {
	73	RUNNING = 0,
	74	SUSPENDED,
	75	};
	76
	77	struct fsl_edma_hw_tcd {
	78	__le32 saddr;
	79	__le16 soff;
	80	__le16 attr;
	81	__le32 nbytes;
	82	__le32 slast;
	83	__le32 daddr;
	84	__le16 doff;
	85	__le16 citer;
	86	__le32 dlast_sga;
	87	__le16 csr;
	88	__le16 biter;
	89	};
	90
72f5801a FL	91	struct fsl_edma3_ch_reg {
	92	__le32 ch_csr;
	93	__le32 ch_es;
	94	__le32 ch_int;
	95	__le32 ch_sbr;
	96	__le32 ch_pri;
	97	__le32 ch_mux;
	98	__le32 ch_mattr; /* edma4, reserved for edma3 */
	99	__le32 ch_reserved;
	100	struct fsl_edma_hw_tcd tcd;
	101	} __packed;
	102
377eaf3b AD	103	/*
	104	* These are iomem pointers, for both v32 and v64.
	105	*/
	106	struct edma_regs {
	107	void __iomem *cr;
	108	void __iomem *es;
	109	void __iomem *erqh;
	110	void __iomem erql; / aka erq on v32 */
	111	void __iomem *eeih;
	112	void __iomem eeil; / aka eei on v32 */
	113	void __iomem *seei;
	114	void __iomem *ceei;
	115	void __iomem *serq;
	116	void __iomem *cerq;
	117	void __iomem *cint;
	118	void __iomem *cerr;
	119	void __iomem *ssrt;
	120	void __iomem *cdne;
	121	void __iomem *inth;
	122	void __iomem *intl;
	123	void __iomem *errh;
	124	void __iomem *errl;
377eaf3b AD	125	};
377eaf3b AD	126
9d831528 AD	127	struct fsl_edma_sw_tcd {
	128	dma_addr_t ptcd;
	129	struct fsl_edma_hw_tcd *vtcd;
	130	};
	131
9d831528 AD	132	struct fsl_edma_chan {
	133	struct virt_dma_chan vchan;
	134	enum dma_status status;
	135	enum fsl_edma_pm_state pm_state;
	136	bool idle;
	137	u32 slave_id;
	138	struct fsl_edma_engine *edma;
	139	struct fsl_edma_desc *edesc;
0e819e35 VK	140	struct dma_slave_config cfg;
0e819e35 VK	141	u32 attr;
e0674853	142	bool is_sw;
9d831528	143	struct dma_pool *tcd_pool;
0fa89f97 LT	144	dma_addr_t dma_dev_addr;
	145	u32 dma_dev_size;
	146	enum dma_data_direction dma_dir;
9b05554c	147	char chan_name[32];
7536f8b3	148	struct fsl_edma_hw_tcd __iomem *tcd;
72f5801a FL	149	u32 real_count;
	150	struct work_struct issue_worker;
	151	struct platform_device *pdev;
	152	struct device *pd_dev;
	153	u32 srcid;
	154	struct clk *clk;
	155	int priority;
	156	int hw_chanid;
	157	int txirq;
	158	bool is_rxchan;
	159	bool is_remote;
	160	bool is_multi_fifo;
9d831528 AD	161	};
	162
	163	struct fsl_edma_desc {
	164	struct virt_dma_desc vdesc;
	165	struct fsl_edma_chan *echan;
	166	bool iscyclic;
0e819e35	167	enum dma_transfer_direction dirn;
9d831528 AD	168	unsigned int n_tcds;
	169	struct fsl_edma_sw_tcd tcd[];
	170	};
	171
9e006b24 FL	172	#define FSL_EDMA_DRV_HAS_DMACLK BIT(0)
9e006b24 FL	173	#define FSL_EDMA_DRV_MUX_SWAP BIT(1)
c26e6114 FL	174	#define FSL_EDMA_DRV_CONFIG32 BIT(2)
	175	#define FSL_EDMA_DRV_WRAP_IO BIT(3)
	176	#define FSL_EDMA_DRV_EDMA64 BIT(4)
72f5801a FL	177	#define FSL_EDMA_DRV_HAS_PD BIT(5)
	178	#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
	179	#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
	180	/* imx8 QM audio edma remote local swapped */
	181	#define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
	182	/* control and status register is in tcd address space, edma3 reg layout */
	183	#define FSL_EDMA_DRV_SPLIT_REG BIT(9)
	184	#define FSL_EDMA_DRV_BUS_8BYTE BIT(10)
	185	#define FSL_EDMA_DRV_DEV_TO_DEV BIT(11)
	186	#define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12)
3c67c523 FL	187	/* Need clean CHn_CSR DONE before enable TCD's ESG */
	188	#define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13)
	189	/* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
	190	#define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14)
72f5801a FL	191
	192	#define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG \| \
	193	FSL_EDMA_DRV_BUS_8BYTE \| \
	194	FSL_EDMA_DRV_DEV_TO_DEV \| \
3c67c523 FL	195	FSL_EDMA_DRV_ALIGN_64BYTE \| \
	196	FSL_EDMA_DRV_CLEAR_DONE_E_SG \| \
	197	FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
	198
	199	#define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG \| \
	200	FSL_EDMA_DRV_BUS_8BYTE \| \
	201	FSL_EDMA_DRV_DEV_TO_DEV \| \
	202	FSL_EDMA_DRV_ALIGN_64BYTE \| \
	203	FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
72f5801a	204
af802728	205	struct fsl_edma_drvdata {
72f5801a FL	206	u32 dmamuxs; /* only used before v3 */
	207	u32 chreg_off;
	208	u32 chreg_space_sz;
9e006b24	209	u32 flags;
af802728 RG	210	int (setup_irq)(struct platform_device pdev,
	211	struct fsl_edma_engine *fsl_edma);
	212	};
	213
9d831528 AD	214	struct fsl_edma_engine {
	215	struct dma_device dma_dev;
	216	void __iomem *membase;
	217	void __iomem *muxbase[DMAMUX_NR];
	218	struct clk *muxclk[DMAMUX_NR];
232a7f18	219	struct clk *dmaclk;
72f5801a	220	struct clk *chclk;
9d831528	221	struct mutex fsl_edma_mutex;
af802728	222	const struct fsl_edma_drvdata *drvdata;
9d831528 AD	223	u32 n_chans;
	224	int txirq;
	225	int errirq;
	226	bool big_endian;
377eaf3b	227	struct edma_regs regs;
72f5801a	228	u64 chan_masked;
c223bafd	229	struct fsl_edma_chan chans[] __counted_by(n_chans);
9d831528 AD	230	};
9d831528 AD	231
7536f8b3 FL	232	#define edma_read_tcdreg(chan, __name) \
	233	(sizeof(chan->tcd->__name) == sizeof(u32) ? \
	234	edma_readl(chan->edma, &chan->tcd->__name) : \
	235	edma_readw(chan->edma, &chan->tcd->__name))
	236
	237	#define edma_write_tcdreg(chan, val, __name) \
	238	(sizeof(chan->tcd->__name) == sizeof(u32) ? \
	239	edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \
	240	edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
	241
72f5801a FL	242	#define edma_readl_chreg(chan, __name) \
	243	edma_readl(chan->edma, \
	244	(void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
	245
	246	#define edma_writel_chreg(chan, val, __name) \
	247	edma_writel(chan->edma, val, \
	248	(void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
	249
9d831528 AD	250	/*
	251	* R/W functions for big- or little-endian registers:
	252	* The eDMA controller's endian is independent of the CPU core's endian.
	253	* For the big-endian IP module, the offset for 8-bit or 16-bit registers
	254	* should also be swapped opposite to that in little-endian IP.
	255	*/
	256	static inline u32 edma_readl(struct fsl_edma_engine edma, void __iomem addr)
	257	{
	258	if (edma->big_endian)
	259	return ioread32be(addr);
	260	else
	261	return ioread32(addr);
	262	}
	263
7536f8b3 FL	264	static inline u16 edma_readw(struct fsl_edma_engine edma, void __iomem addr)
	265	{
	266	if (edma->big_endian)
	267	return ioread16be(addr);
	268	else
	269	return ioread16(addr);
	270	}
	271
9d831528 AD	272	static inline void edma_writeb(struct fsl_edma_engine *edma,
	273	u8 val, void __iomem *addr)
	274	{
	275	/* swap the reg offset for these in big-endian mode */
	276	if (edma->big_endian)
	277	iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
	278	else
	279	iowrite8(val, addr);
	280	}
	281
	282	static inline void edma_writew(struct fsl_edma_engine *edma,
	283	u16 val, void __iomem *addr)
	284	{
	285	/* swap the reg offset for these in big-endian mode */
	286	if (edma->big_endian)
	287	iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
	288	else
	289	iowrite16(val, addr);
	290	}
	291
	292	static inline void edma_writel(struct fsl_edma_engine *edma,
	293	u32 val, void __iomem *addr)
	294	{
	295	if (edma->big_endian)
	296	iowrite32be(val, addr);
	297	else
	298	iowrite32(val, addr);
	299	}
	300
	301	static inline struct fsl_edma_chan to_fsl_edma_chan(struct dma_chan chan)
	302	{
	303	return container_of(chan, struct fsl_edma_chan, vchan.chan);
	304	}
	305
72f5801a FL	306	static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
	307	{
	308	return fsl_chan->edma->drvdata->flags;
	309	}
	310
9d831528 AD	311	static inline struct fsl_edma_desc to_fsl_edma_desc(struct virt_dma_desc vd)
	312	{
	313	return container_of(vd, struct fsl_edma_desc, vdesc);
	314	}
	315
79434f9b FL	316	static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
	317	{
	318	fsl_chan->status = DMA_ERROR;
	319	fsl_chan->idle = true;
	320	}
	321
	322	void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
9d831528 AD	323	void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
	324	void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
	325	unsigned int slot, bool enable);
	326	void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
	327	int fsl_edma_terminate_all(struct dma_chan *chan);
	328	int fsl_edma_pause(struct dma_chan *chan);
	329	int fsl_edma_resume(struct dma_chan *chan);
	330	int fsl_edma_slave_config(struct dma_chan *chan,
	331	struct dma_slave_config *cfg);
	332	enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
	333	dma_cookie_t cookie, struct dma_tx_state *txstate);
	334	struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
	335	struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
	336	size_t period_len, enum dma_transfer_direction direction,
	337	unsigned long flags);
	338	struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
	339	struct dma_chan chan, struct scatterlist sgl,
	340	unsigned int sg_len, enum dma_transfer_direction direction,
	341	unsigned long flags, void *context);
e0674853 JZ	342	struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
	343	struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
	344	size_t len, unsigned long flags);
9d831528 AD	345	void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
	346	void fsl_edma_issue_pending(struct dma_chan *chan);
	347	int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
	348	void fsl_edma_free_chan_resources(struct dma_chan *chan);
	349	void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
377eaf3b	350	void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
9d831528 AD	351
9d831528 AD	352	#endif /* _FSL_EDMA_COMMON_H_ */