[linux-block.git] / drivers / dma / fsl-edma-common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
 */
#ifndef _FSL_EDMA_COMMON_H_
#define _FSL_EDMA_COMMON_H_

#include <linux/dma-direction.h>
#include <linux/platform_device.h>
#include "virt-dma.h"

#define EDMA_CR_EDBG		BIT(1)
#define EDMA_CR_ERCA		BIT(2)
#define EDMA_CR_ERGA		BIT(3)
#define EDMA_CR_HOE		BIT(4)
#define EDMA_CR_HALT		BIT(5)
#define EDMA_CR_CLM		BIT(6)
#define EDMA_CR_EMLM		BIT(7)
#define EDMA_CR_ECX		BIT(16)
#define EDMA_CR_CX		BIT(17)

#define EDMA_SEEI_SEEI(x)	((x) & GENMASK(4, 0))
#define EDMA_CEEI_CEEI(x)	((x) & GENMASK(4, 0))
#define EDMA_CINT_CINT(x)	((x) & GENMASK(4, 0))
#define EDMA_CERR_CERR(x)	((x) & GENMASK(4, 0))

#define EDMA_TCD_ATTR_DSIZE(x)		(((x) & GENMASK(2, 0)))
#define EDMA_TCD_ATTR_DMOD(x)		(((x) & GENMASK(4, 0)) << 3)
#define EDMA_TCD_ATTR_SSIZE(x)		(((x) & GENMASK(2, 0)) << 8)
#define EDMA_TCD_ATTR_SMOD(x)		(((x) & GENMASK(4, 0)) << 11)
#define EDMA_TCD_ATTR_DSIZE_8BIT	0
#define EDMA_TCD_ATTR_DSIZE_16BIT	BIT(0)
#define EDMA_TCD_ATTR_DSIZE_32BIT	BIT(1)
#define EDMA_TCD_ATTR_DSIZE_64BIT	(BIT(0) | BIT(1))
#define EDMA_TCD_ATTR_DSIZE_32BYTE	(BIT(3) | BIT(0))
#define EDMA_TCD_ATTR_SSIZE_8BIT	0
#define EDMA_TCD_ATTR_SSIZE_16BIT	(EDMA_TCD_ATTR_DSIZE_16BIT << 8)
#define EDMA_TCD_ATTR_SSIZE_32BIT	(EDMA_TCD_ATTR_DSIZE_32BIT << 8)
#define EDMA_TCD_ATTR_SSIZE_64BIT	(EDMA_TCD_ATTR_DSIZE_64BIT << 8)
#define EDMA_TCD_ATTR_SSIZE_32BYTE	(EDMA_TCD_ATTR_DSIZE_32BYTE << 8)

#define EDMA_TCD_CITER_CITER(x)		((x) & GENMASK(14, 0))
#define EDMA_TCD_BITER_BITER(x)		((x) & GENMASK(14, 0))

#define EDMA_TCD_CSR_START		BIT(0)
#define EDMA_TCD_CSR_INT_MAJOR		BIT(1)
#define EDMA_TCD_CSR_INT_HALF		BIT(2)
#define EDMA_TCD_CSR_D_REQ		BIT(3)
#define EDMA_TCD_CSR_E_SG		BIT(4)
#define EDMA_TCD_CSR_E_LINK		BIT(5)
#define EDMA_TCD_CSR_ACTIVE		BIT(6)
#define EDMA_TCD_CSR_DONE		BIT(7)

#define EDMAMUX_CHCFG_DIS		0x0
#define EDMAMUX_CHCFG_ENBL		0x80
#define EDMAMUX_CHCFG_SOURCE(n)		((n) & 0x3F)

#define DMAMUX_NR	2

#define FSL_EDMA_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
				 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
enum fsl_edma_pm_state {
	RUNNING = 0,
	SUSPENDED,
};

struct fsl_edma_hw_tcd {
	__le32	saddr;
	__le16	soff;
	__le16	attr;
	__le32	nbytes;
	__le32	slast;
	__le32	daddr;
	__le16	doff;
	__le16	citer;
	__le32	dlast_sga;
	__le16	csr;
	__le16	biter;
};

/*
 * These are iomem pointers, for both v32 and v64.
 */
struct edma_regs {
	void __iomem *cr;
	void __iomem *es;
	void __iomem *erqh;
	void __iomem *erql;	/* aka erq on v32 */
	void __iomem *eeih;
	void __iomem *eeil;	/* aka eei on v32 */
	void __iomem *seei;
	void __iomem *ceei;
	void __iomem *serq;
	void __iomem *cerq;
	void __iomem *cint;
	void __iomem *cerr;
	void __iomem *ssrt;
	void __iomem *cdne;
	void __iomem *inth;
	void __iomem *intl;
	void __iomem *errh;
	void __iomem *errl;
	struct fsl_edma_hw_tcd __iomem *tcd;
};

struct fsl_edma_sw_tcd {
	dma_addr_t			ptcd;
	struct fsl_edma_hw_tcd		*vtcd;
};

struct fsl_edma_chan {
	struct virt_dma_chan		vchan;
	enum dma_status			status;
	enum fsl_edma_pm_state		pm_state;
	bool				idle;
	u32				slave_id;
	struct fsl_edma_engine		*edma;
	struct fsl_edma_desc		*edesc;
	struct dma_slave_config		cfg;
	u32				attr;
	struct dma_pool			*tcd_pool;
	dma_addr_t			dma_dev_addr;
	u32				dma_dev_size;
	enum dma_data_direction		dma_dir;
};

struct fsl_edma_desc {
	struct virt_dma_desc		vdesc;
	struct fsl_edma_chan		*echan;
	bool				iscyclic;
	enum dma_transfer_direction	dirn;
	unsigned int			n_tcds;
	struct fsl_edma_sw_tcd		tcd[];
};

enum edma_version {
	v1, /* 32ch, Vybrid, mpc57x, etc */
	v2, /* 64ch Coldfire */
};

struct fsl_edma_drvdata {
	enum edma_version	version;
	u32			dmamuxs;
	int			(*setup_irq)(struct platform_device *pdev,
					     struct fsl_edma_engine *fsl_edma);
};

struct fsl_edma_engine {
	struct dma_device	dma_dev;
	void __iomem		*membase;
	void __iomem		*muxbase[DMAMUX_NR];
	struct clk		*muxclk[DMAMUX_NR];
	struct mutex		fsl_edma_mutex;
	const struct fsl_edma_drvdata *drvdata;
	u32			n_chans;
	int			txirq;
	int			errirq;
	bool			big_endian;
	struct edma_regs	regs;
	struct fsl_edma_chan	chans[];
};

/*
 * R/W functions for big- or little-endian registers:
 * The eDMA controller's endian is independent of the CPU core's endian.
 * For the big-endian IP module, the offset for 8-bit or 16-bit registers
 * should also be swapped opposite to that in little-endian IP.
 */
static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
{
	if (edma->big_endian)
		return ioread32be(addr);
	else
		return ioread32(addr);
}

static inline void edma_writeb(struct fsl_edma_engine *edma,
			       u8 val, void __iomem *addr)
{
	/* swap the reg offset for these in big-endian mode */
	if (edma->big_endian)
		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
	else
		iowrite8(val, addr);
}

static inline void edma_writew(struct fsl_edma_engine *edma,
			       u16 val, void __iomem *addr)
{
	/* swap the reg offset for these in big-endian mode */
	if (edma->big_endian)
		iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
	else
		iowrite16(val, addr);
}

static inline void edma_writel(struct fsl_edma_engine *edma,
			       u32 val, void __iomem *addr)
{
	if (edma->big_endian)
		iowrite32be(val, addr);
	else
		iowrite32(val, addr);
}

static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct fsl_edma_chan, vchan.chan);
}

static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
{
	return container_of(vd, struct fsl_edma_desc, vdesc);
}

void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
			unsigned int slot, bool enable);
void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
int fsl_edma_terminate_all(struct dma_chan *chan);
int fsl_edma_pause(struct dma_chan *chan);
int fsl_edma_resume(struct dma_chan *chan);
int fsl_edma_slave_config(struct dma_chan *chan,
				 struct dma_slave_config *cfg);
enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
		dma_cookie_t cookie, struct dma_tx_state *txstate);
struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction,
		unsigned long flags);
struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags, void *context);
void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
void fsl_edma_issue_pending(struct dma_chan *chan);
int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
void fsl_edma_free_chan_resources(struct dma_chan *chan);
void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
void fsl_edma_setup_regs(struct fsl_edma_engine *edma);

#endif /* _FSL_EDMA_COMMON_H_ */
Commit	Line	Data
9d831528 AD	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright 2013-2014 Freescale Semiconductor, Inc.
	4	* Copyright 2018 Angelo Dureghello <angelo@sysam.it>
	5	*/
	6	#ifndef _FSL_EDMA_COMMON_H_
	7	#define _FSL_EDMA_COMMON_H_
	8
0fa89f97	9	#include <linux/dma-direction.h>
af802728	10	#include <linux/platform_device.h>
9d831528 AD	11	#include "virt-dma.h"
9d831528 AD	12
9d831528 AD	13	#define EDMA_CR_EDBG BIT(1)
	14	#define EDMA_CR_ERCA BIT(2)
	15	#define EDMA_CR_ERGA BIT(3)
	16	#define EDMA_CR_HOE BIT(4)
	17	#define EDMA_CR_HALT BIT(5)
	18	#define EDMA_CR_CLM BIT(6)
	19	#define EDMA_CR_EMLM BIT(7)
	20	#define EDMA_CR_ECX BIT(16)
	21	#define EDMA_CR_CX BIT(17)
	22
4d6d3a90 AD	23	#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
	24	#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
	25	#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
	26	#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
9d831528	27
4d6d3a90 AD	28	#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
	29	#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
	30	#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
	31	#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
	32	#define EDMA_TCD_ATTR_DSIZE_8BIT 0
	33	#define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0)
	34	#define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1)
	35	#define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) \| BIT(1))
	36	#define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) \| BIT(0))
	37	#define EDMA_TCD_ATTR_SSIZE_8BIT 0
	38	#define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8)
	39	#define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8)
	40	#define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8)
	41	#define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8)
9d831528	42
4d6d3a90 AD	43	#define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0))
4d6d3a90 AD	44	#define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0))
9d831528 AD	45
	46	#define EDMA_TCD_CSR_START BIT(0)
	47	#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
	48	#define EDMA_TCD_CSR_INT_HALF BIT(2)
	49	#define EDMA_TCD_CSR_D_REQ BIT(3)
	50	#define EDMA_TCD_CSR_E_SG BIT(4)
	51	#define EDMA_TCD_CSR_E_LINK BIT(5)
	52	#define EDMA_TCD_CSR_ACTIVE BIT(6)
	53	#define EDMA_TCD_CSR_DONE BIT(7)
	54
	55	#define EDMAMUX_CHCFG_DIS 0x0
	56	#define EDMAMUX_CHCFG_ENBL 0x80
	57	#define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
	58
	59	#define DMAMUX_NR 2
	60
	61	#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
	62	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
	63	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) \| \
	64	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
	65	enum fsl_edma_pm_state {
	66	RUNNING = 0,
	67	SUSPENDED,
	68	};
	69
	70	struct fsl_edma_hw_tcd {
	71	__le32 saddr;
	72	__le16 soff;
	73	__le16 attr;
	74	__le32 nbytes;
	75	__le32 slast;
	76	__le32 daddr;
	77	__le16 doff;
	78	__le16 citer;
	79	__le32 dlast_sga;
	80	__le16 csr;
	81	__le16 biter;
	82	};
	83
377eaf3b AD	84	/*
	85	* These are iomem pointers, for both v32 and v64.
	86	*/
	87	struct edma_regs {
	88	void __iomem *cr;
	89	void __iomem *es;
	90	void __iomem *erqh;
	91	void __iomem erql; / aka erq on v32 */
	92	void __iomem *eeih;
	93	void __iomem eeil; / aka eei on v32 */
	94	void __iomem *seei;
	95	void __iomem *ceei;
	96	void __iomem *serq;
	97	void __iomem *cerq;
	98	void __iomem *cint;
	99	void __iomem *cerr;
	100	void __iomem *ssrt;
	101	void __iomem *cdne;
	102	void __iomem *inth;
	103	void __iomem *intl;
	104	void __iomem *errh;
	105	void __iomem *errl;
	106	struct fsl_edma_hw_tcd __iomem *tcd;
	107	};
	108
9d831528 AD	109	struct fsl_edma_sw_tcd {
	110	dma_addr_t ptcd;
	111	struct fsl_edma_hw_tcd *vtcd;
	112	};
	113
9d831528 AD	114	struct fsl_edma_chan {
	115	struct virt_dma_chan vchan;
	116	enum dma_status status;
	117	enum fsl_edma_pm_state pm_state;
	118	bool idle;
	119	u32 slave_id;
	120	struct fsl_edma_engine *edma;
	121	struct fsl_edma_desc *edesc;
0e819e35 VK	122	struct dma_slave_config cfg;
0e819e35 VK	123	u32 attr;
9d831528	124	struct dma_pool *tcd_pool;
0fa89f97 LT	125	dma_addr_t dma_dev_addr;
	126	u32 dma_dev_size;
	127	enum dma_data_direction dma_dir;
9d831528 AD	128	};
	129
	130	struct fsl_edma_desc {
	131	struct virt_dma_desc vdesc;
	132	struct fsl_edma_chan *echan;
	133	bool iscyclic;
0e819e35	134	enum dma_transfer_direction dirn;
9d831528 AD	135	unsigned int n_tcds;
	136	struct fsl_edma_sw_tcd tcd[];
	137	};
	138
377eaf3b	139	enum edma_version {
32685552	140	v1, /* 32ch, Vybrid, mpc57x, etc */
377eaf3b AD	141	v2, /* 64ch Coldfire */
	142	};
	143
af802728 RG	144	struct fsl_edma_drvdata {
	145	enum edma_version version;
	146	u32 dmamuxs;
	147	int (setup_irq)(struct platform_device pdev,
	148	struct fsl_edma_engine *fsl_edma);
	149	};
	150
9d831528 AD	151	struct fsl_edma_engine {
	152	struct dma_device dma_dev;
	153	void __iomem *membase;
	154	void __iomem *muxbase[DMAMUX_NR];
	155	struct clk *muxclk[DMAMUX_NR];
	156	struct mutex fsl_edma_mutex;
af802728	157	const struct fsl_edma_drvdata *drvdata;
9d831528 AD	158	u32 n_chans;
	159	int txirq;
	160	int errirq;
	161	bool big_endian;
377eaf3b	162	struct edma_regs regs;
9d831528 AD	163	struct fsl_edma_chan chans[];
	164	};
	165
	166	/*
	167	* R/W functions for big- or little-endian registers:
	168	* The eDMA controller's endian is independent of the CPU core's endian.
	169	* For the big-endian IP module, the offset for 8-bit or 16-bit registers
	170	* should also be swapped opposite to that in little-endian IP.
	171	*/
	172	static inline u32 edma_readl(struct fsl_edma_engine edma, void __iomem addr)
	173	{
	174	if (edma->big_endian)
	175	return ioread32be(addr);
	176	else
	177	return ioread32(addr);
	178	}
	179
	180	static inline void edma_writeb(struct fsl_edma_engine *edma,
	181	u8 val, void __iomem *addr)
	182	{
	183	/* swap the reg offset for these in big-endian mode */
	184	if (edma->big_endian)
	185	iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
	186	else
	187	iowrite8(val, addr);
	188	}
	189
	190	static inline void edma_writew(struct fsl_edma_engine *edma,
	191	u16 val, void __iomem *addr)
	192	{
	193	/* swap the reg offset for these in big-endian mode */
	194	if (edma->big_endian)
	195	iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
	196	else
	197	iowrite16(val, addr);
	198	}
	199
	200	static inline void edma_writel(struct fsl_edma_engine *edma,
	201	u32 val, void __iomem *addr)
	202	{
	203	if (edma->big_endian)
	204	iowrite32be(val, addr);
	205	else
	206	iowrite32(val, addr);
	207	}
	208
	209	static inline struct fsl_edma_chan to_fsl_edma_chan(struct dma_chan chan)
	210	{
	211	return container_of(chan, struct fsl_edma_chan, vchan.chan);
	212	}
	213
	214	static inline struct fsl_edma_desc to_fsl_edma_desc(struct virt_dma_desc vd)
	215	{
	216	return container_of(vd, struct fsl_edma_desc, vdesc);
	217	}
	218
	219	void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
	220	void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
	221	unsigned int slot, bool enable);
	222	void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
	223	int fsl_edma_terminate_all(struct dma_chan *chan);
	224	int fsl_edma_pause(struct dma_chan *chan);
	225	int fsl_edma_resume(struct dma_chan *chan);
	226	int fsl_edma_slave_config(struct dma_chan *chan,
227	struct dma_slave_config *cfg);
228	enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
229	dma_cookie_t cookie, struct dma_tx_state *txstate);
230	struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
231	struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
232	size_t period_len, enum dma_transfer_direction direction,
233	unsigned long flags);
234	struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
235	struct dma_chan chan, struct scatterlist sgl,
236	unsigned int sg_len, enum dma_transfer_direction direction,
237	unsigned long flags, void *context);
238	void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
239	void fsl_edma_issue_pending(struct dma_chan *chan);
240	int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
241	void fsl_edma_free_chan_resources(struct dma_chan *chan);
242	void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
377eaf3b	243	void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
9d831528 AD	244
9d831528 AD	245	#endif /* _FSL_EDMA_COMMON_H_ */