[linux-block.git] / drivers / dma / dw-axi-dmac / dw-axi-dmac.h

// SPDX-License-Identifier:  GPL-2.0
// (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)

/*
 * Synopsys DesignWare AXI DMA Controller driver.
 *
 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 */

#ifndef _AXI_DMA_PLATFORM_H
#define _AXI_DMA_PLATFORM_H

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dmaengine.h>
#include <linux/types.h>

#include "../virt-dma.h"

#define DMAC_MAX_CHANNELS	8
#define DMAC_MAX_MASTERS	2
#define DMAC_MAX_BLK_SIZE	0x200000

struct dw_axi_dma_hcfg {
	u32	nr_channels;
	u32	nr_masters;
	u32	m_data_width;
	u32	block_size[DMAC_MAX_CHANNELS];
	u32	priority[DMAC_MAX_CHANNELS];
	/* maximum supported axi burst length */
	u32	axi_rw_burst_len;
	bool	restrict_axi_burst_len;
};

struct axi_dma_chan {
	struct axi_dma_chip		*chip;
	void __iomem			*chan_regs;
	u8				id;
	u8				hw_handshake_num;
	atomic_t			descs_allocated;

	struct dma_pool			*desc_pool;
	struct virt_dma_chan		vc;

	struct axi_dma_desc		*desc;
	struct dma_slave_config		config;
	enum dma_transfer_direction	direction;
	bool				cyclic;
	/* these other elements are all protected by vc.lock */
	bool				is_paused;
};

struct dw_axi_dma {
	struct dma_device	dma;
	struct dw_axi_dma_hcfg	*hdata;
	struct device_dma_parameters	dma_parms;

	/* channels */
	struct axi_dma_chan	*chan;
};

struct axi_dma_chip {
	struct device		*dev;
	int			irq;
	void __iomem		*regs;
	void __iomem		*apb_regs;
	struct clk		*core_clk;
	struct clk		*cfgr_clk;
	struct dw_axi_dma	*dw;
};

/* LLI == Linked List Item */
struct __packed axi_dma_lli {
	__le64		sar;
	__le64		dar;
	__le32		block_ts_lo;
	__le32		block_ts_hi;
	__le64		llp;
	__le32		ctl_lo;
	__le32		ctl_hi;
	__le32		sstat;
	__le32		dstat;
	__le32		status_lo;
	__le32		status_hi;
	__le32		reserved_lo;
	__le32		reserved_hi;
};

struct axi_dma_hw_desc {
	struct axi_dma_lli	*lli;
	dma_addr_t		llp;
	u32			len;
};

struct axi_dma_desc {
	struct axi_dma_hw_desc	*hw_desc;

	struct virt_dma_desc		vd;
	struct axi_dma_chan		*chan;
	u32				completed_blocks;
	u32				length;
	u32				period_len;
};

static inline struct device *dchan2dev(struct dma_chan *dchan)
{
	return &dchan->dev->device;
}

static inline struct device *chan2dev(struct axi_dma_chan *chan)
{
	return &chan->vc.chan.dev->device;
}

static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
{
	return container_of(vd, struct axi_dma_desc, vd);
}

static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
{
	return container_of(vc, struct axi_dma_chan, vc);
}

static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
{
	return vc_to_axi_dma_chan(to_virt_chan(dchan));
}


#define COMMON_REG_LEN		0x100
#define CHAN_REG_LEN		0x100

/* Common registers offset */
#define DMAC_ID			0x000 /* R DMAC ID */
#define DMAC_COMPVER		0x008 /* R DMAC Component Version */
#define DMAC_CFG		0x010 /* R/W DMAC Configuration */
#define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
#define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
#define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
#define DMAC_INTSTATUS		0x030 /* R DMAC Interrupt Status */
#define DMAC_COMMON_INTCLEAR	0x038 /* W DMAC Interrupt Clear */
#define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
#define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
#define DMAC_COMMON_INTSTATUS	0x050 /* R DMAC Interrupt Status */
#define DMAC_RESET		0x058 /* R DMAC Reset Register1 */

/* DMA channel registers offset */
#define CH_SAR			0x000 /* R/W Chan Source Address */
#define CH_DAR			0x008 /* R/W Chan Destination Address */
#define CH_BLOCK_TS		0x010 /* R/W Chan Block Transfer Size */
#define CH_CTL			0x018 /* R/W Chan Control */
#define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
#define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
#define CH_CFG			0x020 /* R/W Chan Configuration */
#define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
#define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
#define CH_LLP			0x028 /* R/W Chan Linked List Pointer */
#define CH_STATUS		0x030 /* R Chan Status */
#define CH_SWHSSRC		0x038 /* R/W Chan SW Handshake Source */
#define CH_SWHSDST		0x040 /* R/W Chan SW Handshake Destination */
#define CH_BLK_TFR_RESUMEREQ	0x048 /* W Chan Block Transfer Resume Req */
#define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
#define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
#define CH_SSTAT		0x060 /* R Chan Source Status */
#define CH_DSTAT		0x068 /* R Chan Destination Status */
#define CH_SSTATAR		0x070 /* R/W Chan Source Status Fetch Addr */
#define CH_DSTATAR		0x078 /* R/W Chan Destination Status Fetch Addr */
#define CH_INTSTATUS_ENA	0x080 /* R/W Chan Interrupt Status Enable */
#define CH_INTSTATUS		0x088 /* R/W Chan Interrupt Status */
#define CH_INTSIGNAL_ENA	0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR		0x098 /* W Chan Interrupt Clear */

/* These Apb registers are used by Intel KeemBay SoC */
#define DMAC_APB_CFG		0x000 /* DMAC Apb Configuration Register */
#define DMAC_APB_STAT		0x004 /* DMAC Apb Status Register */
#define DMAC_APB_DEBUG_STAT_0	0x008 /* DMAC Apb Debug Status Register 0 */
#define DMAC_APB_DEBUG_STAT_1	0x00C /* DMAC Apb Debug Status Register 1 */
#define DMAC_APB_HW_HS_SEL_0	0x010 /* DMAC Apb HW HS register 0 */
#define DMAC_APB_HW_HS_SEL_1	0x014 /* DMAC Apb HW HS register 1 */
#define DMAC_APB_LPI		0x018 /* DMAC Apb Low Power Interface Reg */
#define DMAC_APB_BYTE_WR_CH_EN	0x01C /* DMAC Apb Byte Write Enable */
#define DMAC_APB_HALFWORD_WR_CH_EN	0x020 /* DMAC Halfword write enables */

#define UNUSED_CHANNEL		0x3F /* Set unused DMA channel to 0x3F */
#define MAX_BLOCK_SIZE		0x1000 /* 1024 blocks * 4 bytes data width */

/* DMAC_CFG */
#define DMAC_EN_POS			0
#define DMAC_EN_MASK			BIT(DMAC_EN_POS)

#define INT_EN_POS			1
#define INT_EN_MASK			BIT(INT_EN_POS)

#define DMAC_CHAN_EN_SHIFT		0
#define DMAC_CHAN_EN_WE_SHIFT		8

#define DMAC_CHAN_SUSP_SHIFT		16
#define DMAC_CHAN_SUSP_WE_SHIFT		24

/* CH_CTL_H */
#define CH_CTL_H_ARLEN_EN		BIT(6)
#define CH_CTL_H_ARLEN_POS		7
#define CH_CTL_H_AWLEN_EN		BIT(15)
#define CH_CTL_H_AWLEN_POS		16

enum {
	DWAXIDMAC_ARWLEN_1		= 0,
	DWAXIDMAC_ARWLEN_2		= 1,
	DWAXIDMAC_ARWLEN_4		= 3,
	DWAXIDMAC_ARWLEN_8		= 7,
	DWAXIDMAC_ARWLEN_16		= 15,
	DWAXIDMAC_ARWLEN_32		= 31,
	DWAXIDMAC_ARWLEN_64		= 63,
	DWAXIDMAC_ARWLEN_128		= 127,
	DWAXIDMAC_ARWLEN_256		= 255,
	DWAXIDMAC_ARWLEN_MIN		= DWAXIDMAC_ARWLEN_1,
	DWAXIDMAC_ARWLEN_MAX		= DWAXIDMAC_ARWLEN_256
};

#define CH_CTL_H_LLI_LAST		BIT(30)
#define CH_CTL_H_LLI_VALID		BIT(31)

/* CH_CTL_L */
#define CH_CTL_L_LAST_WRITE_EN		BIT(30)

#define CH_CTL_L_DST_MSIZE_POS		18
#define CH_CTL_L_SRC_MSIZE_POS		14

enum {
	DWAXIDMAC_BURST_TRANS_LEN_1	= 0,
	DWAXIDMAC_BURST_TRANS_LEN_4,
	DWAXIDMAC_BURST_TRANS_LEN_8,
	DWAXIDMAC_BURST_TRANS_LEN_16,
	DWAXIDMAC_BURST_TRANS_LEN_32,
	DWAXIDMAC_BURST_TRANS_LEN_64,
	DWAXIDMAC_BURST_TRANS_LEN_128,
	DWAXIDMAC_BURST_TRANS_LEN_256,
	DWAXIDMAC_BURST_TRANS_LEN_512,
	DWAXIDMAC_BURST_TRANS_LEN_1024
};

#define CH_CTL_L_DST_WIDTH_POS		11
#define CH_CTL_L_SRC_WIDTH_POS		8

#define CH_CTL_L_DST_INC_POS		6
#define CH_CTL_L_SRC_INC_POS		4
enum {
	DWAXIDMAC_CH_CTL_L_INC		= 0,
	DWAXIDMAC_CH_CTL_L_NOINC
};

#define CH_CTL_L_DST_MAST		BIT(2)
#define CH_CTL_L_SRC_MAST		BIT(0)

/* CH_CFG_H */
#define CH_CFG_H_PRIORITY_POS		17
#define CH_CFG_H_HS_SEL_DST_POS		4
#define CH_CFG_H_HS_SEL_SRC_POS		3
enum {
	DWAXIDMAC_HS_SEL_HW		= 0,
	DWAXIDMAC_HS_SEL_SW
};

#define CH_CFG_H_TT_FC_POS		0
enum {
	DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC	= 0,
	DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
	DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
	DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
	DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
	DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
	DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
	DWAXIDMAC_TT_FC_PER_TO_PER_DST
};

/* CH_CFG_L */
#define CH_CFG_L_DST_MULTBLK_TYPE_POS	2
#define CH_CFG_L_SRC_MULTBLK_TYPE_POS	0
enum {
	DWAXIDMAC_MBLK_TYPE_CONTIGUOUS	= 0,
	DWAXIDMAC_MBLK_TYPE_RELOAD,
	DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
	DWAXIDMAC_MBLK_TYPE_LL
};

/**
 * DW AXI DMA channel interrupts
 *
 * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
 * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
 * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
 * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
 * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
 * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
 * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
 * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
 * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
 * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
 * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
 * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
 * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
 * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
 * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
 * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
 * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
 * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
 * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
 * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
 * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
 * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
 * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
 * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
 * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
 * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
 * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
 * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
 */
enum {
	DWAXIDMAC_IRQ_NONE		= 0,
	DWAXIDMAC_IRQ_BLOCK_TRF		= BIT(0),
	DWAXIDMAC_IRQ_DMA_TRF		= BIT(1),
	DWAXIDMAC_IRQ_SRC_TRAN		= BIT(3),
	DWAXIDMAC_IRQ_DST_TRAN		= BIT(4),
	DWAXIDMAC_IRQ_SRC_DEC_ERR	= BIT(5),
	DWAXIDMAC_IRQ_DST_DEC_ERR	= BIT(6),
	DWAXIDMAC_IRQ_SRC_SLV_ERR	= BIT(7),
	DWAXIDMAC_IRQ_DST_SLV_ERR	= BIT(8),
	DWAXIDMAC_IRQ_LLI_RD_DEC_ERR	= BIT(9),
	DWAXIDMAC_IRQ_LLI_WR_DEC_ERR	= BIT(10),
	DWAXIDMAC_IRQ_LLI_RD_SLV_ERR	= BIT(11),
	DWAXIDMAC_IRQ_LLI_WR_SLV_ERR	= BIT(12),
	DWAXIDMAC_IRQ_INVALID_ERR	= BIT(13),
	DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR	= BIT(14),
	DWAXIDMAC_IRQ_DEC_ERR		= BIT(16),
	DWAXIDMAC_IRQ_WR2RO_ERR		= BIT(17),
	DWAXIDMAC_IRQ_RD2RWO_ERR	= BIT(18),
	DWAXIDMAC_IRQ_WRONCHEN_ERR	= BIT(19),
	DWAXIDMAC_IRQ_SHADOWREG_ERR	= BIT(20),
	DWAXIDMAC_IRQ_WRONHOLD_ERR	= BIT(21),
	DWAXIDMAC_IRQ_LOCK_CLEARED	= BIT(27),
	DWAXIDMAC_IRQ_SRC_SUSPENDED	= BIT(28),
	DWAXIDMAC_IRQ_SUSPENDED		= BIT(29),
	DWAXIDMAC_IRQ_DISABLED		= BIT(30),
	DWAXIDMAC_IRQ_ABORTED		= BIT(31),
	DWAXIDMAC_IRQ_ALL_ERR		= (GENMASK(21, 16) | GENMASK(14, 5)),
	DWAXIDMAC_IRQ_ALL		= GENMASK(31, 0)
};

enum {
	DWAXIDMAC_TRANS_WIDTH_8		= 0,
	DWAXIDMAC_TRANS_WIDTH_16,
	DWAXIDMAC_TRANS_WIDTH_32,
	DWAXIDMAC_TRANS_WIDTH_64,
	DWAXIDMAC_TRANS_WIDTH_128,
	DWAXIDMAC_TRANS_WIDTH_256,
	DWAXIDMAC_TRANS_WIDTH_512,
	DWAXIDMAC_TRANS_WIDTH_MAX	= DWAXIDMAC_TRANS_WIDTH_512
};

#endif /* _AXI_DMA_PLATFORM_H */
Commit	Line	Data
1fe20f1b EP	1	// SPDX-License-Identifier: GPL-2.0
	2	// (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
	3
	4	/*
	5	* Synopsys DesignWare AXI DMA Controller driver.
	6	*
	7	* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
	8	*/
	9
	10	#ifndef _AXI_DMA_PLATFORM_H
	11	#define _AXI_DMA_PLATFORM_H
	12
	13	#include <linux/bitops.h>
	14	#include <linux/clk.h>
	15	#include <linux/device.h>
	16	#include <linux/dmaengine.h>
	17	#include <linux/types.h>
	18
	19	#include "../virt-dma.h"
	20
	21	#define DMAC_MAX_CHANNELS 8
	22	#define DMAC_MAX_MASTERS 2
	23	#define DMAC_MAX_BLK_SIZE 0x200000
	24
	25	struct dw_axi_dma_hcfg {
	26	u32 nr_channels;
	27	u32 nr_masters;
	28	u32 m_data_width;
	29	u32 block_size[DMAC_MAX_CHANNELS];
	30	u32 priority[DMAC_MAX_CHANNELS];
	31	/* maximum supported axi burst length */
	32	u32 axi_rw_burst_len;
	33	bool restrict_axi_burst_len;
	34	};
	35
	36	struct axi_dma_chan {
	37	struct axi_dma_chip *chip;
	38	void __iomem *chan_regs;
	39	u8 id;
b428c6fa	40	u8 hw_handshake_num;
1fe20f1b EP	41	atomic_t descs_allocated;
1fe20f1b EP	42
0b9d2fb3	43	struct dma_pool *desc_pool;
1fe20f1b EP	44	struct virt_dma_chan vc;
1fe20f1b EP	45
ef6fb2d6	46	struct axi_dma_desc *desc;
66c6c945	47	struct dma_slave_config config;
eec91760	48	enum dma_transfer_direction direction;
1deb96c0	49	bool cyclic;
1fe20f1b EP	50	/* these other elements are all protected by vc.lock */
	51	bool is_paused;
	52	};
	53
	54	struct dw_axi_dma {
	55	struct dma_device dma;
	56	struct dw_axi_dma_hcfg *hdata;
78a90a1e	57	struct device_dma_parameters dma_parms;
1fe20f1b EP	58
	59	/* channels */
	60	struct axi_dma_chan *chan;
	61	};
	62
	63	struct axi_dma_chip {
	64	struct device *dev;
	65	int irq;
	66	void __iomem *regs;
8fb1dae0	67	void __iomem *apb_regs;
1fe20f1b EP	68	struct clk *core_clk;
	69	struct clk *cfgr_clk;
	70	struct dw_axi_dma *dw;
	71	};
	72
	73	/* LLI == Linked List Item */
	74	struct __packed axi_dma_lli {
	75	__le64 sar;
	76	__le64 dar;
	77	__le32 block_ts_lo;
	78	__le32 block_ts_hi;
	79	__le64 llp;
	80	__le32 ctl_lo;
	81	__le32 ctl_hi;
	82	__le32 sstat;
	83	__le32 dstat;
	84	__le32 status_lo;
bdcb2c5d	85	__le32 status_hi;
1fe20f1b EP	86	__le32 reserved_lo;
	87	__le32 reserved_hi;
	88	};
	89
ef6fb2d6 SJH	90	struct axi_dma_hw_desc {
	91	struct axi_dma_lli *lli;
	92	dma_addr_t llp;
8e55444d	93	u32 len;
ef6fb2d6 SJH	94	};
ef6fb2d6 SJH	95
1fe20f1b	96	struct axi_dma_desc {
ef6fb2d6	97	struct axi_dma_hw_desc *hw_desc;
1fe20f1b EP	98
	99	struct virt_dma_desc vd;
	100	struct axi_dma_chan *chan;
1deb96c0	101	u32 completed_blocks;
8e55444d	102	u32 length;
f80f7c96	103	u32 period_len;
1fe20f1b EP	104	};
	105
	106	static inline struct device dchan2dev(struct dma_chan dchan)
	107	{
	108	return &dchan->dev->device;
	109	}
	110
	111	static inline struct device chan2dev(struct axi_dma_chan chan)
	112	{
	113	return &chan->vc.chan.dev->device;
	114	}
	115
	116	static inline struct axi_dma_desc vd_to_axi_desc(struct virt_dma_desc vd)
	117	{
	118	return container_of(vd, struct axi_dma_desc, vd);
	119	}
	120
	121	static inline struct axi_dma_chan vc_to_axi_dma_chan(struct virt_dma_chan vc)
	122	{
	123	return container_of(vc, struct axi_dma_chan, vc);
	124	}
	125
	126	static inline struct axi_dma_chan dchan_to_axi_dma_chan(struct dma_chan dchan)
	127	{
	128	return vc_to_axi_dma_chan(to_virt_chan(dchan));
	129	}
	130
	131
	132	#define COMMON_REG_LEN 0x100
	133	#define CHAN_REG_LEN 0x100
	134
	135	/* Common registers offset */
	136	#define DMAC_ID 0x000 /* R DMAC ID */
	137	#define DMAC_COMPVER 0x008 /* R DMAC Component Version */
	138	#define DMAC_CFG 0x010 /* R/W DMAC Configuration */
	139	#define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
	140	#define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
	141	#define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
	142	#define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
	143	#define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
	144	#define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
	145	#define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
	146	#define DMAC_COMMON_INTSTATUS 0x050 /* R DMAC Interrupt Status */
	147	#define DMAC_RESET 0x058 /* R DMAC Reset Register1 */
	148
	149	/* DMA channel registers offset */
	150	#define CH_SAR 0x000 /* R/W Chan Source Address */
	151	#define CH_DAR 0x008 /* R/W Chan Destination Address */
	152	#define CH_BLOCK_TS 0x010 /* R/W Chan Block Transfer Size */
	153	#define CH_CTL 0x018 /* R/W Chan Control */
	154	#define CH_CTL_L 0x018 /* R/W Chan Control 00-31 */
	155	#define CH_CTL_H 0x01C /* R/W Chan Control 32-63 */
	156	#define CH_CFG 0x020 /* R/W Chan Configuration */
	157	#define CH_CFG_L 0x020 /* R/W Chan Configuration 00-31 */
	158	#define CH_CFG_H 0x024 /* R/W Chan Configuration 32-63 */
	159	#define CH_LLP 0x028 /* R/W Chan Linked List Pointer */
	160	#define CH_STATUS 0x030 /* R Chan Status */
	161	#define CH_SWHSSRC 0x038 /* R/W Chan SW Handshake Source */
	162	#define CH_SWHSDST 0x040 /* R/W Chan SW Handshake Destination */
	163	#define CH_BLK_TFR_RESUMEREQ 0x048 /* W Chan Block Transfer Resume Req */
	164	#define CH_AXI_ID 0x050 /* R/W Chan AXI ID */
	165	#define CH_AXI_QOS 0x058 /* R/W Chan AXI QOS */
	166	#define CH_SSTAT 0x060 /* R Chan Source Status */
	167	#define CH_DSTAT 0x068 /* R Chan Destination Status */
168	#define CH_SSTATAR 0x070 /* R/W Chan Source Status Fetch Addr */
169	#define CH_DSTATAR 0x078 /* R/W Chan Destination Status Fetch Addr */
170	#define CH_INTSTATUS_ENA 0x080 /* R/W Chan Interrupt Status Enable */
171	#define CH_INTSTATUS 0x088 /* R/W Chan Interrupt Status */
172	#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
173	#define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
174
8fb1dae0 SJH	175	/* These Apb registers are used by Intel KeemBay SoC */
	176	#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
	177	#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
	178	#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
	179	#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
	180	#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
	181	#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
	182	#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
	183	#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
	184	#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
	185
	186	#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
	187	#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
1fe20f1b EP	188
	189	/* DMAC_CFG */
	190	#define DMAC_EN_POS 0
	191	#define DMAC_EN_MASK BIT(DMAC_EN_POS)
	192
	193	#define INT_EN_POS 1
	194	#define INT_EN_MASK BIT(INT_EN_POS)
	195
	196	#define DMAC_CHAN_EN_SHIFT 0
	197	#define DMAC_CHAN_EN_WE_SHIFT 8
	198
	199	#define DMAC_CHAN_SUSP_SHIFT 16
	200	#define DMAC_CHAN_SUSP_WE_SHIFT 24
	201
	202	/* CH_CTL_H */
	203	#define CH_CTL_H_ARLEN_EN BIT(6)
	204	#define CH_CTL_H_ARLEN_POS 7
	205	#define CH_CTL_H_AWLEN_EN BIT(15)
	206	#define CH_CTL_H_AWLEN_POS 16
	207
	208	enum {
	209	DWAXIDMAC_ARWLEN_1 = 0,
	210	DWAXIDMAC_ARWLEN_2 = 1,
	211	DWAXIDMAC_ARWLEN_4 = 3,
	212	DWAXIDMAC_ARWLEN_8 = 7,
	213	DWAXIDMAC_ARWLEN_16 = 15,
	214	DWAXIDMAC_ARWLEN_32 = 31,
	215	DWAXIDMAC_ARWLEN_64 = 63,
	216	DWAXIDMAC_ARWLEN_128 = 127,
	217	DWAXIDMAC_ARWLEN_256 = 255,
	218	DWAXIDMAC_ARWLEN_MIN = DWAXIDMAC_ARWLEN_1,
	219	DWAXIDMAC_ARWLEN_MAX = DWAXIDMAC_ARWLEN_256
	220	};
	221
	222	#define CH_CTL_H_LLI_LAST BIT(30)
	223	#define CH_CTL_H_LLI_VALID BIT(31)
	224
	225	/* CH_CTL_L */
	226	#define CH_CTL_L_LAST_WRITE_EN BIT(30)
	227
	228	#define CH_CTL_L_DST_MSIZE_POS 18
	229	#define CH_CTL_L_SRC_MSIZE_POS 14
	230
	231	enum {
	232	DWAXIDMAC_BURST_TRANS_LEN_1 = 0,
	233	DWAXIDMAC_BURST_TRANS_LEN_4,
	234	DWAXIDMAC_BURST_TRANS_LEN_8,
	235	DWAXIDMAC_BURST_TRANS_LEN_16,
	236	DWAXIDMAC_BURST_TRANS_LEN_32,
	237	DWAXIDMAC_BURST_TRANS_LEN_64,
	238	DWAXIDMAC_BURST_TRANS_LEN_128,
	239	DWAXIDMAC_BURST_TRANS_LEN_256,
	240	DWAXIDMAC_BURST_TRANS_LEN_512,
	241	DWAXIDMAC_BURST_TRANS_LEN_1024
	242	};
	243
	244	#define CH_CTL_L_DST_WIDTH_POS 11
	245	#define CH_CTL_L_SRC_WIDTH_POS 8
	246
	247	#define CH_CTL_L_DST_INC_POS 6
	248	#define CH_CTL_L_SRC_INC_POS 4
	249	enum {
	250	DWAXIDMAC_CH_CTL_L_INC = 0,
	251	DWAXIDMAC_CH_CTL_L_NOINC
252	};
253
254	#define CH_CTL_L_DST_MAST BIT(2)
255	#define CH_CTL_L_SRC_MAST BIT(0)
256
257	/* CH_CFG_H */
258	#define CH_CFG_H_PRIORITY_POS 17
259	#define CH_CFG_H_HS_SEL_DST_POS 4
260	#define CH_CFG_H_HS_SEL_SRC_POS 3
261	enum {
262	DWAXIDMAC_HS_SEL_HW = 0,
263	DWAXIDMAC_HS_SEL_SW
264	};
265
266	#define CH_CFG_H_TT_FC_POS 0
267	enum {
268	DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0,
269	DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
270	DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
271	DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
272	DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
273	DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
274	DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
275	DWAXIDMAC_TT_FC_PER_TO_PER_DST
276	};
277
278	/* CH_CFG_L */
279	#define CH_CFG_L_DST_MULTBLK_TYPE_POS 2
280	#define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0
281	enum {
282	DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0,
283	DWAXIDMAC_MBLK_TYPE_RELOAD,
284	DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
285	DWAXIDMAC_MBLK_TYPE_LL
286	};
287
288	/**
289	* DW AXI DMA channel interrupts
290	*
291	* @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
292	* @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
293	* @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
294	* @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
295	* @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
296	* @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
297	* @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
298	* @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
299	* @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
300	* @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
301	* @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
302	* @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
303	* @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
304	* @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
305	* @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
306	* @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
307	* @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
308	* @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
309	* @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
310	* @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
311	* @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
312	* @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
313	* @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
314	* @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
315	* @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
316	* @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
317	* @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
318	* @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
319	*/
320	enum {
321	DWAXIDMAC_IRQ_NONE = 0,
322	DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0),
323	DWAXIDMAC_IRQ_DMA_TRF = BIT(1),
324	DWAXIDMAC_IRQ_SRC_TRAN = BIT(3),
325	DWAXIDMAC_IRQ_DST_TRAN = BIT(4),
326	DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5),
327	DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6),
328	DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7),
329	DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8),
330	DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9),
331	DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10),
332	DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11),
333	DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12),
334	DWAXIDMAC_IRQ_INVALID_ERR = BIT(13),
335	DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14),
336	DWAXIDMAC_IRQ_DEC_ERR = BIT(16),
337	DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17),
338	DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18),
339	DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19),
340	DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20),
341	DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21),
342	DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27),
343	DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28),
344	DWAXIDMAC_IRQ_SUSPENDED = BIT(29),
345	DWAXIDMAC_IRQ_DISABLED = BIT(30),
346	DWAXIDMAC_IRQ_ABORTED = BIT(31),
347	DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) \| GENMASK(14, 5)),
348	DWAXIDMAC_IRQ_ALL = GENMASK(31, 0)
349	};
350
351	enum {
352	DWAXIDMAC_TRANS_WIDTH_8 = 0,
353	DWAXIDMAC_TRANS_WIDTH_16,
354	DWAXIDMAC_TRANS_WIDTH_32,
355	DWAXIDMAC_TRANS_WIDTH_64,
356	DWAXIDMAC_TRANS_WIDTH_128,
357	DWAXIDMAC_TRANS_WIDTH_256,
358	DWAXIDMAC_TRANS_WIDTH_512,
359	DWAXIDMAC_TRANS_WIDTH_MAX = DWAXIDMAC_TRANS_WIDTH_512
360	};
361
362	#endif /* _AXI_DMA_PLATFORM_H */