Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/delay.h> |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/module.h> | |
3bfb1d20 | 24 | #include <linux/slab.h> |
bb32baf7 | 25 | #include <linux/pm_runtime.h> |
3bfb1d20 | 26 | |
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
327e6970 | 40 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 43 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 44 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 45 | DW_DMA_MSIZE_16; \ |
495aea4b | 46 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 47 | DW_DMA_MSIZE_16; \ |
f301c062 | 48 | \ |
327e6970 VK |
49 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
50 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
51 | | DWC_CTLL_LLP_D_EN \ |
52 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
53 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
54 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 55 | }) |
3bfb1d20 | 56 | |
3bfb1d20 HS |
57 | /* |
58 | * Number of descriptors to allocate for each channel. This should be | |
59 | * made configurable somehow; preferably, the clients (at least the | |
60 | * ones using slave transfers) should be able to give us a hint. | |
61 | */ | |
62 | #define NR_DESCS_PER_CHANNEL 64 | |
63 | ||
029a40e9 AS |
64 | /* The set of bus widths supported by the DMA controller */ |
65 | #define DW_DMA_BUSWIDTHS \ | |
66 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
67 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
68 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
69 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | |
70 | ||
3bfb1d20 | 71 | /*----------------------------------------------------------------------*/ |
3bfb1d20 | 72 | |
41d5e59c DW |
73 | static struct device *chan2dev(struct dma_chan *chan) |
74 | { | |
75 | return &chan->dev->device; | |
76 | } | |
41d5e59c | 77 | |
3bfb1d20 HS |
78 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
79 | { | |
e63a47a3 | 80 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
81 | } |
82 | ||
3bfb1d20 HS |
83 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
84 | { | |
85 | struct dw_desc *desc, *_desc; | |
86 | struct dw_desc *ret = NULL; | |
87 | unsigned int i = 0; | |
69cea5a0 | 88 | unsigned long flags; |
3bfb1d20 | 89 | |
69cea5a0 | 90 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 91 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 92 | i++; |
3bfb1d20 HS |
93 | if (async_tx_test_ack(&desc->txd)) { |
94 | list_del(&desc->desc_node); | |
95 | ret = desc; | |
96 | break; | |
97 | } | |
41d5e59c | 98 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 99 | } |
69cea5a0 | 100 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 101 | |
41d5e59c | 102 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
103 | |
104 | return ret; | |
105 | } | |
106 | ||
3bfb1d20 HS |
107 | /* |
108 | * Move a descriptor, including any children, to the free list. | |
109 | * `desc' must not be on any lists. | |
110 | */ | |
111 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
112 | { | |
69cea5a0 VK |
113 | unsigned long flags; |
114 | ||
3bfb1d20 HS |
115 | if (desc) { |
116 | struct dw_desc *child; | |
117 | ||
69cea5a0 | 118 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 119 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 120 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
121 | "moving child desc %p to freelist\n", |
122 | child); | |
e0bd0f8c | 123 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 124 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 125 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 126 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
127 | } |
128 | } | |
129 | ||
61e183f8 VK |
130 | static void dwc_initialize(struct dw_dma_chan *dwc) |
131 | { | |
132 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
61e183f8 VK |
133 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
134 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
135 | ||
136 | if (dwc->initialized == true) | |
137 | return; | |
138 | ||
3fe6409c AS |
139 | cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); |
140 | cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); | |
61e183f8 VK |
141 | |
142 | channel_writel(dwc, CFG_LO, cfglo); | |
143 | channel_writel(dwc, CFG_HI, cfghi); | |
144 | ||
145 | /* Enable interrupts */ | |
146 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
147 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
148 | ||
149 | dwc->initialized = true; | |
150 | } | |
151 | ||
3bfb1d20 HS |
152 | /*----------------------------------------------------------------------*/ |
153 | ||
39416677 | 154 | static inline unsigned int dwc_fast_ffs(unsigned long long v) |
4c2d56c5 AS |
155 | { |
156 | /* | |
157 | * We can be a lot more clever here, but this should take care | |
158 | * of the most common optimization. | |
159 | */ | |
160 | if (!(v & 7)) | |
161 | return 3; | |
162 | else if (!(v & 3)) | |
163 | return 2; | |
164 | else if (!(v & 1)) | |
165 | return 1; | |
166 | return 0; | |
167 | } | |
168 | ||
f52b36d2 | 169 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
170 | { |
171 | dev_err(chan2dev(&dwc->chan), | |
172 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
173 | channel_readl(dwc, SAR), | |
174 | channel_readl(dwc, DAR), | |
175 | channel_readl(dwc, LLP), | |
176 | channel_readl(dwc, CTL_HI), | |
177 | channel_readl(dwc, CTL_LO)); | |
178 | } | |
179 | ||
3f936207 AS |
180 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
181 | { | |
182 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
183 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
184 | cpu_relax(); | |
185 | } | |
186 | ||
1d455437 AS |
187 | /*----------------------------------------------------------------------*/ |
188 | ||
fed2574b AS |
189 | /* Perform single block transfer */ |
190 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
191 | struct dw_desc *desc) | |
192 | { | |
193 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
194 | u32 ctllo; | |
195 | ||
1d566f11 AS |
196 | /* |
197 | * Software emulation of LLP mode relies on interrupts to continue | |
198 | * multi block transfer. | |
199 | */ | |
fed2574b AS |
200 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
201 | ||
202 | channel_writel(dwc, SAR, desc->lli.sar); | |
203 | channel_writel(dwc, DAR, desc->lli.dar); | |
204 | channel_writel(dwc, CTL_LO, ctllo); | |
205 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
206 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
207 | |
208 | /* Move pointer to next descriptor */ | |
209 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
210 | } |
211 | ||
3bfb1d20 HS |
212 | /* Called with dwc->lock held and bh disabled */ |
213 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
214 | { | |
215 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 216 | unsigned long was_soft_llp; |
3bfb1d20 HS |
217 | |
218 | /* ASSERT: channel is idle */ | |
219 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 220 | dev_err(chan2dev(&dwc->chan), |
550da64b JN |
221 | "%s: BUG: Attempted to start non-idle channel\n", |
222 | __func__); | |
1d455437 | 223 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
224 | |
225 | /* The tasklet will hopefully advance the queue... */ | |
226 | return; | |
227 | } | |
228 | ||
fed2574b AS |
229 | if (dwc->nollp) { |
230 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
231 | &dwc->flags); | |
232 | if (was_soft_llp) { | |
233 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 234 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
235 | return; |
236 | } | |
237 | ||
238 | dwc_initialize(dwc); | |
239 | ||
4702d524 | 240 | dwc->residue = first->total_len; |
f5c6a7df | 241 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 242 | |
fdf475fa | 243 | /* Submit first block */ |
fed2574b AS |
244 | dwc_do_single_block(dwc, first); |
245 | ||
246 | return; | |
247 | } | |
248 | ||
61e183f8 VK |
249 | dwc_initialize(dwc); |
250 | ||
3bfb1d20 HS |
251 | channel_writel(dwc, LLP, first->txd.phys); |
252 | channel_writel(dwc, CTL_LO, | |
253 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
254 | channel_writel(dwc, CTL_HI, 0); | |
255 | channel_set_bit(dw, CH_EN, dwc->mask); | |
256 | } | |
257 | ||
e7637c6c AS |
258 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
259 | { | |
cba15617 AS |
260 | struct dw_desc *desc; |
261 | ||
e7637c6c AS |
262 | if (list_empty(&dwc->queue)) |
263 | return; | |
264 | ||
265 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
266 | desc = dwc_first_active(dwc); |
267 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
268 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
269 | } |
270 | ||
3bfb1d20 HS |
271 | /*----------------------------------------------------------------------*/ |
272 | ||
273 | static void | |
5fedefb8 VK |
274 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
275 | bool callback_required) | |
3bfb1d20 | 276 | { |
5fedefb8 VK |
277 | dma_async_tx_callback callback = NULL; |
278 | void *param = NULL; | |
3bfb1d20 | 279 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 280 | struct dw_desc *child; |
69cea5a0 | 281 | unsigned long flags; |
3bfb1d20 | 282 | |
41d5e59c | 283 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 284 | |
69cea5a0 | 285 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 286 | dma_cookie_complete(txd); |
5fedefb8 VK |
287 | if (callback_required) { |
288 | callback = txd->callback; | |
289 | param = txd->callback_param; | |
290 | } | |
3bfb1d20 | 291 | |
e518076e VK |
292 | /* async_tx_ack */ |
293 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
294 | async_tx_ack(&child->txd); | |
295 | async_tx_ack(&desc->txd); | |
296 | ||
e0bd0f8c | 297 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
298 | list_move(&desc->desc_node, &dwc->free_list); |
299 | ||
d38a8c62 | 300 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
301 | spin_unlock_irqrestore(&dwc->lock, flags); |
302 | ||
21e93c1e | 303 | if (callback) |
3bfb1d20 HS |
304 | callback(param); |
305 | } | |
306 | ||
307 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
308 | { | |
309 | struct dw_desc *desc, *_desc; | |
310 | LIST_HEAD(list); | |
69cea5a0 | 311 | unsigned long flags; |
3bfb1d20 | 312 | |
69cea5a0 | 313 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 314 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 315 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
316 | "BUG: XFER bit set, but channel not idle!\n"); |
317 | ||
318 | /* Try to continue after resetting the channel... */ | |
3f936207 | 319 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
320 | } |
321 | ||
322 | /* | |
323 | * Submit queued descriptors ASAP, i.e. before we go through | |
324 | * the completed ones. | |
325 | */ | |
3bfb1d20 | 326 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 327 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 328 | |
69cea5a0 VK |
329 | spin_unlock_irqrestore(&dwc->lock, flags); |
330 | ||
3bfb1d20 | 331 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 332 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
333 | } |
334 | ||
4702d524 AS |
335 | /* Returns how many bytes were already received from source */ |
336 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
337 | { | |
338 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
339 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
340 | ||
341 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
342 | } | |
343 | ||
3bfb1d20 HS |
344 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
345 | { | |
346 | dma_addr_t llp; | |
347 | struct dw_desc *desc, *_desc; | |
348 | struct dw_desc *child; | |
349 | u32 status_xfer; | |
69cea5a0 | 350 | unsigned long flags; |
3bfb1d20 | 351 | |
69cea5a0 | 352 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
353 | llp = channel_readl(dwc, LLP); |
354 | status_xfer = dma_readl(dw, RAW.XFER); | |
355 | ||
356 | if (status_xfer & dwc->mask) { | |
357 | /* Everything we've submitted is done */ | |
358 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
359 | |
360 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
361 | struct list_head *head, *active = dwc->tx_node_active; |
362 | ||
363 | /* | |
364 | * We are inside first active descriptor. | |
365 | * Otherwise something is really wrong. | |
366 | */ | |
367 | desc = dwc_first_active(dwc); | |
368 | ||
369 | head = &desc->tx_list; | |
370 | if (active != head) { | |
4702d524 AS |
371 | /* Update desc to reflect last sent one */ |
372 | if (active != head->next) | |
373 | desc = to_dw_desc(active->prev); | |
374 | ||
375 | dwc->residue -= desc->len; | |
376 | ||
fdf475fa | 377 | child = to_dw_desc(active); |
77bcc497 AS |
378 | |
379 | /* Submit next block */ | |
fdf475fa | 380 | dwc_do_single_block(dwc, child); |
77bcc497 | 381 | |
fdf475fa | 382 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
383 | return; |
384 | } | |
fdf475fa | 385 | |
77bcc497 AS |
386 | /* We are done here */ |
387 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
388 | } | |
4702d524 AS |
389 | |
390 | dwc->residue = 0; | |
391 | ||
69cea5a0 VK |
392 | spin_unlock_irqrestore(&dwc->lock, flags); |
393 | ||
3bfb1d20 HS |
394 | dwc_complete_all(dw, dwc); |
395 | return; | |
396 | } | |
397 | ||
69cea5a0 | 398 | if (list_empty(&dwc->active_list)) { |
4702d524 | 399 | dwc->residue = 0; |
69cea5a0 | 400 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 401 | return; |
69cea5a0 | 402 | } |
087809fc | 403 | |
77bcc497 AS |
404 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
405 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 406 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 407 | return; |
69cea5a0 | 408 | } |
087809fc | 409 | |
5a87f0e6 | 410 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
411 | |
412 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 413 | /* Initial residue value */ |
4702d524 AS |
414 | dwc->residue = desc->total_len; |
415 | ||
75c61225 | 416 | /* Check first descriptors addr */ |
69cea5a0 VK |
417 | if (desc->txd.phys == llp) { |
418 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 419 | return; |
69cea5a0 | 420 | } |
84adccfb | 421 | |
75c61225 | 422 | /* Check first descriptors llp */ |
69cea5a0 | 423 | if (desc->lli.llp == llp) { |
3bfb1d20 | 424 | /* This one is currently in progress */ |
4702d524 | 425 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 426 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 427 | return; |
69cea5a0 | 428 | } |
3bfb1d20 | 429 | |
4702d524 AS |
430 | dwc->residue -= desc->len; |
431 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 432 | if (child->lli.llp == llp) { |
3bfb1d20 | 433 | /* Currently in progress */ |
4702d524 | 434 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 435 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 436 | return; |
69cea5a0 | 437 | } |
4702d524 AS |
438 | dwc->residue -= child->len; |
439 | } | |
3bfb1d20 HS |
440 | |
441 | /* | |
442 | * No descriptors so far seem to be in progress, i.e. | |
443 | * this one must be done. | |
444 | */ | |
69cea5a0 | 445 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 446 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 447 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
448 | } |
449 | ||
41d5e59c | 450 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
451 | "BUG: All descriptors done, but channel not idle!\n"); |
452 | ||
453 | /* Try to continue after resetting the channel... */ | |
3f936207 | 454 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 455 | |
e7637c6c | 456 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 457 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
458 | } |
459 | ||
93aad1bc | 460 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 461 | { |
21d43f49 AS |
462 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
463 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
464 | } |
465 | ||
466 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
467 | { | |
468 | struct dw_desc *bad_desc; | |
469 | struct dw_desc *child; | |
69cea5a0 | 470 | unsigned long flags; |
3bfb1d20 HS |
471 | |
472 | dwc_scan_descriptors(dw, dwc); | |
473 | ||
69cea5a0 VK |
474 | spin_lock_irqsave(&dwc->lock, flags); |
475 | ||
3bfb1d20 HS |
476 | /* |
477 | * The descriptor currently at the head of the active list is | |
478 | * borked. Since we don't have any way to report errors, we'll | |
479 | * just have to scream loudly and try to carry on. | |
480 | */ | |
481 | bad_desc = dwc_first_active(dwc); | |
482 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 483 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
484 | |
485 | /* Clear the error flag and try to restart the controller */ | |
486 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
487 | if (!list_empty(&dwc->active_list)) | |
488 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
489 | ||
490 | /* | |
ba84bd71 | 491 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
492 | * when someone submits a bad physical address in a |
493 | * descriptor, we should consider ourselves lucky that the | |
494 | * controller flagged an error instead of scribbling over | |
495 | * random memory locations. | |
496 | */ | |
ba84bd71 AS |
497 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
498 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 499 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 500 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
501 | dwc_dump_lli(dwc, &child->lli); |
502 | ||
69cea5a0 VK |
503 | spin_unlock_irqrestore(&dwc->lock, flags); |
504 | ||
3bfb1d20 | 505 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 506 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
507 | } |
508 | ||
d9de4519 HCE |
509 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
510 | ||
8004cbb4 | 511 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
512 | { |
513 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
514 | return channel_readl(dwc, SAR); | |
515 | } | |
516 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
517 | ||
8004cbb4 | 518 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
519 | { |
520 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
521 | return channel_readl(dwc, DAR); | |
522 | } | |
523 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
524 | ||
75c61225 | 525 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 526 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
2895b2ca | 527 | u32 status_block, u32 status_err, u32 status_xfer) |
d9de4519 | 528 | { |
69cea5a0 VK |
529 | unsigned long flags; |
530 | ||
2895b2ca | 531 | if (status_block & dwc->mask) { |
d9de4519 HCE |
532 | void (*callback)(void *param); |
533 | void *callback_param; | |
534 | ||
535 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
536 | channel_readl(dwc, LLP)); | |
2895b2ca | 537 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
538 | |
539 | callback = dwc->cdesc->period_callback; | |
540 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
541 | |
542 | if (callback) | |
d9de4519 | 543 | callback(callback_param); |
d9de4519 HCE |
544 | } |
545 | ||
546 | /* | |
547 | * Error and transfer complete are highly unlikely, and will most | |
548 | * likely be due to a configuration error by the user. | |
549 | */ | |
550 | if (unlikely(status_err & dwc->mask) || | |
551 | unlikely(status_xfer & dwc->mask)) { | |
552 | int i; | |
553 | ||
fc61f6b4 AS |
554 | dev_err(chan2dev(&dwc->chan), |
555 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
556 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
557 | |
558 | spin_lock_irqsave(&dwc->lock, flags); | |
559 | ||
1d455437 | 560 | dwc_dump_chan_regs(dwc); |
d9de4519 | 561 | |
3f936207 | 562 | dwc_chan_disable(dw, dwc); |
d9de4519 | 563 | |
75c61225 | 564 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
565 | channel_writel(dwc, LLP, 0); |
566 | channel_writel(dwc, CTL_LO, 0); | |
567 | channel_writel(dwc, CTL_HI, 0); | |
568 | ||
2895b2ca | 569 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
570 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
571 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
572 | ||
573 | for (i = 0; i < dwc->cdesc->periods; i++) | |
574 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
575 | |
576 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 | 577 | } |
ee1cdcda AS |
578 | |
579 | /* Re-enable interrupts */ | |
580 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
d9de4519 HCE |
581 | } |
582 | ||
583 | /* ------------------------------------------------------------------------- */ | |
584 | ||
3bfb1d20 HS |
585 | static void dw_dma_tasklet(unsigned long data) |
586 | { | |
587 | struct dw_dma *dw = (struct dw_dma *)data; | |
588 | struct dw_dma_chan *dwc; | |
2895b2ca | 589 | u32 status_block; |
3bfb1d20 HS |
590 | u32 status_xfer; |
591 | u32 status_err; | |
592 | int i; | |
593 | ||
2895b2ca | 594 | status_block = dma_readl(dw, RAW.BLOCK); |
7fe7b2f4 | 595 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
596 | status_err = dma_readl(dw, RAW.ERROR); |
597 | ||
2e4c364e | 598 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
599 | |
600 | for (i = 0; i < dw->dma.chancnt; i++) { | |
601 | dwc = &dw->chan[i]; | |
d9de4519 | 602 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
2895b2ca MR |
603 | dwc_handle_cyclic(dw, dwc, status_block, status_err, |
604 | status_xfer); | |
d9de4519 | 605 | else if (status_err & (1 << i)) |
3bfb1d20 | 606 | dwc_handle_error(dw, dwc); |
77bcc497 | 607 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 608 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
609 | } |
610 | ||
ee1cdcda | 611 | /* Re-enable interrupts */ |
3bfb1d20 | 612 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
3bfb1d20 HS |
613 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
614 | } | |
615 | ||
616 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
617 | { | |
618 | struct dw_dma *dw = dev_id; | |
02a21b79 | 619 | u32 status; |
3bfb1d20 | 620 | |
02a21b79 AS |
621 | /* Check if we have any interrupt from the DMAC which is not in use */ |
622 | if (!dw->in_use) | |
623 | return IRQ_NONE; | |
624 | ||
625 | status = dma_readl(dw, STATUS_INT); | |
3783cef8 AS |
626 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
627 | ||
628 | /* Check if we have any interrupt from the DMAC */ | |
02a21b79 | 629 | if (!status) |
3783cef8 | 630 | return IRQ_NONE; |
3bfb1d20 HS |
631 | |
632 | /* | |
633 | * Just disable the interrupts. We'll turn them back on in the | |
634 | * softirq handler. | |
635 | */ | |
636 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 637 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
638 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
639 | ||
640 | status = dma_readl(dw, STATUS_INT); | |
641 | if (status) { | |
642 | dev_err(dw->dma.dev, | |
643 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
644 | status); | |
645 | ||
646 | /* Try to recover */ | |
647 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
2895b2ca | 648 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
3bfb1d20 HS |
649 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
650 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
651 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
652 | } | |
653 | ||
654 | tasklet_schedule(&dw->tasklet); | |
655 | ||
656 | return IRQ_HANDLED; | |
657 | } | |
658 | ||
659 | /*----------------------------------------------------------------------*/ | |
660 | ||
661 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
662 | { | |
663 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
664 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
665 | dma_cookie_t cookie; | |
69cea5a0 | 666 | unsigned long flags; |
3bfb1d20 | 667 | |
69cea5a0 | 668 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 669 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
670 | |
671 | /* | |
672 | * REVISIT: We should attempt to chain as many descriptors as | |
673 | * possible, perhaps even appending to those already submitted | |
674 | * for DMA. But this is hard to do in a race-free manner. | |
675 | */ | |
3bfb1d20 | 676 | |
dd8ecfca AS |
677 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); |
678 | list_add_tail(&desc->desc_node, &dwc->queue); | |
3bfb1d20 | 679 | |
69cea5a0 | 680 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
681 | |
682 | return cookie; | |
683 | } | |
684 | ||
685 | static struct dma_async_tx_descriptor * | |
686 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
687 | size_t len, unsigned long flags) | |
688 | { | |
689 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 690 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
691 | struct dw_desc *desc; |
692 | struct dw_desc *first; | |
693 | struct dw_desc *prev; | |
694 | size_t xfer_count; | |
695 | size_t offset; | |
696 | unsigned int src_width; | |
697 | unsigned int dst_width; | |
3d4f8605 | 698 | unsigned int data_width; |
3bfb1d20 HS |
699 | u32 ctllo; |
700 | ||
2f45d613 | 701 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
702 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
703 | &dest, &src, len, flags); | |
3bfb1d20 HS |
704 | |
705 | if (unlikely(!len)) { | |
2e4c364e | 706 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
707 | return NULL; |
708 | } | |
709 | ||
0fdb567f AS |
710 | dwc->direction = DMA_MEM_TO_MEM; |
711 | ||
f776076b AB |
712 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
713 | dw->data_width[dwc->dst_master]); | |
a0982004 | 714 | |
3d4f8605 | 715 | src_width = dst_width = min_t(unsigned int, data_width, |
39416677 | 716 | dwc_fast_ffs(src | dest | len)); |
3bfb1d20 | 717 | |
327e6970 | 718 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
719 | | DWC_CTLL_DST_WIDTH(dst_width) |
720 | | DWC_CTLL_SRC_WIDTH(src_width) | |
721 | | DWC_CTLL_DST_INC | |
722 | | DWC_CTLL_SRC_INC | |
723 | | DWC_CTLL_FC_M2M; | |
724 | prev = first = NULL; | |
725 | ||
726 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
727 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 728 | dwc->block_size); |
3bfb1d20 HS |
729 | |
730 | desc = dwc_desc_get(dwc); | |
731 | if (!desc) | |
732 | goto err_desc_get; | |
733 | ||
734 | desc->lli.sar = src + offset; | |
735 | desc->lli.dar = dest + offset; | |
736 | desc->lli.ctllo = ctllo; | |
737 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 738 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
739 | |
740 | if (!first) { | |
741 | first = desc; | |
742 | } else { | |
743 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 744 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 745 | &first->tx_list); |
3bfb1d20 HS |
746 | } |
747 | prev = desc; | |
748 | } | |
749 | ||
3bfb1d20 HS |
750 | if (flags & DMA_PREP_INTERRUPT) |
751 | /* Trigger interrupt after last block */ | |
752 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
753 | ||
754 | prev->lli.llp = 0; | |
3bfb1d20 | 755 | first->txd.flags = flags; |
30d38a32 | 756 | first->total_len = len; |
3bfb1d20 HS |
757 | |
758 | return &first->txd; | |
759 | ||
760 | err_desc_get: | |
761 | dwc_desc_put(dwc, first); | |
762 | return NULL; | |
763 | } | |
764 | ||
765 | static struct dma_async_tx_descriptor * | |
766 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 767 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 768 | unsigned long flags, void *context) |
3bfb1d20 HS |
769 | { |
770 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 771 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 772 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
773 | struct dw_desc *prev; |
774 | struct dw_desc *first; | |
775 | u32 ctllo; | |
776 | dma_addr_t reg; | |
777 | unsigned int reg_width; | |
778 | unsigned int mem_width; | |
a0982004 | 779 | unsigned int data_width; |
3bfb1d20 HS |
780 | unsigned int i; |
781 | struct scatterlist *sg; | |
782 | size_t total_len = 0; | |
783 | ||
2e4c364e | 784 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 785 | |
495aea4b | 786 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
787 | return NULL; |
788 | ||
0fdb567f AS |
789 | dwc->direction = direction; |
790 | ||
3bfb1d20 HS |
791 | prev = first = NULL; |
792 | ||
3bfb1d20 | 793 | switch (direction) { |
db8196df | 794 | case DMA_MEM_TO_DEV: |
39416677 | 795 | reg_width = __ffs(sconfig->dst_addr_width); |
327e6970 VK |
796 | reg = sconfig->dst_addr; |
797 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
798 | | DWC_CTLL_DST_WIDTH(reg_width) |
799 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
800 | | DWC_CTLL_SRC_INC); |
801 | ||
802 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
803 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
804 | ||
f776076b | 805 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 806 | |
3bfb1d20 HS |
807 | for_each_sg(sgl, sg, sg_len, i) { |
808 | struct dw_desc *desc; | |
69dc14b5 | 809 | u32 len, dlen, mem; |
3bfb1d20 | 810 | |
cbb796cc | 811 | mem = sg_dma_address(sg); |
69dc14b5 | 812 | len = sg_dma_len(sg); |
6bc711f6 | 813 | |
a0982004 | 814 | mem_width = min_t(unsigned int, |
39416677 | 815 | data_width, dwc_fast_ffs(mem | len)); |
3bfb1d20 | 816 | |
69dc14b5 | 817 | slave_sg_todev_fill_desc: |
3bfb1d20 | 818 | desc = dwc_desc_get(dwc); |
b2607227 | 819 | if (!desc) |
3bfb1d20 | 820 | goto err_desc_get; |
3bfb1d20 | 821 | |
3bfb1d20 HS |
822 | desc->lli.sar = mem; |
823 | desc->lli.dar = reg; | |
824 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
825 | if ((len >> mem_width) > dwc->block_size) { |
826 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
827 | mem += dlen; |
828 | len -= dlen; | |
829 | } else { | |
830 | dlen = len; | |
831 | len = 0; | |
832 | } | |
833 | ||
834 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 835 | desc->len = dlen; |
3bfb1d20 HS |
836 | |
837 | if (!first) { | |
838 | first = desc; | |
839 | } else { | |
840 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 841 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 842 | &first->tx_list); |
3bfb1d20 HS |
843 | } |
844 | prev = desc; | |
69dc14b5 VK |
845 | total_len += dlen; |
846 | ||
847 | if (len) | |
848 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
849 | } |
850 | break; | |
db8196df | 851 | case DMA_DEV_TO_MEM: |
39416677 | 852 | reg_width = __ffs(sconfig->src_addr_width); |
327e6970 VK |
853 | reg = sconfig->src_addr; |
854 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
855 | | DWC_CTLL_SRC_WIDTH(reg_width) |
856 | | DWC_CTLL_DST_INC | |
327e6970 VK |
857 | | DWC_CTLL_SRC_FIX); |
858 | ||
859 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
860 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 861 | |
f776076b | 862 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 863 | |
3bfb1d20 HS |
864 | for_each_sg(sgl, sg, sg_len, i) { |
865 | struct dw_desc *desc; | |
69dc14b5 | 866 | u32 len, dlen, mem; |
3bfb1d20 | 867 | |
cbb796cc | 868 | mem = sg_dma_address(sg); |
3bfb1d20 | 869 | len = sg_dma_len(sg); |
6bc711f6 | 870 | |
a0982004 | 871 | mem_width = min_t(unsigned int, |
39416677 | 872 | data_width, dwc_fast_ffs(mem | len)); |
3bfb1d20 | 873 | |
69dc14b5 VK |
874 | slave_sg_fromdev_fill_desc: |
875 | desc = dwc_desc_get(dwc); | |
b2607227 | 876 | if (!desc) |
69dc14b5 | 877 | goto err_desc_get; |
69dc14b5 | 878 | |
3bfb1d20 HS |
879 | desc->lli.sar = reg; |
880 | desc->lli.dar = mem; | |
881 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
882 | if ((len >> reg_width) > dwc->block_size) { |
883 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
884 | mem += dlen; |
885 | len -= dlen; | |
886 | } else { | |
887 | dlen = len; | |
888 | len = 0; | |
889 | } | |
890 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 891 | desc->len = dlen; |
3bfb1d20 HS |
892 | |
893 | if (!first) { | |
894 | first = desc; | |
895 | } else { | |
896 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 897 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 898 | &first->tx_list); |
3bfb1d20 HS |
899 | } |
900 | prev = desc; | |
69dc14b5 VK |
901 | total_len += dlen; |
902 | ||
903 | if (len) | |
904 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
905 | } |
906 | break; | |
907 | default: | |
908 | return NULL; | |
909 | } | |
910 | ||
911 | if (flags & DMA_PREP_INTERRUPT) | |
912 | /* Trigger interrupt after last block */ | |
913 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
914 | ||
915 | prev->lli.llp = 0; | |
30d38a32 | 916 | first->total_len = total_len; |
3bfb1d20 HS |
917 | |
918 | return &first->txd; | |
919 | ||
920 | err_desc_get: | |
b2607227 JN |
921 | dev_err(chan2dev(chan), |
922 | "not enough descriptors available. Direction %d\n", direction); | |
3bfb1d20 HS |
923 | dwc_desc_put(dwc, first); |
924 | return NULL; | |
925 | } | |
926 | ||
4d130de2 AS |
927 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
928 | { | |
929 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
930 | struct dw_dma_slave *dws = param; | |
931 | ||
3fe6409c | 932 | if (dws->dma_dev != chan->device->dev) |
4d130de2 AS |
933 | return false; |
934 | ||
935 | /* We have to copy data since dws can be temporary storage */ | |
936 | ||
937 | dwc->src_id = dws->src_id; | |
938 | dwc->dst_id = dws->dst_id; | |
939 | ||
940 | dwc->src_master = dws->src_master; | |
941 | dwc->dst_master = dws->dst_master; | |
942 | ||
943 | return true; | |
944 | } | |
945 | EXPORT_SYMBOL_GPL(dw_dma_filter); | |
946 | ||
327e6970 VK |
947 | /* |
948 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
949 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
950 | * | |
951 | * NOTE: burst size 2 is not supported by controller. | |
952 | * | |
953 | * This can be done by finding least significant bit set: n & (n - 1) | |
954 | */ | |
955 | static inline void convert_burst(u32 *maxburst) | |
956 | { | |
957 | if (*maxburst > 1) | |
958 | *maxburst = fls(*maxburst) - 2; | |
959 | else | |
960 | *maxburst = 0; | |
961 | } | |
962 | ||
a4b0d348 | 963 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
327e6970 VK |
964 | { |
965 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
966 | ||
495aea4b AS |
967 | /* Check if chan will be configured for slave transfers */ |
968 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
969 | return -EINVAL; |
970 | ||
971 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 972 | dwc->direction = sconfig->direction; |
327e6970 VK |
973 | |
974 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
975 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
a4b0d348 | 980 | static int dwc_pause(struct dma_chan *chan) |
21fe3c52 | 981 | { |
a4b0d348 MR |
982 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
983 | unsigned long flags; | |
984 | unsigned int count = 20; /* timeout iterations */ | |
985 | u32 cfglo; | |
986 | ||
987 | spin_lock_irqsave(&dwc->lock, flags); | |
21fe3c52 | 988 | |
a4b0d348 | 989 | cfglo = channel_readl(dwc, CFG_LO); |
21fe3c52 | 990 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
123b69ab AS |
991 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
992 | udelay(2); | |
21fe3c52 AS |
993 | |
994 | dwc->paused = true; | |
a4b0d348 MR |
995 | |
996 | spin_unlock_irqrestore(&dwc->lock, flags); | |
997 | ||
998 | return 0; | |
21fe3c52 AS |
999 | } |
1000 | ||
1001 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
1002 | { | |
1003 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1004 | ||
1005 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1006 | ||
1007 | dwc->paused = false; | |
1008 | } | |
1009 | ||
a4b0d348 | 1010 | static int dwc_resume(struct dma_chan *chan) |
3bfb1d20 HS |
1011 | { |
1012 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
69cea5a0 | 1013 | unsigned long flags; |
3bfb1d20 | 1014 | |
a4b0d348 MR |
1015 | if (!dwc->paused) |
1016 | return 0; | |
c3635c78 | 1017 | |
a4b0d348 | 1018 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1019 | |
a4b0d348 | 1020 | dwc_chan_resume(dwc); |
3bfb1d20 | 1021 | |
a4b0d348 | 1022 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1023 | |
a4b0d348 MR |
1024 | return 0; |
1025 | } | |
3bfb1d20 | 1026 | |
a4b0d348 MR |
1027 | static int dwc_terminate_all(struct dma_chan *chan) |
1028 | { | |
1029 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1030 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1031 | struct dw_desc *desc, *_desc; | |
1032 | unsigned long flags; | |
1033 | LIST_HEAD(list); | |
3bfb1d20 | 1034 | |
a4b0d348 | 1035 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b | 1036 | |
a4b0d348 | 1037 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
fed2574b | 1038 | |
a4b0d348 | 1039 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1040 | |
a4b0d348 | 1041 | dwc_chan_resume(dwc); |
a7c57cf7 | 1042 | |
a4b0d348 MR |
1043 | /* active_list entries will end up before queued entries */ |
1044 | list_splice_init(&dwc->queue, &list); | |
1045 | list_splice_init(&dwc->active_list, &list); | |
a7c57cf7 | 1046 | |
a4b0d348 | 1047 | spin_unlock_irqrestore(&dwc->lock, flags); |
a7c57cf7 | 1048 | |
a4b0d348 MR |
1049 | /* Flush all pending and queued descriptors */ |
1050 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1051 | dwc_descriptor_complete(dwc, desc, false); | |
c3635c78 LW |
1052 | |
1053 | return 0; | |
3bfb1d20 HS |
1054 | } |
1055 | ||
4702d524 AS |
1056 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1057 | { | |
1058 | unsigned long flags; | |
1059 | u32 residue; | |
1060 | ||
1061 | spin_lock_irqsave(&dwc->lock, flags); | |
1062 | ||
1063 | residue = dwc->residue; | |
1064 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1065 | residue -= dwc_get_sent(dwc); | |
1066 | ||
1067 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1068 | return residue; | |
1069 | } | |
1070 | ||
3bfb1d20 | 1071 | static enum dma_status |
07934481 LW |
1072 | dwc_tx_status(struct dma_chan *chan, |
1073 | dma_cookie_t cookie, | |
1074 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1075 | { |
1076 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1077 | enum dma_status ret; |
3bfb1d20 | 1078 | |
96a2af41 | 1079 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1080 | if (ret == DMA_COMPLETE) |
12381dc0 | 1081 | return ret; |
3bfb1d20 | 1082 | |
12381dc0 | 1083 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1084 | |
12381dc0 | 1085 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1086 | if (ret != DMA_COMPLETE) |
4702d524 | 1087 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1088 | |
effd5cf6 | 1089 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1090 | return DMA_PAUSED; |
3bfb1d20 HS |
1091 | |
1092 | return ret; | |
1093 | } | |
1094 | ||
1095 | static void dwc_issue_pending(struct dma_chan *chan) | |
1096 | { | |
1097 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 1098 | unsigned long flags; |
3bfb1d20 | 1099 | |
dd8ecfca AS |
1100 | spin_lock_irqsave(&dwc->lock, flags); |
1101 | if (list_empty(&dwc->active_list)) | |
1102 | dwc_dostart_first_queued(dwc); | |
1103 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
1104 | } |
1105 | ||
99d9bf4e AS |
1106 | /*----------------------------------------------------------------------*/ |
1107 | ||
1108 | static void dw_dma_off(struct dw_dma *dw) | |
1109 | { | |
1110 | int i; | |
1111 | ||
1112 | dma_writel(dw, CFG, 0); | |
1113 | ||
1114 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 1115 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
99d9bf4e AS |
1116 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1117 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1118 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1119 | ||
1120 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1121 | cpu_relax(); | |
1122 | ||
1123 | for (i = 0; i < dw->dma.chancnt; i++) | |
1124 | dw->chan[i].initialized = false; | |
1125 | } | |
1126 | ||
1127 | static void dw_dma_on(struct dw_dma *dw) | |
1128 | { | |
1129 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1130 | } | |
1131 | ||
aa1e6f1a | 1132 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1133 | { |
1134 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1135 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1136 | struct dw_desc *desc; | |
3bfb1d20 | 1137 | int i; |
69cea5a0 | 1138 | unsigned long flags; |
3bfb1d20 | 1139 | |
2e4c364e | 1140 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1141 | |
3bfb1d20 HS |
1142 | /* ASSERT: channel is idle */ |
1143 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1144 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1145 | return -EIO; |
1146 | } | |
1147 | ||
d3ee98cd | 1148 | dma_cookie_init(chan); |
3bfb1d20 | 1149 | |
3bfb1d20 HS |
1150 | /* |
1151 | * NOTE: some controllers may have additional features that we | |
1152 | * need to initialize here, like "scatter-gather" (which | |
1153 | * doesn't mean what you think it means), and status writeback. | |
1154 | */ | |
1155 | ||
3fe6409c AS |
1156 | /* |
1157 | * We need controller-specific data to set up slave transfers. | |
1158 | */ | |
1159 | if (chan->private && !dw_dma_filter(chan, chan->private)) { | |
1160 | dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | ||
99d9bf4e AS |
1164 | /* Enable controller here if needed */ |
1165 | if (!dw->in_use) | |
1166 | dw_dma_on(dw); | |
1167 | dw->in_use |= dwc->mask; | |
1168 | ||
69cea5a0 | 1169 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1170 | i = dwc->descs_allocated; |
1171 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1172 | dma_addr_t phys; |
1173 | ||
69cea5a0 | 1174 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1175 | |
f8122a82 | 1176 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1177 | if (!desc) |
1178 | goto err_desc_alloc; | |
3bfb1d20 | 1179 | |
f8122a82 | 1180 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1181 | |
e0bd0f8c | 1182 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1183 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1184 | desc->txd.tx_submit = dwc_tx_submit; | |
1185 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1186 | desc->txd.phys = phys; |
cbd65312 | 1187 | |
3bfb1d20 HS |
1188 | dwc_desc_put(dwc, desc); |
1189 | ||
69cea5a0 | 1190 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1191 | i = ++dwc->descs_allocated; |
1192 | } | |
1193 | ||
69cea5a0 | 1194 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1195 | |
2e4c364e | 1196 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1197 | |
cbd65312 AS |
1198 | return i; |
1199 | ||
1200 | err_desc_alloc: | |
cbd65312 AS |
1201 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1202 | ||
3bfb1d20 HS |
1203 | return i; |
1204 | } | |
1205 | ||
1206 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1207 | { | |
1208 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1209 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1210 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1211 | unsigned long flags; |
3bfb1d20 HS |
1212 | LIST_HEAD(list); |
1213 | ||
2e4c364e | 1214 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1215 | dwc->descs_allocated); |
1216 | ||
1217 | /* ASSERT: channel is idle */ | |
1218 | BUG_ON(!list_empty(&dwc->active_list)); | |
1219 | BUG_ON(!list_empty(&dwc->queue)); | |
1220 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1221 | ||
69cea5a0 | 1222 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1223 | list_splice_init(&dwc->free_list, &list); |
1224 | dwc->descs_allocated = 0; | |
3fe6409c AS |
1225 | |
1226 | /* Clear custom channel configuration */ | |
1227 | dwc->src_id = 0; | |
1228 | dwc->dst_id = 0; | |
1229 | ||
1230 | dwc->src_master = 0; | |
1231 | dwc->dst_master = 0; | |
1232 | ||
61e183f8 | 1233 | dwc->initialized = false; |
3bfb1d20 HS |
1234 | |
1235 | /* Disable interrupts */ | |
1236 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
2895b2ca | 1237 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
3bfb1d20 HS |
1238 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1239 | ||
69cea5a0 | 1240 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1241 | |
99d9bf4e AS |
1242 | /* Disable controller in case it was a last user */ |
1243 | dw->in_use &= ~dwc->mask; | |
1244 | if (!dw->in_use) | |
1245 | dw_dma_off(dw); | |
1246 | ||
3bfb1d20 | 1247 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { |
41d5e59c | 1248 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1249 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1250 | } |
1251 | ||
2e4c364e | 1252 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1253 | } |
1254 | ||
d9de4519 HCE |
1255 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1256 | ||
1257 | /** | |
1258 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1259 | * @chan: the DMA channel to start | |
1260 | * | |
1261 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1262 | * -errno on failure. | |
1263 | */ | |
1264 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1265 | { | |
1266 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
ee1cdcda | 1267 | struct dw_dma *dw = to_dw_dma(chan->device); |
69cea5a0 | 1268 | unsigned long flags; |
d9de4519 HCE |
1269 | |
1270 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1271 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1272 | return -ENODEV; | |
1273 | } | |
1274 | ||
69cea5a0 | 1275 | spin_lock_irqsave(&dwc->lock, flags); |
ee1cdcda AS |
1276 | |
1277 | /* Enable interrupts to perform cyclic transfer */ | |
1278 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
1279 | ||
df3bb8a0 | 1280 | dwc_dostart(dwc, dwc->cdesc->desc[0]); |
ee1cdcda | 1281 | |
69cea5a0 | 1282 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1283 | |
1284 | return 0; | |
1285 | } | |
1286 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1287 | ||
1288 | /** | |
1289 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1290 | * @chan: the DMA channel to stop | |
1291 | * | |
1292 | * Must be called with soft interrupts disabled. | |
1293 | */ | |
1294 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1295 | { | |
1296 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1297 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1298 | unsigned long flags; |
d9de4519 | 1299 | |
69cea5a0 | 1300 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1301 | |
3f936207 | 1302 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1303 | |
69cea5a0 | 1304 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1305 | } |
1306 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1307 | ||
1308 | /** | |
1309 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1310 | * @chan: the DMA channel to prepare | |
1311 | * @buf_addr: physical DMA address where the buffer starts | |
1312 | * @buf_len: total number of bytes for the entire buffer | |
1313 | * @period_len: number of bytes for each period | |
1314 | * @direction: transfer direction, to or from device | |
1315 | * | |
1316 | * Must be called before trying to start the transfer. Returns a valid struct | |
1317 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1318 | */ | |
1319 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1320 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1321 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1322 | { |
1323 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1324 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1325 | struct dw_cyclic_desc *cdesc; |
1326 | struct dw_cyclic_desc *retval = NULL; | |
1327 | struct dw_desc *desc; | |
1328 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1329 | unsigned long was_cyclic; |
1330 | unsigned int reg_width; | |
1331 | unsigned int periods; | |
1332 | unsigned int i; | |
69cea5a0 | 1333 | unsigned long flags; |
d9de4519 | 1334 | |
69cea5a0 | 1335 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1336 | if (dwc->nollp) { |
1337 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1338 | dev_dbg(chan2dev(&dwc->chan), | |
1339 | "channel doesn't support LLP transfers\n"); | |
1340 | return ERR_PTR(-EINVAL); | |
1341 | } | |
1342 | ||
d9de4519 | 1343 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1344 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1345 | dev_dbg(chan2dev(&dwc->chan), |
1346 | "queue and/or active list are not empty\n"); | |
1347 | return ERR_PTR(-EBUSY); | |
1348 | } | |
1349 | ||
1350 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1351 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1352 | if (was_cyclic) { |
1353 | dev_dbg(chan2dev(&dwc->chan), | |
1354 | "channel already prepared for cyclic DMA\n"); | |
1355 | return ERR_PTR(-EBUSY); | |
1356 | } | |
1357 | ||
1358 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1359 | |
f44b92f4 AS |
1360 | if (unlikely(!is_slave_direction(direction))) |
1361 | goto out_err; | |
1362 | ||
0fdb567f AS |
1363 | dwc->direction = direction; |
1364 | ||
327e6970 VK |
1365 | if (direction == DMA_MEM_TO_DEV) |
1366 | reg_width = __ffs(sconfig->dst_addr_width); | |
1367 | else | |
1368 | reg_width = __ffs(sconfig->src_addr_width); | |
1369 | ||
d9de4519 HCE |
1370 | periods = buf_len / period_len; |
1371 | ||
1372 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1373 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1374 | goto out_err; |
1375 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1376 | goto out_err; | |
1377 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1378 | goto out_err; | |
d9de4519 HCE |
1379 | |
1380 | retval = ERR_PTR(-ENOMEM); | |
1381 | ||
1382 | if (periods > NR_DESCS_PER_CHANNEL) | |
1383 | goto out_err; | |
1384 | ||
1385 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1386 | if (!cdesc) | |
1387 | goto out_err; | |
1388 | ||
1389 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1390 | if (!cdesc->desc) | |
1391 | goto out_err_alloc; | |
1392 | ||
1393 | for (i = 0; i < periods; i++) { | |
1394 | desc = dwc_desc_get(dwc); | |
1395 | if (!desc) | |
1396 | goto out_err_desc_get; | |
1397 | ||
1398 | switch (direction) { | |
db8196df | 1399 | case DMA_MEM_TO_DEV: |
327e6970 | 1400 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1401 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1402 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1403 | | DWC_CTLL_DST_WIDTH(reg_width) |
1404 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1405 | | DWC_CTLL_DST_FIX | |
1406 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1407 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1408 | |
1409 | desc->lli.ctllo |= sconfig->device_fc ? | |
1410 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1411 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1412 | ||
d9de4519 | 1413 | break; |
db8196df | 1414 | case DMA_DEV_TO_MEM: |
d9de4519 | 1415 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1416 | desc->lli.sar = sconfig->src_addr; |
1417 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1418 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1419 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1420 | | DWC_CTLL_DST_INC | |
1421 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1422 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1423 | |
1424 | desc->lli.ctllo |= sconfig->device_fc ? | |
1425 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1426 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1427 | ||
d9de4519 HCE |
1428 | break; |
1429 | default: | |
1430 | break; | |
1431 | } | |
1432 | ||
1433 | desc->lli.ctlhi = (period_len >> reg_width); | |
1434 | cdesc->desc[i] = desc; | |
1435 | ||
f8122a82 | 1436 | if (last) |
d9de4519 | 1437 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1438 | |
1439 | last = desc; | |
1440 | } | |
1441 | ||
75c61225 | 1442 | /* Let's make a cyclic list */ |
d9de4519 | 1443 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1444 | |
5a87f0e6 AS |
1445 | dev_dbg(chan2dev(&dwc->chan), |
1446 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1447 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1448 | |
1449 | cdesc->periods = periods; | |
1450 | dwc->cdesc = cdesc; | |
1451 | ||
1452 | return cdesc; | |
1453 | ||
1454 | out_err_desc_get: | |
1455 | while (i--) | |
1456 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1457 | out_err_alloc: | |
1458 | kfree(cdesc); | |
1459 | out_err: | |
1460 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1461 | return (struct dw_cyclic_desc *)retval; | |
1462 | } | |
1463 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1464 | ||
1465 | /** | |
1466 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1467 | * @chan: the DMA channel to free | |
1468 | */ | |
1469 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1470 | { | |
1471 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1472 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1473 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1474 | int i; | |
69cea5a0 | 1475 | unsigned long flags; |
d9de4519 | 1476 | |
2e4c364e | 1477 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1478 | |
1479 | if (!cdesc) | |
1480 | return; | |
1481 | ||
69cea5a0 | 1482 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1483 | |
3f936207 | 1484 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1485 | |
2895b2ca | 1486 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
1487 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1488 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1489 | ||
69cea5a0 | 1490 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1491 | |
1492 | for (i = 0; i < cdesc->periods; i++) | |
1493 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1494 | ||
1495 | kfree(cdesc->desc); | |
1496 | kfree(cdesc); | |
1497 | ||
1498 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1499 | } | |
1500 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1501 | ||
3bfb1d20 HS |
1502 | /*----------------------------------------------------------------------*/ |
1503 | ||
9cade1a4 | 1504 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1505 | { |
3bfb1d20 | 1506 | struct dw_dma *dw; |
30cb2639 | 1507 | bool autocfg = false; |
482c67ea | 1508 | unsigned int dw_params; |
4a63a8b3 | 1509 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1510 | int err; |
1511 | int i; | |
1512 | ||
000871ce AS |
1513 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1514 | if (!dw) | |
1515 | return -ENOMEM; | |
1516 | ||
1517 | dw->regs = chip->regs; | |
1518 | chip->dw = dw; | |
1519 | ||
bb32baf7 AS |
1520 | pm_runtime_get_sync(chip->dev); |
1521 | ||
30cb2639 AS |
1522 | if (!pdata) { |
1523 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); | |
1524 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); | |
482c67ea | 1525 | |
30cb2639 AS |
1526 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
1527 | if (!autocfg) { | |
1528 | err = -EINVAL; | |
1529 | goto err_pdata; | |
1530 | } | |
123de543 | 1531 | |
9cade1a4 | 1532 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
8be4f523 AS |
1533 | if (!pdata) { |
1534 | err = -ENOMEM; | |
1535 | goto err_pdata; | |
1536 | } | |
123de543 | 1537 | |
30cb2639 AS |
1538 | /* Get hardware configuration parameters */ |
1539 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; | |
1540 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; | |
1541 | for (i = 0; i < pdata->nr_masters; i++) { | |
1542 | pdata->data_width[i] = | |
1543 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1544 | } | |
1545 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); | |
1546 | ||
123de543 AS |
1547 | /* Fill platform data with the default values */ |
1548 | pdata->is_private = true; | |
df5c7386 | 1549 | pdata->is_memcpy = true; |
123de543 AS |
1550 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
1551 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
30cb2639 | 1552 | } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
8be4f523 AS |
1553 | err = -EINVAL; |
1554 | goto err_pdata; | |
1555 | } | |
123de543 | 1556 | |
30cb2639 | 1557 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
000871ce | 1558 | GFP_KERNEL); |
8be4f523 AS |
1559 | if (!dw->chan) { |
1560 | err = -ENOMEM; | |
1561 | goto err_pdata; | |
1562 | } | |
3bfb1d20 | 1563 | |
75c61225 | 1564 | /* Get hardware configuration parameters */ |
30cb2639 AS |
1565 | dw->nr_masters = pdata->nr_masters; |
1566 | for (i = 0; i < dw->nr_masters; i++) | |
1567 | dw->data_width[i] = pdata->data_width[i]; | |
a0982004 | 1568 | |
11f932ec | 1569 | /* Calculate all channel mask before DMA setup */ |
30cb2639 | 1570 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
11f932ec | 1571 | |
75c61225 | 1572 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1573 | dw_dma_off(dw); |
1574 | ||
75c61225 | 1575 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1576 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1577 | sizeof(struct dw_desc), 4, 0); |
1578 | if (!dw->desc_pool) { | |
9cade1a4 | 1579 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1580 | err = -ENOMEM; |
1581 | goto err_pdata; | |
f8122a82 AS |
1582 | } |
1583 | ||
3bfb1d20 HS |
1584 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1585 | ||
97977f75 AS |
1586 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1587 | "dw_dmac", dw); | |
1588 | if (err) | |
8be4f523 | 1589 | goto err_pdata; |
97977f75 | 1590 | |
3bfb1d20 | 1591 | INIT_LIST_HEAD(&dw->dma.channels); |
30cb2639 | 1592 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1593 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1594 | ||
1595 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1596 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1597 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1598 | list_add_tail(&dwc->chan.device_node, | |
1599 | &dw->dma.channels); | |
1600 | else | |
1601 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1602 | |
93317e8e VK |
1603 | /* 7 is highest priority & 0 is lowest. */ |
1604 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
30cb2639 | 1605 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1606 | else |
1607 | dwc->priority = i; | |
1608 | ||
3bfb1d20 HS |
1609 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1610 | spin_lock_init(&dwc->lock); | |
1611 | dwc->mask = 1 << i; | |
1612 | ||
1613 | INIT_LIST_HEAD(&dwc->active_list); | |
1614 | INIT_LIST_HEAD(&dwc->queue); | |
1615 | INIT_LIST_HEAD(&dwc->free_list); | |
1616 | ||
1617 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1618 | |
0fdb567f | 1619 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1620 | |
75c61225 | 1621 | /* Hardware configuration */ |
fed2574b AS |
1622 | if (autocfg) { |
1623 | unsigned int dwc_params; | |
6bea0f6d | 1624 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
9cade1a4 | 1625 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1626 | |
9cade1a4 | 1627 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1628 | |
9cade1a4 AS |
1629 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1630 | dwc_params); | |
985a6c7d | 1631 | |
1d566f11 AS |
1632 | /* |
1633 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1634 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1635 | * up to 0x0a for 4095. |
1636 | */ | |
4a63a8b3 AS |
1637 | dwc->block_size = |
1638 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1639 | dwc->nollp = |
1640 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1641 | } else { | |
4a63a8b3 | 1642 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1643 | |
1644 | /* Check if channel supports multi block transfer */ | |
1645 | channel_writel(dwc, LLP, 0xfffffffc); | |
1646 | dwc->nollp = | |
1647 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1648 | channel_writel(dwc, LLP, 0); | |
1649 | } | |
3bfb1d20 HS |
1650 | } |
1651 | ||
11f932ec | 1652 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1653 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1654 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1655 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1656 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1657 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1658 | ||
df5c7386 | 1659 | /* Set capabilities */ |
3bfb1d20 | 1660 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
95ea759e JI |
1661 | if (pdata->is_private) |
1662 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
df5c7386 AS |
1663 | if (pdata->is_memcpy) |
1664 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1665 | ||
9cade1a4 | 1666 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1667 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1668 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1669 | ||
1670 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
3bfb1d20 | 1671 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
029a40e9 | 1672 | |
a4b0d348 MR |
1673 | dw->dma.device_config = dwc_config; |
1674 | dw->dma.device_pause = dwc_pause; | |
1675 | dw->dma.device_resume = dwc_resume; | |
1676 | dw->dma.device_terminate_all = dwc_terminate_all; | |
3bfb1d20 | 1677 | |
07934481 | 1678 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1679 | dw->dma.device_issue_pending = dwc_issue_pending; |
1680 | ||
029a40e9 AS |
1681 | /* DMA capabilities */ |
1682 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; | |
1683 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; | |
1684 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | | |
1685 | BIT(DMA_MEM_TO_MEM); | |
1686 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1687 | ||
1222934e AS |
1688 | err = dma_async_device_register(&dw->dma); |
1689 | if (err) | |
1690 | goto err_dma_register; | |
1691 | ||
9cade1a4 | 1692 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
30cb2639 | 1693 | pdata->nr_channels); |
3bfb1d20 | 1694 | |
bb32baf7 AS |
1695 | pm_runtime_put_sync_suspend(chip->dev); |
1696 | ||
3bfb1d20 | 1697 | return 0; |
8be4f523 | 1698 | |
1222934e AS |
1699 | err_dma_register: |
1700 | free_irq(chip->irq, dw); | |
8be4f523 | 1701 | err_pdata: |
bb32baf7 | 1702 | pm_runtime_put_sync_suspend(chip->dev); |
8be4f523 | 1703 | return err; |
3bfb1d20 | 1704 | } |
9cade1a4 | 1705 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1706 | |
9cade1a4 | 1707 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1708 | { |
9cade1a4 | 1709 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1710 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 | 1711 | |
bb32baf7 AS |
1712 | pm_runtime_get_sync(chip->dev); |
1713 | ||
3bfb1d20 HS |
1714 | dw_dma_off(dw); |
1715 | dma_async_device_unregister(&dw->dma); | |
1716 | ||
97977f75 | 1717 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1718 | tasklet_kill(&dw->tasklet); |
1719 | ||
1720 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1721 | chan.device_node) { | |
1722 | list_del(&dwc->chan.device_node); | |
1723 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1724 | } | |
1725 | ||
bb32baf7 | 1726 | pm_runtime_put_sync_suspend(chip->dev); |
3bfb1d20 HS |
1727 | return 0; |
1728 | } | |
9cade1a4 | 1729 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1730 | |
2540f74b | 1731 | int dw_dma_disable(struct dw_dma_chip *chip) |
3bfb1d20 | 1732 | { |
9cade1a4 | 1733 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1734 | |
6168d567 | 1735 | dw_dma_off(dw); |
3bfb1d20 HS |
1736 | return 0; |
1737 | } | |
2540f74b | 1738 | EXPORT_SYMBOL_GPL(dw_dma_disable); |
3bfb1d20 | 1739 | |
2540f74b | 1740 | int dw_dma_enable(struct dw_dma_chip *chip) |
3bfb1d20 | 1741 | { |
9cade1a4 | 1742 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1743 | |
7a83c045 | 1744 | dw_dma_on(dw); |
3bfb1d20 | 1745 | return 0; |
3bfb1d20 | 1746 | } |
2540f74b | 1747 | EXPORT_SYMBOL_GPL(dw_dma_enable); |
3bfb1d20 HS |
1748 | |
1749 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1750 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1751 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
da89947b | 1752 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |