Commit | Line | Data |
---|---|---|
61a76496 AS |
1 | # |
2 | # DMA engine configuration for dw | |
3 | # | |
4 | ||
9cade1a4 | 5 | config DW_DMAC_CORE |
61a76496 AS |
6 | tristate "Synopsys DesignWare AHB DMA support" |
7 | depends on GENERIC_HARDIRQS | |
8 | select DMA_ENGINE | |
9cade1a4 AS |
9 | |
10 | config DW_DMAC | |
11 | tristate "Synopsys DesignWare AHB DMA platform driver" | |
12 | select DW_DMAC_CORE | |
61a76496 AS |
13 | default y if CPU_AT32AP7000 |
14 | help | |
15 | Support the Synopsys DesignWare AHB DMA controller. This | |
16 | can be integrated in chips such as the Atmel AT32ap7000. | |
17 | ||
18 | config DW_DMAC_BIG_ENDIAN_IO | |
19 | bool "Use big endian I/O register access" | |
20 | default y if AVR32 | |
9cade1a4 | 21 | depends on DW_DMAC_CORE |
61a76496 AS |
22 | help |
23 | Say yes here to use big endian I/O access when reading and writing | |
24 | to the DMA controller registers. This is needed on some platforms, | |
25 | like the Atmel AVR32 architecture. | |
26 | ||
27 | If unsure, use the default setting. |