Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
4a776f0a HS |
2 | /* |
3 | * DMA Engine test module | |
4 | * | |
5 | * Copyright (C) 2007 Atmel Corporation | |
851b7e16 | 6 | * Copyright (C) 2013 Intel Corporation |
4a776f0a | 7 | */ |
872f05c6 DW |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
9 | ||
ef759e4a | 10 | #include <linux/err.h> |
4a776f0a | 11 | #include <linux/delay.h> |
b7f080cf | 12 | #include <linux/dma-mapping.h> |
4a776f0a | 13 | #include <linux/dmaengine.h> |
981ed70d | 14 | #include <linux/freezer.h> |
4a776f0a HS |
15 | #include <linux/init.h> |
16 | #include <linux/kthread.h> | |
0881e7bd | 17 | #include <linux/sched/task.h> |
4a776f0a HS |
18 | #include <linux/module.h> |
19 | #include <linux/moduleparam.h> | |
20 | #include <linux/random.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
4a776f0a HS |
22 | #include <linux/wait.h> |
23 | ||
24 | static unsigned int test_buf_size = 16384; | |
a6c268d0 | 25 | module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
26 | MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); |
27 | ||
a85159fe | 28 | static char test_device[32]; |
a6c268d0 AS |
29 | module_param_string(device, test_device, sizeof(test_device), |
30 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
31 | MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); |
32 | ||
33 | static unsigned int threads_per_chan = 1; | |
a6c268d0 | 34 | module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
35 | MODULE_PARM_DESC(threads_per_chan, |
36 | "Number of threads to start per channel (default: 1)"); | |
37 | ||
38 | static unsigned int max_channels; | |
a6c268d0 | 39 | module_param(max_channels, uint, S_IRUGO | S_IWUSR); |
33df8ca0 | 40 | MODULE_PARM_DESC(max_channels, |
4a776f0a HS |
41 | "Maximum number of channels to use (default: all)"); |
42 | ||
0a2ff57d | 43 | static unsigned int iterations; |
a6c268d0 | 44 | module_param(iterations, uint, S_IRUGO | S_IWUSR); |
0a2ff57d NF |
45 | MODULE_PARM_DESC(iterations, |
46 | "Iterations before stopping test (default: infinite)"); | |
47 | ||
d8646724 | 48 | static unsigned int dmatest; |
a0d4cb44 KA |
49 | module_param(dmatest, uint, S_IRUGO | S_IWUSR); |
50 | MODULE_PARM_DESC(dmatest, | |
c678fa66 | 51 | "dmatest 0-memcpy 1-memset (default: 0)"); |
a0d4cb44 | 52 | |
b54d5cb9 | 53 | static unsigned int xor_sources = 3; |
a6c268d0 | 54 | module_param(xor_sources, uint, S_IRUGO | S_IWUSR); |
b54d5cb9 DW |
55 | MODULE_PARM_DESC(xor_sources, |
56 | "Number of xor source buffers (default: 3)"); | |
57 | ||
58691d64 | 58 | static unsigned int pq_sources = 3; |
a6c268d0 | 59 | module_param(pq_sources, uint, S_IRUGO | S_IWUSR); |
58691d64 DW |
60 | MODULE_PARM_DESC(pq_sources, |
61 | "Number of p+q source buffers (default: 3)"); | |
62 | ||
d42efe6b | 63 | static int timeout = 3000; |
35c5fc02 | 64 | module_param(timeout, int, S_IRUGO | S_IWUSR); |
85ee7a1d | 65 | MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " |
85f78cec | 66 | "Pass -1 for infinite timeout"); |
d42efe6b | 67 | |
e3b9c347 DW |
68 | static bool noverify; |
69 | module_param(noverify, bool, S_IRUGO | S_IWUSR); | |
2e67a087 YS |
70 | MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)"); |
71 | ||
72 | static bool norandom; | |
73 | module_param(norandom, bool, 0644); | |
74 | MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)"); | |
4a776f0a | 75 | |
50137a7d DW |
76 | static bool verbose; |
77 | module_param(verbose, bool, S_IRUGO | S_IWUSR); | |
78 | MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); | |
4a776f0a | 79 | |
a875abfa SA |
80 | static int alignment = -1; |
81 | module_param(alignment, int, 0644); | |
82 | MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))"); | |
83 | ||
13396a13 SA |
84 | static unsigned int transfer_size; |
85 | module_param(transfer_size, uint, 0644); | |
86 | MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))"); | |
87 | ||
7f2b7226 AS |
88 | static bool polled; |
89 | module_param(polled, bool, S_IRUGO | S_IWUSR); | |
90 | MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts"); | |
91 | ||
e03e93a9 | 92 | /** |
15b8a8ea | 93 | * struct dmatest_params - test parameters. |
e03e93a9 AS |
94 | * @buf_size: size of the memcpy test buffer |
95 | * @channel: bus ID of the channel to test | |
96 | * @device: bus ID of the DMA Engine to test | |
97 | * @threads_per_chan: number of threads to start per channel | |
98 | * @max_channels: maximum number of channels to use | |
99 | * @iterations: iterations before stopping test | |
100 | * @xor_sources: number of xor source buffers | |
101 | * @pq_sources: number of p+q source buffers | |
85f78cec | 102 | * @timeout: transfer timeout in msec, -1 for infinite timeout |
7f2b7226 AS |
103 | * @noverify: disable data verification |
104 | * @norandom: disable random offset setup | |
105 | * @alignment: custom data address alignment taken as 2^alignment | |
106 | * @transfer_size: custom transfer size in bytes | |
107 | * @polled: use polling for completion instead of interrupts | |
e03e93a9 | 108 | */ |
15b8a8ea | 109 | struct dmatest_params { |
e03e93a9 AS |
110 | unsigned int buf_size; |
111 | char channel[20]; | |
a85159fe | 112 | char device[32]; |
e03e93a9 AS |
113 | unsigned int threads_per_chan; |
114 | unsigned int max_channels; | |
115 | unsigned int iterations; | |
116 | unsigned int xor_sources; | |
117 | unsigned int pq_sources; | |
85f78cec | 118 | int timeout; |
e3b9c347 | 119 | bool noverify; |
2e67a087 | 120 | bool norandom; |
a875abfa | 121 | int alignment; |
13396a13 | 122 | unsigned int transfer_size; |
fb9816f9 | 123 | bool polled; |
15b8a8ea AS |
124 | }; |
125 | ||
126 | /** | |
127 | * struct dmatest_info - test information. | |
128 | * @params: test parameters | |
5332f8b1 AS |
129 | * @channels: channels under test |
130 | * @nr_channels: number of channels under test | |
851b7e16 | 131 | * @lock: access protection to the fields of this structure |
5332f8b1 | 132 | * @did_init: module has been initialized completely |
ce65d55f | 133 | * @last_error: test has faced configuration issues |
15b8a8ea | 134 | */ |
a310d037 | 135 | static struct dmatest_info { |
15b8a8ea AS |
136 | /* Test parameters */ |
137 | struct dmatest_params params; | |
838cc704 AS |
138 | |
139 | /* Internal state */ | |
140 | struct list_head channels; | |
141 | unsigned int nr_channels; | |
ce65d55f | 142 | int last_error; |
851b7e16 | 143 | struct mutex lock; |
a310d037 DW |
144 | bool did_init; |
145 | } test_info = { | |
146 | .channels = LIST_HEAD_INIT(test_info.channels), | |
147 | .lock = __MUTEX_INITIALIZER(test_info.lock), | |
148 | }; | |
851b7e16 | 149 | |
a310d037 DW |
150 | static int dmatest_run_set(const char *val, const struct kernel_param *kp); |
151 | static int dmatest_run_get(char *val, const struct kernel_param *kp); | |
9c27847d | 152 | static const struct kernel_param_ops run_ops = { |
a310d037 DW |
153 | .set = dmatest_run_set, |
154 | .get = dmatest_run_get, | |
e03e93a9 | 155 | }; |
a310d037 DW |
156 | static bool dmatest_run; |
157 | module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); | |
158 | MODULE_PARM_DESC(run, "Run the test (default: false)"); | |
e03e93a9 | 159 | |
d53513d5 SA |
160 | static int dmatest_chan_set(const char *val, const struct kernel_param *kp); |
161 | static int dmatest_chan_get(char *val, const struct kernel_param *kp); | |
162 | static const struct kernel_param_ops multi_chan_ops = { | |
163 | .set = dmatest_chan_set, | |
164 | .get = dmatest_chan_get, | |
165 | }; | |
166 | ||
167 | static char test_channel[20]; | |
168 | static struct kparam_string newchan_kps = { | |
169 | .string = test_channel, | |
170 | .maxlen = 20, | |
171 | }; | |
172 | module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644); | |
173 | MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); | |
174 | ||
175 | static int dmatest_test_list_get(char *val, const struct kernel_param *kp); | |
176 | static const struct kernel_param_ops test_list_ops = { | |
177 | .get = dmatest_test_list_get, | |
178 | }; | |
179 | module_param_cb(test_list, &test_list_ops, NULL, 0444); | |
180 | MODULE_PARM_DESC(test_list, "Print current test list"); | |
181 | ||
a310d037 DW |
182 | /* Maximum amount of mismatched bytes in buffer to print */ |
183 | #define MAX_ERROR_COUNT 32 | |
184 | ||
185 | /* | |
186 | * Initialization patterns. All bytes in the source buffer has bit 7 | |
187 | * set, all bytes in the destination buffer has bit 7 cleared. | |
188 | * | |
189 | * Bit 6 is set for all bytes which are to be copied by the DMA | |
190 | * engine. Bit 5 is set for all bytes which are to be overwritten by | |
191 | * the DMA engine. | |
192 | * | |
193 | * The remaining bits are the inverse of a counter which increments by | |
194 | * one for each byte address. | |
195 | */ | |
196 | #define PATTERN_SRC 0x80 | |
197 | #define PATTERN_DST 0x00 | |
198 | #define PATTERN_COPY 0x40 | |
199 | #define PATTERN_OVERWRITE 0x20 | |
200 | #define PATTERN_COUNT_MASK 0x1f | |
61b5f54d | 201 | #define PATTERN_MEMSET_IDX 0x01 |
851b7e16 | 202 | |
6138f967 SA |
203 | /* Fixed point arithmetic ops */ |
204 | #define FIXPT_SHIFT 8 | |
205 | #define FIXPNT_MASK 0xFF | |
206 | #define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT) | |
207 | #define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT) | |
208 | #define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT) | |
209 | ||
6f6a23a2 AW |
210 | /* poor man's completion - we want to use wait_event_freezable() on it */ |
211 | struct dmatest_done { | |
212 | bool done; | |
213 | wait_queue_head_t *wait; | |
214 | }; | |
215 | ||
361deb72 AA |
216 | struct dmatest_data { |
217 | u8 **raw; | |
218 | u8 **aligned; | |
219 | unsigned int cnt; | |
220 | unsigned int off; | |
221 | }; | |
222 | ||
a310d037 DW |
223 | struct dmatest_thread { |
224 | struct list_head node; | |
225 | struct dmatest_info *info; | |
226 | struct task_struct *task; | |
227 | struct dma_chan *chan; | |
361deb72 AA |
228 | struct dmatest_data src; |
229 | struct dmatest_data dst; | |
a310d037 | 230 | enum dma_transaction_type type; |
6f6a23a2 AW |
231 | wait_queue_head_t done_wait; |
232 | struct dmatest_done test_done; | |
a310d037 | 233 | bool done; |
d53513d5 | 234 | bool pending; |
a310d037 | 235 | }; |
95019c8c | 236 | |
a310d037 DW |
237 | struct dmatest_chan { |
238 | struct list_head node; | |
239 | struct dma_chan *chan; | |
240 | struct list_head threads; | |
e03e93a9 AS |
241 | }; |
242 | ||
2d88ce76 DW |
243 | static DECLARE_WAIT_QUEUE_HEAD(thread_wait); |
244 | static bool wait; | |
245 | ||
246 | static bool is_threaded_test_run(struct dmatest_info *info) | |
247 | { | |
248 | struct dmatest_chan *dtc; | |
249 | ||
250 | list_for_each_entry(dtc, &info->channels, node) { | |
251 | struct dmatest_thread *thread; | |
252 | ||
253 | list_for_each_entry(thread, &dtc->threads, node) { | |
aa72f1d2 | 254 | if (!thread->done && !thread->pending) |
2d88ce76 DW |
255 | return true; |
256 | } | |
257 | } | |
258 | ||
259 | return false; | |
260 | } | |
261 | ||
d53513d5 SA |
262 | static bool is_threaded_test_pending(struct dmatest_info *info) |
263 | { | |
264 | struct dmatest_chan *dtc; | |
265 | ||
266 | list_for_each_entry(dtc, &info->channels, node) { | |
267 | struct dmatest_thread *thread; | |
268 | ||
269 | list_for_each_entry(thread, &dtc->threads, node) { | |
270 | if (thread->pending) | |
271 | return true; | |
272 | } | |
273 | } | |
274 | ||
275 | return false; | |
276 | } | |
277 | ||
2d88ce76 DW |
278 | static int dmatest_wait_get(char *val, const struct kernel_param *kp) |
279 | { | |
280 | struct dmatest_info *info = &test_info; | |
281 | struct dmatest_params *params = &info->params; | |
282 | ||
283 | if (params->iterations) | |
284 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
285 | wait = true; | |
286 | return param_get_bool(val, kp); | |
287 | } | |
288 | ||
9c27847d | 289 | static const struct kernel_param_ops wait_ops = { |
2d88ce76 DW |
290 | .get = dmatest_wait_get, |
291 | .set = param_set_bool, | |
292 | }; | |
293 | module_param_cb(wait, &wait_ops, &wait, S_IRUGO); | |
294 | MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); | |
e03e93a9 | 295 | |
15b8a8ea | 296 | static bool dmatest_match_channel(struct dmatest_params *params, |
e03e93a9 | 297 | struct dma_chan *chan) |
4a776f0a | 298 | { |
15b8a8ea | 299 | if (params->channel[0] == '\0') |
4a776f0a | 300 | return true; |
15b8a8ea | 301 | return strcmp(dma_chan_name(chan), params->channel) == 0; |
4a776f0a HS |
302 | } |
303 | ||
15b8a8ea | 304 | static bool dmatest_match_device(struct dmatest_params *params, |
e03e93a9 | 305 | struct dma_device *device) |
4a776f0a | 306 | { |
15b8a8ea | 307 | if (params->device[0] == '\0') |
4a776f0a | 308 | return true; |
15b8a8ea | 309 | return strcmp(dev_name(device->dev), params->device) == 0; |
4a776f0a HS |
310 | } |
311 | ||
312 | static unsigned long dmatest_random(void) | |
313 | { | |
314 | unsigned long buf; | |
315 | ||
be9fa5a4 | 316 | prandom_bytes(&buf, sizeof(buf)); |
4a776f0a HS |
317 | return buf; |
318 | } | |
319 | ||
61b5f54d SK |
320 | static inline u8 gen_inv_idx(u8 index, bool is_memset) |
321 | { | |
322 | u8 val = is_memset ? PATTERN_MEMSET_IDX : index; | |
323 | ||
324 | return ~val & PATTERN_COUNT_MASK; | |
325 | } | |
326 | ||
327 | static inline u8 gen_src_value(u8 index, bool is_memset) | |
328 | { | |
329 | return PATTERN_SRC | gen_inv_idx(index, is_memset); | |
330 | } | |
331 | ||
332 | static inline u8 gen_dst_value(u8 index, bool is_memset) | |
333 | { | |
334 | return PATTERN_DST | gen_inv_idx(index, is_memset); | |
335 | } | |
336 | ||
e03e93a9 | 337 | static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, |
61b5f54d | 338 | unsigned int buf_size, bool is_memset) |
4a776f0a HS |
339 | { |
340 | unsigned int i; | |
b54d5cb9 DW |
341 | u8 *buf; |
342 | ||
343 | for (; (buf = *bufs); bufs++) { | |
344 | for (i = 0; i < start; i++) | |
61b5f54d | 345 | buf[i] = gen_src_value(i, is_memset); |
b54d5cb9 | 346 | for ( ; i < start + len; i++) |
61b5f54d | 347 | buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY; |
e03e93a9 | 348 | for ( ; i < buf_size; i++) |
61b5f54d | 349 | buf[i] = gen_src_value(i, is_memset); |
b54d5cb9 DW |
350 | buf++; |
351 | } | |
4a776f0a HS |
352 | } |
353 | ||
e03e93a9 | 354 | static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, |
61b5f54d | 355 | unsigned int buf_size, bool is_memset) |
4a776f0a HS |
356 | { |
357 | unsigned int i; | |
b54d5cb9 DW |
358 | u8 *buf; |
359 | ||
360 | for (; (buf = *bufs); bufs++) { | |
361 | for (i = 0; i < start; i++) | |
61b5f54d | 362 | buf[i] = gen_dst_value(i, is_memset); |
b54d5cb9 | 363 | for ( ; i < start + len; i++) |
61b5f54d SK |
364 | buf[i] = gen_dst_value(i, is_memset) | |
365 | PATTERN_OVERWRITE; | |
e03e93a9 | 366 | for ( ; i < buf_size; i++) |
61b5f54d | 367 | buf[i] = gen_dst_value(i, is_memset); |
b54d5cb9 | 368 | } |
4a776f0a HS |
369 | } |
370 | ||
7b610178 | 371 | static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, |
61b5f54d | 372 | unsigned int counter, bool is_srcbuf, bool is_memset) |
7b610178 DW |
373 | { |
374 | u8 diff = actual ^ pattern; | |
61b5f54d | 375 | u8 expected = pattern | gen_inv_idx(counter, is_memset); |
7b610178 DW |
376 | const char *thread_name = current->comm; |
377 | ||
378 | if (is_srcbuf) | |
379 | pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", | |
380 | thread_name, index, expected, actual); | |
381 | else if ((pattern & PATTERN_COPY) | |
382 | && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) | |
383 | pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", | |
384 | thread_name, index, expected, actual); | |
385 | else if (diff & PATTERN_SRC) | |
386 | pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", | |
387 | thread_name, index, expected, actual); | |
388 | else | |
389 | pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", | |
390 | thread_name, index, expected, actual); | |
391 | } | |
392 | ||
393 | static unsigned int dmatest_verify(u8 **bufs, unsigned int start, | |
394 | unsigned int end, unsigned int counter, u8 pattern, | |
61b5f54d | 395 | bool is_srcbuf, bool is_memset) |
4a776f0a HS |
396 | { |
397 | unsigned int i; | |
398 | unsigned int error_count = 0; | |
399 | u8 actual; | |
b54d5cb9 DW |
400 | u8 expected; |
401 | u8 *buf; | |
402 | unsigned int counter_orig = counter; | |
403 | ||
404 | for (; (buf = *bufs); bufs++) { | |
405 | counter = counter_orig; | |
406 | for (i = start; i < end; i++) { | |
407 | actual = buf[i]; | |
61b5f54d | 408 | expected = pattern | gen_inv_idx(counter, is_memset); |
b54d5cb9 | 409 | if (actual != expected) { |
7b610178 DW |
410 | if (error_count < MAX_ERROR_COUNT) |
411 | dmatest_mismatch(actual, pattern, i, | |
61b5f54d SK |
412 | counter, is_srcbuf, |
413 | is_memset); | |
b54d5cb9 DW |
414 | error_count++; |
415 | } | |
416 | counter++; | |
4a776f0a | 417 | } |
4a776f0a HS |
418 | } |
419 | ||
74b5c07a | 420 | if (error_count > MAX_ERROR_COUNT) |
7b610178 | 421 | pr_warn("%s: %u errors suppressed\n", |
74b5c07a | 422 | current->comm, error_count - MAX_ERROR_COUNT); |
4a776f0a HS |
423 | |
424 | return error_count; | |
425 | } | |
426 | ||
adfa543e TH |
427 | |
428 | static void dmatest_callback(void *arg) | |
e44e0aa3 | 429 | { |
adfa543e | 430 | struct dmatest_done *done = arg; |
6f6a23a2 | 431 | struct dmatest_thread *thread = |
66b3bd23 | 432 | container_of(done, struct dmatest_thread, test_done); |
6f6a23a2 AW |
433 | if (!thread->done) { |
434 | done->done = true; | |
435 | wake_up_all(done->wait); | |
436 | } else { | |
437 | /* | |
438 | * If thread->done, it means that this callback occurred | |
439 | * after the parent thread has cleaned up. This can | |
440 | * happen in the case that driver doesn't implement | |
441 | * the terminate_all() functionality and a dma operation | |
442 | * did not occur within the timeout period | |
443 | */ | |
444 | WARN(1, "dmatest: Kernel memory may be corrupted!!\n"); | |
445 | } | |
e44e0aa3 DW |
446 | } |
447 | ||
8be9e32b AM |
448 | static unsigned int min_odd(unsigned int x, unsigned int y) |
449 | { | |
450 | unsigned int val = min(x, y); | |
451 | ||
452 | return val % 2 ? val : val - 1; | |
453 | } | |
454 | ||
872f05c6 DW |
455 | static void result(const char *err, unsigned int n, unsigned int src_off, |
456 | unsigned int dst_off, unsigned int len, unsigned long data) | |
d86b2f29 | 457 | { |
ef759e4a AS |
458 | if (IS_ERR_VALUE(data)) { |
459 | pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n", | |
460 | current->comm, n, err, src_off, dst_off, len, data); | |
461 | } else { | |
462 | pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", | |
463 | current->comm, n, err, src_off, dst_off, len, data); | |
464 | } | |
d86b2f29 AS |
465 | } |
466 | ||
872f05c6 DW |
467 | static void dbg_result(const char *err, unsigned int n, unsigned int src_off, |
468 | unsigned int dst_off, unsigned int len, | |
469 | unsigned long data) | |
95019c8c | 470 | { |
2acec150 | 471 | pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
a835bb85 | 472 | current->comm, n, err, src_off, dst_off, len, data); |
95019c8c AS |
473 | } |
474 | ||
a835bb85 AS |
475 | #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ |
476 | if (verbose) \ | |
477 | result(err, n, src_off, dst_off, len, data); \ | |
478 | else \ | |
479 | dbg_result(err, n, src_off, dst_off, len, data);\ | |
50137a7d | 480 | }) |
95019c8c | 481 | |
86727443 | 482 | static unsigned long long dmatest_persec(s64 runtime, unsigned int val) |
d86b2f29 | 483 | { |
86727443 | 484 | unsigned long long per_sec = 1000000; |
d86b2f29 | 485 | |
86727443 DW |
486 | if (runtime <= 0) |
487 | return 0; | |
95019c8c | 488 | |
86727443 DW |
489 | /* drop precision until runtime is 32-bits */ |
490 | while (runtime > UINT_MAX) { | |
491 | runtime >>= 1; | |
492 | per_sec <<= 1; | |
95019c8c AS |
493 | } |
494 | ||
86727443 | 495 | per_sec *= val; |
6138f967 | 496 | per_sec = INT_TO_FIXPT(per_sec); |
86727443 | 497 | do_div(per_sec, runtime); |
6138f967 | 498 | |
86727443 | 499 | return per_sec; |
95019c8c AS |
500 | } |
501 | ||
86727443 | 502 | static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) |
95019c8c | 503 | { |
6138f967 | 504 | return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10)); |
95019c8c AS |
505 | } |
506 | ||
3b6679f9 AA |
507 | static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt) |
508 | { | |
509 | unsigned int i; | |
510 | ||
511 | for (i = 0; i < cnt; i++) | |
512 | kfree(d->raw[i]); | |
513 | ||
514 | kfree(d->aligned); | |
515 | kfree(d->raw); | |
516 | } | |
517 | ||
518 | static void dmatest_free_test_data(struct dmatest_data *d) | |
519 | { | |
520 | __dmatest_free_test_data(d, d->cnt); | |
521 | } | |
522 | ||
523 | static int dmatest_alloc_test_data(struct dmatest_data *d, | |
524 | unsigned int buf_size, u8 align) | |
525 | { | |
526 | unsigned int i = 0; | |
527 | ||
528 | d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL); | |
529 | if (!d->raw) | |
530 | return -ENOMEM; | |
531 | ||
532 | d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL); | |
533 | if (!d->aligned) | |
534 | goto err; | |
535 | ||
536 | for (i = 0; i < d->cnt; i++) { | |
537 | d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL); | |
538 | if (!d->raw[i]) | |
539 | goto err; | |
540 | ||
541 | /* align to alignment restriction */ | |
542 | if (align) | |
543 | d->aligned[i] = PTR_ALIGN(d->raw[i], align); | |
544 | else | |
545 | d->aligned[i] = d->raw[i]; | |
546 | } | |
547 | ||
548 | return 0; | |
549 | err: | |
550 | __dmatest_free_test_data(d, i); | |
551 | return -ENOMEM; | |
552 | } | |
553 | ||
4a776f0a HS |
554 | /* |
555 | * This function repeatedly tests DMA transfers of various lengths and | |
b54d5cb9 DW |
556 | * offsets for a given operation type until it is told to exit by |
557 | * kthread_stop(). There may be multiple threads running this function | |
558 | * in parallel for a single channel, and there may be multiple channels | |
559 | * being tested in parallel. | |
4a776f0a HS |
560 | * |
561 | * Before each test, the source and destination buffer is initialized | |
562 | * with a known pattern. This pattern is different depending on | |
563 | * whether it's in an area which is supposed to be copied or | |
564 | * overwritten, and different in the source and destination buffers. | |
565 | * So if the DMA engine doesn't copy exactly what we tell it to copy, | |
566 | * we'll notice. | |
567 | */ | |
568 | static int dmatest_func(void *data) | |
569 | { | |
570 | struct dmatest_thread *thread = data; | |
6f6a23a2 | 571 | struct dmatest_done *done = &thread->test_done; |
e03e93a9 | 572 | struct dmatest_info *info; |
15b8a8ea | 573 | struct dmatest_params *params; |
4a776f0a | 574 | struct dma_chan *chan; |
8be9e32b | 575 | struct dma_device *dev; |
adc0f941 | 576 | struct device *dma_dev; |
4a776f0a HS |
577 | unsigned int error_count; |
578 | unsigned int failed_tests = 0; | |
579 | unsigned int total_tests = 0; | |
580 | dma_cookie_t cookie; | |
581 | enum dma_status status; | |
b54d5cb9 | 582 | enum dma_ctrl_flags flags; |
945b5af3 | 583 | u8 *pq_coefs = NULL; |
4a776f0a | 584 | int ret; |
41d00bb7 | 585 | unsigned int buf_size; |
361deb72 AA |
586 | struct dmatest_data *src; |
587 | struct dmatest_data *dst; | |
b54d5cb9 | 588 | int i; |
e9405ef0 | 589 | ktime_t ktime, start, diff; |
8b0e1953 TG |
590 | ktime_t filltime = 0; |
591 | ktime_t comparetime = 0; | |
86727443 DW |
592 | s64 runtime = 0; |
593 | unsigned long long total_len = 0; | |
6138f967 | 594 | unsigned long long iops = 0; |
d6481608 | 595 | u8 align = 0; |
61b5f54d | 596 | bool is_memset = false; |
72ef08bf LA |
597 | dma_addr_t *srcs; |
598 | dma_addr_t *dma_pq; | |
4a776f0a | 599 | |
adfa543e | 600 | set_freezable(); |
4a776f0a HS |
601 | |
602 | ret = -ENOMEM; | |
4a776f0a HS |
603 | |
604 | smp_rmb(); | |
d53513d5 | 605 | thread->pending = false; |
e03e93a9 | 606 | info = thread->info; |
15b8a8ea | 607 | params = &info->params; |
4a776f0a | 608 | chan = thread->chan; |
8be9e32b | 609 | dev = chan->device; |
adc0f941 PU |
610 | dma_dev = dmaengine_get_dma_device(chan); |
611 | ||
361deb72 AA |
612 | src = &thread->src; |
613 | dst = &thread->dst; | |
d6481608 | 614 | if (thread->type == DMA_MEMCPY) { |
a875abfa SA |
615 | align = params->alignment < 0 ? dev->copy_align : |
616 | params->alignment; | |
361deb72 | 617 | src->cnt = dst->cnt = 1; |
61b5f54d | 618 | } else if (thread->type == DMA_MEMSET) { |
a875abfa SA |
619 | align = params->alignment < 0 ? dev->fill_align : |
620 | params->alignment; | |
361deb72 | 621 | src->cnt = dst->cnt = 1; |
61b5f54d | 622 | is_memset = true; |
d6481608 | 623 | } else if (thread->type == DMA_XOR) { |
8be9e32b | 624 | /* force odd to ensure dst = src */ |
361deb72 AA |
625 | src->cnt = min_odd(params->xor_sources | 1, dev->max_xor); |
626 | dst->cnt = 1; | |
a875abfa SA |
627 | align = params->alignment < 0 ? dev->xor_align : |
628 | params->alignment; | |
58691d64 | 629 | } else if (thread->type == DMA_PQ) { |
8be9e32b | 630 | /* force odd to ensure dst = src */ |
361deb72 AA |
631 | src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); |
632 | dst->cnt = 2; | |
a875abfa SA |
633 | align = params->alignment < 0 ? dev->pq_align : |
634 | params->alignment; | |
945b5af3 | 635 | |
31d18257 | 636 | pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL); |
945b5af3 AS |
637 | if (!pq_coefs) |
638 | goto err_thread_type; | |
639 | ||
361deb72 | 640 | for (i = 0; i < src->cnt; i++) |
58691d64 | 641 | pq_coefs[i] = 1; |
b54d5cb9 | 642 | } else |
945b5af3 | 643 | goto err_thread_type; |
b54d5cb9 | 644 | |
787d3083 | 645 | /* Check if buffer count fits into map count variable (u8) */ |
361deb72 | 646 | if ((src->cnt + dst->cnt) >= 255) { |
787d3083 | 647 | pr_err("too many buffers (%d of 255 supported)\n", |
361deb72 | 648 | src->cnt + dst->cnt); |
3f3c7554 | 649 | goto err_free_coefs; |
787d3083 AA |
650 | } |
651 | ||
41d00bb7 AA |
652 | buf_size = params->buf_size; |
653 | if (1 << align > buf_size) { | |
787d3083 | 654 | pr_err("%u-byte buffer too small for %d-byte alignment\n", |
41d00bb7 | 655 | buf_size, 1 << align); |
3f3c7554 | 656 | goto err_free_coefs; |
787d3083 AA |
657 | } |
658 | ||
3b6679f9 | 659 | if (dmatest_alloc_test_data(src, buf_size, align) < 0) |
3f3c7554 | 660 | goto err_free_coefs; |
d6481608 | 661 | |
3b6679f9 AA |
662 | if (dmatest_alloc_test_data(dst, buf_size, align) < 0) |
663 | goto err_src; | |
b54d5cb9 | 664 | |
e44e0aa3 DW |
665 | set_user_nice(current, 10); |
666 | ||
361deb72 | 667 | srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL); |
72ef08bf | 668 | if (!srcs) |
3b6679f9 | 669 | goto err_dst; |
72ef08bf | 670 | |
361deb72 | 671 | dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL); |
72ef08bf LA |
672 | if (!dma_pq) |
673 | goto err_srcs_array; | |
674 | ||
b203bd3f | 675 | /* |
d1cab34c | 676 | * src and dst buffers are freed by ourselves below |
b203bd3f | 677 | */ |
fb9816f9 PU |
678 | if (params->polled) |
679 | flags = DMA_CTRL_ACK; | |
680 | else | |
681 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; | |
4a776f0a | 682 | |
86727443 | 683 | ktime = ktime_get(); |
b9f96020 AS |
684 | while (!(kthread_should_stop() || |
685 | (params->iterations && total_tests >= params->iterations))) { | |
b54d5cb9 | 686 | struct dma_async_tx_descriptor *tx = NULL; |
4076e755 | 687 | struct dmaengine_unmap_data *um; |
4076e755 | 688 | dma_addr_t *dsts; |
361deb72 | 689 | unsigned int len; |
d86be86e | 690 | |
4a776f0a HS |
691 | total_tests++; |
692 | ||
13396a13 | 693 | if (params->transfer_size) { |
41d00bb7 | 694 | if (params->transfer_size >= buf_size) { |
13396a13 | 695 | pr_err("%u-byte transfer size must be lower than %u-buffer size\n", |
41d00bb7 | 696 | params->transfer_size, buf_size); |
13396a13 SA |
697 | break; |
698 | } | |
699 | len = params->transfer_size; | |
700 | } else if (params->norandom) { | |
41d00bb7 | 701 | len = buf_size; |
13396a13 | 702 | } else { |
41d00bb7 | 703 | len = dmatest_random() % buf_size + 1; |
13396a13 | 704 | } |
ede23a58 | 705 | |
13396a13 SA |
706 | /* Do not alter transfer size explicitly defined by user */ |
707 | if (!params->transfer_size) { | |
708 | len = (len >> align) << align; | |
709 | if (!len) | |
710 | len = 1 << align; | |
711 | } | |
ede23a58 AS |
712 | total_len += len; |
713 | ||
2e67a087 | 714 | if (params->norandom) { |
361deb72 AA |
715 | src->off = 0; |
716 | dst->off = 0; | |
e3b9c347 | 717 | } else { |
41d00bb7 AA |
718 | src->off = dmatest_random() % (buf_size - len + 1); |
719 | dst->off = dmatest_random() % (buf_size - len + 1); | |
e3b9c347 | 720 | |
361deb72 AA |
721 | src->off = (src->off >> align) << align; |
722 | dst->off = (dst->off >> align) << align; | |
2e67a087 | 723 | } |
e3b9c347 | 724 | |
2e67a087 YS |
725 | if (!params->noverify) { |
726 | start = ktime_get(); | |
361deb72 | 727 | dmatest_init_srcs(src->aligned, src->off, len, |
41d00bb7 | 728 | buf_size, is_memset); |
361deb72 | 729 | dmatest_init_dsts(dst->aligned, dst->off, len, |
41d00bb7 | 730 | buf_size, is_memset); |
e9405ef0 SK |
731 | |
732 | diff = ktime_sub(ktime_get(), start); | |
733 | filltime = ktime_add(filltime, diff); | |
e3b9c347 DW |
734 | } |
735 | ||
adc0f941 | 736 | um = dmaengine_get_unmap_data(dma_dev, src->cnt + dst->cnt, |
4076e755 DW |
737 | GFP_KERNEL); |
738 | if (!um) { | |
739 | failed_tests++; | |
740 | result("unmap data NULL", total_tests, | |
361deb72 | 741 | src->off, dst->off, len, ret); |
4076e755 DW |
742 | continue; |
743 | } | |
4a776f0a | 744 | |
41d00bb7 | 745 | um->len = buf_size; |
361deb72 AA |
746 | for (i = 0; i < src->cnt; i++) { |
747 | void *buf = src->aligned[i]; | |
4076e755 | 748 | struct page *pg = virt_to_page(buf); |
f62e5f61 | 749 | unsigned long pg_off = offset_in_page(buf); |
4076e755 | 750 | |
adc0f941 | 751 | um->addr[i] = dma_map_page(dma_dev, pg, pg_off, |
4076e755 | 752 | um->len, DMA_TO_DEVICE); |
361deb72 | 753 | srcs[i] = um->addr[i] + src->off; |
adc0f941 | 754 | ret = dma_mapping_error(dma_dev, um->addr[i]); |
afde3be1 | 755 | if (ret) { |
872f05c6 | 756 | result("src mapping error", total_tests, |
361deb72 | 757 | src->off, dst->off, len, ret); |
6454368a | 758 | goto error_unmap_continue; |
afde3be1 | 759 | } |
4076e755 | 760 | um->to_cnt++; |
b54d5cb9 | 761 | } |
d86be86e | 762 | /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ |
361deb72 AA |
763 | dsts = &um->addr[src->cnt]; |
764 | for (i = 0; i < dst->cnt; i++) { | |
765 | void *buf = dst->aligned[i]; | |
4076e755 | 766 | struct page *pg = virt_to_page(buf); |
f62e5f61 | 767 | unsigned long pg_off = offset_in_page(buf); |
4076e755 | 768 | |
adc0f941 | 769 | dsts[i] = dma_map_page(dma_dev, pg, pg_off, um->len, |
4076e755 | 770 | DMA_BIDIRECTIONAL); |
adc0f941 | 771 | ret = dma_mapping_error(dma_dev, dsts[i]); |
afde3be1 | 772 | if (ret) { |
872f05c6 | 773 | result("dst mapping error", total_tests, |
361deb72 | 774 | src->off, dst->off, len, ret); |
6454368a | 775 | goto error_unmap_continue; |
afde3be1 | 776 | } |
4076e755 | 777 | um->bidi_cnt++; |
b54d5cb9 DW |
778 | } |
779 | ||
780 | if (thread->type == DMA_MEMCPY) | |
781 | tx = dev->device_prep_dma_memcpy(chan, | |
361deb72 | 782 | dsts[0] + dst->off, |
4076e755 | 783 | srcs[0], len, flags); |
61b5f54d SK |
784 | else if (thread->type == DMA_MEMSET) |
785 | tx = dev->device_prep_dma_memset(chan, | |
361deb72 AA |
786 | dsts[0] + dst->off, |
787 | *(src->aligned[0] + src->off), | |
61b5f54d | 788 | len, flags); |
b54d5cb9 DW |
789 | else if (thread->type == DMA_XOR) |
790 | tx = dev->device_prep_dma_xor(chan, | |
361deb72 AA |
791 | dsts[0] + dst->off, |
792 | srcs, src->cnt, | |
b54d5cb9 | 793 | len, flags); |
58691d64 | 794 | else if (thread->type == DMA_PQ) { |
361deb72 AA |
795 | for (i = 0; i < dst->cnt; i++) |
796 | dma_pq[i] = dsts[i] + dst->off; | |
4076e755 | 797 | tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, |
361deb72 | 798 | src->cnt, pq_coefs, |
58691d64 DW |
799 | len, flags); |
800 | } | |
d86be86e | 801 | |
d86be86e | 802 | if (!tx) { |
361deb72 AA |
803 | result("prep error", total_tests, src->off, |
804 | dst->off, len, ret); | |
d86be86e | 805 | msleep(100); |
6454368a | 806 | goto error_unmap_continue; |
d86be86e | 807 | } |
e44e0aa3 | 808 | |
6f6a23a2 | 809 | done->done = false; |
fb9816f9 PU |
810 | if (!params->polled) { |
811 | tx->callback = dmatest_callback; | |
812 | tx->callback_param = done; | |
813 | } | |
d86be86e AN |
814 | cookie = tx->tx_submit(tx); |
815 | ||
4a776f0a | 816 | if (dma_submit_error(cookie)) { |
361deb72 AA |
817 | result("submit error", total_tests, src->off, |
818 | dst->off, len, ret); | |
4a776f0a | 819 | msleep(100); |
6454368a | 820 | goto error_unmap_continue; |
4a776f0a | 821 | } |
4a776f0a | 822 | |
fb9816f9 PU |
823 | if (params->polled) { |
824 | status = dma_sync_wait(chan, cookie); | |
825 | dmaengine_terminate_sync(chan); | |
826 | if (status == DMA_COMPLETE) | |
827 | done->done = true; | |
828 | } else { | |
829 | dma_async_issue_pending(chan); | |
830 | ||
831 | wait_event_freezable_timeout(thread->done_wait, | |
832 | done->done, | |
833 | msecs_to_jiffies(params->timeout)); | |
981ed70d | 834 | |
fb9816f9 PU |
835 | status = dma_async_is_tx_complete(chan, cookie, NULL, |
836 | NULL); | |
837 | } | |
4a776f0a | 838 | |
6f6a23a2 | 839 | if (!done->done) { |
361deb72 | 840 | result("test timed out", total_tests, src->off, dst->off, |
872f05c6 | 841 | len, 0); |
6454368a | 842 | goto error_unmap_continue; |
47ec7f09 DJ |
843 | } else if (status != DMA_COMPLETE && |
844 | !(dma_has_cap(DMA_COMPLETION_NO_ORDER, | |
845 | dev->cap_mask) && | |
846 | status == DMA_OUT_OF_ORDER)) { | |
872f05c6 DW |
847 | result(status == DMA_ERROR ? |
848 | "completion error status" : | |
361deb72 AA |
849 | "completion busy status", total_tests, src->off, |
850 | dst->off, len, ret); | |
6454368a | 851 | goto error_unmap_continue; |
4a776f0a | 852 | } |
e44e0aa3 | 853 | |
6454368a AS |
854 | dmaengine_unmap_put(um); |
855 | ||
e3b9c347 | 856 | if (params->noverify) { |
361deb72 AA |
857 | verbose_result("test passed", total_tests, src->off, |
858 | dst->off, len, 0); | |
e3b9c347 DW |
859 | continue; |
860 | } | |
4a776f0a | 861 | |
e9405ef0 | 862 | start = ktime_get(); |
872f05c6 | 863 | pr_debug("%s: verifying source buffer...\n", current->comm); |
361deb72 | 864 | error_count = dmatest_verify(src->aligned, 0, src->off, |
61b5f54d | 865 | 0, PATTERN_SRC, true, is_memset); |
361deb72 AA |
866 | error_count += dmatest_verify(src->aligned, src->off, |
867 | src->off + len, src->off, | |
61b5f54d | 868 | PATTERN_SRC | PATTERN_COPY, true, is_memset); |
361deb72 | 869 | error_count += dmatest_verify(src->aligned, src->off + len, |
41d00bb7 | 870 | buf_size, src->off + len, |
61b5f54d | 871 | PATTERN_SRC, true, is_memset); |
7b610178 | 872 | |
872f05c6 | 873 | pr_debug("%s: verifying dest buffer...\n", current->comm); |
361deb72 | 874 | error_count += dmatest_verify(dst->aligned, 0, dst->off, |
61b5f54d SK |
875 | 0, PATTERN_DST, false, is_memset); |
876 | ||
361deb72 AA |
877 | error_count += dmatest_verify(dst->aligned, dst->off, |
878 | dst->off + len, src->off, | |
61b5f54d SK |
879 | PATTERN_SRC | PATTERN_COPY, false, is_memset); |
880 | ||
361deb72 | 881 | error_count += dmatest_verify(dst->aligned, dst->off + len, |
41d00bb7 | 882 | buf_size, dst->off + len, |
61b5f54d | 883 | PATTERN_DST, false, is_memset); |
4a776f0a | 884 | |
e9405ef0 SK |
885 | diff = ktime_sub(ktime_get(), start); |
886 | comparetime = ktime_add(comparetime, diff); | |
887 | ||
4a776f0a | 888 | if (error_count) { |
361deb72 | 889 | result("data error", total_tests, src->off, dst->off, |
872f05c6 | 890 | len, error_count); |
4a776f0a HS |
891 | failed_tests++; |
892 | } else { | |
361deb72 AA |
893 | verbose_result("test passed", total_tests, src->off, |
894 | dst->off, len, 0); | |
4a776f0a | 895 | } |
6454368a AS |
896 | |
897 | continue; | |
898 | ||
899 | error_unmap_continue: | |
900 | dmaengine_unmap_put(um); | |
901 | failed_tests++; | |
4a776f0a | 902 | } |
e9405ef0 SK |
903 | ktime = ktime_sub(ktime_get(), ktime); |
904 | ktime = ktime_sub(ktime, comparetime); | |
905 | ktime = ktime_sub(ktime, filltime); | |
906 | runtime = ktime_to_us(ktime); | |
4a776f0a HS |
907 | |
908 | ret = 0; | |
72ef08bf LA |
909 | kfree(dma_pq); |
910 | err_srcs_array: | |
911 | kfree(srcs); | |
3b6679f9 AA |
912 | err_dst: |
913 | dmatest_free_test_data(dst); | |
914 | err_src: | |
915 | dmatest_free_test_data(src); | |
3f3c7554 | 916 | err_free_coefs: |
945b5af3 AS |
917 | kfree(pq_coefs); |
918 | err_thread_type: | |
6138f967 SA |
919 | iops = dmatest_persec(runtime, total_tests); |
920 | pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n", | |
86727443 | 921 | current->comm, total_tests, failed_tests, |
6138f967 | 922 | FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops), |
86727443 | 923 | dmatest_KBs(runtime, total_len), ret); |
0a2ff57d | 924 | |
9704efaa | 925 | /* terminate all transfers on specified channels */ |
6f6a23a2 | 926 | if (ret || failed_tests) |
fbffb6b4 | 927 | dmaengine_terminate_sync(chan); |
5e034f7b | 928 | |
3e5ccd86 | 929 | thread->done = true; |
2d88ce76 | 930 | wake_up(&thread_wait); |
0a2ff57d | 931 | |
4a776f0a HS |
932 | return ret; |
933 | } | |
934 | ||
935 | static void dmatest_cleanup_channel(struct dmatest_chan *dtc) | |
936 | { | |
937 | struct dmatest_thread *thread; | |
938 | struct dmatest_thread *_thread; | |
939 | int ret; | |
940 | ||
941 | list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { | |
942 | ret = kthread_stop(thread->task); | |
0adff800 DW |
943 | pr_debug("thread %s exited with status %d\n", |
944 | thread->task->comm, ret); | |
4a776f0a | 945 | list_del(&thread->node); |
2d88ce76 | 946 | put_task_struct(thread->task); |
4a776f0a HS |
947 | kfree(thread); |
948 | } | |
9704efaa VK |
949 | |
950 | /* terminate all transfers on specified channels */ | |
fbffb6b4 | 951 | dmaengine_terminate_sync(dtc->chan); |
9704efaa | 952 | |
4a776f0a HS |
953 | kfree(dtc); |
954 | } | |
955 | ||
e03e93a9 AS |
956 | static int dmatest_add_threads(struct dmatest_info *info, |
957 | struct dmatest_chan *dtc, enum dma_transaction_type type) | |
4a776f0a | 958 | { |
15b8a8ea | 959 | struct dmatest_params *params = &info->params; |
b54d5cb9 DW |
960 | struct dmatest_thread *thread; |
961 | struct dma_chan *chan = dtc->chan; | |
962 | char *op; | |
963 | unsigned int i; | |
4a776f0a | 964 | |
b54d5cb9 DW |
965 | if (type == DMA_MEMCPY) |
966 | op = "copy"; | |
61b5f54d SK |
967 | else if (type == DMA_MEMSET) |
968 | op = "set"; | |
b54d5cb9 DW |
969 | else if (type == DMA_XOR) |
970 | op = "xor"; | |
58691d64 DW |
971 | else if (type == DMA_PQ) |
972 | op = "pq"; | |
b54d5cb9 DW |
973 | else |
974 | return -EINVAL; | |
4a776f0a | 975 | |
15b8a8ea | 976 | for (i = 0; i < params->threads_per_chan; i++) { |
4a776f0a HS |
977 | thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); |
978 | if (!thread) { | |
0adff800 DW |
979 | pr_warn("No memory for %s-%s%u\n", |
980 | dma_chan_name(chan), op, i); | |
4a776f0a HS |
981 | break; |
982 | } | |
e03e93a9 | 983 | thread->info = info; |
4a776f0a | 984 | thread->chan = dtc->chan; |
b54d5cb9 | 985 | thread->type = type; |
6f6a23a2 AW |
986 | thread->test_done.wait = &thread->done_wait; |
987 | init_waitqueue_head(&thread->done_wait); | |
4a776f0a | 988 | smp_wmb(); |
2d88ce76 | 989 | thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", |
b54d5cb9 | 990 | dma_chan_name(chan), op, i); |
4a776f0a | 991 | if (IS_ERR(thread->task)) { |
2d88ce76 | 992 | pr_warn("Failed to create thread %s-%s%u\n", |
0adff800 | 993 | dma_chan_name(chan), op, i); |
4a776f0a HS |
994 | kfree(thread); |
995 | break; | |
996 | } | |
997 | ||
998 | /* srcbuf and dstbuf are allocated by the thread itself */ | |
2d88ce76 | 999 | get_task_struct(thread->task); |
4a776f0a | 1000 | list_add_tail(&thread->node, &dtc->threads); |
d53513d5 | 1001 | thread->pending = true; |
4a776f0a HS |
1002 | } |
1003 | ||
b54d5cb9 DW |
1004 | return i; |
1005 | } | |
1006 | ||
e03e93a9 AS |
1007 | static int dmatest_add_channel(struct dmatest_info *info, |
1008 | struct dma_chan *chan) | |
b54d5cb9 DW |
1009 | { |
1010 | struct dmatest_chan *dtc; | |
1011 | struct dma_device *dma_dev = chan->device; | |
1012 | unsigned int thread_count = 0; | |
b9033e68 | 1013 | int cnt; |
b54d5cb9 DW |
1014 | |
1015 | dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); | |
1016 | if (!dtc) { | |
0adff800 | 1017 | pr_warn("No memory for %s\n", dma_chan_name(chan)); |
b54d5cb9 DW |
1018 | return -ENOMEM; |
1019 | } | |
1020 | ||
1021 | dtc->chan = chan; | |
1022 | INIT_LIST_HEAD(&dtc->threads); | |
1023 | ||
47ec7f09 DJ |
1024 | if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) && |
1025 | info->params.polled) { | |
1026 | info->params.polled = false; | |
1027 | pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n"); | |
1028 | } | |
1029 | ||
b54d5cb9 | 1030 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { |
a0d4cb44 KA |
1031 | if (dmatest == 0) { |
1032 | cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); | |
1033 | thread_count += cnt > 0 ? cnt : 0; | |
1034 | } | |
b54d5cb9 | 1035 | } |
a0d4cb44 | 1036 | |
61b5f54d | 1037 | if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { |
a0d4cb44 | 1038 | if (dmatest == 1) { |
c678fa66 | 1039 | cnt = dmatest_add_threads(info, dtc, DMA_MEMSET); |
a0d4cb44 KA |
1040 | thread_count += cnt > 0 ? cnt : 0; |
1041 | } | |
1042 | } | |
1043 | ||
b54d5cb9 | 1044 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
e03e93a9 | 1045 | cnt = dmatest_add_threads(info, dtc, DMA_XOR); |
f1aef8b6 | 1046 | thread_count += cnt > 0 ? cnt : 0; |
b54d5cb9 | 1047 | } |
58691d64 | 1048 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { |
e03e93a9 | 1049 | cnt = dmatest_add_threads(info, dtc, DMA_PQ); |
d07a74a5 | 1050 | thread_count += cnt > 0 ? cnt : 0; |
58691d64 | 1051 | } |
b54d5cb9 | 1052 | |
d53513d5 | 1053 | pr_info("Added %u threads using %s\n", |
b54d5cb9 | 1054 | thread_count, dma_chan_name(chan)); |
4a776f0a | 1055 | |
838cc704 AS |
1056 | list_add_tail(&dtc->node, &info->channels); |
1057 | info->nr_channels++; | |
4a776f0a | 1058 | |
33df8ca0 | 1059 | return 0; |
4a776f0a HS |
1060 | } |
1061 | ||
7dd60251 | 1062 | static bool filter(struct dma_chan *chan, void *param) |
4a776f0a | 1063 | { |
da75ba24 | 1064 | return dmatest_match_channel(param, chan) && dmatest_match_device(param, chan->device); |
4a776f0a HS |
1065 | } |
1066 | ||
a9e55495 DW |
1067 | static void request_channels(struct dmatest_info *info, |
1068 | enum dma_transaction_type type) | |
4a776f0a | 1069 | { |
33df8ca0 | 1070 | dma_cap_mask_t mask; |
33df8ca0 DW |
1071 | |
1072 | dma_cap_zero(mask); | |
a9e55495 | 1073 | dma_cap_set(type, mask); |
33df8ca0 | 1074 | for (;;) { |
a9e55495 DW |
1075 | struct dmatest_params *params = &info->params; |
1076 | struct dma_chan *chan; | |
1077 | ||
15b8a8ea | 1078 | chan = dma_request_channel(mask, filter, params); |
33df8ca0 | 1079 | if (chan) { |
a9e55495 | 1080 | if (dmatest_add_channel(info, chan)) { |
33df8ca0 DW |
1081 | dma_release_channel(chan); |
1082 | break; /* add_channel failed, punt */ | |
1083 | } | |
1084 | } else | |
1085 | break; /* no more channels available */ | |
15b8a8ea AS |
1086 | if (params->max_channels && |
1087 | info->nr_channels >= params->max_channels) | |
33df8ca0 DW |
1088 | break; /* we have all we need */ |
1089 | } | |
4a776f0a | 1090 | } |
4a776f0a | 1091 | |
d53513d5 | 1092 | static void add_threaded_test(struct dmatest_info *info) |
851b7e16 | 1093 | { |
a9e55495 | 1094 | struct dmatest_params *params = &info->params; |
851b7e16 | 1095 | |
a9e55495 DW |
1096 | /* Copy test parameters */ |
1097 | params->buf_size = test_buf_size; | |
1098 | strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); | |
1099 | strlcpy(params->device, strim(test_device), sizeof(params->device)); | |
1100 | params->threads_per_chan = threads_per_chan; | |
1101 | params->max_channels = max_channels; | |
1102 | params->iterations = iterations; | |
1103 | params->xor_sources = xor_sources; | |
1104 | params->pq_sources = pq_sources; | |
1105 | params->timeout = timeout; | |
e3b9c347 | 1106 | params->noverify = noverify; |
2e67a087 | 1107 | params->norandom = norandom; |
a875abfa | 1108 | params->alignment = alignment; |
13396a13 | 1109 | params->transfer_size = transfer_size; |
fb9816f9 | 1110 | params->polled = polled; |
a9e55495 DW |
1111 | |
1112 | request_channels(info, DMA_MEMCPY); | |
61b5f54d | 1113 | request_channels(info, DMA_MEMSET); |
a9e55495 DW |
1114 | request_channels(info, DMA_XOR); |
1115 | request_channels(info, DMA_PQ); | |
851b7e16 | 1116 | } |
851b7e16 | 1117 | |
d53513d5 SA |
1118 | static void run_pending_tests(struct dmatest_info *info) |
1119 | { | |
1120 | struct dmatest_chan *dtc; | |
1121 | unsigned int thread_count = 0; | |
1122 | ||
1123 | list_for_each_entry(dtc, &info->channels, node) { | |
1124 | struct dmatest_thread *thread; | |
1125 | ||
1126 | thread_count = 0; | |
1127 | list_for_each_entry(thread, &dtc->threads, node) { | |
1128 | wake_up_process(thread->task); | |
1129 | thread_count++; | |
1130 | } | |
1131 | pr_info("Started %u threads using %s\n", | |
1132 | thread_count, dma_chan_name(dtc->chan)); | |
1133 | } | |
1134 | } | |
1135 | ||
a310d037 | 1136 | static void stop_threaded_test(struct dmatest_info *info) |
4a776f0a | 1137 | { |
33df8ca0 | 1138 | struct dmatest_chan *dtc, *_dtc; |
7cbd4877 | 1139 | struct dma_chan *chan; |
33df8ca0 | 1140 | |
838cc704 | 1141 | list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { |
33df8ca0 | 1142 | list_del(&dtc->node); |
7cbd4877 | 1143 | chan = dtc->chan; |
33df8ca0 | 1144 | dmatest_cleanup_channel(dtc); |
0adff800 | 1145 | pr_debug("dropped channel %s\n", dma_chan_name(chan)); |
7cbd4877 | 1146 | dma_release_channel(chan); |
33df8ca0 | 1147 | } |
838cc704 AS |
1148 | |
1149 | info->nr_channels = 0; | |
4a776f0a | 1150 | } |
e03e93a9 | 1151 | |
d53513d5 | 1152 | static void start_threaded_tests(struct dmatest_info *info) |
851b7e16 | 1153 | { |
a310d037 DW |
1154 | /* we might be called early to set run=, defer running until all |
1155 | * parameters have been evaluated | |
1156 | */ | |
1157 | if (!info->did_init) | |
a9e55495 | 1158 | return; |
851b7e16 | 1159 | |
d53513d5 | 1160 | run_pending_tests(info); |
851b7e16 AS |
1161 | } |
1162 | ||
a310d037 | 1163 | static int dmatest_run_get(char *val, const struct kernel_param *kp) |
851b7e16 | 1164 | { |
a310d037 | 1165 | struct dmatest_info *info = &test_info; |
851b7e16 AS |
1166 | |
1167 | mutex_lock(&info->lock); | |
a310d037 DW |
1168 | if (is_threaded_test_run(info)) { |
1169 | dmatest_run = true; | |
3e5ccd86 | 1170 | } else { |
d53513d5 SA |
1171 | if (!is_threaded_test_pending(info)) |
1172 | stop_threaded_test(info); | |
a310d037 | 1173 | dmatest_run = false; |
3e5ccd86 | 1174 | } |
851b7e16 | 1175 | mutex_unlock(&info->lock); |
851b7e16 | 1176 | |
a310d037 | 1177 | return param_get_bool(val, kp); |
851b7e16 AS |
1178 | } |
1179 | ||
a310d037 | 1180 | static int dmatest_run_set(const char *val, const struct kernel_param *kp) |
95019c8c | 1181 | { |
a310d037 DW |
1182 | struct dmatest_info *info = &test_info; |
1183 | int ret; | |
95019c8c | 1184 | |
a310d037 DW |
1185 | mutex_lock(&info->lock); |
1186 | ret = param_set_bool(val, kp); | |
1187 | if (ret) { | |
851b7e16 | 1188 | mutex_unlock(&info->lock); |
a310d037 | 1189 | return ret; |
d53513d5 | 1190 | } else if (dmatest_run) { |
6b41030f | 1191 | if (!is_threaded_test_pending(info)) { |
ce65d55f VM |
1192 | /* |
1193 | * We have nothing to run. This can be due to: | |
1194 | */ | |
1195 | ret = info->last_error; | |
1196 | if (ret) { | |
1197 | /* 1) Misconfiguration */ | |
1198 | pr_err("Channel misconfigured, can't continue\n"); | |
1199 | mutex_unlock(&info->lock); | |
1200 | return ret; | |
1201 | } else { | |
1202 | /* 2) We rely on defaults */ | |
1203 | pr_info("No channels configured, continue with any\n"); | |
1204 | if (!is_threaded_test_run(info)) | |
1205 | stop_threaded_test(info); | |
1206 | add_threaded_test(info); | |
1207 | } | |
6b41030f VM |
1208 | } |
1209 | start_threaded_tests(info); | |
d53513d5 SA |
1210 | } else { |
1211 | stop_threaded_test(info); | |
1212 | } | |
1213 | ||
1214 | mutex_unlock(&info->lock); | |
1215 | ||
1216 | return ret; | |
1217 | } | |
1218 | ||
1219 | static int dmatest_chan_set(const char *val, const struct kernel_param *kp) | |
1220 | { | |
1221 | struct dmatest_info *info = &test_info; | |
1222 | struct dmatest_chan *dtc; | |
1223 | char chan_reset_val[20]; | |
ce65d55f | 1224 | int ret; |
d53513d5 SA |
1225 | |
1226 | mutex_lock(&info->lock); | |
1227 | ret = param_set_copystring(val, kp); | |
1228 | if (ret) { | |
1229 | mutex_unlock(&info->lock); | |
1230 | return ret; | |
1231 | } | |
1232 | /*Clear any previously run threads */ | |
1233 | if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) | |
1234 | stop_threaded_test(info); | |
1235 | /* Reject channels that are already registered */ | |
1236 | if (is_threaded_test_pending(info)) { | |
1237 | list_for_each_entry(dtc, &info->channels, node) { | |
1238 | if (strcmp(dma_chan_name(dtc->chan), | |
1239 | strim(test_channel)) == 0) { | |
1240 | dtc = list_last_entry(&info->channels, | |
1241 | struct dmatest_chan, | |
1242 | node); | |
1243 | strlcpy(chan_reset_val, | |
1244 | dma_chan_name(dtc->chan), | |
1245 | sizeof(chan_reset_val)); | |
1246 | ret = -EBUSY; | |
1247 | goto add_chan_err; | |
1248 | } | |
1249 | } | |
95019c8c AS |
1250 | } |
1251 | ||
d53513d5 SA |
1252 | add_threaded_test(info); |
1253 | ||
1254 | /* Check if channel was added successfully */ | |
b28de385 | 1255 | if (!list_empty(&info->channels)) { |
d53513d5 SA |
1256 | /* |
1257 | * if new channel was not successfully added, revert the | |
1258 | * "test_channel" string to the name of the last successfully | |
1259 | * added channel. exception for when users issues empty string | |
1260 | * to channel parameter. | |
1261 | */ | |
b28de385 | 1262 | dtc = list_last_entry(&info->channels, struct dmatest_chan, node); |
d53513d5 SA |
1263 | if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0) |
1264 | && (strcmp("", strim(test_channel)) != 0)) { | |
1265 | ret = -EINVAL; | |
1266 | strlcpy(chan_reset_val, dma_chan_name(dtc->chan), | |
1267 | sizeof(chan_reset_val)); | |
1268 | goto add_chan_err; | |
1269 | } | |
1270 | ||
1271 | } else { | |
1272 | /* Clear test_channel if no channels were added successfully */ | |
1273 | strlcpy(chan_reset_val, "", sizeof(chan_reset_val)); | |
a310d037 | 1274 | ret = -EBUSY; |
d53513d5 SA |
1275 | goto add_chan_err; |
1276 | } | |
1277 | ||
ce65d55f | 1278 | info->last_error = ret; |
d53513d5 SA |
1279 | mutex_unlock(&info->lock); |
1280 | ||
1281 | return ret; | |
851b7e16 | 1282 | |
d53513d5 SA |
1283 | add_chan_err: |
1284 | param_set_copystring(chan_reset_val, kp); | |
ce65d55f | 1285 | info->last_error = ret; |
a310d037 | 1286 | mutex_unlock(&info->lock); |
851b7e16 | 1287 | |
a310d037 | 1288 | return ret; |
851b7e16 AS |
1289 | } |
1290 | ||
d53513d5 SA |
1291 | static int dmatest_chan_get(char *val, const struct kernel_param *kp) |
1292 | { | |
1293 | struct dmatest_info *info = &test_info; | |
1294 | ||
1295 | mutex_lock(&info->lock); | |
1296 | if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) { | |
1297 | stop_threaded_test(info); | |
1298 | strlcpy(test_channel, "", sizeof(test_channel)); | |
1299 | } | |
1300 | mutex_unlock(&info->lock); | |
1301 | ||
1302 | return param_get_string(val, kp); | |
1303 | } | |
1304 | ||
1305 | static int dmatest_test_list_get(char *val, const struct kernel_param *kp) | |
1306 | { | |
1307 | struct dmatest_info *info = &test_info; | |
1308 | struct dmatest_chan *dtc; | |
1309 | unsigned int thread_count = 0; | |
1310 | ||
1311 | list_for_each_entry(dtc, &info->channels, node) { | |
1312 | struct dmatest_thread *thread; | |
1313 | ||
1314 | thread_count = 0; | |
1315 | list_for_each_entry(thread, &dtc->threads, node) { | |
1316 | thread_count++; | |
1317 | } | |
1318 | pr_info("%u threads using %s\n", | |
1319 | thread_count, dma_chan_name(dtc->chan)); | |
1320 | } | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
e03e93a9 AS |
1325 | static int __init dmatest_init(void) |
1326 | { | |
1327 | struct dmatest_info *info = &test_info; | |
2d88ce76 | 1328 | struct dmatest_params *params = &info->params; |
e03e93a9 | 1329 | |
a310d037 DW |
1330 | if (dmatest_run) { |
1331 | mutex_lock(&info->lock); | |
d53513d5 SA |
1332 | add_threaded_test(info); |
1333 | run_pending_tests(info); | |
a310d037 DW |
1334 | mutex_unlock(&info->lock); |
1335 | } | |
838cc704 | 1336 | |
2d88ce76 DW |
1337 | if (params->iterations && wait) |
1338 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
95019c8c | 1339 | |
a310d037 DW |
1340 | /* module parameters are stable, inittime tests are started, |
1341 | * let userspace take over 'run' control | |
1342 | */ | |
1343 | info->did_init = true; | |
851b7e16 | 1344 | |
851b7e16 | 1345 | return 0; |
e03e93a9 AS |
1346 | } |
1347 | /* when compiled-in wait for drivers to load first */ | |
1348 | late_initcall(dmatest_init); | |
1349 | ||
1350 | static void __exit dmatest_exit(void) | |
1351 | { | |
1352 | struct dmatest_info *info = &test_info; | |
1353 | ||
a310d037 | 1354 | mutex_lock(&info->lock); |
e03e93a9 | 1355 | stop_threaded_test(info); |
a310d037 | 1356 | mutex_unlock(&info->lock); |
e03e93a9 | 1357 | } |
4a776f0a HS |
1358 | module_exit(dmatest_exit); |
1359 | ||
e05503ef | 1360 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
4a776f0a | 1361 | MODULE_LICENSE("GPL v2"); |