Commit | Line | Data |
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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
c13c8260 CL |
14 | * The full GNU General Public License is included in this distribution in the |
15 | * file called COPYING. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * This code implements the DMA subsystem. It provides a HW-neutral interface | |
20 | * for other kernel code to use asynchronous memory copy capabilities, | |
21 | * if present, and allows different HW DMA drivers to register as providing | |
22 | * this capability. | |
23 | * | |
24 | * Due to the fact we are accelerating what is already a relatively fast | |
25 | * operation, the code goes to great lengths to avoid additional overhead, | |
26 | * such as locking. | |
27 | * | |
28 | * LOCKING: | |
29 | * | |
aa1e6f1a DW |
30 | * The subsystem keeps a global list of dma_device structs it is protected by a |
31 | * mutex, dma_list_mutex. | |
c13c8260 | 32 | * |
f27c580c DW |
33 | * A subsystem can get access to a channel by calling dmaengine_get() followed |
34 | * by dma_find_channel(), or if it has need for an exclusive channel it can call | |
35 | * dma_request_channel(). Once a channel is allocated a reference is taken | |
36 | * against its corresponding driver to disable removal. | |
37 | * | |
c13c8260 CL |
38 | * Each device has a channels list, which runs unlocked but is never modified |
39 | * once the device is registered, it's just setup by the driver. | |
40 | * | |
44348e8a | 41 | * See Documentation/driver-api/dmaengine for more details |
c13c8260 CL |
42 | */ |
43 | ||
63433250 JP |
44 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
45 | ||
a8135d0d | 46 | #include <linux/platform_device.h> |
b7f080cf | 47 | #include <linux/dma-mapping.h> |
c13c8260 CL |
48 | #include <linux/init.h> |
49 | #include <linux/module.h> | |
7405f74b | 50 | #include <linux/mm.h> |
c13c8260 CL |
51 | #include <linux/device.h> |
52 | #include <linux/dmaengine.h> | |
53 | #include <linux/hardirq.h> | |
54 | #include <linux/spinlock.h> | |
55 | #include <linux/percpu.h> | |
56 | #include <linux/rcupdate.h> | |
57 | #include <linux/mutex.h> | |
7405f74b | 58 | #include <linux/jiffies.h> |
2ba05622 | 59 | #include <linux/rculist.h> |
864498aa | 60 | #include <linux/idr.h> |
5a0e3ad6 | 61 | #include <linux/slab.h> |
4e82f5dd AS |
62 | #include <linux/acpi.h> |
63 | #include <linux/acpi_dma.h> | |
9a6cecc8 | 64 | #include <linux/of_dma.h> |
45c463ae | 65 | #include <linux/mempool.h> |
98fa15f3 | 66 | #include <linux/numa.h> |
c13c8260 CL |
67 | |
68 | static DEFINE_MUTEX(dma_list_mutex); | |
adc064cd | 69 | static DEFINE_IDA(dma_ida); |
c13c8260 | 70 | static LIST_HEAD(dma_device_list); |
6f49a57a | 71 | static long dmaengine_ref_count; |
c13c8260 CL |
72 | |
73 | /* --- sysfs implementation --- */ | |
74 | ||
41d5e59c DW |
75 | /** |
76 | * dev_to_dma_chan - convert a device pointer to the its sysfs container object | |
77 | * @dev - device node | |
78 | * | |
79 | * Must be called under dma_list_mutex | |
80 | */ | |
81 | static struct dma_chan *dev_to_dma_chan(struct device *dev) | |
82 | { | |
83 | struct dma_chan_dev *chan_dev; | |
84 | ||
85 | chan_dev = container_of(dev, typeof(*chan_dev), device); | |
86 | return chan_dev->chan; | |
87 | } | |
88 | ||
58b267d3 GKH |
89 | static ssize_t memcpy_count_show(struct device *dev, |
90 | struct device_attribute *attr, char *buf) | |
c13c8260 | 91 | { |
41d5e59c | 92 | struct dma_chan *chan; |
c13c8260 CL |
93 | unsigned long count = 0; |
94 | int i; | |
41d5e59c | 95 | int err; |
c13c8260 | 96 | |
41d5e59c DW |
97 | mutex_lock(&dma_list_mutex); |
98 | chan = dev_to_dma_chan(dev); | |
99 | if (chan) { | |
100 | for_each_possible_cpu(i) | |
101 | count += per_cpu_ptr(chan->local, i)->memcpy_count; | |
102 | err = sprintf(buf, "%lu\n", count); | |
103 | } else | |
104 | err = -ENODEV; | |
105 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 106 | |
41d5e59c | 107 | return err; |
c13c8260 | 108 | } |
58b267d3 | 109 | static DEVICE_ATTR_RO(memcpy_count); |
c13c8260 | 110 | |
58b267d3 GKH |
111 | static ssize_t bytes_transferred_show(struct device *dev, |
112 | struct device_attribute *attr, char *buf) | |
c13c8260 | 113 | { |
41d5e59c | 114 | struct dma_chan *chan; |
c13c8260 CL |
115 | unsigned long count = 0; |
116 | int i; | |
41d5e59c | 117 | int err; |
c13c8260 | 118 | |
41d5e59c DW |
119 | mutex_lock(&dma_list_mutex); |
120 | chan = dev_to_dma_chan(dev); | |
121 | if (chan) { | |
122 | for_each_possible_cpu(i) | |
123 | count += per_cpu_ptr(chan->local, i)->bytes_transferred; | |
124 | err = sprintf(buf, "%lu\n", count); | |
125 | } else | |
126 | err = -ENODEV; | |
127 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 128 | |
41d5e59c | 129 | return err; |
c13c8260 | 130 | } |
58b267d3 | 131 | static DEVICE_ATTR_RO(bytes_transferred); |
c13c8260 | 132 | |
58b267d3 GKH |
133 | static ssize_t in_use_show(struct device *dev, struct device_attribute *attr, |
134 | char *buf) | |
c13c8260 | 135 | { |
41d5e59c DW |
136 | struct dma_chan *chan; |
137 | int err; | |
c13c8260 | 138 | |
41d5e59c DW |
139 | mutex_lock(&dma_list_mutex); |
140 | chan = dev_to_dma_chan(dev); | |
141 | if (chan) | |
142 | err = sprintf(buf, "%d\n", chan->client_count); | |
143 | else | |
144 | err = -ENODEV; | |
145 | mutex_unlock(&dma_list_mutex); | |
146 | ||
147 | return err; | |
c13c8260 | 148 | } |
58b267d3 | 149 | static DEVICE_ATTR_RO(in_use); |
c13c8260 | 150 | |
58b267d3 GKH |
151 | static struct attribute *dma_dev_attrs[] = { |
152 | &dev_attr_memcpy_count.attr, | |
153 | &dev_attr_bytes_transferred.attr, | |
154 | &dev_attr_in_use.attr, | |
155 | NULL, | |
c13c8260 | 156 | }; |
58b267d3 | 157 | ATTRIBUTE_GROUPS(dma_dev); |
c13c8260 | 158 | |
41d5e59c DW |
159 | static void chan_dev_release(struct device *dev) |
160 | { | |
161 | struct dma_chan_dev *chan_dev; | |
162 | ||
163 | chan_dev = container_of(dev, typeof(*chan_dev), device); | |
864498aa | 164 | if (atomic_dec_and_test(chan_dev->idr_ref)) { |
485258b4 | 165 | ida_free(&dma_ida, chan_dev->dev_id); |
864498aa DW |
166 | kfree(chan_dev->idr_ref); |
167 | } | |
41d5e59c DW |
168 | kfree(chan_dev); |
169 | } | |
170 | ||
c13c8260 | 171 | static struct class dma_devclass = { |
891f78ea | 172 | .name = "dma", |
58b267d3 | 173 | .dev_groups = dma_dev_groups, |
41d5e59c | 174 | .dev_release = chan_dev_release, |
c13c8260 CL |
175 | }; |
176 | ||
177 | /* --- client and device registration --- */ | |
178 | ||
59b5ec21 DW |
179 | #define dma_device_satisfies_mask(device, mask) \ |
180 | __dma_device_satisfies_mask((device), &(mask)) | |
d379b01e | 181 | static int |
a53e28da LPC |
182 | __dma_device_satisfies_mask(struct dma_device *device, |
183 | const dma_cap_mask_t *want) | |
d379b01e DW |
184 | { |
185 | dma_cap_mask_t has; | |
186 | ||
59b5ec21 | 187 | bitmap_and(has.bits, want->bits, device->cap_mask.bits, |
d379b01e DW |
188 | DMA_TX_TYPE_END); |
189 | return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END); | |
190 | } | |
191 | ||
6f49a57a DW |
192 | static struct module *dma_chan_to_owner(struct dma_chan *chan) |
193 | { | |
194 | return chan->device->dev->driver->owner; | |
195 | } | |
196 | ||
197 | /** | |
198 | * balance_ref_count - catch up the channel reference count | |
199 | * @chan - channel to balance ->client_count versus dmaengine_ref_count | |
200 | * | |
201 | * balance_ref_count must be called under dma_list_mutex | |
202 | */ | |
203 | static void balance_ref_count(struct dma_chan *chan) | |
204 | { | |
205 | struct module *owner = dma_chan_to_owner(chan); | |
206 | ||
207 | while (chan->client_count < dmaengine_ref_count) { | |
208 | __module_get(owner); | |
209 | chan->client_count++; | |
210 | } | |
211 | } | |
212 | ||
213 | /** | |
214 | * dma_chan_get - try to grab a dma channel's parent driver module | |
215 | * @chan - channel to grab | |
216 | * | |
217 | * Must be called under dma_list_mutex | |
218 | */ | |
219 | static int dma_chan_get(struct dma_chan *chan) | |
220 | { | |
6f49a57a | 221 | struct module *owner = dma_chan_to_owner(chan); |
d2f4f99d | 222 | int ret; |
6f49a57a | 223 | |
d2f4f99d | 224 | /* The channel is already in use, update client count */ |
6f49a57a DW |
225 | if (chan->client_count) { |
226 | __module_get(owner); | |
d2f4f99d MR |
227 | goto out; |
228 | } | |
6f49a57a | 229 | |
d2f4f99d MR |
230 | if (!try_module_get(owner)) |
231 | return -ENODEV; | |
6f49a57a DW |
232 | |
233 | /* allocate upon first client reference */ | |
c4b54a64 MR |
234 | if (chan->device->device_alloc_chan_resources) { |
235 | ret = chan->device->device_alloc_chan_resources(chan); | |
236 | if (ret < 0) | |
237 | goto err_out; | |
238 | } | |
6f49a57a | 239 | |
d2f4f99d MR |
240 | if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) |
241 | balance_ref_count(chan); | |
242 | ||
243 | out: | |
244 | chan->client_count++; | |
245 | return 0; | |
246 | ||
247 | err_out: | |
248 | module_put(owner); | |
249 | return ret; | |
6f49a57a DW |
250 | } |
251 | ||
252 | /** | |
253 | * dma_chan_put - drop a reference to a dma channel's parent driver module | |
254 | * @chan - channel to release | |
255 | * | |
256 | * Must be called under dma_list_mutex | |
257 | */ | |
258 | static void dma_chan_put(struct dma_chan *chan) | |
259 | { | |
c4b54a64 | 260 | /* This channel is not in use, bail out */ |
6f49a57a | 261 | if (!chan->client_count) |
c4b54a64 MR |
262 | return; |
263 | ||
6f49a57a DW |
264 | chan->client_count--; |
265 | module_put(dma_chan_to_owner(chan)); | |
c4b54a64 MR |
266 | |
267 | /* This channel is not in use anymore, free it */ | |
b36f09c3 LPC |
268 | if (!chan->client_count && chan->device->device_free_chan_resources) { |
269 | /* Make sure all operations have completed */ | |
270 | dmaengine_synchronize(chan); | |
6f49a57a | 271 | chan->device->device_free_chan_resources(chan); |
b36f09c3 | 272 | } |
56f13c0d PU |
273 | |
274 | /* If the channel is used via a DMA request router, free the mapping */ | |
275 | if (chan->router && chan->router->route_free) { | |
276 | chan->router->route_free(chan->router->dev, chan->route_data); | |
277 | chan->router = NULL; | |
278 | chan->route_data = NULL; | |
279 | } | |
6f49a57a DW |
280 | } |
281 | ||
7405f74b DW |
282 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) |
283 | { | |
284 | enum dma_status status; | |
285 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); | |
286 | ||
287 | dma_async_issue_pending(chan); | |
288 | do { | |
289 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); | |
290 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
ef859312 | 291 | dev_err(chan->device->dev, "%s: timeout!\n", __func__); |
7405f74b DW |
292 | return DMA_ERROR; |
293 | } | |
2cbe7feb BZ |
294 | if (status != DMA_IN_PROGRESS) |
295 | break; | |
296 | cpu_relax(); | |
297 | } while (1); | |
7405f74b DW |
298 | |
299 | return status; | |
300 | } | |
301 | EXPORT_SYMBOL(dma_sync_wait); | |
302 | ||
bec08513 DW |
303 | /** |
304 | * dma_cap_mask_all - enable iteration over all operation types | |
305 | */ | |
306 | static dma_cap_mask_t dma_cap_mask_all; | |
307 | ||
308 | /** | |
309 | * dma_chan_tbl_ent - tracks channel allocations per core/operation | |
310 | * @chan - associated channel for this entry | |
311 | */ | |
312 | struct dma_chan_tbl_ent { | |
313 | struct dma_chan *chan; | |
314 | }; | |
315 | ||
316 | /** | |
317 | * channel_table - percpu lookup table for memory-to-memory offload providers | |
318 | */ | |
a29d8b8e | 319 | static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END]; |
bec08513 DW |
320 | |
321 | static int __init dma_channel_table_init(void) | |
322 | { | |
323 | enum dma_transaction_type cap; | |
324 | int err = 0; | |
325 | ||
326 | bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END); | |
327 | ||
59b5ec21 DW |
328 | /* 'interrupt', 'private', and 'slave' are channel capabilities, |
329 | * but are not associated with an operation so they do not need | |
330 | * an entry in the channel_table | |
bec08513 DW |
331 | */ |
332 | clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits); | |
59b5ec21 | 333 | clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits); |
bec08513 DW |
334 | clear_bit(DMA_SLAVE, dma_cap_mask_all.bits); |
335 | ||
336 | for_each_dma_cap_mask(cap, dma_cap_mask_all) { | |
337 | channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent); | |
338 | if (!channel_table[cap]) { | |
339 | err = -ENOMEM; | |
340 | break; | |
341 | } | |
342 | } | |
343 | ||
344 | if (err) { | |
63433250 | 345 | pr_err("initialization failure\n"); |
bec08513 | 346 | for_each_dma_cap_mask(cap, dma_cap_mask_all) |
a9507ca3 | 347 | free_percpu(channel_table[cap]); |
bec08513 DW |
348 | } |
349 | ||
350 | return err; | |
351 | } | |
652afc27 | 352 | arch_initcall(dma_channel_table_init); |
bec08513 DW |
353 | |
354 | /** | |
355 | * dma_find_channel - find a channel to carry out the operation | |
356 | * @tx_type: transaction type | |
357 | */ | |
358 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) | |
359 | { | |
e7dcaa47 | 360 | return this_cpu_read(channel_table[tx_type]->chan); |
bec08513 DW |
361 | } |
362 | EXPORT_SYMBOL(dma_find_channel); | |
a2bd1140 | 363 | |
2ba05622 DW |
364 | /** |
365 | * dma_issue_pending_all - flush all pending operations across all channels | |
366 | */ | |
367 | void dma_issue_pending_all(void) | |
368 | { | |
369 | struct dma_device *device; | |
370 | struct dma_chan *chan; | |
371 | ||
2ba05622 | 372 | rcu_read_lock(); |
59b5ec21 DW |
373 | list_for_each_entry_rcu(device, &dma_device_list, global_node) { |
374 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
375 | continue; | |
2ba05622 DW |
376 | list_for_each_entry(chan, &device->channels, device_node) |
377 | if (chan->client_count) | |
378 | device->device_issue_pending(chan); | |
59b5ec21 | 379 | } |
2ba05622 DW |
380 | rcu_read_unlock(); |
381 | } | |
382 | EXPORT_SYMBOL(dma_issue_pending_all); | |
383 | ||
bec08513 | 384 | /** |
c4d27c4d BG |
385 | * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu |
386 | */ | |
387 | static bool dma_chan_is_local(struct dma_chan *chan, int cpu) | |
388 | { | |
389 | int node = dev_to_node(chan->device->dev); | |
98fa15f3 AK |
390 | return node == NUMA_NO_NODE || |
391 | cpumask_test_cpu(cpu, cpumask_of_node(node)); | |
c4d27c4d BG |
392 | } |
393 | ||
394 | /** | |
395 | * min_chan - returns the channel with min count and in the same numa-node as the cpu | |
bec08513 | 396 | * @cap: capability to match |
c4d27c4d | 397 | * @cpu: cpu index which the channel should be close to |
bec08513 | 398 | * |
c4d27c4d BG |
399 | * If some channels are close to the given cpu, the one with the lowest |
400 | * reference count is returned. Otherwise, cpu is ignored and only the | |
401 | * reference count is taken into account. | |
402 | * Must be called under dma_list_mutex. | |
bec08513 | 403 | */ |
c4d27c4d | 404 | static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu) |
bec08513 DW |
405 | { |
406 | struct dma_device *device; | |
407 | struct dma_chan *chan; | |
bec08513 | 408 | struct dma_chan *min = NULL; |
c4d27c4d | 409 | struct dma_chan *localmin = NULL; |
bec08513 DW |
410 | |
411 | list_for_each_entry(device, &dma_device_list, global_node) { | |
59b5ec21 DW |
412 | if (!dma_has_cap(cap, device->cap_mask) || |
413 | dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
bec08513 DW |
414 | continue; |
415 | list_for_each_entry(chan, &device->channels, device_node) { | |
416 | if (!chan->client_count) | |
417 | continue; | |
c4d27c4d | 418 | if (!min || chan->table_count < min->table_count) |
bec08513 DW |
419 | min = chan; |
420 | ||
c4d27c4d BG |
421 | if (dma_chan_is_local(chan, cpu)) |
422 | if (!localmin || | |
423 | chan->table_count < localmin->table_count) | |
424 | localmin = chan; | |
bec08513 | 425 | } |
bec08513 DW |
426 | } |
427 | ||
c4d27c4d | 428 | chan = localmin ? localmin : min; |
bec08513 | 429 | |
c4d27c4d BG |
430 | if (chan) |
431 | chan->table_count++; | |
bec08513 | 432 | |
c4d27c4d | 433 | return chan; |
bec08513 DW |
434 | } |
435 | ||
436 | /** | |
437 | * dma_channel_rebalance - redistribute the available channels | |
438 | * | |
439 | * Optimize for cpu isolation (each cpu gets a dedicated channel for an | |
440 | * operation type) in the SMP case, and operation isolation (avoid | |
441 | * multi-tasking channels) in the non-SMP case. Must be called under | |
442 | * dma_list_mutex. | |
443 | */ | |
444 | static void dma_channel_rebalance(void) | |
445 | { | |
446 | struct dma_chan *chan; | |
447 | struct dma_device *device; | |
448 | int cpu; | |
449 | int cap; | |
bec08513 DW |
450 | |
451 | /* undo the last distribution */ | |
452 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
453 | for_each_possible_cpu(cpu) | |
454 | per_cpu_ptr(channel_table[cap], cpu)->chan = NULL; | |
455 | ||
59b5ec21 DW |
456 | list_for_each_entry(device, &dma_device_list, global_node) { |
457 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
458 | continue; | |
bec08513 DW |
459 | list_for_each_entry(chan, &device->channels, device_node) |
460 | chan->table_count = 0; | |
59b5ec21 | 461 | } |
bec08513 DW |
462 | |
463 | /* don't populate the channel_table if no clients are available */ | |
464 | if (!dmaengine_ref_count) | |
465 | return; | |
466 | ||
467 | /* redistribute available channels */ | |
bec08513 DW |
468 | for_each_dma_cap_mask(cap, dma_cap_mask_all) |
469 | for_each_online_cpu(cpu) { | |
c4d27c4d | 470 | chan = min_chan(cap, cpu); |
bec08513 DW |
471 | per_cpu_ptr(channel_table[cap], cpu)->chan = chan; |
472 | } | |
473 | } | |
474 | ||
0d5484b1 LP |
475 | int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) |
476 | { | |
477 | struct dma_device *device; | |
478 | ||
479 | if (!chan || !caps) | |
480 | return -EINVAL; | |
481 | ||
482 | device = chan->device; | |
483 | ||
484 | /* check if the channel supports slave transactions */ | |
dd4e91d5 AS |
485 | if (!(test_bit(DMA_SLAVE, device->cap_mask.bits) || |
486 | test_bit(DMA_CYCLIC, device->cap_mask.bits))) | |
0d5484b1 LP |
487 | return -ENXIO; |
488 | ||
489 | /* | |
490 | * Check whether it reports it uses the generic slave | |
491 | * capabilities, if not, that means it doesn't support any | |
492 | * kind of slave capabilities reporting. | |
493 | */ | |
494 | if (!device->directions) | |
495 | return -ENXIO; | |
496 | ||
497 | caps->src_addr_widths = device->src_addr_widths; | |
498 | caps->dst_addr_widths = device->dst_addr_widths; | |
499 | caps->directions = device->directions; | |
6d5bbed3 | 500 | caps->max_burst = device->max_burst; |
0d5484b1 | 501 | caps->residue_granularity = device->residue_granularity; |
9eeacd3a | 502 | caps->descriptor_reuse = device->descriptor_reuse; |
d8095f94 MS |
503 | caps->cmd_pause = !!device->device_pause; |
504 | caps->cmd_resume = !!device->device_resume; | |
0d5484b1 LP |
505 | caps->cmd_terminate = !!device->device_terminate_all; |
506 | ||
507 | return 0; | |
508 | } | |
509 | EXPORT_SYMBOL_GPL(dma_get_slave_caps); | |
510 | ||
a53e28da LPC |
511 | static struct dma_chan *private_candidate(const dma_cap_mask_t *mask, |
512 | struct dma_device *dev, | |
e2346677 | 513 | dma_filter_fn fn, void *fn_param) |
59b5ec21 DW |
514 | { |
515 | struct dma_chan *chan; | |
59b5ec21 | 516 | |
26b64256 | 517 | if (mask && !__dma_device_satisfies_mask(dev, mask)) { |
ef859312 | 518 | dev_dbg(dev->dev, "%s: wrong capabilities\n", __func__); |
59b5ec21 DW |
519 | return NULL; |
520 | } | |
521 | /* devices with multiple channels need special handling as we need to | |
522 | * ensure that all channels are either private or public. | |
523 | */ | |
524 | if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask)) | |
525 | list_for_each_entry(chan, &dev->channels, device_node) { | |
526 | /* some channels are already publicly allocated */ | |
527 | if (chan->client_count) | |
528 | return NULL; | |
529 | } | |
530 | ||
531 | list_for_each_entry(chan, &dev->channels, device_node) { | |
532 | if (chan->client_count) { | |
ef859312 | 533 | dev_dbg(dev->dev, "%s: %s busy\n", |
41d5e59c | 534 | __func__, dma_chan_name(chan)); |
59b5ec21 DW |
535 | continue; |
536 | } | |
e2346677 | 537 | if (fn && !fn(chan, fn_param)) { |
ef859312 | 538 | dev_dbg(dev->dev, "%s: %s filter said false\n", |
e2346677 DW |
539 | __func__, dma_chan_name(chan)); |
540 | continue; | |
541 | } | |
542 | return chan; | |
59b5ec21 DW |
543 | } |
544 | ||
e2346677 | 545 | return NULL; |
59b5ec21 DW |
546 | } |
547 | ||
7bd903c5 PU |
548 | static struct dma_chan *find_candidate(struct dma_device *device, |
549 | const dma_cap_mask_t *mask, | |
550 | dma_filter_fn fn, void *fn_param) | |
551 | { | |
552 | struct dma_chan *chan = private_candidate(mask, device, fn, fn_param); | |
553 | int err; | |
554 | ||
555 | if (chan) { | |
556 | /* Found a suitable channel, try to grab, prep, and return it. | |
557 | * We first set DMA_PRIVATE to disable balance_ref_count as this | |
558 | * channel will not be published in the general-purpose | |
559 | * allocator | |
560 | */ | |
561 | dma_cap_set(DMA_PRIVATE, device->cap_mask); | |
562 | device->privatecnt++; | |
563 | err = dma_chan_get(chan); | |
564 | ||
565 | if (err) { | |
566 | if (err == -ENODEV) { | |
ef859312 JN |
567 | dev_dbg(device->dev, "%s: %s module removed\n", |
568 | __func__, dma_chan_name(chan)); | |
7bd903c5 PU |
569 | list_del_rcu(&device->global_node); |
570 | } else | |
ef859312 JN |
571 | dev_dbg(device->dev, |
572 | "%s: failed to get %s: (%d)\n", | |
7bd903c5 PU |
573 | __func__, dma_chan_name(chan), err); |
574 | ||
575 | if (--device->privatecnt == 0) | |
576 | dma_cap_clear(DMA_PRIVATE, device->cap_mask); | |
577 | ||
578 | chan = ERR_PTR(err); | |
579 | } | |
580 | } | |
581 | ||
582 | return chan ? chan : ERR_PTR(-EPROBE_DEFER); | |
583 | } | |
584 | ||
59b5ec21 | 585 | /** |
19d643d6 | 586 | * dma_get_slave_channel - try to get specific channel exclusively |
7bb587f4 ZG |
587 | * @chan: target channel |
588 | */ | |
589 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan) | |
590 | { | |
591 | int err = -EBUSY; | |
592 | ||
593 | /* lock against __dma_request_channel */ | |
594 | mutex_lock(&dma_list_mutex); | |
595 | ||
d9a6c8f5 | 596 | if (chan->client_count == 0) { |
214fc4e4 PU |
597 | struct dma_device *device = chan->device; |
598 | ||
599 | dma_cap_set(DMA_PRIVATE, device->cap_mask); | |
600 | device->privatecnt++; | |
7bb587f4 | 601 | err = dma_chan_get(chan); |
214fc4e4 | 602 | if (err) { |
ef859312 JN |
603 | dev_dbg(chan->device->dev, |
604 | "%s: failed to get %s: (%d)\n", | |
d9a6c8f5 | 605 | __func__, dma_chan_name(chan), err); |
214fc4e4 PU |
606 | chan = NULL; |
607 | if (--device->privatecnt == 0) | |
608 | dma_cap_clear(DMA_PRIVATE, device->cap_mask); | |
609 | } | |
d9a6c8f5 | 610 | } else |
7bb587f4 ZG |
611 | chan = NULL; |
612 | ||
613 | mutex_unlock(&dma_list_mutex); | |
614 | ||
7bb587f4 ZG |
615 | |
616 | return chan; | |
617 | } | |
618 | EXPORT_SYMBOL_GPL(dma_get_slave_channel); | |
619 | ||
8010dad5 SW |
620 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device) |
621 | { | |
622 | dma_cap_mask_t mask; | |
623 | struct dma_chan *chan; | |
8010dad5 SW |
624 | |
625 | dma_cap_zero(mask); | |
626 | dma_cap_set(DMA_SLAVE, mask); | |
627 | ||
628 | /* lock against __dma_request_channel */ | |
629 | mutex_lock(&dma_list_mutex); | |
630 | ||
7bd903c5 | 631 | chan = find_candidate(device, &mask, NULL, NULL); |
8010dad5 SW |
632 | |
633 | mutex_unlock(&dma_list_mutex); | |
634 | ||
7bd903c5 | 635 | return IS_ERR(chan) ? NULL : chan; |
8010dad5 SW |
636 | } |
637 | EXPORT_SYMBOL_GPL(dma_get_any_slave_channel); | |
638 | ||
59b5ec21 | 639 | /** |
6b9019a7 | 640 | * __dma_request_channel - try to allocate an exclusive channel |
59b5ec21 DW |
641 | * @mask: capabilities that the channel must satisfy |
642 | * @fn: optional callback to disposition available channels | |
643 | * @fn_param: opaque parameter to pass to dma_filter_fn | |
0ad7c000 SW |
644 | * |
645 | * Returns pointer to appropriate DMA channel on success or NULL. | |
59b5ec21 | 646 | */ |
a53e28da LPC |
647 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
648 | dma_filter_fn fn, void *fn_param) | |
59b5ec21 DW |
649 | { |
650 | struct dma_device *device, *_d; | |
651 | struct dma_chan *chan = NULL; | |
59b5ec21 DW |
652 | |
653 | /* Find a channel */ | |
654 | mutex_lock(&dma_list_mutex); | |
655 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { | |
7bd903c5 PU |
656 | chan = find_candidate(device, mask, fn, fn_param); |
657 | if (!IS_ERR(chan)) | |
658 | break; | |
59b5ec21 | 659 | |
7bd903c5 | 660 | chan = NULL; |
59b5ec21 DW |
661 | } |
662 | mutex_unlock(&dma_list_mutex); | |
663 | ||
4c4d7f87 | 664 | pr_debug("%s: %s (%s)\n", |
63433250 JP |
665 | __func__, |
666 | chan ? "success" : "fail", | |
41d5e59c | 667 | chan ? dma_chan_name(chan) : NULL); |
59b5ec21 DW |
668 | |
669 | return chan; | |
670 | } | |
671 | EXPORT_SYMBOL_GPL(__dma_request_channel); | |
672 | ||
a8135d0d PU |
673 | static const struct dma_slave_map *dma_filter_match(struct dma_device *device, |
674 | const char *name, | |
675 | struct device *dev) | |
676 | { | |
677 | int i; | |
678 | ||
679 | if (!device->filter.mapcnt) | |
680 | return NULL; | |
681 | ||
682 | for (i = 0; i < device->filter.mapcnt; i++) { | |
683 | const struct dma_slave_map *map = &device->filter.map[i]; | |
684 | ||
685 | if (!strcmp(map->devname, dev_name(dev)) && | |
686 | !strcmp(map->slave, name)) | |
687 | return map; | |
688 | } | |
689 | ||
690 | return NULL; | |
691 | } | |
692 | ||
9a6cecc8 | 693 | /** |
a8135d0d | 694 | * dma_request_chan - try to allocate an exclusive slave channel |
9a6cecc8 JH |
695 | * @dev: pointer to client device structure |
696 | * @name: slave channel name | |
0ad7c000 SW |
697 | * |
698 | * Returns pointer to appropriate DMA channel on success or an error pointer. | |
9a6cecc8 | 699 | */ |
a8135d0d | 700 | struct dma_chan *dma_request_chan(struct device *dev, const char *name) |
9a6cecc8 | 701 | { |
a8135d0d PU |
702 | struct dma_device *d, *_d; |
703 | struct dma_chan *chan = NULL; | |
704 | ||
9a6cecc8 JH |
705 | /* If device-tree is present get slave info from here */ |
706 | if (dev->of_node) | |
a8135d0d | 707 | chan = of_dma_request_slave_channel(dev->of_node, name); |
9a6cecc8 | 708 | |
4e82f5dd | 709 | /* If device was enumerated by ACPI get slave info from here */ |
a8135d0d PU |
710 | if (has_acpi_companion(dev) && !chan) |
711 | chan = acpi_dma_request_slave_chan_by_name(dev, name); | |
712 | ||
713 | if (chan) { | |
714 | /* Valid channel found or requester need to be deferred */ | |
715 | if (!IS_ERR(chan) || PTR_ERR(chan) == -EPROBE_DEFER) | |
716 | return chan; | |
717 | } | |
718 | ||
719 | /* Try to find the channel via the DMA filter map(s) */ | |
720 | mutex_lock(&dma_list_mutex); | |
721 | list_for_each_entry_safe(d, _d, &dma_device_list, global_node) { | |
722 | dma_cap_mask_t mask; | |
723 | const struct dma_slave_map *map = dma_filter_match(d, name, dev); | |
4e82f5dd | 724 | |
a8135d0d PU |
725 | if (!map) |
726 | continue; | |
727 | ||
728 | dma_cap_zero(mask); | |
729 | dma_cap_set(DMA_SLAVE, mask); | |
4e82f5dd | 730 | |
a8135d0d PU |
731 | chan = find_candidate(d, &mask, d->filter.fn, map->param); |
732 | if (!IS_ERR(chan)) | |
733 | break; | |
734 | } | |
735 | mutex_unlock(&dma_list_mutex); | |
736 | ||
737 | return chan ? chan : ERR_PTR(-EPROBE_DEFER); | |
0ad7c000 | 738 | } |
a8135d0d | 739 | EXPORT_SYMBOL_GPL(dma_request_chan); |
0ad7c000 SW |
740 | |
741 | /** | |
742 | * dma_request_slave_channel - try to allocate an exclusive slave channel | |
743 | * @dev: pointer to client device structure | |
744 | * @name: slave channel name | |
745 | * | |
746 | * Returns pointer to appropriate DMA channel on success or NULL. | |
747 | */ | |
748 | struct dma_chan *dma_request_slave_channel(struct device *dev, | |
749 | const char *name) | |
750 | { | |
a8135d0d | 751 | struct dma_chan *ch = dma_request_chan(dev, name); |
0ad7c000 SW |
752 | if (IS_ERR(ch)) |
753 | return NULL; | |
05aa1a77 | 754 | |
0ad7c000 | 755 | return ch; |
9a6cecc8 JH |
756 | } |
757 | EXPORT_SYMBOL_GPL(dma_request_slave_channel); | |
758 | ||
a8135d0d PU |
759 | /** |
760 | * dma_request_chan_by_mask - allocate a channel satisfying certain capabilities | |
761 | * @mask: capabilities that the channel must satisfy | |
762 | * | |
763 | * Returns pointer to appropriate DMA channel on success or an error pointer. | |
764 | */ | |
765 | struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask) | |
766 | { | |
767 | struct dma_chan *chan; | |
768 | ||
769 | if (!mask) | |
770 | return ERR_PTR(-ENODEV); | |
771 | ||
772 | chan = __dma_request_channel(mask, NULL, NULL); | |
ec8ca8e3 PU |
773 | if (!chan) { |
774 | mutex_lock(&dma_list_mutex); | |
775 | if (list_empty(&dma_device_list)) | |
776 | chan = ERR_PTR(-EPROBE_DEFER); | |
777 | else | |
778 | chan = ERR_PTR(-ENODEV); | |
779 | mutex_unlock(&dma_list_mutex); | |
780 | } | |
a8135d0d PU |
781 | |
782 | return chan; | |
783 | } | |
784 | EXPORT_SYMBOL_GPL(dma_request_chan_by_mask); | |
785 | ||
59b5ec21 DW |
786 | void dma_release_channel(struct dma_chan *chan) |
787 | { | |
788 | mutex_lock(&dma_list_mutex); | |
789 | WARN_ONCE(chan->client_count != 1, | |
790 | "chan reference count %d != 1\n", chan->client_count); | |
791 | dma_chan_put(chan); | |
0f571515 AN |
792 | /* drop PRIVATE cap enabled by __dma_request_channel() */ |
793 | if (--chan->device->privatecnt == 0) | |
794 | dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask); | |
59b5ec21 DW |
795 | mutex_unlock(&dma_list_mutex); |
796 | } | |
797 | EXPORT_SYMBOL_GPL(dma_release_channel); | |
798 | ||
d379b01e | 799 | /** |
209b84a8 | 800 | * dmaengine_get - register interest in dma_channels |
d379b01e | 801 | */ |
209b84a8 | 802 | void dmaengine_get(void) |
d379b01e | 803 | { |
6f49a57a DW |
804 | struct dma_device *device, *_d; |
805 | struct dma_chan *chan; | |
806 | int err; | |
807 | ||
c13c8260 | 808 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
809 | dmaengine_ref_count++; |
810 | ||
811 | /* try to grab channels */ | |
59b5ec21 DW |
812 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { |
813 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
814 | continue; | |
6f49a57a DW |
815 | list_for_each_entry(chan, &device->channels, device_node) { |
816 | err = dma_chan_get(chan); | |
817 | if (err == -ENODEV) { | |
818 | /* module removed before we could use it */ | |
2ba05622 | 819 | list_del_rcu(&device->global_node); |
6f49a57a DW |
820 | break; |
821 | } else if (err) | |
ef859312 JN |
822 | dev_dbg(chan->device->dev, |
823 | "%s: failed to get %s: (%d)\n", | |
824 | __func__, dma_chan_name(chan), err); | |
6f49a57a | 825 | } |
59b5ec21 | 826 | } |
6f49a57a | 827 | |
bec08513 DW |
828 | /* if this is the first reference and there were channels |
829 | * waiting we need to rebalance to get those channels | |
830 | * incorporated into the channel table | |
831 | */ | |
832 | if (dmaengine_ref_count == 1) | |
833 | dma_channel_rebalance(); | |
c13c8260 | 834 | mutex_unlock(&dma_list_mutex); |
c13c8260 | 835 | } |
209b84a8 | 836 | EXPORT_SYMBOL(dmaengine_get); |
c13c8260 CL |
837 | |
838 | /** | |
209b84a8 | 839 | * dmaengine_put - let dma drivers be removed when ref_count == 0 |
c13c8260 | 840 | */ |
209b84a8 | 841 | void dmaengine_put(void) |
c13c8260 | 842 | { |
d379b01e | 843 | struct dma_device *device; |
c13c8260 CL |
844 | struct dma_chan *chan; |
845 | ||
c13c8260 | 846 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
847 | dmaengine_ref_count--; |
848 | BUG_ON(dmaengine_ref_count < 0); | |
849 | /* drop channel references */ | |
59b5ec21 DW |
850 | list_for_each_entry(device, &dma_device_list, global_node) { |
851 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
852 | continue; | |
6f49a57a DW |
853 | list_for_each_entry(chan, &device->channels, device_node) |
854 | dma_chan_put(chan); | |
59b5ec21 | 855 | } |
c13c8260 | 856 | mutex_unlock(&dma_list_mutex); |
c13c8260 | 857 | } |
209b84a8 | 858 | EXPORT_SYMBOL(dmaengine_put); |
c13c8260 | 859 | |
138f4c35 DW |
860 | static bool device_has_all_tx_types(struct dma_device *device) |
861 | { | |
862 | /* A device that satisfies this test has channels that will never cause | |
863 | * an async_tx channel switch event as all possible operation types can | |
864 | * be handled. | |
865 | */ | |
866 | #ifdef CONFIG_ASYNC_TX_DMA | |
867 | if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask)) | |
868 | return false; | |
869 | #endif | |
870 | ||
d57d3a48 | 871 | #if IS_ENABLED(CONFIG_ASYNC_MEMCPY) |
138f4c35 DW |
872 | if (!dma_has_cap(DMA_MEMCPY, device->cap_mask)) |
873 | return false; | |
874 | #endif | |
875 | ||
d57d3a48 | 876 | #if IS_ENABLED(CONFIG_ASYNC_XOR) |
138f4c35 DW |
877 | if (!dma_has_cap(DMA_XOR, device->cap_mask)) |
878 | return false; | |
7b3cc2b1 DW |
879 | |
880 | #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
4499a24d DW |
881 | if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask)) |
882 | return false; | |
138f4c35 | 883 | #endif |
7b3cc2b1 | 884 | #endif |
138f4c35 | 885 | |
d57d3a48 | 886 | #if IS_ENABLED(CONFIG_ASYNC_PQ) |
138f4c35 DW |
887 | if (!dma_has_cap(DMA_PQ, device->cap_mask)) |
888 | return false; | |
7b3cc2b1 DW |
889 | |
890 | #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA | |
4499a24d DW |
891 | if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask)) |
892 | return false; | |
138f4c35 | 893 | #endif |
7b3cc2b1 | 894 | #endif |
138f4c35 DW |
895 | |
896 | return true; | |
897 | } | |
898 | ||
257b17ca DW |
899 | static int get_dma_id(struct dma_device *device) |
900 | { | |
485258b4 | 901 | int rc = ida_alloc(&dma_ida, GFP_KERNEL); |
69ee266b | 902 | |
485258b4 MW |
903 | if (rc < 0) |
904 | return rc; | |
905 | device->dev_id = rc; | |
906 | return 0; | |
257b17ca DW |
907 | } |
908 | ||
c13c8260 | 909 | /** |
6508871e | 910 | * dma_async_device_register - registers DMA devices found |
c13c8260 CL |
911 | * @device: &dma_device |
912 | */ | |
913 | int dma_async_device_register(struct dma_device *device) | |
914 | { | |
ff487fb7 | 915 | int chancnt = 0, rc; |
c13c8260 | 916 | struct dma_chan* chan; |
864498aa | 917 | atomic_t *idr_ref; |
c13c8260 CL |
918 | |
919 | if (!device) | |
920 | return -ENODEV; | |
921 | ||
7405f74b | 922 | /* validate device routines */ |
3eeb5156 VK |
923 | if (!device->dev) { |
924 | pr_err("DMAdevice must have dev\n"); | |
925 | return -EIO; | |
926 | } | |
927 | ||
928 | if (dma_has_cap(DMA_MEMCPY, device->cap_mask) && !device->device_prep_dma_memcpy) { | |
929 | dev_err(device->dev, | |
930 | "Device claims capability %s, but op is not defined\n", | |
931 | "DMA_MEMCPY"); | |
932 | return -EIO; | |
933 | } | |
934 | ||
935 | if (dma_has_cap(DMA_XOR, device->cap_mask) && !device->device_prep_dma_xor) { | |
936 | dev_err(device->dev, | |
937 | "Device claims capability %s, but op is not defined\n", | |
938 | "DMA_XOR"); | |
939 | return -EIO; | |
940 | } | |
941 | ||
942 | if (dma_has_cap(DMA_XOR_VAL, device->cap_mask) && !device->device_prep_dma_xor_val) { | |
943 | dev_err(device->dev, | |
944 | "Device claims capability %s, but op is not defined\n", | |
945 | "DMA_XOR_VAL"); | |
946 | return -EIO; | |
947 | } | |
948 | ||
949 | if (dma_has_cap(DMA_PQ, device->cap_mask) && !device->device_prep_dma_pq) { | |
950 | dev_err(device->dev, | |
951 | "Device claims capability %s, but op is not defined\n", | |
952 | "DMA_PQ"); | |
953 | return -EIO; | |
954 | } | |
955 | ||
956 | if (dma_has_cap(DMA_PQ_VAL, device->cap_mask) && !device->device_prep_dma_pq_val) { | |
957 | dev_err(device->dev, | |
958 | "Device claims capability %s, but op is not defined\n", | |
959 | "DMA_PQ_VAL"); | |
960 | return -EIO; | |
961 | } | |
962 | ||
963 | if (dma_has_cap(DMA_MEMSET, device->cap_mask) && !device->device_prep_dma_memset) { | |
964 | dev_err(device->dev, | |
965 | "Device claims capability %s, but op is not defined\n", | |
966 | "DMA_MEMSET"); | |
967 | return -EIO; | |
968 | } | |
969 | ||
970 | if (dma_has_cap(DMA_INTERRUPT, device->cap_mask) && !device->device_prep_dma_interrupt) { | |
971 | dev_err(device->dev, | |
972 | "Device claims capability %s, but op is not defined\n", | |
973 | "DMA_INTERRUPT"); | |
974 | return -EIO; | |
975 | } | |
976 | ||
977 | if (dma_has_cap(DMA_CYCLIC, device->cap_mask) && !device->device_prep_dma_cyclic) { | |
978 | dev_err(device->dev, | |
979 | "Device claims capability %s, but op is not defined\n", | |
980 | "DMA_CYCLIC"); | |
981 | return -EIO; | |
982 | } | |
983 | ||
984 | if (dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && !device->device_prep_interleaved_dma) { | |
985 | dev_err(device->dev, | |
986 | "Device claims capability %s, but op is not defined\n", | |
987 | "DMA_INTERLEAVE"); | |
988 | return -EIO; | |
989 | } | |
990 | ||
991 | ||
992 | if (!device->device_tx_status) { | |
993 | dev_err(device->dev, "Device tx_status is not defined\n"); | |
994 | return -EIO; | |
995 | } | |
996 | ||
997 | ||
998 | if (!device->device_issue_pending) { | |
999 | dev_err(device->dev, "Device issue_pending is not defined\n"); | |
1000 | return -EIO; | |
1001 | } | |
7405f74b | 1002 | |
138f4c35 | 1003 | /* note: this only matters in the |
5fc6d897 | 1004 | * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case |
138f4c35 DW |
1005 | */ |
1006 | if (device_has_all_tx_types(device)) | |
1007 | dma_cap_set(DMA_ASYNC_TX, device->cap_mask); | |
1008 | ||
864498aa DW |
1009 | idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL); |
1010 | if (!idr_ref) | |
1011 | return -ENOMEM; | |
257b17ca DW |
1012 | rc = get_dma_id(device); |
1013 | if (rc != 0) { | |
1014 | kfree(idr_ref); | |
864498aa | 1015 | return rc; |
257b17ca DW |
1016 | } |
1017 | ||
1018 | atomic_set(idr_ref, 0); | |
c13c8260 CL |
1019 | |
1020 | /* represent channels in sysfs. Probably want devs too */ | |
1021 | list_for_each_entry(chan, &device->channels, device_node) { | |
257b17ca | 1022 | rc = -ENOMEM; |
c13c8260 CL |
1023 | chan->local = alloc_percpu(typeof(*chan->local)); |
1024 | if (chan->local == NULL) | |
257b17ca | 1025 | goto err_out; |
41d5e59c DW |
1026 | chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); |
1027 | if (chan->dev == NULL) { | |
1028 | free_percpu(chan->local); | |
257b17ca DW |
1029 | chan->local = NULL; |
1030 | goto err_out; | |
41d5e59c | 1031 | } |
c13c8260 CL |
1032 | |
1033 | chan->chan_id = chancnt++; | |
41d5e59c DW |
1034 | chan->dev->device.class = &dma_devclass; |
1035 | chan->dev->device.parent = device->dev; | |
1036 | chan->dev->chan = chan; | |
864498aa DW |
1037 | chan->dev->idr_ref = idr_ref; |
1038 | chan->dev->dev_id = device->dev_id; | |
1039 | atomic_inc(idr_ref); | |
41d5e59c | 1040 | dev_set_name(&chan->dev->device, "dma%dchan%d", |
06190d84 | 1041 | device->dev_id, chan->chan_id); |
c13c8260 | 1042 | |
41d5e59c | 1043 | rc = device_register(&chan->dev->device); |
ff487fb7 | 1044 | if (rc) { |
ff487fb7 JG |
1045 | free_percpu(chan->local); |
1046 | chan->local = NULL; | |
257b17ca DW |
1047 | kfree(chan->dev); |
1048 | atomic_dec(idr_ref); | |
ff487fb7 JG |
1049 | goto err_out; |
1050 | } | |
7cc5bf9a | 1051 | chan->client_count = 0; |
c13c8260 | 1052 | } |
76d7b84b VK |
1053 | |
1054 | if (!chancnt) { | |
1055 | dev_err(device->dev, "%s: device has no channels!\n", __func__); | |
1056 | rc = -ENODEV; | |
1057 | goto err_out; | |
1058 | } | |
1059 | ||
59b5ec21 | 1060 | device->chancnt = chancnt; |
c13c8260 CL |
1061 | |
1062 | mutex_lock(&dma_list_mutex); | |
59b5ec21 DW |
1063 | /* take references on public channels */ |
1064 | if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
6f49a57a DW |
1065 | list_for_each_entry(chan, &device->channels, device_node) { |
1066 | /* if clients are already waiting for channels we need | |
1067 | * to take references on their behalf | |
1068 | */ | |
1069 | if (dma_chan_get(chan) == -ENODEV) { | |
1070 | /* note we can only get here for the first | |
1071 | * channel as the remaining channels are | |
1072 | * guaranteed to get a reference | |
1073 | */ | |
1074 | rc = -ENODEV; | |
1075 | mutex_unlock(&dma_list_mutex); | |
1076 | goto err_out; | |
1077 | } | |
1078 | } | |
2ba05622 | 1079 | list_add_tail_rcu(&device->global_node, &dma_device_list); |
0f571515 AN |
1080 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) |
1081 | device->privatecnt++; /* Always private */ | |
bec08513 | 1082 | dma_channel_rebalance(); |
c13c8260 CL |
1083 | mutex_unlock(&dma_list_mutex); |
1084 | ||
c13c8260 | 1085 | return 0; |
ff487fb7 JG |
1086 | |
1087 | err_out: | |
257b17ca DW |
1088 | /* if we never registered a channel just release the idr */ |
1089 | if (atomic_read(idr_ref) == 0) { | |
485258b4 | 1090 | ida_free(&dma_ida, device->dev_id); |
257b17ca DW |
1091 | kfree(idr_ref); |
1092 | return rc; | |
1093 | } | |
1094 | ||
ff487fb7 JG |
1095 | list_for_each_entry(chan, &device->channels, device_node) { |
1096 | if (chan->local == NULL) | |
1097 | continue; | |
41d5e59c DW |
1098 | mutex_lock(&dma_list_mutex); |
1099 | chan->dev->chan = NULL; | |
1100 | mutex_unlock(&dma_list_mutex); | |
1101 | device_unregister(&chan->dev->device); | |
ff487fb7 JG |
1102 | free_percpu(chan->local); |
1103 | } | |
1104 | return rc; | |
c13c8260 | 1105 | } |
765e3d8a | 1106 | EXPORT_SYMBOL(dma_async_device_register); |
c13c8260 | 1107 | |
6508871e | 1108 | /** |
6f49a57a | 1109 | * dma_async_device_unregister - unregister a DMA device |
6508871e | 1110 | * @device: &dma_device |
f27c580c DW |
1111 | * |
1112 | * This routine is called by dma driver exit routines, dmaengine holds module | |
1113 | * references to prevent it being called while channels are in use. | |
6508871e RD |
1114 | */ |
1115 | void dma_async_device_unregister(struct dma_device *device) | |
c13c8260 CL |
1116 | { |
1117 | struct dma_chan *chan; | |
c13c8260 CL |
1118 | |
1119 | mutex_lock(&dma_list_mutex); | |
2ba05622 | 1120 | list_del_rcu(&device->global_node); |
bec08513 | 1121 | dma_channel_rebalance(); |
c13c8260 CL |
1122 | mutex_unlock(&dma_list_mutex); |
1123 | ||
1124 | list_for_each_entry(chan, &device->channels, device_node) { | |
6f49a57a DW |
1125 | WARN_ONCE(chan->client_count, |
1126 | "%s called while %d clients hold a reference\n", | |
1127 | __func__, chan->client_count); | |
41d5e59c DW |
1128 | mutex_lock(&dma_list_mutex); |
1129 | chan->dev->chan = NULL; | |
1130 | mutex_unlock(&dma_list_mutex); | |
1131 | device_unregister(&chan->dev->device); | |
adef4772 | 1132 | free_percpu(chan->local); |
c13c8260 | 1133 | } |
c13c8260 | 1134 | } |
765e3d8a | 1135 | EXPORT_SYMBOL(dma_async_device_unregister); |
c13c8260 | 1136 | |
f39b948d HS |
1137 | static void dmam_device_release(struct device *dev, void *res) |
1138 | { | |
1139 | struct dma_device *device; | |
1140 | ||
1141 | device = *(struct dma_device **)res; | |
1142 | dma_async_device_unregister(device); | |
1143 | } | |
1144 | ||
1145 | /** | |
1146 | * dmaenginem_async_device_register - registers DMA devices found | |
1147 | * @device: &dma_device | |
1148 | * | |
1149 | * The operation is managed and will be undone on driver detach. | |
1150 | */ | |
1151 | int dmaenginem_async_device_register(struct dma_device *device) | |
1152 | { | |
1153 | void *p; | |
1154 | int ret; | |
1155 | ||
1156 | p = devres_alloc(dmam_device_release, sizeof(void *), GFP_KERNEL); | |
1157 | if (!p) | |
1158 | return -ENOMEM; | |
1159 | ||
1160 | ret = dma_async_device_register(device); | |
1161 | if (!ret) { | |
1162 | *(struct dma_device **)p = device; | |
1163 | devres_add(device->dev, p); | |
1164 | } else { | |
1165 | devres_free(p); | |
1166 | } | |
1167 | ||
1168 | return ret; | |
1169 | } | |
1170 | EXPORT_SYMBOL(dmaenginem_async_device_register); | |
1171 | ||
45c463ae DW |
1172 | struct dmaengine_unmap_pool { |
1173 | struct kmem_cache *cache; | |
1174 | const char *name; | |
1175 | mempool_t *pool; | |
1176 | size_t size; | |
1177 | }; | |
7405f74b | 1178 | |
45c463ae DW |
1179 | #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) } |
1180 | static struct dmaengine_unmap_pool unmap_pool[] = { | |
1181 | __UNMAP_POOL(2), | |
3cc377b9 | 1182 | #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) |
45c463ae DW |
1183 | __UNMAP_POOL(16), |
1184 | __UNMAP_POOL(128), | |
1185 | __UNMAP_POOL(256), | |
1186 | #endif | |
1187 | }; | |
0036731c | 1188 | |
45c463ae DW |
1189 | static struct dmaengine_unmap_pool *__get_unmap_pool(int nr) |
1190 | { | |
1191 | int order = get_count_order(nr); | |
1192 | ||
1193 | switch (order) { | |
1194 | case 0 ... 1: | |
1195 | return &unmap_pool[0]; | |
23f963e9 | 1196 | #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID) |
45c463ae DW |
1197 | case 2 ... 4: |
1198 | return &unmap_pool[1]; | |
1199 | case 5 ... 7: | |
1200 | return &unmap_pool[2]; | |
1201 | case 8: | |
1202 | return &unmap_pool[3]; | |
23f963e9 | 1203 | #endif |
45c463ae DW |
1204 | default: |
1205 | BUG(); | |
1206 | return NULL; | |
0036731c | 1207 | } |
45c463ae | 1208 | } |
7405f74b | 1209 | |
45c463ae DW |
1210 | static void dmaengine_unmap(struct kref *kref) |
1211 | { | |
1212 | struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref); | |
1213 | struct device *dev = unmap->dev; | |
1214 | int cnt, i; | |
1215 | ||
1216 | cnt = unmap->to_cnt; | |
1217 | for (i = 0; i < cnt; i++) | |
1218 | dma_unmap_page(dev, unmap->addr[i], unmap->len, | |
1219 | DMA_TO_DEVICE); | |
1220 | cnt += unmap->from_cnt; | |
1221 | for (; i < cnt; i++) | |
1222 | dma_unmap_page(dev, unmap->addr[i], unmap->len, | |
1223 | DMA_FROM_DEVICE); | |
1224 | cnt += unmap->bidi_cnt; | |
7476bd79 DW |
1225 | for (; i < cnt; i++) { |
1226 | if (unmap->addr[i] == 0) | |
1227 | continue; | |
45c463ae DW |
1228 | dma_unmap_page(dev, unmap->addr[i], unmap->len, |
1229 | DMA_BIDIRECTIONAL); | |
7476bd79 | 1230 | } |
c1f43dd9 | 1231 | cnt = unmap->map_cnt; |
45c463ae DW |
1232 | mempool_free(unmap, __get_unmap_pool(cnt)->pool); |
1233 | } | |
7405f74b | 1234 | |
45c463ae DW |
1235 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) |
1236 | { | |
1237 | if (unmap) | |
1238 | kref_put(&unmap->kref, dmaengine_unmap); | |
1239 | } | |
1240 | EXPORT_SYMBOL_GPL(dmaengine_unmap_put); | |
7405f74b | 1241 | |
45c463ae DW |
1242 | static void dmaengine_destroy_unmap_pool(void) |
1243 | { | |
1244 | int i; | |
1245 | ||
1246 | for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { | |
1247 | struct dmaengine_unmap_pool *p = &unmap_pool[i]; | |
1248 | ||
240eb916 | 1249 | mempool_destroy(p->pool); |
45c463ae | 1250 | p->pool = NULL; |
240eb916 | 1251 | kmem_cache_destroy(p->cache); |
45c463ae DW |
1252 | p->cache = NULL; |
1253 | } | |
7405f74b | 1254 | } |
7405f74b | 1255 | |
45c463ae | 1256 | static int __init dmaengine_init_unmap_pool(void) |
7405f74b | 1257 | { |
45c463ae | 1258 | int i; |
7405f74b | 1259 | |
45c463ae DW |
1260 | for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { |
1261 | struct dmaengine_unmap_pool *p = &unmap_pool[i]; | |
1262 | size_t size; | |
0036731c | 1263 | |
45c463ae DW |
1264 | size = sizeof(struct dmaengine_unmap_data) + |
1265 | sizeof(dma_addr_t) * p->size; | |
1266 | ||
1267 | p->cache = kmem_cache_create(p->name, size, 0, | |
1268 | SLAB_HWCACHE_ALIGN, NULL); | |
1269 | if (!p->cache) | |
1270 | break; | |
1271 | p->pool = mempool_create_slab_pool(1, p->cache); | |
1272 | if (!p->pool) | |
1273 | break; | |
0036731c | 1274 | } |
7405f74b | 1275 | |
45c463ae DW |
1276 | if (i == ARRAY_SIZE(unmap_pool)) |
1277 | return 0; | |
7405f74b | 1278 | |
45c463ae DW |
1279 | dmaengine_destroy_unmap_pool(); |
1280 | return -ENOMEM; | |
1281 | } | |
7405f74b | 1282 | |
89716462 | 1283 | struct dmaengine_unmap_data * |
45c463ae DW |
1284 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) |
1285 | { | |
1286 | struct dmaengine_unmap_data *unmap; | |
1287 | ||
1288 | unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags); | |
1289 | if (!unmap) | |
1290 | return NULL; | |
1291 | ||
1292 | memset(unmap, 0, sizeof(*unmap)); | |
1293 | kref_init(&unmap->kref); | |
1294 | unmap->dev = dev; | |
c1f43dd9 | 1295 | unmap->map_cnt = nr; |
45c463ae DW |
1296 | |
1297 | return unmap; | |
7405f74b | 1298 | } |
89716462 | 1299 | EXPORT_SYMBOL(dmaengine_get_unmap_data); |
7405f74b | 1300 | |
7405f74b DW |
1301 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, |
1302 | struct dma_chan *chan) | |
1303 | { | |
1304 | tx->chan = chan; | |
5fc6d897 | 1305 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
7405f74b | 1306 | spin_lock_init(&tx->lock); |
caa20d97 | 1307 | #endif |
7405f74b DW |
1308 | } |
1309 | EXPORT_SYMBOL(dma_async_tx_descriptor_init); | |
1310 | ||
07f2211e DW |
1311 | /* dma_wait_for_async_tx - spin wait for a transaction to complete |
1312 | * @tx: in-flight transaction to wait on | |
07f2211e DW |
1313 | */ |
1314 | enum dma_status | |
1315 | dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
1316 | { | |
95475e57 | 1317 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); |
07f2211e DW |
1318 | |
1319 | if (!tx) | |
adfedd9a | 1320 | return DMA_COMPLETE; |
07f2211e | 1321 | |
95475e57 DW |
1322 | while (tx->cookie == -EBUSY) { |
1323 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
ef859312 JN |
1324 | dev_err(tx->chan->device->dev, |
1325 | "%s timeout waiting for descriptor submission\n", | |
1326 | __func__); | |
95475e57 DW |
1327 | return DMA_ERROR; |
1328 | } | |
1329 | cpu_relax(); | |
1330 | } | |
1331 | return dma_sync_wait(tx->chan, tx->cookie); | |
07f2211e DW |
1332 | } |
1333 | EXPORT_SYMBOL_GPL(dma_wait_for_async_tx); | |
1334 | ||
1335 | /* dma_run_dependencies - helper routine for dma drivers to process | |
1336 | * (start) dependent operations on their target channel | |
1337 | * @tx: transaction with dependencies | |
1338 | */ | |
1339 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx) | |
1340 | { | |
caa20d97 | 1341 | struct dma_async_tx_descriptor *dep = txd_next(tx); |
07f2211e DW |
1342 | struct dma_async_tx_descriptor *dep_next; |
1343 | struct dma_chan *chan; | |
1344 | ||
1345 | if (!dep) | |
1346 | return; | |
1347 | ||
dd59b853 | 1348 | /* we'll submit tx->next now, so clear the link */ |
caa20d97 | 1349 | txd_clear_next(tx); |
07f2211e DW |
1350 | chan = dep->chan; |
1351 | ||
1352 | /* keep submitting up until a channel switch is detected | |
1353 | * in that case we will be called again as a result of | |
1354 | * processing the interrupt from async_tx_channel_switch | |
1355 | */ | |
1356 | for (; dep; dep = dep_next) { | |
caa20d97 DW |
1357 | txd_lock(dep); |
1358 | txd_clear_parent(dep); | |
1359 | dep_next = txd_next(dep); | |
07f2211e | 1360 | if (dep_next && dep_next->chan == chan) |
caa20d97 | 1361 | txd_clear_next(dep); /* ->next will be submitted */ |
07f2211e DW |
1362 | else |
1363 | dep_next = NULL; /* submit current dep and terminate */ | |
caa20d97 | 1364 | txd_unlock(dep); |
07f2211e DW |
1365 | |
1366 | dep->tx_submit(dep); | |
1367 | } | |
1368 | ||
1369 | chan->device->device_issue_pending(chan); | |
1370 | } | |
1371 | EXPORT_SYMBOL_GPL(dma_run_dependencies); | |
1372 | ||
c13c8260 CL |
1373 | static int __init dma_bus_init(void) |
1374 | { | |
45c463ae DW |
1375 | int err = dmaengine_init_unmap_pool(); |
1376 | ||
1377 | if (err) | |
1378 | return err; | |
c13c8260 CL |
1379 | return class_register(&dma_devclass); |
1380 | } | |
652afc27 | 1381 | arch_initcall(dma_bus_init); |
c13c8260 | 1382 | |
bec08513 | 1383 |