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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
d894fc60 AS |
2 | /* |
3 | * Ingenic JZ4780 DMA controller | |
4 | * | |
5 | * Copyright (c) 2015 Imagination Technologies | |
6 | * Author: Alex Smith <alex@alex-smith.me.uk> | |
d894fc60 AS |
7 | */ |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/dmapool.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of.h> | |
6147b032 | 15 | #include <linux/of_device.h> |
d894fc60 AS |
16 | #include <linux/of_dma.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | ||
20 | #include "dmaengine.h" | |
21 | #include "virt-dma.h" | |
22 | ||
d894fc60 | 23 | /* Global registers. */ |
33633583 PC |
24 | #define JZ_DMA_REG_DMAC 0x00 |
25 | #define JZ_DMA_REG_DIRQP 0x04 | |
26 | #define JZ_DMA_REG_DDR 0x08 | |
27 | #define JZ_DMA_REG_DDRS 0x0c | |
29870eb7 PC |
28 | #define JZ_DMA_REG_DCKE 0x10 |
29 | #define JZ_DMA_REG_DCKES 0x14 | |
30 | #define JZ_DMA_REG_DCKEC 0x18 | |
33633583 PC |
31 | #define JZ_DMA_REG_DMACP 0x1c |
32 | #define JZ_DMA_REG_DSIRQP 0x20 | |
33 | #define JZ_DMA_REG_DSIRQM 0x24 | |
34 | #define JZ_DMA_REG_DCIRQP 0x28 | |
35 | #define JZ_DMA_REG_DCIRQM 0x2c | |
d894fc60 AS |
36 | |
37 | /* Per-channel registers. */ | |
38 | #define JZ_DMA_REG_CHAN(n) (n * 0x20) | |
33633583 PC |
39 | #define JZ_DMA_REG_DSA 0x00 |
40 | #define JZ_DMA_REG_DTA 0x04 | |
41 | #define JZ_DMA_REG_DTC 0x08 | |
42 | #define JZ_DMA_REG_DRT 0x0c | |
43 | #define JZ_DMA_REG_DCS 0x10 | |
44 | #define JZ_DMA_REG_DCM 0x14 | |
45 | #define JZ_DMA_REG_DDA 0x18 | |
46 | #define JZ_DMA_REG_DSD 0x1c | |
d894fc60 AS |
47 | |
48 | #define JZ_DMA_DMAC_DMAE BIT(0) | |
49 | #define JZ_DMA_DMAC_AR BIT(2) | |
50 | #define JZ_DMA_DMAC_HLT BIT(3) | |
17a8e30e | 51 | #define JZ_DMA_DMAC_FAIC BIT(27) |
d894fc60 AS |
52 | #define JZ_DMA_DMAC_FMSC BIT(31) |
53 | ||
54 | #define JZ_DMA_DRT_AUTO 0x8 | |
55 | ||
56 | #define JZ_DMA_DCS_CTE BIT(0) | |
57 | #define JZ_DMA_DCS_HLT BIT(2) | |
58 | #define JZ_DMA_DCS_TT BIT(3) | |
59 | #define JZ_DMA_DCS_AR BIT(4) | |
60 | #define JZ_DMA_DCS_DES8 BIT(30) | |
61 | ||
62 | #define JZ_DMA_DCM_LINK BIT(0) | |
63 | #define JZ_DMA_DCM_TIE BIT(1) | |
64 | #define JZ_DMA_DCM_STDE BIT(2) | |
65 | #define JZ_DMA_DCM_TSZ_SHIFT 8 | |
66 | #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT) | |
67 | #define JZ_DMA_DCM_DP_SHIFT 12 | |
68 | #define JZ_DMA_DCM_SP_SHIFT 14 | |
69 | #define JZ_DMA_DCM_DAI BIT(22) | |
70 | #define JZ_DMA_DCM_SAI BIT(23) | |
71 | ||
72 | #define JZ_DMA_SIZE_4_BYTE 0x0 | |
73 | #define JZ_DMA_SIZE_1_BYTE 0x1 | |
74 | #define JZ_DMA_SIZE_2_BYTE 0x2 | |
75 | #define JZ_DMA_SIZE_16_BYTE 0x3 | |
76 | #define JZ_DMA_SIZE_32_BYTE 0x4 | |
77 | #define JZ_DMA_SIZE_64_BYTE 0x5 | |
78 | #define JZ_DMA_SIZE_128_BYTE 0x6 | |
79 | ||
80 | #define JZ_DMA_WIDTH_32_BIT 0x0 | |
81 | #define JZ_DMA_WIDTH_8_BIT 0x1 | |
82 | #define JZ_DMA_WIDTH_16_BIT 0x2 | |
83 | ||
84 | #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
85 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
86 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
87 | ||
33633583 PC |
88 | #define JZ4780_DMA_CTRL_OFFSET 0x1000 |
89 | ||
29870eb7 PC |
90 | /* macros for use with jz4780_dma_soc_data.flags */ |
91 | #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0) | |
92 | #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1) | |
93 | #define JZ_SOC_DATA_PER_CHAN_PM BIT(2) | |
ae9156b6 | 94 | #define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3) |
29870eb7 | 95 | |
d894fc60 AS |
96 | /** |
97 | * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller. | |
98 | * @dcm: value for the DCM (channel command) register | |
99 | * @dsa: source address | |
100 | * @dta: target address | |
101 | * @dtc: transfer count (number of blocks of the transfer size specified in DCM | |
102 | * to transfer) in the low 24 bits, offset of the next descriptor from the | |
103 | * descriptor base address in the upper 8 bits. | |
d894fc60 AS |
104 | */ |
105 | struct jz4780_dma_hwdesc { | |
106 | uint32_t dcm; | |
107 | uint32_t dsa; | |
108 | uint32_t dta; | |
109 | uint32_t dtc; | |
d894fc60 AS |
110 | }; |
111 | ||
112 | /* Size of allocations for hardware descriptor blocks. */ | |
113 | #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE | |
114 | #define JZ_DMA_MAX_DESC \ | |
115 | (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc)) | |
116 | ||
117 | struct jz4780_dma_desc { | |
118 | struct virt_dma_desc vdesc; | |
119 | ||
120 | struct jz4780_dma_hwdesc *desc; | |
121 | dma_addr_t desc_phys; | |
122 | unsigned int count; | |
123 | enum dma_transaction_type type; | |
124 | uint32_t status; | |
125 | }; | |
126 | ||
127 | struct jz4780_dma_chan { | |
128 | struct virt_dma_chan vchan; | |
129 | unsigned int id; | |
130 | struct dma_pool *desc_pool; | |
131 | ||
132 | uint32_t transfer_type; | |
133 | uint32_t transfer_shift; | |
134 | struct dma_slave_config config; | |
135 | ||
136 | struct jz4780_dma_desc *desc; | |
137 | unsigned int curr_hwdesc; | |
138 | }; | |
139 | ||
6147b032 PC |
140 | struct jz4780_dma_soc_data { |
141 | unsigned int nb_channels; | |
29870eb7 PC |
142 | unsigned int transfer_ord_max; |
143 | unsigned long flags; | |
6147b032 PC |
144 | }; |
145 | ||
d894fc60 AS |
146 | struct jz4780_dma_dev { |
147 | struct dma_device dma_device; | |
33633583 PC |
148 | void __iomem *chn_base; |
149 | void __iomem *ctrl_base; | |
d894fc60 AS |
150 | struct clk *clk; |
151 | unsigned int irq; | |
6147b032 | 152 | const struct jz4780_dma_soc_data *soc_data; |
d894fc60 AS |
153 | |
154 | uint32_t chan_reserved; | |
6147b032 | 155 | struct jz4780_dma_chan chan[]; |
d894fc60 AS |
156 | }; |
157 | ||
026fd406 AS |
158 | struct jz4780_dma_filter_data { |
159 | struct device_node *of_node; | |
d894fc60 AS |
160 | uint32_t transfer_type; |
161 | int channel; | |
162 | }; | |
163 | ||
164 | static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan) | |
165 | { | |
166 | return container_of(chan, struct jz4780_dma_chan, vchan.chan); | |
167 | } | |
168 | ||
169 | static inline struct jz4780_dma_desc *to_jz4780_dma_desc( | |
170 | struct virt_dma_desc *vdesc) | |
171 | { | |
172 | return container_of(vdesc, struct jz4780_dma_desc, vdesc); | |
173 | } | |
174 | ||
175 | static inline struct jz4780_dma_dev *jz4780_dma_chan_parent( | |
176 | struct jz4780_dma_chan *jzchan) | |
177 | { | |
178 | return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev, | |
179 | dma_device); | |
180 | } | |
181 | ||
33633583 PC |
182 | static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma, |
183 | unsigned int chn, unsigned int reg) | |
184 | { | |
185 | return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); | |
186 | } | |
187 | ||
188 | static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma, | |
189 | unsigned int chn, unsigned int reg, uint32_t val) | |
190 | { | |
191 | writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); | |
192 | } | |
193 | ||
194 | static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma, | |
d894fc60 AS |
195 | unsigned int reg) |
196 | { | |
33633583 | 197 | return readl(jzdma->ctrl_base + reg); |
d894fc60 AS |
198 | } |
199 | ||
33633583 | 200 | static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma, |
d894fc60 AS |
201 | unsigned int reg, uint32_t val) |
202 | { | |
33633583 | 203 | writel(val, jzdma->ctrl_base + reg); |
d894fc60 AS |
204 | } |
205 | ||
29870eb7 PC |
206 | static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, |
207 | unsigned int chn) | |
208 | { | |
ae9156b6 PC |
209 | if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) { |
210 | unsigned int reg; | |
211 | ||
212 | if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC) | |
213 | reg = JZ_DMA_REG_DCKE; | |
214 | else | |
215 | reg = JZ_DMA_REG_DCKES; | |
216 | ||
217 | jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn)); | |
218 | } | |
29870eb7 PC |
219 | } |
220 | ||
221 | static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, | |
222 | unsigned int chn) | |
223 | { | |
ae9156b6 PC |
224 | if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) && |
225 | !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)) | |
29870eb7 | 226 | jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn)); |
d894fc60 AS |
227 | } |
228 | ||
229 | static struct jz4780_dma_desc *jz4780_dma_desc_alloc( | |
230 | struct jz4780_dma_chan *jzchan, unsigned int count, | |
231 | enum dma_transaction_type type) | |
232 | { | |
233 | struct jz4780_dma_desc *desc; | |
234 | ||
235 | if (count > JZ_DMA_MAX_DESC) | |
236 | return NULL; | |
237 | ||
238 | desc = kzalloc(sizeof(*desc), GFP_NOWAIT); | |
239 | if (!desc) | |
240 | return NULL; | |
241 | ||
242 | desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT, | |
243 | &desc->desc_phys); | |
244 | if (!desc->desc) { | |
245 | kfree(desc); | |
246 | return NULL; | |
247 | } | |
248 | ||
249 | desc->count = count; | |
250 | desc->type = type; | |
251 | return desc; | |
252 | } | |
253 | ||
254 | static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc) | |
255 | { | |
256 | struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc); | |
257 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan); | |
258 | ||
259 | dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys); | |
260 | kfree(desc); | |
261 | } | |
262 | ||
29870eb7 PC |
263 | static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan, |
264 | unsigned long val, uint32_t *shift) | |
d894fc60 | 265 | { |
29870eb7 | 266 | struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); |
dc578f31 | 267 | int ord = ffs(val) - 1; |
d894fc60 | 268 | |
dc578f31 AS |
269 | /* |
270 | * 8 byte transfer sizes unsupported so fall back on 4. If it's larger | |
271 | * than the maximum, just limit it. It is perfectly safe to fall back | |
272 | * in this way since we won't exceed the maximum burst size supported | |
273 | * by the device, the only effect is reduced efficiency. This is better | |
274 | * than refusing to perform the request at all. | |
275 | */ | |
276 | if (ord == 3) | |
277 | ord = 2; | |
29870eb7 PC |
278 | else if (ord > jzdma->soc_data->transfer_ord_max) |
279 | ord = jzdma->soc_data->transfer_ord_max; | |
dc578f31 AS |
280 | |
281 | *shift = ord; | |
282 | ||
283 | switch (ord) { | |
d894fc60 AS |
284 | case 0: |
285 | return JZ_DMA_SIZE_1_BYTE; | |
286 | case 1: | |
287 | return JZ_DMA_SIZE_2_BYTE; | |
288 | case 2: | |
289 | return JZ_DMA_SIZE_4_BYTE; | |
290 | case 4: | |
291 | return JZ_DMA_SIZE_16_BYTE; | |
292 | case 5: | |
293 | return JZ_DMA_SIZE_32_BYTE; | |
294 | case 6: | |
295 | return JZ_DMA_SIZE_64_BYTE; | |
d894fc60 | 296 | default: |
dc578f31 | 297 | return JZ_DMA_SIZE_128_BYTE; |
d894fc60 AS |
298 | } |
299 | } | |
300 | ||
839896ef | 301 | static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan, |
d894fc60 AS |
302 | struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len, |
303 | enum dma_transfer_direction direction) | |
304 | { | |
305 | struct dma_slave_config *config = &jzchan->config; | |
306 | uint32_t width, maxburst, tsz; | |
d894fc60 AS |
307 | |
308 | if (direction == DMA_MEM_TO_DEV) { | |
309 | desc->dcm = JZ_DMA_DCM_SAI; | |
310 | desc->dsa = addr; | |
311 | desc->dta = config->dst_addr; | |
d894fc60 AS |
312 | |
313 | width = config->dst_addr_width; | |
314 | maxburst = config->dst_maxburst; | |
315 | } else { | |
316 | desc->dcm = JZ_DMA_DCM_DAI; | |
317 | desc->dsa = config->src_addr; | |
318 | desc->dta = addr; | |
d894fc60 AS |
319 | |
320 | width = config->src_addr_width; | |
321 | maxburst = config->src_maxburst; | |
322 | } | |
323 | ||
324 | /* | |
325 | * This calculates the maximum transfer size that can be used with the | |
326 | * given address, length, width and maximum burst size. The address | |
327 | * must be aligned to the transfer size, the total length must be | |
328 | * divisible by the transfer size, and we must not use more than the | |
329 | * maximum burst specified by the user. | |
330 | */ | |
29870eb7 | 331 | tsz = jz4780_dma_transfer_size(jzchan, addr | len | (width * maxburst), |
dc578f31 | 332 | &jzchan->transfer_shift); |
d894fc60 AS |
333 | |
334 | switch (width) { | |
335 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
336 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
337 | break; | |
338 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
339 | width = JZ_DMA_WIDTH_32_BIT; | |
340 | break; | |
341 | default: | |
342 | return -EINVAL; | |
343 | } | |
344 | ||
345 | desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT; | |
346 | desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT; | |
347 | desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT; | |
348 | ||
dc578f31 | 349 | desc->dtc = len >> jzchan->transfer_shift; |
839896ef | 350 | return 0; |
d894fc60 AS |
351 | } |
352 | ||
353 | static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg( | |
354 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
46fa5168 AS |
355 | enum dma_transfer_direction direction, unsigned long flags, |
356 | void *context) | |
d894fc60 AS |
357 | { |
358 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
359 | struct jz4780_dma_desc *desc; | |
360 | unsigned int i; | |
361 | int err; | |
362 | ||
363 | desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE); | |
364 | if (!desc) | |
365 | return NULL; | |
366 | ||
367 | for (i = 0; i < sg_len; i++) { | |
368 | err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], | |
839896ef AS |
369 | sg_dma_address(&sgl[i]), |
370 | sg_dma_len(&sgl[i]), | |
371 | direction); | |
fc878efe CIK |
372 | if (err < 0) { |
373 | jz4780_dma_desc_free(&jzchan->desc->vdesc); | |
839896ef | 374 | return NULL; |
fc878efe | 375 | } |
d894fc60 AS |
376 | |
377 | desc->desc[i].dcm |= JZ_DMA_DCM_TIE; | |
378 | ||
379 | if (i != (sg_len - 1)) { | |
380 | /* Automatically proceeed to the next descriptor. */ | |
381 | desc->desc[i].dcm |= JZ_DMA_DCM_LINK; | |
382 | ||
383 | /* | |
384 | * The upper 8 bits of the DTC field in the descriptor | |
385 | * must be set to (offset from descriptor base of next | |
386 | * descriptor >> 4). | |
387 | */ | |
388 | desc->desc[i].dtc |= | |
389 | (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; | |
390 | } | |
391 | } | |
392 | ||
393 | return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); | |
394 | } | |
395 | ||
396 | static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic( | |
397 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
398 | size_t period_len, enum dma_transfer_direction direction, | |
399 | unsigned long flags) | |
400 | { | |
401 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
402 | struct jz4780_dma_desc *desc; | |
403 | unsigned int periods, i; | |
404 | int err; | |
405 | ||
406 | if (buf_len % period_len) | |
407 | return NULL; | |
408 | ||
409 | periods = buf_len / period_len; | |
410 | ||
411 | desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC); | |
412 | if (!desc) | |
413 | return NULL; | |
414 | ||
415 | for (i = 0; i < periods; i++) { | |
416 | err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr, | |
839896ef | 417 | period_len, direction); |
fc878efe CIK |
418 | if (err < 0) { |
419 | jz4780_dma_desc_free(&jzchan->desc->vdesc); | |
839896ef | 420 | return NULL; |
fc878efe | 421 | } |
d894fc60 AS |
422 | |
423 | buf_addr += period_len; | |
424 | ||
425 | /* | |
426 | * Set the link bit to indicate that the controller should | |
427 | * automatically proceed to the next descriptor. In | |
428 | * jz4780_dma_begin(), this will be cleared if we need to issue | |
429 | * an interrupt after each period. | |
430 | */ | |
431 | desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK; | |
432 | ||
433 | /* | |
434 | * The upper 8 bits of the DTC field in the descriptor must be | |
435 | * set to (offset from descriptor base of next descriptor >> 4). | |
436 | * If this is the last descriptor, link it back to the first, | |
437 | * i.e. leave offset set to 0, otherwise point to the next one. | |
438 | */ | |
439 | if (i != (periods - 1)) { | |
440 | desc->desc[i].dtc |= | |
441 | (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; | |
442 | } | |
443 | } | |
444 | ||
445 | return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); | |
446 | } | |
447 | ||
4f5db8c8 | 448 | static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( |
d894fc60 AS |
449 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
450 | size_t len, unsigned long flags) | |
451 | { | |
452 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
453 | struct jz4780_dma_desc *desc; | |
454 | uint32_t tsz; | |
d894fc60 AS |
455 | |
456 | desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY); | |
457 | if (!desc) | |
458 | return NULL; | |
459 | ||
29870eb7 | 460 | tsz = jz4780_dma_transfer_size(jzchan, dest | src | len, |
dc578f31 | 461 | &jzchan->transfer_shift); |
d894fc60 | 462 | |
5eed7d84 PC |
463 | jzchan->transfer_type = JZ_DMA_DRT_AUTO; |
464 | ||
d894fc60 AS |
465 | desc->desc[0].dsa = src; |
466 | desc->desc[0].dta = dest; | |
d894fc60 AS |
467 | desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI | |
468 | tsz << JZ_DMA_DCM_TSZ_SHIFT | | |
469 | JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT | | |
470 | JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT; | |
839896ef | 471 | desc->desc[0].dtc = len >> jzchan->transfer_shift; |
d894fc60 AS |
472 | |
473 | return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); | |
474 | } | |
475 | ||
476 | static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) | |
477 | { | |
478 | struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); | |
479 | struct virt_dma_desc *vdesc; | |
480 | unsigned int i; | |
481 | dma_addr_t desc_phys; | |
482 | ||
483 | if (!jzchan->desc) { | |
484 | vdesc = vchan_next_desc(&jzchan->vchan); | |
485 | if (!vdesc) | |
486 | return; | |
487 | ||
488 | list_del(&vdesc->node); | |
489 | ||
490 | jzchan->desc = to_jz4780_dma_desc(vdesc); | |
491 | jzchan->curr_hwdesc = 0; | |
492 | ||
493 | if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) { | |
494 | /* | |
495 | * The DMA controller doesn't support triggering an | |
496 | * interrupt after processing each descriptor, only | |
497 | * after processing an entire terminated list of | |
498 | * descriptors. For a cyclic DMA setup the list of | |
499 | * descriptors is not terminated so we can never get an | |
500 | * interrupt. | |
501 | * | |
502 | * If the user requested a callback for a cyclic DMA | |
503 | * setup then we workaround this hardware limitation | |
504 | * here by degrading to a set of unlinked descriptors | |
505 | * which we will submit in sequence in response to the | |
506 | * completion of processing the previous descriptor. | |
507 | */ | |
508 | for (i = 0; i < jzchan->desc->count; i++) | |
509 | jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK; | |
510 | } | |
511 | } else { | |
512 | /* | |
513 | * There is an existing transfer, therefore this must be one | |
514 | * for which we unlinked the descriptors above. Advance to the | |
515 | * next one in the list. | |
516 | */ | |
517 | jzchan->curr_hwdesc = | |
518 | (jzchan->curr_hwdesc + 1) % jzchan->desc->count; | |
519 | } | |
520 | ||
29870eb7 PC |
521 | /* Enable the channel's clock. */ |
522 | jz4780_dma_chan_enable(jzdma, jzchan->id); | |
523 | ||
5eed7d84 PC |
524 | /* Use 4-word descriptors. */ |
525 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); | |
526 | ||
527 | /* Set transfer type. */ | |
528 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT, | |
529 | jzchan->transfer_type); | |
d894fc60 | 530 | |
9e4e3a4c DS |
531 | /* |
532 | * Set the transfer count. This is redundant for a descriptor-driven | |
533 | * transfer. However, there can be a delay between the transfer start | |
534 | * time and when DTCn reg contains the new transfer count. Setting | |
535 | * it explicitly ensures residue is computed correctly at all times. | |
536 | */ | |
537 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC, | |
538 | jzchan->desc->desc[jzchan->curr_hwdesc].dtc); | |
d894fc60 AS |
539 | |
540 | /* Write descriptor address and initiate descriptor fetch. */ | |
541 | desc_phys = jzchan->desc->desc_phys + | |
542 | (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc)); | |
33633583 PC |
543 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys); |
544 | jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id)); | |
d894fc60 AS |
545 | |
546 | /* Enable the channel. */ | |
33633583 | 547 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, |
5eed7d84 | 548 | JZ_DMA_DCS_CTE); |
d894fc60 AS |
549 | } |
550 | ||
551 | static void jz4780_dma_issue_pending(struct dma_chan *chan) | |
552 | { | |
553 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
554 | unsigned long flags; | |
555 | ||
556 | spin_lock_irqsave(&jzchan->vchan.lock, flags); | |
557 | ||
558 | if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc) | |
559 | jz4780_dma_begin(jzchan); | |
560 | ||
561 | spin_unlock_irqrestore(&jzchan->vchan.lock, flags); | |
562 | } | |
563 | ||
46fa5168 | 564 | static int jz4780_dma_terminate_all(struct dma_chan *chan) |
d894fc60 | 565 | { |
46fa5168 | 566 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); |
d894fc60 AS |
567 | struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); |
568 | unsigned long flags; | |
569 | LIST_HEAD(head); | |
570 | ||
571 | spin_lock_irqsave(&jzchan->vchan.lock, flags); | |
572 | ||
573 | /* Clear the DMA status and stop the transfer. */ | |
33633583 | 574 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); |
d894fc60 | 575 | if (jzchan->desc) { |
f0dd52c8 | 576 | vchan_terminate_vdesc(&jzchan->desc->vdesc); |
d894fc60 AS |
577 | jzchan->desc = NULL; |
578 | } | |
579 | ||
29870eb7 PC |
580 | jz4780_dma_chan_disable(jzdma, jzchan->id); |
581 | ||
d894fc60 AS |
582 | vchan_get_all_descriptors(&jzchan->vchan, &head); |
583 | ||
584 | spin_unlock_irqrestore(&jzchan->vchan.lock, flags); | |
585 | ||
586 | vchan_dma_desc_free_list(&jzchan->vchan, &head); | |
587 | return 0; | |
588 | } | |
589 | ||
f0dd52c8 PU |
590 | static void jz4780_dma_synchronize(struct dma_chan *chan) |
591 | { | |
592 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
29870eb7 | 593 | struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); |
f0dd52c8 PU |
594 | |
595 | vchan_synchronize(&jzchan->vchan); | |
29870eb7 | 596 | jz4780_dma_chan_disable(jzdma, jzchan->id); |
f0dd52c8 PU |
597 | } |
598 | ||
46fa5168 AS |
599 | static int jz4780_dma_config(struct dma_chan *chan, |
600 | struct dma_slave_config *config) | |
d894fc60 | 601 | { |
46fa5168 AS |
602 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); |
603 | ||
d894fc60 AS |
604 | if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
605 | || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)) | |
606 | return -EINVAL; | |
607 | ||
608 | /* Copy the reset of the slave configuration, it is used later. */ | |
609 | memcpy(&jzchan->config, config, sizeof(jzchan->config)); | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan, | |
615 | struct jz4780_dma_desc *desc, unsigned int next_sg) | |
616 | { | |
617 | struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); | |
f3c045df | 618 | unsigned int count = 0; |
d894fc60 AS |
619 | unsigned int i; |
620 | ||
d894fc60 | 621 | for (i = next_sg; i < desc->count; i++) |
f3c045df | 622 | count += desc->desc[i].dtc & GENMASK(23, 0); |
d894fc60 | 623 | |
f3c045df DS |
624 | if (next_sg != 0) |
625 | count += jz4780_dma_chn_readl(jzdma, jzchan->id, | |
33633583 | 626 | JZ_DMA_REG_DTC); |
d894fc60 | 627 | |
f3c045df | 628 | return count << jzchan->transfer_shift; |
d894fc60 AS |
629 | } |
630 | ||
631 | static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan, | |
632 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
633 | { | |
634 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
635 | struct virt_dma_desc *vdesc; | |
636 | enum dma_status status; | |
637 | unsigned long flags; | |
1f0b0f23 | 638 | unsigned long residue = 0; |
d894fc60 AS |
639 | |
640 | status = dma_cookie_status(chan, cookie, txstate); | |
641 | if ((status == DMA_COMPLETE) || (txstate == NULL)) | |
642 | return status; | |
643 | ||
644 | spin_lock_irqsave(&jzchan->vchan.lock, flags); | |
645 | ||
646 | vdesc = vchan_find_desc(&jzchan->vchan, cookie); | |
647 | if (vdesc) { | |
648 | /* On the issued list, so hasn't been processed yet */ | |
1f0b0f23 | 649 | residue = jz4780_dma_desc_residue(jzchan, |
d894fc60 AS |
650 | to_jz4780_dma_desc(vdesc), 0); |
651 | } else if (cookie == jzchan->desc->vdesc.tx.cookie) { | |
1f0b0f23 | 652 | residue = jz4780_dma_desc_residue(jzchan, jzchan->desc, |
83ef4fb7 | 653 | jzchan->curr_hwdesc + 1); |
1f0b0f23 DS |
654 | } |
655 | dma_set_residue(txstate, residue); | |
d894fc60 AS |
656 | |
657 | if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc | |
839896ef AS |
658 | && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) |
659 | status = DMA_ERROR; | |
d894fc60 AS |
660 | |
661 | spin_unlock_irqrestore(&jzchan->vchan.lock, flags); | |
662 | return status; | |
663 | } | |
664 | ||
4e4106f5 PC |
665 | static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma, |
666 | struct jz4780_dma_chan *jzchan) | |
d894fc60 AS |
667 | { |
668 | uint32_t dcs; | |
4e4106f5 | 669 | bool ack = true; |
d894fc60 AS |
670 | |
671 | spin_lock(&jzchan->vchan.lock); | |
672 | ||
33633583 PC |
673 | dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS); |
674 | jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); | |
d894fc60 AS |
675 | |
676 | if (dcs & JZ_DMA_DCS_AR) { | |
677 | dev_warn(&jzchan->vchan.chan.dev->device, | |
678 | "address error (DCS=0x%x)\n", dcs); | |
679 | } | |
680 | ||
681 | if (dcs & JZ_DMA_DCS_HLT) { | |
682 | dev_warn(&jzchan->vchan.chan.dev->device, | |
683 | "channel halt (DCS=0x%x)\n", dcs); | |
684 | } | |
685 | ||
686 | if (jzchan->desc) { | |
687 | jzchan->desc->status = dcs; | |
688 | ||
689 | if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) { | |
690 | if (jzchan->desc->type == DMA_CYCLIC) { | |
691 | vchan_cyclic_callback(&jzchan->desc->vdesc); | |
4e4106f5 PC |
692 | |
693 | jz4780_dma_begin(jzchan); | |
694 | } else if (dcs & JZ_DMA_DCS_TT) { | |
d894fc60 AS |
695 | vchan_cookie_complete(&jzchan->desc->vdesc); |
696 | jzchan->desc = NULL; | |
d894fc60 | 697 | |
4e4106f5 PC |
698 | jz4780_dma_begin(jzchan); |
699 | } else { | |
700 | /* False positive - continue the transfer */ | |
701 | ack = false; | |
702 | jz4780_dma_chn_writel(jzdma, jzchan->id, | |
703 | JZ_DMA_REG_DCS, | |
704 | JZ_DMA_DCS_CTE); | |
705 | } | |
d894fc60 AS |
706 | } |
707 | } else { | |
708 | dev_err(&jzchan->vchan.chan.dev->device, | |
709 | "channel IRQ with no active transfer\n"); | |
710 | } | |
711 | ||
712 | spin_unlock(&jzchan->vchan.lock); | |
4e4106f5 PC |
713 | |
714 | return ack; | |
d894fc60 AS |
715 | } |
716 | ||
717 | static irqreturn_t jz4780_dma_irq_handler(int irq, void *data) | |
718 | { | |
719 | struct jz4780_dma_dev *jzdma = data; | |
4e4106f5 | 720 | unsigned int nb_channels = jzdma->soc_data->nb_channels; |
d894fc60 AS |
721 | uint32_t pending, dmac; |
722 | int i; | |
723 | ||
33633583 | 724 | pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP); |
d894fc60 | 725 | |
4e4106f5 PC |
726 | for_each_set_bit(i, (unsigned long *)&pending, nb_channels) { |
727 | if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i])) | |
728 | pending &= ~BIT(i); | |
d894fc60 AS |
729 | } |
730 | ||
731 | /* Clear halt and address error status of all channels. */ | |
33633583 | 732 | dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC); |
d894fc60 | 733 | dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR); |
33633583 | 734 | jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac); |
d894fc60 AS |
735 | |
736 | /* Clear interrupt pending status. */ | |
4e4106f5 | 737 | jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending); |
d894fc60 AS |
738 | |
739 | return IRQ_HANDLED; | |
740 | } | |
741 | ||
742 | static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan) | |
743 | { | |
744 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
745 | ||
746 | jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device), | |
747 | chan->device->dev, | |
748 | JZ_DMA_DESC_BLOCK_SIZE, | |
749 | PAGE_SIZE, 0); | |
750 | if (!jzchan->desc_pool) { | |
751 | dev_err(&chan->dev->device, | |
752 | "failed to allocate descriptor pool\n"); | |
753 | return -ENOMEM; | |
754 | } | |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
759 | static void jz4780_dma_free_chan_resources(struct dma_chan *chan) | |
760 | { | |
761 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
762 | ||
763 | vchan_free_chan_resources(&jzchan->vchan); | |
764 | dma_pool_destroy(jzchan->desc_pool); | |
765 | jzchan->desc_pool = NULL; | |
766 | } | |
767 | ||
768 | static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param) | |
769 | { | |
770 | struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); | |
771 | struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); | |
026fd406 AS |
772 | struct jz4780_dma_filter_data *data = param; |
773 | ||
774 | if (jzdma->dma_device.dev->of_node != data->of_node) | |
775 | return false; | |
d894fc60 AS |
776 | |
777 | if (data->channel > -1) { | |
778 | if (data->channel != jzchan->id) | |
779 | return false; | |
780 | } else if (jzdma->chan_reserved & BIT(jzchan->id)) { | |
781 | return false; | |
782 | } | |
783 | ||
784 | jzchan->transfer_type = data->transfer_type; | |
785 | ||
786 | return true; | |
787 | } | |
788 | ||
789 | static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, | |
790 | struct of_dma *ofdma) | |
791 | { | |
792 | struct jz4780_dma_dev *jzdma = ofdma->of_dma_data; | |
793 | dma_cap_mask_t mask = jzdma->dma_device.cap_mask; | |
026fd406 | 794 | struct jz4780_dma_filter_data data; |
d894fc60 AS |
795 | |
796 | if (dma_spec->args_count != 2) | |
797 | return NULL; | |
798 | ||
026fd406 | 799 | data.of_node = ofdma->of_node; |
d894fc60 AS |
800 | data.transfer_type = dma_spec->args[0]; |
801 | data.channel = dma_spec->args[1]; | |
802 | ||
803 | if (data.channel > -1) { | |
6147b032 | 804 | if (data.channel >= jzdma->soc_data->nb_channels) { |
d894fc60 AS |
805 | dev_err(jzdma->dma_device.dev, |
806 | "device requested non-existent channel %u\n", | |
807 | data.channel); | |
808 | return NULL; | |
809 | } | |
810 | ||
811 | /* Can only select a channel marked as reserved. */ | |
812 | if (!(jzdma->chan_reserved & BIT(data.channel))) { | |
813 | dev_err(jzdma->dma_device.dev, | |
814 | "device requested unreserved channel %u\n", | |
815 | data.channel); | |
816 | return NULL; | |
817 | } | |
d894fc60 | 818 | |
d3273e10 AS |
819 | jzdma->chan[data.channel].transfer_type = data.transfer_type; |
820 | ||
821 | return dma_get_slave_channel( | |
822 | &jzdma->chan[data.channel].vchan.chan); | |
823 | } else { | |
824 | return dma_request_channel(mask, jz4780_dma_filter_fn, &data); | |
825 | } | |
d894fc60 AS |
826 | } |
827 | ||
828 | static int jz4780_dma_probe(struct platform_device *pdev) | |
829 | { | |
830 | struct device *dev = &pdev->dev; | |
6147b032 | 831 | const struct jz4780_dma_soc_data *soc_data; |
d894fc60 AS |
832 | struct jz4780_dma_dev *jzdma; |
833 | struct jz4780_dma_chan *jzchan; | |
834 | struct dma_device *dd; | |
835 | struct resource *res; | |
836 | int i, ret; | |
837 | ||
54f919a0 PC |
838 | if (!dev->of_node) { |
839 | dev_err(dev, "This driver must be probed from devicetree\n"); | |
840 | return -EINVAL; | |
841 | } | |
842 | ||
6147b032 PC |
843 | soc_data = device_get_match_data(dev); |
844 | if (!soc_data) | |
845 | return -EINVAL; | |
846 | ||
ed414d58 GS |
847 | jzdma = devm_kzalloc(dev, struct_size(jzdma, chan, |
848 | soc_data->nb_channels), GFP_KERNEL); | |
d894fc60 AS |
849 | if (!jzdma) |
850 | return -ENOMEM; | |
851 | ||
6147b032 | 852 | jzdma->soc_data = soc_data; |
d894fc60 AS |
853 | platform_set_drvdata(pdev, jzdma); |
854 | ||
855 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
856 | if (!res) { | |
857 | dev_err(dev, "failed to get I/O memory\n"); | |
858 | return -EINVAL; | |
859 | } | |
860 | ||
33633583 PC |
861 | jzdma->chn_base = devm_ioremap_resource(dev, res); |
862 | if (IS_ERR(jzdma->chn_base)) | |
863 | return PTR_ERR(jzdma->chn_base); | |
864 | ||
865 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
866 | if (res) { | |
867 | jzdma->ctrl_base = devm_ioremap_resource(dev, res); | |
868 | if (IS_ERR(jzdma->ctrl_base)) | |
869 | return PTR_ERR(jzdma->ctrl_base); | |
29870eb7 | 870 | } else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) { |
33633583 PC |
871 | /* |
872 | * On JZ4780, if the second memory resource was not supplied, | |
873 | * assume we're using an old devicetree, and calculate the | |
874 | * offset to the control registers. | |
875 | */ | |
876 | jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET; | |
29870eb7 PC |
877 | } else { |
878 | dev_err(dev, "failed to get I/O memory\n"); | |
879 | return -EINVAL; | |
33633583 | 880 | } |
d894fc60 | 881 | |
839896ef AS |
882 | ret = platform_get_irq(pdev, 0); |
883 | if (ret < 0) { | |
d894fc60 | 884 | dev_err(dev, "failed to get IRQ: %d\n", ret); |
839896ef | 885 | return ret; |
d894fc60 AS |
886 | } |
887 | ||
839896ef AS |
888 | jzdma->irq = ret; |
889 | ||
d509a83c AS |
890 | ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev), |
891 | jzdma); | |
d894fc60 AS |
892 | if (ret) { |
893 | dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq); | |
839896ef | 894 | return ret; |
d894fc60 AS |
895 | } |
896 | ||
897 | jzdma->clk = devm_clk_get(dev, NULL); | |
898 | if (IS_ERR(jzdma->clk)) { | |
899 | dev_err(dev, "failed to get clock\n"); | |
d509a83c AS |
900 | ret = PTR_ERR(jzdma->clk); |
901 | goto err_free_irq; | |
d894fc60 AS |
902 | } |
903 | ||
904 | clk_prepare_enable(jzdma->clk); | |
905 | ||
906 | /* Property is optional, if it doesn't exist the value will remain 0. */ | |
907 | of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels", | |
908 | 0, &jzdma->chan_reserved); | |
909 | ||
910 | dd = &jzdma->dma_device; | |
911 | ||
912 | dma_cap_set(DMA_MEMCPY, dd->cap_mask); | |
913 | dma_cap_set(DMA_SLAVE, dd->cap_mask); | |
914 | dma_cap_set(DMA_CYCLIC, dd->cap_mask); | |
915 | ||
916 | dd->dev = dev; | |
77a68e56 | 917 | dd->copy_align = DMAENGINE_ALIGN_4_BYTES; |
d894fc60 AS |
918 | dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources; |
919 | dd->device_free_chan_resources = jz4780_dma_free_chan_resources; | |
920 | dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg; | |
921 | dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic; | |
922 | dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy; | |
46fa5168 | 923 | dd->device_config = jz4780_dma_config; |
d894fc60 | 924 | dd->device_terminate_all = jz4780_dma_terminate_all; |
f0dd52c8 | 925 | dd->device_synchronize = jz4780_dma_synchronize; |
d894fc60 AS |
926 | dd->device_tx_status = jz4780_dma_tx_status; |
927 | dd->device_issue_pending = jz4780_dma_issue_pending; | |
928 | dd->src_addr_widths = JZ_DMA_BUSWIDTHS; | |
929 | dd->dst_addr_widths = JZ_DMA_BUSWIDTHS; | |
930 | dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
931 | dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
932 | ||
d894fc60 AS |
933 | /* |
934 | * Enable DMA controller, mark all channels as not programmable. | |
935 | * Also set the FMSC bit - it increases MSC performance, so it makes | |
936 | * little sense not to enable it. | |
937 | */ | |
17a8e30e PC |
938 | jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, JZ_DMA_DMAC_DMAE | |
939 | JZ_DMA_DMAC_FAIC | JZ_DMA_DMAC_FMSC); | |
29870eb7 PC |
940 | |
941 | if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA) | |
942 | jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0); | |
d894fc60 AS |
943 | |
944 | INIT_LIST_HEAD(&dd->channels); | |
945 | ||
6147b032 | 946 | for (i = 0; i < soc_data->nb_channels; i++) { |
d894fc60 AS |
947 | jzchan = &jzdma->chan[i]; |
948 | jzchan->id = i; | |
949 | ||
950 | vchan_init(&jzchan->vchan, dd); | |
951 | jzchan->vchan.desc_free = jz4780_dma_desc_free; | |
952 | } | |
953 | ||
0f5a5e57 | 954 | ret = dmaenginem_async_device_register(dd); |
d894fc60 AS |
955 | if (ret) { |
956 | dev_err(dev, "failed to register device\n"); | |
957 | goto err_disable_clk; | |
958 | } | |
959 | ||
960 | /* Register with OF DMA helpers. */ | |
961 | ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate, | |
962 | jzdma); | |
963 | if (ret) { | |
964 | dev_err(dev, "failed to register OF DMA controller\n"); | |
0f5a5e57 | 965 | goto err_disable_clk; |
d894fc60 AS |
966 | } |
967 | ||
968 | dev_info(dev, "JZ4780 DMA controller initialised\n"); | |
969 | return 0; | |
970 | ||
d894fc60 AS |
971 | err_disable_clk: |
972 | clk_disable_unprepare(jzdma->clk); | |
d509a83c AS |
973 | |
974 | err_free_irq: | |
975 | free_irq(jzdma->irq, jzdma); | |
d894fc60 AS |
976 | return ret; |
977 | } | |
978 | ||
979 | static int jz4780_dma_remove(struct platform_device *pdev) | |
980 | { | |
981 | struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev); | |
ae9c02b4 | 982 | int i; |
d894fc60 AS |
983 | |
984 | of_dma_controller_free(pdev->dev.of_node); | |
ae9c02b4 | 985 | |
d509a83c | 986 | free_irq(jzdma->irq, jzdma); |
ae9c02b4 | 987 | |
6147b032 | 988 | for (i = 0; i < jzdma->soc_data->nb_channels; i++) |
ae9c02b4 AS |
989 | tasklet_kill(&jzdma->chan[i].vchan.task); |
990 | ||
d894fc60 AS |
991 | return 0; |
992 | } | |
993 | ||
ffaaa8cc PC |
994 | static const struct jz4780_dma_soc_data jz4740_dma_soc_data = { |
995 | .nb_channels = 6, | |
996 | .transfer_ord_max = 5, | |
997 | }; | |
998 | ||
ae9156b6 PC |
999 | static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = { |
1000 | .nb_channels = 6, | |
1001 | .transfer_ord_max = 5, | |
1002 | .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC, | |
1003 | }; | |
1004 | ||
29870eb7 PC |
1005 | static const struct jz4780_dma_soc_data jz4770_dma_soc_data = { |
1006 | .nb_channels = 6, | |
1007 | .transfer_ord_max = 6, | |
1008 | .flags = JZ_SOC_DATA_PER_CHAN_PM, | |
1009 | }; | |
1010 | ||
6147b032 PC |
1011 | static const struct jz4780_dma_soc_data jz4780_dma_soc_data = { |
1012 | .nb_channels = 32, | |
29870eb7 PC |
1013 | .transfer_ord_max = 7, |
1014 | .flags = JZ_SOC_DATA_ALLOW_LEGACY_DT | JZ_SOC_DATA_PROGRAMMABLE_DMA, | |
6147b032 PC |
1015 | }; |
1016 | ||
d894fc60 | 1017 | static const struct of_device_id jz4780_dma_dt_match[] = { |
ffaaa8cc | 1018 | { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data }, |
ae9156b6 | 1019 | { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data }, |
29870eb7 | 1020 | { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data }, |
6147b032 | 1021 | { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data }, |
d894fc60 AS |
1022 | {}, |
1023 | }; | |
1024 | MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match); | |
1025 | ||
1026 | static struct platform_driver jz4780_dma_driver = { | |
1027 | .probe = jz4780_dma_probe, | |
1028 | .remove = jz4780_dma_remove, | |
1029 | .driver = { | |
1030 | .name = "jz4780-dma", | |
1031 | .of_match_table = of_match_ptr(jz4780_dma_dt_match), | |
1032 | }, | |
1033 | }; | |
1034 | ||
1035 | static int __init jz4780_dma_init(void) | |
1036 | { | |
1037 | return platform_driver_register(&jz4780_dma_driver); | |
1038 | } | |
1039 | subsys_initcall(jz4780_dma_init); | |
1040 | ||
1041 | static void __exit jz4780_dma_exit(void) | |
1042 | { | |
1043 | platform_driver_unregister(&jz4780_dma_driver); | |
1044 | } | |
1045 | module_exit(jz4780_dma_exit); | |
1046 | ||
1047 | MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>"); | |
1048 | MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver"); | |
1049 | MODULE_LICENSE("GPL"); |