Commit | Line | Data |
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754416e1 | 1 | #include <linux/delay.h> |
9b3452d1 SAS |
2 | #include <linux/dmaengine.h> |
3 | #include <linux/dma-mapping.h> | |
4 | #include <linux/platform_device.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/of.h> | |
7 | #include <linux/slab.h> | |
8 | #include <linux/of_dma.h> | |
9 | #include <linux/of_irq.h> | |
10 | #include <linux/dmapool.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/of_address.h> | |
d6aafa2b | 13 | #include <linux/pm_runtime.h> |
9b3452d1 SAS |
14 | #include "dmaengine.h" |
15 | ||
16 | #define DESC_TYPE 27 | |
17 | #define DESC_TYPE_HOST 0x10 | |
18 | #define DESC_TYPE_TEARD 0x13 | |
19 | ||
20 | #define TD_DESC_IS_RX (1 << 16) | |
21 | #define TD_DESC_DMA_NUM 10 | |
22 | ||
23 | #define DESC_LENGTH_BITS_NUM 21 | |
24 | ||
25 | #define DESC_TYPE_USB (5 << 26) | |
26 | #define DESC_PD_COMPLETE (1 << 31) | |
27 | ||
28 | /* DMA engine */ | |
29 | #define DMA_TDFDQ 4 | |
30 | #define DMA_TXGCR(x) (0x800 + (x) * 0x20) | |
31 | #define DMA_RXGCR(x) (0x808 + (x) * 0x20) | |
32 | #define RXHPCRA0 4 | |
33 | ||
34 | #define GCR_CHAN_ENABLE (1 << 31) | |
35 | #define GCR_TEARDOWN (1 << 30) | |
36 | #define GCR_STARV_RETRY (1 << 24) | |
37 | #define GCR_DESC_TYPE_HOST (1 << 14) | |
38 | ||
39 | /* DMA scheduler */ | |
40 | #define DMA_SCHED_CTRL 0 | |
41 | #define DMA_SCHED_CTRL_EN (1 << 31) | |
42 | #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800) | |
43 | ||
44 | #define SCHED_ENTRY0_CHAN(x) ((x) << 0) | |
45 | #define SCHED_ENTRY0_IS_RX (1 << 7) | |
46 | ||
47 | #define SCHED_ENTRY1_CHAN(x) ((x) << 8) | |
48 | #define SCHED_ENTRY1_IS_RX (1 << 15) | |
49 | ||
50 | #define SCHED_ENTRY2_CHAN(x) ((x) << 16) | |
51 | #define SCHED_ENTRY2_IS_RX (1 << 23) | |
52 | ||
53 | #define SCHED_ENTRY3_CHAN(x) ((x) << 24) | |
54 | #define SCHED_ENTRY3_IS_RX (1 << 31) | |
55 | ||
56 | /* Queue manager */ | |
57 | /* 4 KiB of memory for descriptors, 2 for each endpoint */ | |
58 | #define ALLOC_DECS_NUM 128 | |
59 | #define DESCS_AREAS 1 | |
60 | #define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS) | |
61 | #define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4) | |
62 | ||
63 | #define QMGR_LRAM0_BASE 0x80 | |
64 | #define QMGR_LRAM_SIZE 0x84 | |
65 | #define QMGR_LRAM1_BASE 0x88 | |
66 | #define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10) | |
67 | #define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10) | |
68 | #define QMGR_MEMCTRL_IDX_SH 16 | |
69 | #define QMGR_MEMCTRL_DESC_SH 8 | |
70 | ||
71 | #define QMGR_NUM_PEND 5 | |
72 | #define QMGR_PEND(x) (0x90 + (x) * 4) | |
73 | ||
74 | #define QMGR_PENDING_SLOT_Q(x) (x / 32) | |
75 | #define QMGR_PENDING_BIT_Q(x) (x % 32) | |
76 | ||
77 | #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10) | |
78 | #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10) | |
79 | #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10) | |
80 | #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10) | |
81 | ||
82 | /* Glue layer specific */ | |
83 | /* USBSS / USB AM335x */ | |
84 | #define USBSS_IRQ_STATUS 0x28 | |
85 | #define USBSS_IRQ_ENABLER 0x2c | |
86 | #define USBSS_IRQ_CLEARR 0x30 | |
87 | ||
88 | #define USBSS_IRQ_PD_COMP (1 << 2) | |
89 | ||
13bbfb5c DM |
90 | /* Packet Descriptor */ |
91 | #define PD2_ZERO_LENGTH (1 << 19) | |
92 | ||
9b3452d1 SAS |
93 | struct cppi41_channel { |
94 | struct dma_chan chan; | |
95 | struct dma_async_tx_descriptor txd; | |
96 | struct cppi41_dd *cdd; | |
97 | struct cppi41_desc *desc; | |
98 | dma_addr_t desc_phys; | |
99 | void __iomem *gcr_reg; | |
100 | int is_tx; | |
101 | u32 residue; | |
102 | ||
103 | unsigned int q_num; | |
104 | unsigned int q_comp_num; | |
105 | unsigned int port_num; | |
106 | ||
107 | unsigned td_retry; | |
108 | unsigned td_queued:1; | |
109 | unsigned td_seen:1; | |
110 | unsigned td_desc_seen:1; | |
fdea2d09 TL |
111 | |
112 | struct list_head node; /* Node for pending list */ | |
9b3452d1 SAS |
113 | }; |
114 | ||
115 | struct cppi41_desc { | |
116 | u32 pd0; | |
117 | u32 pd1; | |
118 | u32 pd2; | |
119 | u32 pd3; | |
120 | u32 pd4; | |
121 | u32 pd5; | |
122 | u32 pd6; | |
123 | u32 pd7; | |
124 | } __aligned(32); | |
125 | ||
126 | struct chan_queues { | |
127 | u16 submit; | |
128 | u16 complete; | |
129 | }; | |
130 | ||
131 | struct cppi41_dd { | |
132 | struct dma_device ddev; | |
133 | ||
134 | void *qmgr_scratch; | |
135 | dma_addr_t scratch_phys; | |
136 | ||
137 | struct cppi41_desc *cd; | |
138 | dma_addr_t descs_phys; | |
139 | u32 first_td_desc; | |
140 | struct cppi41_channel *chan_busy[ALLOC_DECS_NUM]; | |
141 | ||
142 | void __iomem *usbss_mem; | |
143 | void __iomem *ctrl_mem; | |
144 | void __iomem *sched_mem; | |
145 | void __iomem *qmgr_mem; | |
146 | unsigned int irq; | |
147 | const struct chan_queues *queues_rx; | |
148 | const struct chan_queues *queues_tx; | |
149 | struct chan_queues td_queue; | |
f8964968 | 150 | |
fdea2d09 TL |
151 | struct list_head pending; /* Pending queued transfers */ |
152 | spinlock_t lock; /* Lock for pending list */ | |
153 | ||
f8964968 DM |
154 | /* context for suspend/resume */ |
155 | unsigned int dma_tdfdq; | |
9b3452d1 SAS |
156 | }; |
157 | ||
158 | #define FIST_COMPLETION_QUEUE 93 | |
159 | static struct chan_queues usb_queues_tx[] = { | |
160 | /* USB0 ENDP 1 */ | |
161 | [ 0] = { .submit = 32, .complete = 93}, | |
162 | [ 1] = { .submit = 34, .complete = 94}, | |
163 | [ 2] = { .submit = 36, .complete = 95}, | |
164 | [ 3] = { .submit = 38, .complete = 96}, | |
165 | [ 4] = { .submit = 40, .complete = 97}, | |
166 | [ 5] = { .submit = 42, .complete = 98}, | |
167 | [ 6] = { .submit = 44, .complete = 99}, | |
168 | [ 7] = { .submit = 46, .complete = 100}, | |
169 | [ 8] = { .submit = 48, .complete = 101}, | |
170 | [ 9] = { .submit = 50, .complete = 102}, | |
171 | [10] = { .submit = 52, .complete = 103}, | |
172 | [11] = { .submit = 54, .complete = 104}, | |
173 | [12] = { .submit = 56, .complete = 105}, | |
174 | [13] = { .submit = 58, .complete = 106}, | |
175 | [14] = { .submit = 60, .complete = 107}, | |
176 | ||
177 | /* USB1 ENDP1 */ | |
178 | [15] = { .submit = 62, .complete = 125}, | |
179 | [16] = { .submit = 64, .complete = 126}, | |
180 | [17] = { .submit = 66, .complete = 127}, | |
181 | [18] = { .submit = 68, .complete = 128}, | |
182 | [19] = { .submit = 70, .complete = 129}, | |
183 | [20] = { .submit = 72, .complete = 130}, | |
184 | [21] = { .submit = 74, .complete = 131}, | |
185 | [22] = { .submit = 76, .complete = 132}, | |
186 | [23] = { .submit = 78, .complete = 133}, | |
187 | [24] = { .submit = 80, .complete = 134}, | |
188 | [25] = { .submit = 82, .complete = 135}, | |
189 | [26] = { .submit = 84, .complete = 136}, | |
190 | [27] = { .submit = 86, .complete = 137}, | |
191 | [28] = { .submit = 88, .complete = 138}, | |
192 | [29] = { .submit = 90, .complete = 139}, | |
193 | }; | |
194 | ||
195 | static const struct chan_queues usb_queues_rx[] = { | |
196 | /* USB0 ENDP 1 */ | |
197 | [ 0] = { .submit = 1, .complete = 109}, | |
198 | [ 1] = { .submit = 2, .complete = 110}, | |
199 | [ 2] = { .submit = 3, .complete = 111}, | |
200 | [ 3] = { .submit = 4, .complete = 112}, | |
201 | [ 4] = { .submit = 5, .complete = 113}, | |
202 | [ 5] = { .submit = 6, .complete = 114}, | |
203 | [ 6] = { .submit = 7, .complete = 115}, | |
204 | [ 7] = { .submit = 8, .complete = 116}, | |
205 | [ 8] = { .submit = 9, .complete = 117}, | |
206 | [ 9] = { .submit = 10, .complete = 118}, | |
207 | [10] = { .submit = 11, .complete = 119}, | |
208 | [11] = { .submit = 12, .complete = 120}, | |
209 | [12] = { .submit = 13, .complete = 121}, | |
210 | [13] = { .submit = 14, .complete = 122}, | |
211 | [14] = { .submit = 15, .complete = 123}, | |
212 | ||
213 | /* USB1 ENDP 1 */ | |
214 | [15] = { .submit = 16, .complete = 141}, | |
215 | [16] = { .submit = 17, .complete = 142}, | |
216 | [17] = { .submit = 18, .complete = 143}, | |
217 | [18] = { .submit = 19, .complete = 144}, | |
218 | [19] = { .submit = 20, .complete = 145}, | |
219 | [20] = { .submit = 21, .complete = 146}, | |
220 | [21] = { .submit = 22, .complete = 147}, | |
221 | [22] = { .submit = 23, .complete = 148}, | |
222 | [23] = { .submit = 24, .complete = 149}, | |
223 | [24] = { .submit = 25, .complete = 150}, | |
224 | [25] = { .submit = 26, .complete = 151}, | |
225 | [26] = { .submit = 27, .complete = 152}, | |
226 | [27] = { .submit = 28, .complete = 153}, | |
227 | [28] = { .submit = 29, .complete = 154}, | |
228 | [29] = { .submit = 30, .complete = 155}, | |
229 | }; | |
230 | ||
231 | struct cppi_glue_infos { | |
232 | irqreturn_t (*isr)(int irq, void *data); | |
233 | const struct chan_queues *queues_rx; | |
234 | const struct chan_queues *queues_tx; | |
235 | struct chan_queues td_queue; | |
236 | }; | |
237 | ||
238 | static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c) | |
239 | { | |
240 | return container_of(c, struct cppi41_channel, chan); | |
241 | } | |
242 | ||
243 | static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc) | |
244 | { | |
245 | struct cppi41_channel *c; | |
246 | u32 descs_size; | |
247 | u32 desc_num; | |
248 | ||
249 | descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM; | |
250 | ||
251 | if (!((desc >= cdd->descs_phys) && | |
252 | (desc < (cdd->descs_phys + descs_size)))) { | |
253 | return NULL; | |
254 | } | |
255 | ||
256 | desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc); | |
2d17f7fb | 257 | BUG_ON(desc_num >= ALLOC_DECS_NUM); |
9b3452d1 SAS |
258 | c = cdd->chan_busy[desc_num]; |
259 | cdd->chan_busy[desc_num] = NULL; | |
260 | return c; | |
261 | } | |
262 | ||
263 | static void cppi_writel(u32 val, void *__iomem *mem) | |
264 | { | |
265 | __raw_writel(val, mem); | |
266 | } | |
267 | ||
268 | static u32 cppi_readl(void *__iomem *mem) | |
269 | { | |
270 | return __raw_readl(mem); | |
271 | } | |
272 | ||
273 | static u32 pd_trans_len(u32 val) | |
274 | { | |
275 | return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1); | |
276 | } | |
277 | ||
706ff628 DM |
278 | static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num) |
279 | { | |
280 | u32 desc; | |
281 | ||
282 | desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num)); | |
283 | desc &= ~0x1f; | |
284 | return desc; | |
285 | } | |
286 | ||
9b3452d1 SAS |
287 | static irqreturn_t cppi41_irq(int irq, void *data) |
288 | { | |
289 | struct cppi41_dd *cdd = data; | |
290 | struct cppi41_channel *c; | |
291 | u32 status; | |
292 | int i; | |
293 | ||
294 | status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS); | |
295 | if (!(status & USBSS_IRQ_PD_COMP)) | |
296 | return IRQ_NONE; | |
297 | cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS); | |
298 | ||
299 | for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND; | |
300 | i++) { | |
301 | u32 val; | |
302 | u32 q_num; | |
303 | ||
304 | val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i)); | |
305 | if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) { | |
306 | u32 mask; | |
307 | /* set corresponding bit for completetion Q 93 */ | |
308 | mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE); | |
309 | /* not set all bits for queues less than Q 93 */ | |
310 | mask--; | |
311 | /* now invert and keep only Q 93+ set */ | |
312 | val &= ~mask; | |
313 | } | |
314 | ||
315 | if (val) | |
316 | __iormb(); | |
317 | ||
318 | while (val) { | |
13bbfb5c | 319 | u32 desc, len; |
9b3452d1 SAS |
320 | |
321 | q_num = __fls(val); | |
322 | val &= ~(1 << q_num); | |
323 | q_num += 32 * i; | |
706ff628 | 324 | desc = cppi41_pop_desc(cdd, q_num); |
9b3452d1 SAS |
325 | c = desc_to_chan(cdd, desc); |
326 | if (WARN_ON(!c)) { | |
327 | pr_err("%s() q %d desc %08x\n", __func__, | |
328 | q_num, desc); | |
329 | continue; | |
330 | } | |
9b3452d1 | 331 | |
13bbfb5c DM |
332 | if (c->desc->pd2 & PD2_ZERO_LENGTH) |
333 | len = 0; | |
334 | else | |
335 | len = pd_trans_len(c->desc->pd0); | |
336 | ||
337 | c->residue = pd_trans_len(c->desc->pd6) - len; | |
9b3452d1 | 338 | dma_cookie_complete(&c->txd); |
b310a619 | 339 | dmaengine_desc_get_callback_invoke(&c->txd, NULL); |
fdea2d09 TL |
340 | |
341 | /* Paired with cppi41_dma_issue_pending */ | |
342 | pm_runtime_mark_last_busy(cdd->ddev.dev); | |
343 | pm_runtime_put_autosuspend(cdd->ddev.dev); | |
9b3452d1 SAS |
344 | } |
345 | } | |
346 | return IRQ_HANDLED; | |
347 | } | |
348 | ||
349 | static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx) | |
350 | { | |
351 | dma_cookie_t cookie; | |
352 | ||
353 | cookie = dma_cookie_assign(tx); | |
354 | ||
355 | return cookie; | |
356 | } | |
357 | ||
358 | static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan) | |
359 | { | |
360 | struct cppi41_channel *c = to_cpp41_chan(chan); | |
fdea2d09 TL |
361 | struct cppi41_dd *cdd = c->cdd; |
362 | int error; | |
363 | ||
364 | error = pm_runtime_get_sync(cdd->ddev.dev); | |
365 | if (error < 0) | |
366 | return error; | |
9b3452d1 SAS |
367 | |
368 | dma_cookie_init(chan); | |
369 | dma_async_tx_descriptor_init(&c->txd, chan); | |
370 | c->txd.tx_submit = cppi41_tx_submit; | |
371 | ||
372 | if (!c->is_tx) | |
373 | cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0); | |
374 | ||
fdea2d09 TL |
375 | pm_runtime_mark_last_busy(cdd->ddev.dev); |
376 | pm_runtime_put_autosuspend(cdd->ddev.dev); | |
377 | ||
9b3452d1 SAS |
378 | return 0; |
379 | } | |
380 | ||
381 | static void cppi41_dma_free_chan_resources(struct dma_chan *chan) | |
382 | { | |
fdea2d09 TL |
383 | struct cppi41_channel *c = to_cpp41_chan(chan); |
384 | struct cppi41_dd *cdd = c->cdd; | |
385 | int error; | |
386 | ||
387 | error = pm_runtime_get_sync(cdd->ddev.dev); | |
388 | if (error < 0) | |
389 | return; | |
390 | ||
391 | WARN_ON(!list_empty(&cdd->pending)); | |
392 | ||
393 | pm_runtime_mark_last_busy(cdd->ddev.dev); | |
394 | pm_runtime_put_autosuspend(cdd->ddev.dev); | |
9b3452d1 SAS |
395 | } |
396 | ||
397 | static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan, | |
398 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
399 | { | |
400 | struct cppi41_channel *c = to_cpp41_chan(chan); | |
401 | enum dma_status ret; | |
402 | ||
403 | /* lock */ | |
404 | ret = dma_cookie_status(chan, cookie, txstate); | |
ed83c0c8 | 405 | if (txstate && ret == DMA_COMPLETE) |
9b3452d1 SAS |
406 | txstate->residue = c->residue; |
407 | /* unlock */ | |
408 | ||
409 | return ret; | |
410 | } | |
411 | ||
412 | static void push_desc_queue(struct cppi41_channel *c) | |
413 | { | |
414 | struct cppi41_dd *cdd = c->cdd; | |
415 | u32 desc_num; | |
416 | u32 desc_phys; | |
417 | u32 reg; | |
418 | ||
9b3452d1 SAS |
419 | c->residue = 0; |
420 | ||
421 | reg = GCR_CHAN_ENABLE; | |
422 | if (!c->is_tx) { | |
423 | reg |= GCR_STARV_RETRY; | |
424 | reg |= GCR_DESC_TYPE_HOST; | |
425 | reg |= c->q_comp_num; | |
426 | } | |
427 | ||
428 | cppi_writel(reg, c->gcr_reg); | |
429 | ||
430 | /* | |
431 | * We don't use writel() but __raw_writel() so we have to make sure | |
432 | * that the DMA descriptor in coherent memory made to the main memory | |
433 | * before starting the dma engine. | |
434 | */ | |
435 | __iowmb(); | |
670fc2a8 TL |
436 | |
437 | desc_phys = lower_32_bits(c->desc_phys); | |
438 | desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc); | |
439 | WARN_ON(cdd->chan_busy[desc_num]); | |
440 | cdd->chan_busy[desc_num] = c; | |
441 | ||
442 | reg = (sizeof(struct cppi41_desc) - 24) / 4; | |
443 | reg |= desc_phys; | |
444 | cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num)); | |
445 | } | |
446 | ||
fdea2d09 TL |
447 | static void pending_desc(struct cppi41_channel *c) |
448 | { | |
449 | struct cppi41_dd *cdd = c->cdd; | |
450 | unsigned long flags; | |
451 | ||
452 | spin_lock_irqsave(&cdd->lock, flags); | |
453 | list_add_tail(&c->node, &cdd->pending); | |
454 | spin_unlock_irqrestore(&cdd->lock, flags); | |
455 | } | |
456 | ||
670fc2a8 TL |
457 | static void cppi41_dma_issue_pending(struct dma_chan *chan) |
458 | { | |
459 | struct cppi41_channel *c = to_cpp41_chan(chan); | |
fdea2d09 TL |
460 | struct cppi41_dd *cdd = c->cdd; |
461 | int error; | |
462 | ||
463 | /* PM runtime paired with dmaengine_desc_get_callback_invoke */ | |
464 | error = pm_runtime_get(cdd->ddev.dev); | |
f2f6f828 | 465 | if ((error != -EINPROGRESS) && error < 0) { |
fdea2d09 TL |
466 | dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n", |
467 | error); | |
670fc2a8 | 468 | |
fdea2d09 TL |
469 | return; |
470 | } | |
471 | ||
472 | if (likely(pm_runtime_active(cdd->ddev.dev))) | |
473 | push_desc_queue(c); | |
474 | else | |
475 | pending_desc(c); | |
9b3452d1 SAS |
476 | } |
477 | ||
478 | static u32 get_host_pd0(u32 length) | |
479 | { | |
480 | u32 reg; | |
481 | ||
482 | reg = DESC_TYPE_HOST << DESC_TYPE; | |
483 | reg |= length; | |
484 | ||
485 | return reg; | |
486 | } | |
487 | ||
488 | static u32 get_host_pd1(struct cppi41_channel *c) | |
489 | { | |
490 | u32 reg; | |
491 | ||
492 | reg = 0; | |
493 | ||
494 | return reg; | |
495 | } | |
496 | ||
497 | static u32 get_host_pd2(struct cppi41_channel *c) | |
498 | { | |
499 | u32 reg; | |
500 | ||
501 | reg = DESC_TYPE_USB; | |
502 | reg |= c->q_comp_num; | |
503 | ||
504 | return reg; | |
505 | } | |
506 | ||
507 | static u32 get_host_pd3(u32 length) | |
508 | { | |
509 | u32 reg; | |
510 | ||
511 | /* PD3 = packet size */ | |
512 | reg = length; | |
513 | ||
514 | return reg; | |
515 | } | |
516 | ||
517 | static u32 get_host_pd6(u32 length) | |
518 | { | |
519 | u32 reg; | |
520 | ||
521 | /* PD6 buffer size */ | |
522 | reg = DESC_PD_COMPLETE; | |
523 | reg |= length; | |
524 | ||
525 | return reg; | |
526 | } | |
527 | ||
528 | static u32 get_host_pd4_or_7(u32 addr) | |
529 | { | |
530 | u32 reg; | |
531 | ||
532 | reg = addr; | |
533 | ||
534 | return reg; | |
535 | } | |
536 | ||
537 | static u32 get_host_pd5(void) | |
538 | { | |
539 | u32 reg; | |
540 | ||
541 | reg = 0; | |
542 | ||
543 | return reg; | |
544 | } | |
545 | ||
546 | static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg( | |
547 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len, | |
548 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
549 | { | |
550 | struct cppi41_channel *c = to_cpp41_chan(chan); | |
551 | struct cppi41_desc *d; | |
552 | struct scatterlist *sg; | |
553 | unsigned int i; | |
9b3452d1 | 554 | |
9b3452d1 SAS |
555 | d = c->desc; |
556 | for_each_sg(sgl, sg, sg_len, i) { | |
557 | u32 addr; | |
558 | u32 len; | |
559 | ||
560 | /* We need to use more than one desc once musb supports sg */ | |
9b3452d1 SAS |
561 | addr = lower_32_bits(sg_dma_address(sg)); |
562 | len = sg_dma_len(sg); | |
563 | ||
564 | d->pd0 = get_host_pd0(len); | |
565 | d->pd1 = get_host_pd1(c); | |
566 | d->pd2 = get_host_pd2(c); | |
567 | d->pd3 = get_host_pd3(len); | |
568 | d->pd4 = get_host_pd4_or_7(addr); | |
569 | d->pd5 = get_host_pd5(); | |
570 | d->pd6 = get_host_pd6(len); | |
571 | d->pd7 = get_host_pd4_or_7(addr); | |
572 | ||
573 | d++; | |
574 | } | |
575 | ||
576 | return &c->txd; | |
577 | } | |
578 | ||
9b3452d1 SAS |
579 | static void cppi41_compute_td_desc(struct cppi41_desc *d) |
580 | { | |
581 | d->pd0 = DESC_TYPE_TEARD << DESC_TYPE; | |
582 | } | |
583 | ||
9b3452d1 SAS |
584 | static int cppi41_tear_down_chan(struct cppi41_channel *c) |
585 | { | |
586 | struct cppi41_dd *cdd = c->cdd; | |
587 | struct cppi41_desc *td; | |
588 | u32 reg; | |
589 | u32 desc_phys; | |
590 | u32 td_desc_phys; | |
591 | ||
592 | td = cdd->cd; | |
593 | td += cdd->first_td_desc; | |
594 | ||
595 | td_desc_phys = cdd->descs_phys; | |
596 | td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc); | |
597 | ||
598 | if (!c->td_queued) { | |
599 | cppi41_compute_td_desc(td); | |
600 | __iowmb(); | |
601 | ||
602 | reg = (sizeof(struct cppi41_desc) - 24) / 4; | |
603 | reg |= td_desc_phys; | |
604 | cppi_writel(reg, cdd->qmgr_mem + | |
605 | QMGR_QUEUE_D(cdd->td_queue.submit)); | |
606 | ||
607 | reg = GCR_CHAN_ENABLE; | |
608 | if (!c->is_tx) { | |
609 | reg |= GCR_STARV_RETRY; | |
610 | reg |= GCR_DESC_TYPE_HOST; | |
611 | reg |= c->q_comp_num; | |
612 | } | |
613 | reg |= GCR_TEARDOWN; | |
614 | cppi_writel(reg, c->gcr_reg); | |
615 | c->td_queued = 1; | |
6f9d7056 | 616 | c->td_retry = 500; |
9b3452d1 SAS |
617 | } |
618 | ||
1e378a6d | 619 | if (!c->td_seen || !c->td_desc_seen) { |
9b3452d1 | 620 | |
1e378a6d SAS |
621 | desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete); |
622 | if (!desc_phys) | |
623 | desc_phys = cppi41_pop_desc(cdd, c->q_comp_num); | |
9b3452d1 | 624 | |
1e378a6d SAS |
625 | if (desc_phys == c->desc_phys) { |
626 | c->td_desc_seen = 1; | |
627 | ||
628 | } else if (desc_phys == td_desc_phys) { | |
629 | u32 pd0; | |
9b3452d1 | 630 | |
9b3452d1 | 631 | __iormb(); |
1e378a6d SAS |
632 | pd0 = td->pd0; |
633 | WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD); | |
634 | WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX)); | |
635 | WARN_ON((pd0 & 0x1f) != c->port_num); | |
636 | c->td_seen = 1; | |
637 | } else if (desc_phys) { | |
638 | WARN_ON_ONCE(1); | |
9b3452d1 SAS |
639 | } |
640 | } | |
641 | c->td_retry--; | |
642 | /* | |
643 | * If the TX descriptor / channel is in use, the caller needs to poke | |
644 | * his TD bit multiple times. After that he hardware releases the | |
645 | * transfer descriptor followed by TD descriptor. Waiting seems not to | |
646 | * cause any difference. | |
647 | * RX seems to be thrown out right away. However once the TearDown | |
648 | * descriptor gets through we are done. If we have seens the transfer | |
649 | * descriptor before the TD we fetch it from enqueue, it has to be | |
650 | * there waiting for us. | |
651 | */ | |
754416e1 SAS |
652 | if (!c->td_seen && c->td_retry) { |
653 | udelay(1); | |
9b3452d1 | 654 | return -EAGAIN; |
754416e1 | 655 | } |
9b3452d1 | 656 | WARN_ON(!c->td_retry); |
754416e1 | 657 | |
9b3452d1 | 658 | if (!c->td_desc_seen) { |
706ff628 | 659 | desc_phys = cppi41_pop_desc(cdd, c->q_num); |
754416e1 SAS |
660 | if (!desc_phys) |
661 | desc_phys = cppi41_pop_desc(cdd, c->q_comp_num); | |
9b3452d1 SAS |
662 | WARN_ON(!desc_phys); |
663 | } | |
664 | ||
665 | c->td_queued = 0; | |
666 | c->td_seen = 0; | |
667 | c->td_desc_seen = 0; | |
668 | cppi_writel(0, c->gcr_reg); | |
669 | return 0; | |
670 | } | |
671 | ||
672 | static int cppi41_stop_chan(struct dma_chan *chan) | |
673 | { | |
674 | struct cppi41_channel *c = to_cpp41_chan(chan); | |
675 | struct cppi41_dd *cdd = c->cdd; | |
676 | u32 desc_num; | |
677 | u32 desc_phys; | |
678 | int ret; | |
679 | ||
975faaeb GC |
680 | desc_phys = lower_32_bits(c->desc_phys); |
681 | desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc); | |
682 | if (!cdd->chan_busy[desc_num]) | |
683 | return 0; | |
684 | ||
9b3452d1 SAS |
685 | ret = cppi41_tear_down_chan(c); |
686 | if (ret) | |
687 | return ret; | |
688 | ||
9b3452d1 SAS |
689 | WARN_ON(!cdd->chan_busy[desc_num]); |
690 | cdd->chan_busy[desc_num] = NULL; | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
9b3452d1 SAS |
695 | static void cleanup_chans(struct cppi41_dd *cdd) |
696 | { | |
697 | while (!list_empty(&cdd->ddev.channels)) { | |
698 | struct cppi41_channel *cchan; | |
699 | ||
700 | cchan = list_first_entry(&cdd->ddev.channels, | |
701 | struct cppi41_channel, chan.device_node); | |
702 | list_del(&cchan->chan.device_node); | |
703 | kfree(cchan); | |
704 | } | |
705 | } | |
706 | ||
e327e21f | 707 | static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd) |
9b3452d1 SAS |
708 | { |
709 | struct cppi41_channel *cchan; | |
710 | int i; | |
711 | int ret; | |
712 | u32 n_chans; | |
713 | ||
e327e21f | 714 | ret = of_property_read_u32(dev->of_node, "#dma-channels", |
9b3452d1 SAS |
715 | &n_chans); |
716 | if (ret) | |
717 | return ret; | |
718 | /* | |
719 | * The channels can only be used as TX or as RX. So we add twice | |
720 | * that much dma channels because USB can only do RX or TX. | |
721 | */ | |
722 | n_chans *= 2; | |
723 | ||
724 | for (i = 0; i < n_chans; i++) { | |
725 | cchan = kzalloc(sizeof(*cchan), GFP_KERNEL); | |
726 | if (!cchan) | |
727 | goto err; | |
728 | ||
729 | cchan->cdd = cdd; | |
730 | if (i & 1) { | |
731 | cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1); | |
732 | cchan->is_tx = 1; | |
733 | } else { | |
734 | cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1); | |
735 | cchan->is_tx = 0; | |
736 | } | |
737 | cchan->port_num = i >> 1; | |
738 | cchan->desc = &cdd->cd[i]; | |
739 | cchan->desc_phys = cdd->descs_phys; | |
740 | cchan->desc_phys += i * sizeof(struct cppi41_desc); | |
741 | cchan->chan.device = &cdd->ddev; | |
742 | list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels); | |
743 | } | |
744 | cdd->first_td_desc = n_chans; | |
745 | ||
746 | return 0; | |
747 | err: | |
748 | cleanup_chans(cdd); | |
749 | return -ENOMEM; | |
750 | } | |
751 | ||
e327e21f | 752 | static void purge_descs(struct device *dev, struct cppi41_dd *cdd) |
9b3452d1 SAS |
753 | { |
754 | unsigned int mem_decs; | |
755 | int i; | |
756 | ||
757 | mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc); | |
758 | ||
759 | for (i = 0; i < DESCS_AREAS; i++) { | |
760 | ||
761 | cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i)); | |
762 | cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i)); | |
763 | ||
e327e21f | 764 | dma_free_coherent(dev, mem_decs, cdd->cd, |
9b3452d1 SAS |
765 | cdd->descs_phys); |
766 | } | |
767 | } | |
768 | ||
769 | static void disable_sched(struct cppi41_dd *cdd) | |
770 | { | |
771 | cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL); | |
772 | } | |
773 | ||
b46ce4d0 | 774 | static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd) |
9b3452d1 SAS |
775 | { |
776 | disable_sched(cdd); | |
777 | ||
e327e21f | 778 | purge_descs(dev, cdd); |
9b3452d1 SAS |
779 | |
780 | cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE); | |
781 | cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE); | |
e327e21f | 782 | dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch, |
9b3452d1 SAS |
783 | cdd->scratch_phys); |
784 | } | |
785 | ||
e327e21f | 786 | static int init_descs(struct device *dev, struct cppi41_dd *cdd) |
9b3452d1 SAS |
787 | { |
788 | unsigned int desc_size; | |
789 | unsigned int mem_decs; | |
790 | int i; | |
791 | u32 reg; | |
792 | u32 idx; | |
793 | ||
794 | BUILD_BUG_ON(sizeof(struct cppi41_desc) & | |
795 | (sizeof(struct cppi41_desc) - 1)); | |
796 | BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32); | |
797 | BUILD_BUG_ON(ALLOC_DECS_NUM < 32); | |
798 | ||
799 | desc_size = sizeof(struct cppi41_desc); | |
800 | mem_decs = ALLOC_DECS_NUM * desc_size; | |
801 | ||
802 | idx = 0; | |
803 | for (i = 0; i < DESCS_AREAS; i++) { | |
804 | ||
805 | reg = idx << QMGR_MEMCTRL_IDX_SH; | |
806 | reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH; | |
807 | reg |= ilog2(ALLOC_DECS_NUM) - 5; | |
808 | ||
809 | BUILD_BUG_ON(DESCS_AREAS != 1); | |
e327e21f | 810 | cdd->cd = dma_alloc_coherent(dev, mem_decs, |
9b3452d1 SAS |
811 | &cdd->descs_phys, GFP_KERNEL); |
812 | if (!cdd->cd) | |
813 | return -ENOMEM; | |
814 | ||
815 | cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i)); | |
816 | cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i)); | |
817 | ||
818 | idx += ALLOC_DECS_NUM; | |
819 | } | |
820 | return 0; | |
821 | } | |
822 | ||
823 | static void init_sched(struct cppi41_dd *cdd) | |
824 | { | |
825 | unsigned ch; | |
826 | unsigned word; | |
827 | u32 reg; | |
828 | ||
829 | word = 0; | |
830 | cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL); | |
831 | for (ch = 0; ch < 15 * 2; ch += 2) { | |
832 | ||
833 | reg = SCHED_ENTRY0_CHAN(ch); | |
834 | reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX; | |
835 | ||
836 | reg |= SCHED_ENTRY2_CHAN(ch + 1); | |
837 | reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX; | |
838 | cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word)); | |
839 | word++; | |
840 | } | |
841 | reg = 15 * 2 * 2 - 1; | |
842 | reg |= DMA_SCHED_CTRL_EN; | |
843 | cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL); | |
844 | } | |
845 | ||
e327e21f | 846 | static int init_cppi41(struct device *dev, struct cppi41_dd *cdd) |
9b3452d1 SAS |
847 | { |
848 | int ret; | |
849 | ||
850 | BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1)); | |
e327e21f | 851 | cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE, |
9b3452d1 SAS |
852 | &cdd->scratch_phys, GFP_KERNEL); |
853 | if (!cdd->qmgr_scratch) | |
854 | return -ENOMEM; | |
855 | ||
856 | cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE); | |
857 | cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE); | |
858 | cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE); | |
859 | ||
e327e21f | 860 | ret = init_descs(dev, cdd); |
9b3452d1 SAS |
861 | if (ret) |
862 | goto err_td; | |
863 | ||
864 | cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ); | |
865 | init_sched(cdd); | |
866 | return 0; | |
867 | err_td: | |
b46ce4d0 | 868 | deinit_cppi41(dev, cdd); |
9b3452d1 SAS |
869 | return ret; |
870 | } | |
871 | ||
872 | static struct platform_driver cpp41_dma_driver; | |
873 | /* | |
874 | * The param format is: | |
875 | * X Y | |
876 | * X: Port | |
877 | * Y: 0 = RX else TX | |
878 | */ | |
879 | #define INFO_PORT 0 | |
880 | #define INFO_IS_TX 1 | |
881 | ||
882 | static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param) | |
883 | { | |
884 | struct cppi41_channel *cchan; | |
885 | struct cppi41_dd *cdd; | |
886 | const struct chan_queues *queues; | |
887 | u32 *num = param; | |
888 | ||
889 | if (chan->device->dev->driver != &cpp41_dma_driver.driver) | |
890 | return false; | |
891 | ||
892 | cchan = to_cpp41_chan(chan); | |
893 | ||
894 | if (cchan->port_num != num[INFO_PORT]) | |
895 | return false; | |
896 | ||
897 | if (cchan->is_tx && !num[INFO_IS_TX]) | |
898 | return false; | |
899 | cdd = cchan->cdd; | |
900 | if (cchan->is_tx) | |
901 | queues = cdd->queues_tx; | |
902 | else | |
903 | queues = cdd->queues_rx; | |
904 | ||
905 | BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx)); | |
906 | if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx))) | |
907 | return false; | |
908 | ||
909 | cchan->q_num = queues[cchan->port_num].submit; | |
910 | cchan->q_comp_num = queues[cchan->port_num].complete; | |
911 | return true; | |
912 | } | |
913 | ||
914 | static struct of_dma_filter_info cpp41_dma_info = { | |
915 | .filter_fn = cpp41_dma_filter_fn, | |
916 | }; | |
917 | ||
918 | static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec, | |
919 | struct of_dma *ofdma) | |
920 | { | |
921 | int count = dma_spec->args_count; | |
922 | struct of_dma_filter_info *info = ofdma->of_dma_data; | |
923 | ||
924 | if (!info || !info->filter_fn) | |
925 | return NULL; | |
926 | ||
927 | if (count != 2) | |
928 | return NULL; | |
929 | ||
930 | return dma_request_channel(info->dma_cap, info->filter_fn, | |
931 | &dma_spec->args[0]); | |
932 | } | |
933 | ||
934 | static const struct cppi_glue_infos usb_infos = { | |
935 | .isr = cppi41_irq, | |
936 | .queues_rx = usb_queues_rx, | |
937 | .queues_tx = usb_queues_tx, | |
938 | .td_queue = { .submit = 31, .complete = 0 }, | |
939 | }; | |
940 | ||
941 | static const struct of_device_id cppi41_dma_ids[] = { | |
942 | { .compatible = "ti,am3359-cppi41", .data = &usb_infos}, | |
943 | {}, | |
944 | }; | |
945 | MODULE_DEVICE_TABLE(of, cppi41_dma_ids); | |
946 | ||
e327e21f | 947 | static const struct cppi_glue_infos *get_glue_info(struct device *dev) |
9b3452d1 SAS |
948 | { |
949 | const struct of_device_id *of_id; | |
950 | ||
e327e21f | 951 | of_id = of_match_node(cppi41_dma_ids, dev->of_node); |
9b3452d1 SAS |
952 | if (!of_id) |
953 | return NULL; | |
954 | return of_id->data; | |
955 | } | |
956 | ||
ffeb13aa FB |
957 | #define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
958 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
959 | BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ | |
960 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
961 | ||
9b3452d1 SAS |
962 | static int cppi41_dma_probe(struct platform_device *pdev) |
963 | { | |
964 | struct cppi41_dd *cdd; | |
717d8181 | 965 | struct device *dev = &pdev->dev; |
9b3452d1 SAS |
966 | const struct cppi_glue_infos *glue_info; |
967 | int irq; | |
968 | int ret; | |
969 | ||
717d8181 | 970 | glue_info = get_glue_info(dev); |
9b3452d1 SAS |
971 | if (!glue_info) |
972 | return -EINVAL; | |
973 | ||
f0f3b5fa | 974 | cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL); |
9b3452d1 SAS |
975 | if (!cdd) |
976 | return -ENOMEM; | |
977 | ||
978 | dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask); | |
979 | cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources; | |
980 | cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources; | |
981 | cdd->ddev.device_tx_status = cppi41_dma_tx_status; | |
982 | cdd->ddev.device_issue_pending = cppi41_dma_issue_pending; | |
983 | cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg; | |
3b5a03a6 | 984 | cdd->ddev.device_terminate_all = cppi41_stop_chan; |
ffeb13aa FB |
985 | cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); |
986 | cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS; | |
987 | cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS; | |
988 | cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
717d8181 | 989 | cdd->ddev.dev = dev; |
9b3452d1 SAS |
990 | INIT_LIST_HEAD(&cdd->ddev.channels); |
991 | cpp41_dma_info.dma_cap = cdd->ddev.cap_mask; | |
992 | ||
717d8181 DM |
993 | cdd->usbss_mem = of_iomap(dev->of_node, 0); |
994 | cdd->ctrl_mem = of_iomap(dev->of_node, 1); | |
995 | cdd->sched_mem = of_iomap(dev->of_node, 2); | |
996 | cdd->qmgr_mem = of_iomap(dev->of_node, 3); | |
fdea2d09 TL |
997 | spin_lock_init(&cdd->lock); |
998 | INIT_LIST_HEAD(&cdd->pending); | |
999 | ||
1000 | platform_set_drvdata(pdev, cdd); | |
9b3452d1 SAS |
1001 | |
1002 | if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem || | |
f0f3b5fa KP |
1003 | !cdd->qmgr_mem) |
1004 | return -ENXIO; | |
9b3452d1 | 1005 | |
717d8181 | 1006 | pm_runtime_enable(dev); |
fdea2d09 TL |
1007 | pm_runtime_set_autosuspend_delay(dev, 100); |
1008 | pm_runtime_use_autosuspend(dev); | |
717d8181 | 1009 | ret = pm_runtime_get_sync(dev); |
cbf1e56e | 1010 | if (ret < 0) |
d6aafa2b SAS |
1011 | goto err_get_sync; |
1012 | ||
9b3452d1 SAS |
1013 | cdd->queues_rx = glue_info->queues_rx; |
1014 | cdd->queues_tx = glue_info->queues_tx; | |
1015 | cdd->td_queue = glue_info->td_queue; | |
1016 | ||
717d8181 | 1017 | ret = init_cppi41(dev, cdd); |
9b3452d1 SAS |
1018 | if (ret) |
1019 | goto err_init_cppi; | |
1020 | ||
717d8181 | 1021 | ret = cppi41_add_chans(dev, cdd); |
9b3452d1 SAS |
1022 | if (ret) |
1023 | goto err_chans; | |
1024 | ||
717d8181 | 1025 | irq = irq_of_parse_and_map(dev->of_node, 0); |
f3b77727 JL |
1026 | if (!irq) { |
1027 | ret = -EINVAL; | |
9b3452d1 | 1028 | goto err_irq; |
f3b77727 | 1029 | } |
9b3452d1 SAS |
1030 | |
1031 | cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER); | |
1032 | ||
f0f3b5fa | 1033 | ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED, |
717d8181 | 1034 | dev_name(dev), cdd); |
9b3452d1 SAS |
1035 | if (ret) |
1036 | goto err_irq; | |
1037 | cdd->irq = irq; | |
1038 | ||
1039 | ret = dma_async_device_register(&cdd->ddev); | |
1040 | if (ret) | |
1041 | goto err_dma_reg; | |
1042 | ||
717d8181 | 1043 | ret = of_dma_controller_register(dev->of_node, |
9b3452d1 SAS |
1044 | cppi41_dma_xlate, &cpp41_dma_info); |
1045 | if (ret) | |
1046 | goto err_of; | |
1047 | ||
fdea2d09 TL |
1048 | pm_runtime_mark_last_busy(dev); |
1049 | pm_runtime_put_autosuspend(dev); | |
1050 | ||
9b3452d1 SAS |
1051 | return 0; |
1052 | err_of: | |
1053 | dma_async_device_unregister(&cdd->ddev); | |
1054 | err_dma_reg: | |
9b3452d1 SAS |
1055 | err_irq: |
1056 | cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR); | |
1057 | cleanup_chans(cdd); | |
1058 | err_chans: | |
717d8181 | 1059 | deinit_cppi41(dev, cdd); |
9b3452d1 | 1060 | err_init_cppi: |
fdea2d09 TL |
1061 | pm_runtime_dont_use_autosuspend(dev); |
1062 | pm_runtime_put_sync(dev); | |
d6aafa2b | 1063 | err_get_sync: |
717d8181 | 1064 | pm_runtime_disable(dev); |
9b3452d1 SAS |
1065 | iounmap(cdd->usbss_mem); |
1066 | iounmap(cdd->ctrl_mem); | |
1067 | iounmap(cdd->sched_mem); | |
1068 | iounmap(cdd->qmgr_mem); | |
9b3452d1 SAS |
1069 | return ret; |
1070 | } | |
1071 | ||
1072 | static int cppi41_dma_remove(struct platform_device *pdev) | |
1073 | { | |
1074 | struct cppi41_dd *cdd = platform_get_drvdata(pdev); | |
1075 | ||
1076 | of_dma_controller_free(pdev->dev.of_node); | |
1077 | dma_async_device_unregister(&cdd->ddev); | |
1078 | ||
1079 | cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR); | |
f0f3b5fa | 1080 | devm_free_irq(&pdev->dev, cdd->irq, cdd); |
9b3452d1 | 1081 | cleanup_chans(cdd); |
b46ce4d0 | 1082 | deinit_cppi41(&pdev->dev, cdd); |
9b3452d1 SAS |
1083 | iounmap(cdd->usbss_mem); |
1084 | iounmap(cdd->ctrl_mem); | |
1085 | iounmap(cdd->sched_mem); | |
1086 | iounmap(cdd->qmgr_mem); | |
fdea2d09 TL |
1087 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1088 | pm_runtime_put_sync(&pdev->dev); | |
d6aafa2b | 1089 | pm_runtime_disable(&pdev->dev); |
9b3452d1 SAS |
1090 | return 0; |
1091 | } | |
1092 | ||
522ef614 | 1093 | static int __maybe_unused cppi41_suspend(struct device *dev) |
f97b98d6 DM |
1094 | { |
1095 | struct cppi41_dd *cdd = dev_get_drvdata(dev); | |
1096 | ||
f8964968 | 1097 | cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ); |
f97b98d6 DM |
1098 | cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR); |
1099 | disable_sched(cdd); | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
522ef614 | 1104 | static int __maybe_unused cppi41_resume(struct device *dev) |
f97b98d6 DM |
1105 | { |
1106 | struct cppi41_dd *cdd = dev_get_drvdata(dev); | |
f8964968 | 1107 | struct cppi41_channel *c; |
f97b98d6 DM |
1108 | int i; |
1109 | ||
1110 | for (i = 0; i < DESCS_AREAS; i++) | |
1111 | cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i)); | |
1112 | ||
f8964968 DM |
1113 | list_for_each_entry(c, &cdd->ddev.channels, chan.device_node) |
1114 | if (!c->is_tx) | |
1115 | cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0); | |
1116 | ||
f97b98d6 | 1117 | init_sched(cdd); |
f8964968 DM |
1118 | |
1119 | cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ); | |
1120 | cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE); | |
1121 | cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE); | |
1122 | cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE); | |
1123 | ||
f97b98d6 DM |
1124 | cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER); |
1125 | ||
1126 | return 0; | |
1127 | } | |
fdea2d09 | 1128 | |
522ef614 | 1129 | static int __maybe_unused cppi41_runtime_suspend(struct device *dev) |
fdea2d09 TL |
1130 | { |
1131 | struct cppi41_dd *cdd = dev_get_drvdata(dev); | |
1132 | ||
1133 | WARN_ON(!list_empty(&cdd->pending)); | |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
522ef614 | 1138 | static int __maybe_unused cppi41_runtime_resume(struct device *dev) |
fdea2d09 TL |
1139 | { |
1140 | struct cppi41_dd *cdd = dev_get_drvdata(dev); | |
1141 | struct cppi41_channel *c, *_c; | |
1142 | unsigned long flags; | |
1143 | ||
1144 | spin_lock_irqsave(&cdd->lock, flags); | |
1145 | list_for_each_entry_safe(c, _c, &cdd->pending, node) { | |
1146 | push_desc_queue(c); | |
1147 | list_del(&c->node); | |
1148 | } | |
1149 | spin_unlock_irqrestore(&cdd->lock, flags); | |
1150 | ||
1151 | return 0; | |
1152 | } | |
f97b98d6 | 1153 | |
fdea2d09 TL |
1154 | static const struct dev_pm_ops cppi41_pm_ops = { |
1155 | SET_LATE_SYSTEM_SLEEP_PM_OPS(cppi41_suspend, cppi41_resume) | |
1156 | SET_RUNTIME_PM_OPS(cppi41_runtime_suspend, | |
1157 | cppi41_runtime_resume, | |
1158 | NULL) | |
1159 | }; | |
f97b98d6 | 1160 | |
9b3452d1 SAS |
1161 | static struct platform_driver cpp41_dma_driver = { |
1162 | .probe = cppi41_dma_probe, | |
1163 | .remove = cppi41_dma_remove, | |
1164 | .driver = { | |
1165 | .name = "cppi41-dma-engine", | |
f97b98d6 | 1166 | .pm = &cppi41_pm_ops, |
9b3452d1 SAS |
1167 | .of_match_table = of_match_ptr(cppi41_dma_ids), |
1168 | }, | |
1169 | }; | |
1170 | ||
1171 | module_platform_driver(cpp41_dma_driver); | |
1172 | MODULE_LICENSE("GPL"); | |
1173 | MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>"); |